COMPLEMENTARY MOS SEMICONDUCTOR DEVICE

专利名称：COMPLEMENTARY MOS SEMICONDUCTOR DEVICE

发明人：NUMATA KENJI

申请号：JP10770285

申请日：19850520

公开号：JPS61265859A

公开日：

19861125

专利内容由知识产权出版社提供

摘要：PURPOSE:To contrive improvement in the punch-through resisting property and the latch-up resisting property of the titled semiconductor device by a method wherein, between a P-channel MOSFET and an N-channel MOSFET, at least a source region and a drain region, which adjoin each other at the boundary part of a P-type semiconductor region and an N-type semiconductor region, are formed on the field insulating film of the boundary part. CONSTITUTION:The N<+> type layers 41 and 42 which become source and drain regions are formed on the field insulating film 3, a gate electrode 61 is formed on the surface of a P-type well 2 through the intermediary of a gate insulating film 5, and an N-channel MOSFET is constituted. A P-channel MOSFET is constituted by forming

P<+> type layers 43 and 44 and also by forming a gate electrode 62 on the surface of a substrate 1 through a gate insulating film 52. Then, a P<+> type layer 8 with which a P-well 2 is connected to a VSS potential is formed, and an N<+> type layer 9 with which the substrate 1 is connected to VDD is formed. A CVD insulating film 7 is applied on the surface of the substrate, a contact hole is perforated and a CMOS semiconductor is constituted.

申请人：TOSHIBA CORP

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