vlsi-2013

vlsi-2013
UNIVERSITY OF GLASGOW
Degree of MSc in Engineering
VLSI DESIGN AND CAD (ENG5092)
Friday 13 December 2013
09:30-11:30
Answer FOUR questions
Answer only TWO questions from each of sections A and B Each question is worth 25 marks
The numbers in square brackets in the right-hand margin indicate the marks allotted to the part of the question against which the mark is shown. These marks are for guidance only.
An electronic calculator may be used provided that it does not have a facility for either textual storage or display, or for graphical display.
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Section A : Attempt any TWO questions [50 marks] Q1 (a)
A pipelined system architecture must be able to arbitrarily shift data one bit to the left, one bit to the right, or not at all, in a single clock cycle. Sketch a circuit that will do this using pass-transistor logic. You may assume that there is an input and an output register associated with the device. [8] (b)
A simple digital multiplier relies on a process of successive shifting of data to the left, and addition. (i) Show how you can express a m -bit unsigned binary number using radix-2 notation.
[4] (ii) By expressing two unsigned binary numbers X and Y, of
length m and n respectively, in radix-2 notation, derive a formula for the product Z = XY . [8] (c)
Using your answer for part (b(ii)) of this question, write down the Boolean expression for the partial products that would appear in a logical implementation of the multiplier, and sketch the logic circuit required to calculate a partial product. [5] Q2 (a) Sketch the circuit diagram for a CMOS circuit with the function: D C B A Z ).(++= [8] (b)
A layout is required for the circuit. (i) In the layout for the circuit, what is the minimum number of regions of active required to make all the transistors? [2] (ii) Draw a stick diagram for the circuit, including features such as merged transistor active layers and bulk connections. Clearly label each part of your diagram. Coloured pens or pencils may be used, but are not essential. [9] (c)
What is the advantage of using techniques such as placing more than one transistor on a single region of active. [3] (d) How are the standard cells designed in practice to achieve regular layouts for blocks? Illustrate your answer with a sketch if necessary. [3]
Q3 (a) State the key dimensions th constructed us (b) The Elmore d between cells also be used, compared to u (c) Figure Q3 sho of three furthe the inputs layers of met connected usi interconnect, assume that al
(d) Cell placemen how cell pla minimize dela
Table Q3. Interconne
M1 area capacitance = 0.2 fF/μm M2 edge capacitance = 0.05 fF/μM2 area capacitance = 0.1 fF/μm M2 edge cap acitance = 0.05 fF/μ Co Page 3 of 6
e key MOSFET properties and their relationshi ons that determine the propagation delay a ted using them. more delay model can be used to estimate the int cells in a layout. Identify and describe two other m used, and say what advantages or disadvantages ed to using the Elmore method. Q3 shows the routing connecting the output o
f a cel further cells, labeled A, B and C. The load capaci uts is labeled in Figure Q3. The routin
g is requ f metal (M1 (horizontal) and M2 (vertical)) t
h ed using vias. Using Table Q3 for the electrical p nect, calculate the Elmore delay from Z to input A that all tracks are laid out to be of minimum width,cement strongly influences the overall delay of a c l placement affects delay, and what methods e delay by means of judicious cell placement. Figure Q3. Interconnect routing layout.
nnect electrical properties.
fF/μm 2 5 fF/μm fF/μm 2 5 fF/μm Via resistance = 0.5 ?
M1 resistivity = 0.1 ?/square M2 resistivity = 0.1 ?/square
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onship to the device
of a digital circuit
[5]
he interconnect delay
other methods that can
ages they have when
[8]
f a cell, Z, to the input
capacitance at each of
required to use two
) that are electrically
rical properties of the
nput A only. You may
width, which is 1 μm.
[6] of a circuit. Describe
hods can be used to
[6]
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Section B : Attempt any TWO questions [50 marks]
Q4 (a)
Draw a clearly labeled diagram showing the cross-section of a n-channel MOSFET in a p-type substrate. [4] (b)
Explain what is meant by the term inversion in the operation of a MOSFET. [3] (c) Consider a MOSFET of gate length L and gate width W .
(i) Write down an expression for the gate charge in terms of the gate
capacitance per unit area C ox , the applied gate-to-source voltage
V GS and threshold voltage V th . [2]
(ii) Show that at very low drain-to-source voltage V DS (near 0 V) the
drain current I D is given by
()DS th GS ox n D V V V L W C I ?=μ
where μn is the mobility of electrons near the si licon surface.
[8]
(d) Sketch a transistor layout indicating the active region, the polysilicon gate, and the contact areas for the smallest transistor that can be realized in a CMOS process. Using this, list and explain at least three basic design rules for laying out transistors
assuming that each mask has a worst case misalignment of 0.75λ, where λ is half the gate length. [8]
Q5 (a) Draw a labelled block diagram of a typical sampled data system. [6]
(b) Complex MOS ICs, such as microcontrollers, require on-chip data
conversion capabilities using only MOSFETs and capacitors.
A weighted
capacitor digital-to-analog converter (DAC) is a good example of such a
converter.
(i) Give the circuit diagram of a 3-bit weighted capacitor DAC and
explain its operation. [8] (ii) Comment on the drawbacks of this DAC architecture. [2]
(iii) What is the output voltage of a 3-bit weighted capacitor DAC
when the input word is 110 and the reference voltage V ref = 5V?[2]
(c) Sketch the schematic diagram of a potentiometric DAC using a 2-bit DAC
as an example. What is the main advantage of this DAC implementation?[7]
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Q6 (a) Flash analog-to-digital converters (ADC) are used in high-speed applications such as video and radar signal processing.
(i) Sketch the schematic diagram of a flash ADC using a 3-bit ADC to
illustrate your answer. Specify the relative reference resistor values
of the ADC and explain how high conversion speed is achieved. [7] (ii) If the reference voltage for the ADC is 3 V, specify the actual
reference voltage levels used in the conversion process. What will
be the digital output for an input voltage of 1 V? What range of
input voltages would give the same digital output in this case?
[6]
(b) Sigma-delta analog-to-digital converters (Σ-? ADC) are very popular for
very high resolution (≥16 bit) low-to-medium speed applications such as
digital audio.
(i) Explain what is meant by the term quantization noise. [3]
(ii) State and briefly explain the two techniques employed in Σ-?
ADCs to improve the signal-to-noise ratio. [6] (iii) The signal-to-noise (SNR) for a first order Σ-? ADC is given by
SNR = 6.02(n + 1.5m) – 3.41 dB, where the basic ADC is n-bit and
the oversampling ratio (OSR) is given by 2m. What sample rate is
required to obtain 16-bit resolution if the system uses a 1-bit ADC
and the Nyquist sampling rate is 44 kHz? [3]
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