ACT5230资料

Features
Block Diagram
s Full militarized QED RM5230 microprocessor
s
Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle
q 100, 133 and 150 MHz operating frequency – Consult
Factory for latest speeds q 228 Dhrystone2.1 MIPS
q SPECInt95 4.2 SPECfp95 4.5
s
System interface optomized for embedded applications
q 32-bit system interface lowers total system cost with up to
87.5 MHz operating frequency
q High performance write protocols maximize uncached write bandwidth
q Operates at processor clock divisors 2 through 8q 5V tolerant I/O's
q IEEE 1149.1 JTAG boundary scan
s
Integrated on-chip caches
q 16KB instruction - 2 way set associative q 16KB data - 2 way set associative q Virtually indexed, physically tagged
q Write-back and write-through on per page basis q Early restart on data cache misses
s
Integrated memory management unit
q Fully associative joint TLB (shared by I and D translations)q 48 dual entries map 96 pages
q Variable page size (4KB to 16MB in 4x increments)
s
High-performance floating point unit
q Single cycle repeat rate for common single precision
operations and some double precision operations
q Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations q Single cycle repeat rate for single precision combined multiply-add operation
s
MIPS IV instruction set
q Floating point multiply-add instruction increases
performance in signal processing and graphics applications
q Conditional moves to reduce branch frequency q Index address modes (register + register)
s
Embedded application enhancements
q Specialized DSP integer Multiply-Accumulate instruction
and 3 operand multiply instruction q I and D cache locking by set
q Optional dedicated exception vector for interrupts
s
Fully static CMOS design with power down logic
q Standby reduced power mode with WAIT instruction q 2.5 Watts typical with less than 70 mA standby current
s 128-pin Power Quad-4 package (F22), Consult Factory for
package configuration
Preliminary
Store Buffer
Data Set A Data T ag A DTLB Physical Data T ag B
Instruction Set A
Integer Instruction Register
FP Instruction Register
Instruction Set B Address Buffer Instruction T ag A ITLB Physical
Instruction Tag B
Sys AD
Write Buffer Read Buffer Data Set B
DBus
Control
Floating-point Register File
Joint TLB
Tag
Aux Tag
IntIBus
Floating-point Coprocessor 0
Unpacker/Packer
MAdd, Add, Sub,Cvt
PC Incrementer Branch Adder DV A
Load Aligner
Integer Register File Integer/Address Adder Data TLB Virtual Shifter/Store Aligner
Logic Unit Integer Multiply , Divide
Integer Control
Instruction TLB Virtual F l o a t i n g p o i n t C o n t r o l
Phase Lock Loop
Instruction Select
FPIBus
ABus
System/Memory
Control
Program Counter
IVA
Div , SqRt
32-Bit Superscaler Microprocessor
ACT5230
DESCRIPTION
The ACT5230 is a highly integrated superscalar microprocessor that implements a superset of the MIPS IV Instruction Set Architecture(ISA). It has a high performance 64-bit integer unit, a high throughput, fully pipelined 64-bit floating point unit, an operating system friendly memory management unit with a 48-entry fully associative TLB, a 16 KByte 2-way set associative instruction cache, a 16 KByte 2-way set associative data cache, and a high-performance 32-bit system interface. The ACT5230 can issue both an integer and a floating point instruction in the same cycle.
The ACT5230 is ideally suited for high-end embedded control applications such as internetworking, high performance image manipulation, high speed printing, and 3-D visualization.
HARDWARE OVERVIEW
The ACT5230 offers a high-level of integration targeted at high-performance embedded applications. Some of the key elements of the ACT5230 are briefly described below. Superscalar Dispatch
The ACT5230 has an efficient asymmetric superscalar dispatch unit which allows it to issue an integer instruction and a floating-point computation instruction simultaneously. With respect to superscalar issue, integer instructions include alu, branch, load/store, and floating-point load/store, while floating-point computation instructions include floating-point add, subtract, combined multiply-add, converts, etc. In combination with its high throughput fully pipelined floating-point execution unit, the superscalar capability of the ACT5230 provides unparalleled price/performance in computationally intensive embedded applications.
CPU Registers
Like all MIPS ISA processors, the ACT5230 CPU has a simple, clean user visible state consisting of 32 general purpose registers, two special purpose registers for integer multiplication and division, a program counter, and no condition code bits. Pipeline
For integer operations, loads, stores, and other non-floating-point operations, the ACT5230 uses the simple 5-stage pipeline also found in the QED circuits R4600, R4700, and R5000. In addition to this standard pipeline, the ACT5230 uses an extended seven stage pipeline for floating-point operations. Like the QED R5000, the ACT5230 does virtual to physical translation in parallel with cache access. Integer Unit
Like the QED R5000, the ACT5230 implements the MIPS IV Instruction Set Architecture, and is therefore fully upward compatible with applications that run on processors implementing the earlier generation MIPS I-III instruction sets. Additionally, the ACT5230 includes two implementation specific instructions not found in the baseline MIPS IV ISA but that are useful in the embedded market place. Described in detail in the QED RM5230 datasheet,, these instructions are integer multiply-accumulate and 3-operand integer multiply.
The ACT5230 integer unit includes thirty-two general purpose 64-bit registers, a load/store architecture with single cycle ALU operations (add, sub, logical, shift) and an autonomous multiply/divide unit. Additional register resources include: the HI/LO result registers for the two-operand integer multiply/ divide operations, and the program counter(PC). Register File
The ACT5230 has thirty-two general purpose registers with register location 0 hard wired to zero. These registers are used for scalar integer operations and address calculation. The register file has two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline.
ALU
The ACT5230 ALU consists of the integer adder/ subtractor, the logic unit, and the shifter. The adder performs address calculations in addition to arithmetic operations, the logic unit performs all logical and zero shift data moves, and the shifter performs shifts and store alignment operations. Each of these units is optimized to perform all operations in a single processor cycle
For Detail Information regarding the operation of the Quantum Effect Design (QED) RISCMark™RM5230™, 32-Bit Superscalar Microprocessor see the QED datasheet (Revision 1.2 July 1998).
Absolute Maximum Ratings1
Symbol Rating Range Units T TERM T erminal Voltage with respect to GND-0.52 to 4.6V T CASE Operating T emperature0 to +85°C T BIAS Case T emperature under Bias-55 to +125°C T STG Storage T emperature-55 to +125°C
I IN DC Input Current203mA
I OUT DC Output Current50mA Notes:
1. Stresses above those listed under "AbsoluteMaximums Rating" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2. V IN minimum = -2.0V for pulse width less than 15nS. V IN maximum should not exceed +5.5 Volts.
3. When V IN < 0V or V IN > Vcc.
4. No more than one output should be shorted at one time. Duration of the short should not exceed more than 30 second.
Recommended Operating Conditions
Symbol Parameter Minimum Maximum Units V CC Power Supply Voltage+3.135+3.465V V IH Input High Voltage0.7V CC V CC+ 0.5V V IL Input Low Voltage-0.50.2V CC V T C Operating Temperature Case (Commercial)0 +85°C
DC Characteristics
(V CC = 3.3V ±5%; T CASE = 0°C to +85°C)
Parameter Sym Conditions
133 / 150MHz
Units Min Max
Output Low Voltage V OL1I OL = 20 µA0.1V Output High Voltage V OH1I OL = 20 µA Vcc - 0.1V Output Low Voltage V OL2I OL = 4 mA0.4V Output High Voltage V OH2I OL = 4 mA 2.4V Input High Voltage V IH0.7V CC V CC+ 0.5V Input Low Voltage V IL-0.50.2V CC V Input Current I IN1V IN = 0V-20+20µA Input Current I IN2V IN = V CC-20+20µA Input Current I IN3V IN = 5.5V-250+250µA Input Capacitance C IN10pF Output Capacitance C OUT10pF
AC Characteristics
(V CC = 3.3V ±5%; T CASE = 0°C to +85°C)
Power Consumption
Parameter Symbol Conditions
133MHz, 3.3V 150MHz, 3.3V Units Typ 5
Max Typ 5
Max Active Operating Supply Current
I CC1C L = 0pF , 150/75MHz, No SysAD activity
TBD TBD TBD TBD mA I CC2C L = 50pF , 150/75MHz, R4000 write protocol without FPU operation 1000175011501950mA I CC3
C L = 50pF , 150/75MHz, write re-issue or pipelined writes 1100
20001250
2250mA Standby Current
I SB1C L = 0pF , 150/75MHz TBD TBD mA I SB1
C L = 50pF , 150/75MHz
TBD
TBD
mA
Notes:
5. Typical integer instruction mix and cache miss rates.
Capacitive Load Deration
Symbol Parameter
133 / 150MHz Units Minimum
Maximum
C LD
Load Derate
2
ns/25pF
Clock Parameters
Parameter Symbol Test Conditions
133/150MHz Units Min Max
SysClock High t SCHigh T ransition < 5ns 4ns SysClock Low t SCLow
T ransition < 5ns
4ns SysClock Frequency 633
75MHz SysClock Period t SCP 30ns Clock Jitter for SysClock t JitterIn ±250ps SysClock Rise Time t SCRise 5ns SysClock Fall Time t SCFall 5ns ModeClock Period t ModeCKP 256*t SCP ns JT A Clock Period
t JT AGCKP 4*t SCP ns
Notes:
6. Operation of the ACT5230 is only guaranteed with the Phase Loop enabled.
System Interface Parameters7
Parameter Symbol Test Conditions
133MHz150MHz
Units Min Max Min Max
Data Output8
t DO mode14...13 = 10 (fastest)TBD TBD TBD TBD ns mode14...13 = 11TBD TBD TBD TBD ns mode14...13 = 00 1.08.0 1.08.0ns mode14...13 = 01 (slowest)TBD TBD TBD TBD ns
Data Setup t DS t RISE = 5ns 4.0 4.0ns Data Hold t DH t FALL= 5ns00ns Notes:
7. Timmings are are measured from from 1.5V of the clock to 1.5V of the signal.
8. Capacitive load for all output timing is 50pF.
Boot Time Interface Parameters
Parameter Symbol Test Conditions
133/150MHz
Units Min Max
Mode Data Setup t DS4SysClock cycles Mode Data Hold t DH0SysClock cycles
ACT5230 Microprocessor – PQUAD Pinouts
Pin #Function Pin #Function
Pin # Function Pin # Function 1Vcc 53NC 105Vcc 157NC 2NC 54NC 106NMI*158NC 3NC 55NC 107ExtRqst*159NC 4Vcc 56Vcc 108Reset*160NC 5Vss 57Vss 109ColdReset*161Vcc 6SysAD458ModeIn 110VccOK 162Vss 7NC 59RdRdy*111BigEndian 163SysAD288SysAD560WrRdy*112Vcc 164NC 9NC 61ValidIn*113Vss 165SysAD2910Vcc 62ValidOut*114SysAD16166NC 11Vss 63Release*115NC 167Vcc 12SysAD664VccP 116Vcc 168Vss 13NC 65VssP 117Vss 169SysAD3014Vcc 66SysClock 118SysAD17170NC 15Vss 67Vcc 119NC 171Vcc 16SysAD768Vss 120SysAD18172Vss 17NC 69Vcc 121NC 173SysAD3118SysAD870Vss 122Vcc 174NC 19NC 71Vcc 123Vss 175SysADC220Vcc 72Vss 124SysAD19176SysADC621Vss 73SysCmd0125NC 177Vcc 22SysAD974SysCmd1126Vcc 178Vss 23NC 75SysCmd2127Vss 179SysADC324Vcc 76SysCmd3128SysAD20180SysADC725Vss 77Vcc 129NC 181Vcc 26SysAD1078Vss 130SysAD21182Vss 27NC 79SysCmd4131NC 183SysADC028SysAD1180SysCmd5132Vcc 184SysADC429NC 81Vcc 133Vss 185Vcc 30Vcc 82Vss 134SysAD22186Vss 31Vss 83SysCmd6135NC 187SysADC132SysAD1284SysCmd7136Vcc 188SysADC533NC 85SysCmd8137Vss 189SysAD034Vcc 86SysCmdP 138SysAD23190NC 35Vss 87Vcc 139NC 191Vcc 36SysAD1388Vss 140SysAD24192Vss 37NC 89Vcc 141NC 193SysAD138SysAD1490Vss 142Vcc 194NC 39NC 91Vcc 143Vss 195Vcc 40Vcc 92Vss 144SysAD25196Vss 41Vss 93Int0*145NC 197SysAD242SysAD1594Int1*146Vcc 198NC 43NC 95Int2*147Vss 199SysAD344Vcc 96Int3*148SysAD26200NC 45Vss 97Int4*149NC 201Vcc 46ModeClock 98Int5*150SysAD27202Vss 47JTDO 99Vcc 151NC 203NC 48JTDI 100Vss 152Vcc 204NC 49JTCK 101NC 153Vss 205NC 50JTMS 102NC 154NC 206NC 51Vcc 103NC 155NC 207Vcc 52
Vss
104
NC
156
Vss
208
Vss
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& P i n
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c h a n g e – C o
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F a c t o r y )
Sample Ordering Information
Part Number Screening Speed (MHz)
Package ACT -5230PC-133F22I Industrial Temperature 133 128 Lead PQUAD ACT -5230PC-150F22C Commercial Temperature 150 128 Lead PQUAD ACT -5230PC-200F22T Military Temperature 200 128 Lead PQUAD ACT -5230PC-200F22M
Military Screening
200
128 Lead PQUAD
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Specifications subject to change without notice.
C I R C U I T T E C H N O L O G Y
Part Number Breakdown
ACT–5230PC –133F22M
Aeroflex Circuit Technology
Base Processor Type
133 = 133MHz 150 = 150MHz 200 = 200MHz
Cache Style
Package Type & Size
C = Commercial Temp, 0°C to +70°C I = Industrial T emp, -40°C to +85°C T = Military T emp, -55°C to +125°C
M = Military T emp, -55°C to +125°C, Screened *Q = MIL-PRF-38534 Compliant/SMD if applicable
Screening
* Screened to the individual test methods of MIL-STD-883
PC = Primary Cache
Maximum Pipeline Freq.
Surface Mount Package
F22 = 1.10" SQ 128 Lead PQUAD。