SN74LVC16373DGGR,SN74LVC16373DLR,74LVC16373DGGRE4,SN74LVC16373DLRG4, 规格书,Datasheet 资料

FEATURESDESCRIPTIONDGG OR DL PACKAGE(TOP VIEW)CCCCA buffered output-enable(OE)input can be used to place the eight outputs in either a normal logic state(high orSN74LVC1637316-BIT TRANSPARENT D-TYPE LATCHWITH3-STATE OUTPUTSSCAS315B–NOVEMBER1993–REVISED MARCH2005•Member of the Texas Instruments Widebus™Family•EPIC™(Enhanced-Performance ImplantedCMOS)Submicron Process•Typical V OLP(Output Ground Bounce)<0.8V at V CC=3.3V,T A=25°C•Typical V OHV(Output V OH Undershoot)>2V at V CC=3.3V,T A=25°C•Latch-Up Performance Exceeds250mAPer JEDEC Standard JESD-17•Bus Hold on Data Inputs Eliminates the Needfor External Pullup/Pulldown Resistors•Package Options Include Plastic300-milShrink Small-Outline(DL)and Thin ShrinkSmall-Outline(DGG)PackagesThis16-bit transparent D-type latch is designed for2.7-V to3.6-V V CC operation.The SN74LVC16373is particularly suitable forimplementing buffer registers,I/O ports,bidirectionalbus drivers,and working registers.It can be used astwo8-bit latches or one16-bit latch.When thelatch-enable(LE)input is high,the Q outputs followthe data(D)inputs.When LE is taken low,the Qoutputs are latched at the levels set up at the Dinputs.low logic levels)or a high-impedance state.In the high-impedance state,the outputs neither load nor drive the bus lines significantly.The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.OE does not affect internal operations of the latch.Old data can be retained or new data can be entered while the outputs are in the high-impedance state.To ensure the high-impedance state during power up or power down,OE should be tied to V CC through a pullup resistor;the minimum value of the resistor is determined by the current-sinking capability of the driver.Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.The SN74LVC16373is characterized for operation from–40°C to85°C.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Widebus,EPIC are trademarks of Texas Instruments.PRODUCTION DATA information is current as of publication date.Copyright©1993–2005,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does not1OE 1LE1D1To Seven Other Channels1Q12OE 2LE 2D12Q1To Seven Other Channels1OE 2OE1LE 1D11D21D31D41Q11Q21Q31Q41D51D61D71D81Q51Q61Q71Q82D12D22D32D42Q12Q22Q32Q42D52D62D72D82Q52Q62Q72Q82LE (1) This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.SN74LVC1637316-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTSSCAS315B–NOVEMBER 1993–REVISED MARCH 2005FUNCTION TABLE (EACH 8-BIT SECTION)INPUTSOUTPUTQOE LE D L H H H L H L L L L X Q 0HXXZLOGIC SYMBOL (1)LOGIC DIAGRAM (POSITIVE LOGIC)2Absolute Maximum Ratings(1) Recommended Operating Conditions(1)SN74LVC16373 16-BIT TRANSPARENT D-TYPE LATCHWITH3-STATE OUTPUTS SCAS315B–NOVEMBER1993–REVISED MARCH2005over operating free-air temperature range(unless otherwise noted)MIN MAX UNITV CC Supply voltage range–0.5 4.6VV I Input voltage range(2)–0.5 4.6VV O Output voltage range(2)(3)–0.5V CC+0.5VI IK Input clamp current V I<0–50mAI OK Output clamp current V O<0or V O>V CC±50mAI O Continuous output current V O=0to V CC±50mAContinuous current through V CC or GND±100mADGG package0.85 Maximum power dissipation at T A=55°C(in still air)(4)WDL package 1.2T stg Storage temperature range–65150°C (1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.(3)This value is limited to4.6V maximum.(4)The maximum package power dissipation is calculated using a junction temperature of150°C and a board trace length of750mils.Formore information,refer to the Package Thermal Considerations application note in the1994ABT Advanced BiCMOS Technology Data Book,literature number SCBD002B.MIN MAX UNIT V CC Supply voltage 2.7 3.6VV IH High-level input voltage V CC=2.7V to3.6V2VV IL Low-level input voltage V CC=2.7V to3.6V0.8VV I Input voltage0V CC VV O Output voltage0V CC VV CC=2.7V–12I OH High-level output current mAV CC=3V–24V CC=2.7V12I OL Low-level output current mAV CC=3V24∆t/∆V Input transition rise or fall rate010ns/VT A Operating free-air temperature–4085°C (1)Unused control inputs must be held high or low to prevent them from floating.3Electrical CharacteristicsTiming RequirementsSwitching CharacteristicsOperating CharacteristicsSN74LVC1637316-BIT TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTSSCAS315B–NOVEMBER 1993–REVISED MARCH 2005over recommended operating free-air temperature range (unless otherwise noted)PARAMETERTEST CONDITIONSV CC (1)MIN TYP (2)MAX UNITI OH =–100µAMIN to MAXV CC –0.22.7V 2.2V OHI OH =–12mA V 3V 2.4I OH =–24mA 3V 2I OL =100µAMIN to MAX0.2V OL I OL =12mA 2.7V 0.4V I OL =24mA 3V 0.55I I V I =V CC or GND 3.6V ±5µA V I =0.8V 75I I(hold)Data inputs3V µA V I =2V–75I OZ V O =V CC or GND 3.6V ±10µA I CC V I =V CC or GND,I O =03.6V 40µA ∆I CC One input at V CC –0.6V,Other inputs at V CC or GND3V to 3.6V 500µA C i V I =V CC or GND 3.3V 3.5pF C o V O =V CC or GND3.3V7pF (1)For conditions shown as MIN or MAX,use the appropriate values under recommended operating conditions.(2)All typical values are at V CC =3.3V,T A =25°C.over recommended operating free-air temperature range (unless otherwise noted)(see Figure 1)V CC =3.3V V CC =2.7V ±0.3V UNITMIN MAXMIN MAX t w Pulse duration,LE high 44ns t su Setup time,data before LE ↓22ns t hHold time,data after LE ↓22ns over recommended ranges of supply voltage and operating free-air temperature,C L =50pF (unless otherwise noted)(see Figure 1)V CC =3.3V V CC =2.7V FROM TO ±0.3V PARAMETERUNIT(INPUT)(OUTPUT)MIN MAX MIN MAXD 1.578t pd Q ns LE 289t en OE Q 1.589ns t disOEQ1.578ns T A =25°CPARAMETERTEST CONDITIONS TYP UNIT Outputs enabled 20C pdPower dissipation capacitance per latchC L =50pF,f =10MHzpFOutputs disabled44PARAMETER MEASUREMENT INFORMATIONFrom Output Under TestC L LOAD CIRCUIT FOR OUTPUTSOpen Data InputTiming Input2.7 V0 V2.7 V0 V2.7 V0 VInputVOLTAGE WAVEFORMS SETUP AND HOLD TIMESVOLTAGE WAVEFORMS PROPAGATION DELAY TIMESINVERTING AND NONINVERTING OUTPUTSVOLTAGE WAVEFORMS PULSE DURATIONInputOutput ControlOutput Waveform 1S1 at 6 V (see Note B)Output Waveform 2S1 at GND (see Note B)V OLV OH 3 V0 V[0 V2.7 VVOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES LOW- AND HIGH-LEVEL ENABLINGOutputOutputt pd t PLZ /t PZL t PHZ /t PZHOpen 6 V GNDTEST S1NOTES: A.C L includes probe and jig capacitance.B.Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control. Waveform2 is for an output with internal conditions such that the ouput is high, except when disabled by the output control.C.All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z O = 50 W , t r ≤ 2.5 ns, t f ≤ 2.5 ns.D.The outputs are measured one at a time, with one transition per measurement.E.t PLZ and t PHZ are the same as t dis .F.t PZL and t PZH are the same as t en .G.t PLH and t PHL are the same as t pd .SN74LVC1637316-BIT TRANSPARENT D-TYPE LATCHWITH 3-STATE OUTPUTSSCAS315B–NOVEMBER 1993–REVISED MARCH 2005Figure 1.Load Circuit and Voltage Waveforms5PACKAGING INFORMATIONOrderable Device Status (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)74LVC16373DGGRE4ACTIVE TSSOP DGG 482000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVC16373DGGR ACTIVE TSSOP DGG 482000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVC16373DL ACTIVE SSOP DL 4825Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVC16373DLG4ACTIVE SSOP DL 4825Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVC16373DLR ACTIVE SSOP DL 481000Green (RoHS &no Sb/Br)CU NIPDAU Level-1-260C-UNLIM SN74LVC16373DLRG4ACTIVESSOPDL481000Green (RoHS &no Sb/Br)CU NIPDAULevel-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -The planned eco-friendly classification:Pb-Free (RoHS),Pb-Free (RoHS Exempt),or Green (RoHS &no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt):This component has a RoHS exemption for either 1)lead-based flip-chip solder bumps used between the die and package,or 2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free (RoHS compatible)as defined above.Green (RoHS &no Sb/Br):TI defines "Green"to mean Pb-Free (RoHS compatible),and free of Bromine (Br)and Antimony (Sb)based flame retardants (Br or Sb do not exceed 0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM6-Aug-2007TAPE AND REEL INFORMATION*All dimensions are nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant SN74LVC16373DGGR TSSOP DGG 482000330.024.48.615.8 1.812.024.0Q1SN74LVC16373DLRSSOPDL481000330.032.411.3516.23.116.032.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) SN74LVC16373DGGR TSSOP DGG482000367.0367.045.0SN74LVC16373DLR SSOP DL481000367.0367.055.0IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,enhancements,improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B.Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All semiconductor products(also referred to herein as“components”)are sold subject to TI’s terms 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