4BI0_1B_que_20120515
BSXE_datasheet_FINAL_4_4_08
Board Station XEPCB LayoutD A T A S HE E Tw w w.m e n t o r.c o mBoard Station XE is the technology leader for the creation of today’s most complex PCB designs.Board Station XE — Powered by AutoActive TechnologyThe Board Station® XE layout tool, powered byAutoActive® technology, is an integral part of the tightly integrated Board Station XE design flow. By combining ease-of-use with advanced functionality, Board Station XE offers designers the leading technology for the creation of today’s most complex designs. Board Station XE includes interactive and customizable multi-pass autorouting controls for design challenges such as differential pair routing, net tuning, manufacturing optimization and microvia and build-up technology.AutoActive — The Technology Leader in PCB DesignAutoActive technology represents a revolutionary step forward for PCB design. The power of industry-leadingauto-routing technology is combined with interactive editing capabilities to produce a single, powerful and easy-to-use design environment. This environment eliminates the burdens of jumping between tools to get your job done and managing differences between the constraints on the autorouter and on interactive editing.AutoActive provides designers with greater control than ever before, with the ability to easily switch between auto-matic and manual editing. From simple tasks, such as defining board areas, to complex procedures that involve maintaining high-speed signal conditions, all objectives are accomplished with the system and the designer working together in real-time. The net result of AutoActive technology is reduced design times, increased productivity and unmatched design quality.What is AutoActive Technology?· A single, integrated, place and route editing environment that reducestotal design time and increasesproductivity·All physical rules and high-speed rules are maintained ·Correct-by-construction design that produces high-quality results withclean-up time eliminated ·Shape-based, true 45 degree routing ·The most advanced autorouting technology ever. Stop and start theautorouter at any time and all results will be correct-by-construction ·Dynamic clean-up of traces through the reduction of segments, preven-tion of acute angles and applicationof pad entry rulesDynamic Area FillsBoard Station XE automatically clears area fills around traces, vias and pads as the board is edited. Dynamic area fills are so fast, Board Station XE allows you to keep your area fillsturned on while you are doing all youredits. Moving a via pushes and shovesother vias, traces and area fills andconnectivity is automatically main-tained.Rules By AreaRules by area functionality greatlyimproves routing around BGAs andother fine-pitched parts. Rule areasrepresent complete rule sets that areobeyed by online and batch DRC and ininteractive and automatic routing. Ruleareas may be defined by layer and canbe assigned to any polygon, rectangle orcircle. Trace widths and clearancesautomatically change when traversinginto or out of the rule area. You mayalso change via sizes and spans in a rulearea to maximize route completion.Multiplow With Variable ViaPatternsBoard Station XE’s multiplow func-tionality allows you to simultaneouslyroute multiple nets, including differen-tial pairs, with true 45 degree routing. Itcan even handle routing through areasof staggered pins. Traces being routedwill push and shove the other vias andtraces out of the way and automaticallyclear area fills as needed. Changes canbe easily made to a variety of selectablevia patterns at the touch of a button,allowing enhanced flexibility forrouting into dense areas of a design.Dynamic Hazard ReviewDesign hazards are dynamicallydisplayed and may be individuallyselected and colored for easy identifica-tion. When a hazard is fixed, it isdynamically removed from the hazardlist.Leverages Legacy Board StationFlowBoard Station XE can be usedquickly and easily by existing BoardStation Layout customers. First, BoardStation XE uses the same libraries(geometries) as the legacy flow. BoardStation XE is integrated with he samefront-end tools and library managementsystem as the legacy tools. Finally,customers can easily import legacyBoard Station Layout designs intoBoard Station XE in order to start newdesigns from an existing one. This allgives customers access to the state-of-the-art layout environment using theirexisting library infrastructure and front-end tools.Board Station XE features market-leading technology for advanced interconnect.High-Speed Design with Board Station XEDesigners today are increasingly challenged by the need to manage signal quality in order to achieve system performance and reduce proto-type iterations. High-speed design with Board Station XE is an integrated part of the AutoActive design environment.Constraint DefinitionBoard Station XE handles an exten-sive set of constraints to meet high-speed performance requirements whether you’re routing interactively or automatically. A common constraint definition environment is shared between schematic capture and layout, allowing the evaluation of critical signals at any design stage. Constraints include same layer and adjacent layer differential pairs, controlled impedance, net scheduling and delay.Net TuningWhile routing interactively, graphic tuning aids are displayed for guidance. Nets modified out-of-tune during edits are automatically re-tuned. The Hazards dialog box dynamically updates as you edit nets, providing instant feedback relative to your constraints. Nets can also be tuned within an autoroute pass. Tuned nets are automatically maintained as you complete the design.Differential Pair RoutingRouting and editing differential pairs with Board Station XE is accomplished with speed and ease that will change your view of high-speed design. Pair spacing rules can be established by both layer and net class. If one trace is edited, the other trace in the pair auto-matically moves with it. Adjacent layerdifferential pair routing capabilities addanother valuable option for routing crit-ical signals on a dense PCB.Xtreme TechnologyPatented Xtreme design technologyenables up to 15 clients to operate on acommon database simultaneously tointeractively develop PCB layouts(XtremePCB) and perform complexmulti-process auto-routing (XtremeAR)while reducing cycle times by up to70%.Advanced InterconnectRoutingThe challenges and of advancedinterconnect are prevalent today withBGA, CSP, COB and DCA packagesincreasing board density. Build-up andmicrovia structures used in these boarddesigns further complicate routing.Board Station XE, powered byAutoActive technology, offers theleading technology for advanced inter-connect designs.Board Station XE supports the defi-nition of complex via structure rulesand the routing of microvia geometries,including comprehensive via-in-padrules. Via spans between any two layersare possible. By moving beyond tradi-tional laminate layer pairing, BoardStation XE facilitates the design ofbuild-up structures on laminate toenable escape patterns from dense, highpin count devices. Build-up areas typi-cally have a smaller clearance than thelaminate beneath them. Board StationXE can establish delay values andclearances per via span to address theseissues. Additionally, Board Station XEfeatures true 45 degree routing for BGAfanout and staggered connectors,enabling localized rule definition tofacilitate escape paths from dense areas. Board Station XE features powerful differential pair routing and net tuning capabilities for advanced high-speed design.MF-04-081025940-wTo learn more about how Board Station XE can improve your PCB layout process, call Mentor Graphics to schedule a complete product demonstra-tion or visit our web site at / for the latest product news.Copyright © 2007 Mentor Graphics Corporation.Mentor Graphics, Board Station and AutoActive are registered trademarks and Xtreme and FabLink are trademarks of Mentor Graphics Corporation.All other trademarks mentioned in this document are trademarks of their respective owners.Printed on RecycledPaperFabLink XE Pro IntegrationBoard Station XE is tightly inte-grated with the new FabLink XE Pro manufacturing data preparation tools FabLink XE Pro provides a stand alone panel creation and editing environment for creating manufacturing data at the panel level that operates on a panel design database. In addition, it provides additional board level functionality,including detailed data views, search-able PDF output, copper balancing,various data outputs and Gerber In/Drill In capabilities. Manufacturing Output Validation (MOV) quickly and easily identifies out of date manufacturing data compared to the design data.FabLink XE interacts with design data at three levels: ManufacturingPreparation, Manufacturing Output and Documentation.Operating System Requirements •Windows 2000 •Windows Server 2003•Windows XP Professional •Linux•Red Hat Enterprise 3(Server & Desktop) •Red Hat Enterprise 4(Server & Desktop) •Red Hat Enterprise 5(Server & Desktop)•SUSE Enterprise 9(Server & Desktop)•SUSE Enterprise 10 (Server & Desktop)•Sun Solaris 2.8, 2.9, 2.10, X86Corporate Headquarters Mentor Graphics Corporation 8005 SW Boeckman Road Wilsonville, OR 97070-7777Phone: 503.685.7000Fax: 503.685.1204Sales and Product Information Phone: 800.547.3000Silicon ValleyMentor Graphics Corporation 1001 Ridder Park DriveSan Jose, California 95131 USA Phone: 408.436.1500Fax: 408.436.1501North American Support Center Phone: 800.547.4303EuropeMentor Graphics Deutschland GmbH Arnulfstrasse 20180634 Munich GermanyPhone: +49.89.57096.0Fax: +49.89.57096.40Pacific RimMentor Graphics (Taiwan)Room 1603, 16FInternational Trade BuildingNo. 333, Section 1, Keelung Road Taipei, Taiwan, ROC Phone: 886.2.87252000Fax: 886.2.27576027JapanMentor Graphics Japan Co., Ltd.Gotenyama Hills7-35, Kita-Shinagawa 4-chome Shinagawa-Ku, Tokyo 140 JapanPhone: 81.3.5488.3033Fax: 81.3.5488.3021。
FTDI UMFT201XB、UMFT220XB 和 UMFT230XB 数据手册说明书
UMFT201XB, UMFT220XB and UMFT230XB DatasheetVersion 1.2Document Reference No.: FT_000506 Clearance No.: FTDI# 272 Future TechnologyDevices InternationalLtdDatasheetUMFT201XB, UMFT220XB,UMFT230XB BreakoutModulesUSB to I2C/UART/FT1248 breakout modules1IntroductionUMFT201XB, UMFT220XB, and UMFT230XB breakoutmodules utilize FTDI’s FT201XQ, FT220XQ, andFT230XQ chips, respectively, to convert USB to serial or parallel interfaces. . These modules support thefollowing popular interfaces:-UMFT201XB bridges from USB to I2C IC.-UMFT220XB bridges from USB to a user chosen, parallel bit interface, FTDI’s FT1248/SPI. Note: 2out of the 4 I/0 lines are available for this module.-UMFT230XB bridges from USB to UART IC. 1.1FeaturesThis module is a breakout board with a lowprofile. It converts USB2.0 Full-Speed to aserial interface and connects the serialsignals to a 2.54mm (0.1”) pitch 10pinfemale receptacle. The boards do not use aUSB connector, but instead the modulesplug directly into the USB host connectorand the pads of the PCB makes electricalcontact with the electrical contacts of theUSB connector.All serial interfaces on these modulesoperate at +3.3V voltage levels, however allI/Os are 5V tolerant.2Driver SupportRoyalty-Free VIRTUAL COM PORT (VCP) DRIVERS for:∙Windows 8 32,64-bit∙Windows 7 32,64-bit∙Windows Vista∙Windows XP 32,64-bit∙Windows XP Embedded∙Windows 4.2 , 5.0 and 6.0 ∙MAC OS OS-X∙Linux 3.0 and greater∙Android Royalty-Free D2XX Direct Drivers (USB Drivers + DLL S/W Interface):∙Windows 8 32,64-bit∙Windows 7 32,64-bit∙Windows Vista∙Windows XP 32,64-bit∙Windows XP Embedded∙Windows 4.2, 5.0 and 6.0∙MAC OS OS-X∙Linux 3.0 and greater∙AndroidThe drivers listed above are all available to download for free from . Various 3rd Party Drivers are also available for various other operating systems - visit for details.3Ordering InformationTable of Contents1Introduction (1)1.1Features (1)2Driver Support (1)3Ordering Information (2)4Signals and Configurations (4)4.1UMFT-XB Module Pin Outs (4)4.2Signal Descriptions (4)4.3UMFT201XB CN2 Signal Descriptions (5)4.4UMFT220XB CN2 Signal Descriptions (5)4.5UMFT230XB CN2 Signal Descriptions (6)4.6CBUS Signal Options (6)4.7Configuring the MTP ROM (7)5Module Dimensions (8)6IC Package Markings (8)7UMFT-XB-WE Module Wire Connections (9)7.1UMFT201XB-WE Wire Connections (9)7.2UMFT220XB-WE Wire Connections (10)7.3UMFT230XB-WE Wire Connections (10)8Module Circuit Schematics (11)8.1UMFT201XB Schematic (11)8.2UMFT220XB Schematic (11)8.3UMFT230XB Schematic (12)9Environmental Compliances (12)10Internal MTP ROM Configuration (13)11Contact Information (14)Appendix A - List of Figures and Tables (15)Appendix B: Revision History (16)4 Signals and ConfigurationsFor all three modules, CN1 connects directly to a USB host or HUB port, or can be connected to a USB extension cable. This connects the USB data signals, 5V USB Bus power and GND. When connecting these modules to a USB host or HUB the USB signal pads should be facing upwards, and when connecting to vertical connector the USB signal pad should be facing right. If the module is plugged in the wrong way, no contact will be made between PCB and HUB, no damage will occur from plugging the module in upside down.4.1UMFT-XB Module Pin Outs4.2 Signal Descriptions4.3UMFT201XB CN2 Signal Descriptions4.4UMFT220XB CN2 Signal Descriptions4.5UMFT230XB CN2 Signal Descriptions4.6CBUS Signal OptionsFor further information on CBUS options, please refer to the relevant x-chip datasheet.* PWREN# must be used with a 10kΩ resistor pull up.**When in USB suspend mode the outputs clocks are also suspended.***The number of CBUS pins available varies for the three different modules.4.7Configuring the MTP ROMThe IC on each of the modules contains an embedded MTP memory that can be used to specify the functions of the CBUS pins, the current drive on each signal pin, current limit for the USB bus and the descriptors of the device. For details on using the MTP ROM/EEPROM programming utility FT_PROG, please see the FT_PROG User Guide.When programming the MT memory please note:i)The Max Bus Power setting of the MTP ROM should specify the maximum current to be drawn fromthe USB host/hub when enumerated. For high-powered USB devices the current limit whenenumerated is between 100mA and 500mA, for low-powered USB devices the current limit is100mA.5Module DimensionsTolerance +/-0.1mm2.3Figure 5.1 UMFT-XB Module DimensionsThe UMFT201XB, UMFT220XB and UMFT230XB modules are mechanically identical. Figure 5.1 Uses UMFT230 to illustrate the mechanical details.6IC Package MarkingsThe date code format is YYXX where XX = 2 digit week number, YY = 2 digit year number. This is followed by the revision letter.The code XXXXXXX is the manufacturing LOT code.FTDIXXXXXXXXXXFT201XQ 51YYWW-D8127UMFT-XB-WE Module Wire Connections7.1 UMFT201XB-WE Wire ConnectionsBLACKBROWN RED ORANGE YELLOW GREEN GREY PURPLE BLUE WHITEFigure 7.1 UMFT201XB-WE Wire Connections (numbers refer to pad numbers on the PCB)Figure 6.1 illustrates the –WE product as a cable. This is only for illustration purposes. The wire ended product consists of individual wires – not a cable7.2 UMFT220XB-WE Wire ConnectionsBLACKBROWN RED ORANGE YELLOW GREEN GREY PURPLE BLUE WHITEFigure 7.2 UMFT220XB-WE Wire Connections (numbers refer to pad numbers on the PCB)Figure 6.2 illustrates the –WE product as a cable. This is only for illustration purposes. The wire ended product consists of individual wires – not a cable7.3UMFT230XB-WE Wire ConnectionsBLACKBROWN RED ORANGE YELLOW GREEN GREY PURPLE BLUE WHITEFigure 7.3 UMFT230XB-WE Wire Connections (numbers refer to pad numbers on the PCB)Figure 6.3 illustrates the –WE product as a cable. This is only for illustration purposes. The wire ended product consists of individual wires – not a cable8Module Circuit Schematics 8.1UMFT201XB SchematicFigure 8.1 UMFT201XB Circuit Schematic8.2UMFT220XB SchematicFigure 8.2 UMFT220XB Circuit Schematic8.3UMFT230XB SchematicFigure 8.3 UMFT230XB Circuit Schematic9Environmental CompliancesThe UMFT-XB modules exclusively use lead free components, and are fully compliant with European Union directive 2002/95/EC.10Internal MTP ROM ConfigurationFollowing a power-on reset or a USB reset the FT-X chips will scan its internal MTP ROM and read the USB configuration descriptors stored there. The default values programmed into the internal MTP ROM in the FT201/220/230XB modules is shown in Table 10.1.The internal MTP ROM in the FT-X chip can be programmed over USB using the utility program FT_PROG. FT_PROG can be downloaded from the . Users who do not have their own USB vendor ID but who would like to use a unique Product ID in their design can apply to FTDI for a free block of unique PIDs. Contact FTDI Support(*********************)forthisservice.11Contact InformationHead Office – Glasgow, UKUnit 1, 2 Seaward Place, Centurion Business Park Glasgow G41 1HHUnited KingdomTel: +44 (0) 141 429 2777Fax: +44 (0) 141 429 2758E-mail (Sales) *******************E-mail (Support) *********************E-mail (General Enquiries) ******************* Branch Office – Taipei, Taiwan2F, No. 516, Sec. 1, NeiHu RoadTaipei 114Taiwan , R.O.C.Tel: +886 (0) 2 8797 1330Fax: +886 (0) 2 8751 9737E-mail (Sales) **********************E-mail (Support) ************************ E-mail (General Enquiries) **********************Branch Office – Hillsboro, Oregon, USA 7130 SW Fir LoopTigard, OR 97223USATel: +1 (503) 547 0988Fax: +1 (503) 547 0987E-Mail (Sales) *********************E-Mail (Support) *********************** E-Mail (General Enquiries) *********************Branch Office – Shanghai, ChinaRoom 1103, No. 666 West Huaihai Road, Shanghai, 200052ChinaTel: +86 (0)21 6235 1596Fax: +86 (0)21 6235 1595E-mail (Sales) *********************E-mail (Support) *********************** E-mail (General Enquiries) *********************Web SiteDistributor and Sales RepresentativesPlease visit the Sales Network page of the FTDI Web site for the contact details of our distributor(s) and sales representative(s) in your country.System and equipment manufacturers and designers are responsible to ensure that their systems, and any Future Technology Devices International Ltd (FTDI) devices incorporated in their systems, meet all applicable safety, regulatory and system-level performance requirements. All application-related information in this document (including application descriptions, suggested FTDI devices and other materials) is provided for reference only. While FTDI has taken care to assure it is accurate, this information is subject to customer confirmation, and FTDI disclaims all liability for system designs and for any applications assistance provided by FTDI. Use of FTDI devices in life support and/or safety applications is entirely at the u ser’s risk, and the user agrees to defend, indemnify and hold harmless FTDI from any and all damages, claims, suits or expense resulting from such use. This document is subject to change without notice. No freedom to use patents or other intellectual property rights is implied by the publication of this document. Neither the whole nor any part of the information contained in, or the product described in this document, may be adapted or reproduced in any material or electronic form without the prior written consent of the copyright holder. Future Technology Devices International Ltd, Unit 1, 2 Seaward Place, Centurion Business Park, Glasgow G41 1HH, United Kingdom. Scotland Registered Company Number: SC136640Appendix A - List of Figures and TablesList of FiguresFigure 5.1 UMFT-XB Module Dimensions (8)Figure 7.1 UMFT201XB-WE Wire Connections (numbers refer to pad numbers on the PCB) (9)Figure 7.2 UMFT220XB-WE Wire Connections (numbers refer to pad numbers on the PCB) (10)Figure 7.3 UMFT230XB-WE Wire Connections (numbers refer to pad numbers on the PCB) (10)Figure 8.1 UMFT201XB Circuit Schematic (11)Figure 8.2 UMFT220XB Circuit Schematic (11)Figure 8.3 UMFT230XB Circuit Schematic (12)List of TablesTable 4.1 Module PinOut List (4)Table 4.2 CN1 PinOut Description (4)Table 4.3 I2C Module Pin Out Description (5)Table 4.4 FT1248 Module Pin Out Description (5)Table 4.5 UART Module Pin Out Description (6)Table 4.6 CBUS Configuration Control (7)Table 10.1 Default Internal MTP ROM Configuration (13)Appendix B: Revision HistoryDocument Title: UMFT201XB, UMFT220XB and UMFT230XBDocument Reference No.: FT_000506Clearance No.: FTDI# 272Product Page: /FT-X.htmDocument Feedback: Send FeedbackVersion 1.0 Initial Datasheet Created 09/02/12 Version 1.1 Updated Photos and added Window 8 to driver support list 31/01/13 Version 1.2 Updated -01 part number 03/07/2015。
Belling BL24C04F 4Kbits (512×8) 电子可编程可读存储器（EEPROM）
Features●Compatible with all I²C bidirectional datatransfer protocol●Memory array:– 4 Kbits (512bytes) of EEPROM–Page size: 16 bytes●Single supply voltage and high speed:–1MHZ–Random and sequential Read modes ●Write:–Byte Write within 3 ms–Page Write within 3 ms–Partial Page Writes Allowed●Write Protect Pin for Hardware Data Protection ●Schmitt Trigger, Filtered Inputs for NoiseSuppression●High-reliability–Endurance: 1 Million Write Cycles–Data Retention: 100 Years●Enhanced ESD/Latch-up protection–HBM 6000V●8-lead PDIP/SOP/TSSOP/ UDFN and TSOT23-5packagesDescription●The BL24C04F provides 2048 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 256 words of 8 bits each. ●The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential.Pin ConfigurationNC A1 A2 GNDVCCWPNCA1A2GNDNCA1A2GNDNCA1A2GNDVCCWPVCCWPVCCWP１２３４8765１２３４１２３４8765876512348765８-lead PDIP８-lead SOP８-lead TSSOP８-pad DFNBottem viewSCLSDASCLSDASCLSDASCLSDAWP VCCSCL SDAGND５４１２３5-lead TSOT23-5Pin DescriptionsTable 1Block DiagramFigure 1DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wire for the BL24C04F. Eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section).SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices.SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.WRITE PROTECT (WP):The BL24C04F has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as shown in the following Table 2.Table 2Functional Description1.Memory OrganizationBL24C04F, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing.2.Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 3).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The BL24C04F features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:1. Clock up to 9 cycles.2. Look for SDA high in each cycle while SCL is high.3. Create a start condition.BL24C04F 4Kbits (512×8)BL24C04F 4Kbits (512×8) Belling Proprietary Information. Unauthorized Photocopy and Duplication Prohibited4-20DATA STABLEDATA STABLEDATA CHANGESDASCLFigure 2. Data ValidityFigure 4. Output Acknowledge3.Device AddressingThe 4K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 5)MSB LSBFigure 5. Device AddressThe device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices.The 4K EEPROM uses A2 and A1 device address bits to allow as much as for devices on the same bus. These 2 bits must be compared to their corresponding hardwired input pins. The A2 and A1 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state.DATA SECURITY: The BL24C04F has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC.4.Write OperationsBYTE WRITE: A write operation requires an 9-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 7).MSB LSBFigure 6. ADDRESSSDA LINE STARTDEVICEADDRESSWRITEMSBLSBR/WACKADDRESSACKLSBACKLSBSTOPDATAFigure 7. Byte WritePAGE WRITE: The 4K EEPROM is capable of an 16-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven more data words. The EEPROM will respond with a "0" after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 8).ST A R TDEVICEADDRESSWRITEMSBLSBR/WACKADDRESSACKLSBACKLSBACKSTOPDATA(n)ACKDATA(n+1)DATA(n+1)SDALINEFigure 8. Page WriteThe data word address lower three bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten.ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue.5.Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ:The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 9).ST A R TDEVICEADDRESSREADMSBLSBR/WACKSTOPDATANOACKSDALINEFigure 9. Current Address ReadRANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 10)STA R TDEVICEADDRESSWRITEMSBLSBR/WACKNote.1*=DON'T CARE bitsADDRESSACKLSBSTOPDATA(n)DEVICEADDRESSSTARTREADACKNOACK DUMMY WRITESDALINEFigure 10. Random ReadSEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as theEEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 11).DEVICE ADDRESS READR/WACKACKACKACKSTOP DATA(n)DATA(n+1)DATA(n+2)DATA(n+x)NOACKSDALINEFigure 11. Sequential ReadElectrical CharacteristicsAbsolute Maximum Stress Ratings：●DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V●Input / Output Voltage . . . . . . . . . . . . . GND-0.3V to VCC+0.3V●Operating Ambient Temperature . . . . . . . . . . . . -40℃ to +85℃●Storage Temperature . . . . . . . . . . . . . . . . . . . . .-65℃ to +150℃●Electrostatic pulse (Human Body model) . . . . . . . . . . . . . 6000VComments:Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.DC Electrical CharacteristicsApplicable over recommended operating range from: TA = -40℃ to +85℃, VCC = +1.7V to +5.5V (unless otherwise noted)Pin CapacitanceApplicable over recommended operating range from TA = 25℃, f = 1.0 MHz, VCC = +1.7VAC Electrical CharacteristicsApplicable over recommended operating range from TA = -40℃ to +85℃, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)Bus TimingFigure 12. SCL: Serial Clock, SDA: Serial Data I/O Write Cycle TimingFigure 13. SCL: Serial Clock, SDA: Serial Data I/OPackage InformationPDIP Outline Dimensions1.This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.4. E and eA measured with the leads constrained to be perpendicular to datum.5. Pointed or rounded lead tips are preferred to ease insertion.6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).Notes:These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc.2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side.3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side.4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm.5. Dimension D and E1 to be determined at Datum Plane H.Figure 17TSOT23-5Figure 18Marking DiagramPDIPBL24C04FYYWW#ZZSSSSSPYY: yearWW :weekZZ: assembly houseSSSSS : Lot IDSOPBL24C04FSSSSSP SSSSS : Lot IDTSSOPBL24C04FSSSSS SSSSS : Lot IDTSOT23-524C04FSSSSSP SSSSS : Lot IDOrdering InformationRevision history。
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OXuPCI954_DS
External—Free ReleaseOxford Semiconductor, Inc.1900 McCarthy Boulevard, Suite 210 © Oxford Semiconductor, Inc. 2007F EATURES• Four 16C950 High performance UART channels • 8-bit Pass-through Local Bus (PCI Bridge )• IEEE1284 Compliant SPP/EPP/ECP parallel port (with external transceiver)• Efficient 32-bit, 33 MHz, multi-function target-only PCIcontroller, fully compliant to PCI Local Bus Specification 3.0 and PCI Power Management Specification 1.1 • Software compatible with OXmPCI954• UARTs fully software compatible with 16C550-type devices • UART operation up to 60 MHz via external clock source. Up to 20 MHz with the crystal oscillator• Baud rates up to 60 Mbps in external 1x clock mode and 15 Mbps in asynchronous mode• 128-byte deep FIFO per transmitter and receiver • Flexible clock prescaler, from 1 to 31.875• Automated in-band flow control using programmable Xon/Xoff in both directions•Automated out-of-band flow control using CTS#/RTS# and/or DSR#/DTR#• Programmable RS485 turnaround delay• Arbitrary trigger levels for receiver and transmitter FIFO interrupts and automatic in-band and out-of-band flow control• Infra-red (IrDA) receiver and transmitter operation • 9-bit data framing, as well as 5, 6, 7, and 8 bits • Detection of bad data in the receiver FIFO• Global Interrupt Status and readable FIFO levels to facilitate implementation of efficient device drivers.• Local registers to provide status/control of device functions • 11 multi-purpose I/O pins, which can be configured as input interrupt pins or ‘wake-up’• Auto-detection of a wide range of optional MICROWIRE TM compatible EEPROMs, to re-configure device parameters • Function access , to pre-configure each function prior to handover to generic device drivers • Operation via I/O or memory mapping• 3.3 V or 5 V operation (PCI Universal Voltage)• Extended operating temperature range: -40° C to 85° C •176-pin LQFP packageD ESCRIPTIONThe OXuPCI954 is a single chip solution for PCI-based serial and parallel expansion add-in cards. It is a dual function PCI device, where function 0 offers four ultra-high performance OX16C950 UARTs, and function 1 is configurable either as an 8-bit local bus or a bi-directional parallel port.Each UART channel in the OXuPCI954 is the fastest available PC-compatible UART, offering data rates up to 15 Mbps and 128-byte deep transmitter and receiver FIFOs. The deep FIFOs reduce CPU overhead and allow utilization of higher data rates. Each UART channel is software compatible with the widely used industry-standard 16C550 devices (and compatibles), as well as the OX16C95x family of high performance UARTs. In addition to increased performance and FIFO size, the UARTs also provide the full set of OX16C95x enhanced features including automated in-band flow control, readable FIFO levels, etc.To enhance device driver efficiency and reduce interrupt latency, internal UARTs have multi-port features such as shadowed FIFO fill levels, a global interrupt source register and Good-Data Status, readable in four adjacent DWORD registers visible to logical functions in I/O space and memory space.Expansion of serial ports beyond four channels is possible using the 8-bit pass-through Local Bus function. This provides a general address/data bus and interrupt capability to a discrete UART part, such as the Oxford SemiconductorOX16C954. Other controllers could be used to provide capabilities beyond additional UART ports. The addressable space provided by the Local Bus can be increased up to 256 bytes, and divided into four chip-select regions. This flexible expansion scheme caters for cards with up to 20 serial ports using external 16C950, 16C954 or compatible devices, or composite applications such as combined serial and parallel port expansion cards. Serial port cards with up to 20 ports (or with 4 serial ports and a parallel port) can be designed without redefining any device or timing parameters.The parallel port is an IEEE 1284 compliant SPP/EPP/ECP parallel port that fully supports the existing Centronics interface. The parallel port can be enabled in place of the local bus. A n external bus transceiver is required for 5V parallel port operation if device is 3.3V sourced.For full flexibility, all the default configuration register values can be overwritten using an optional M ICROWIRE compatibleserial EEPROM. This EEPROM can also be used to provide function access to pre-configure devices on the local bus/parallel port, prior to any PCI configuration accesses and before control is handed to (generic) device drivers.The OXuPCI954 can be used to replace the OXmPCI954 in a PCI application where quad UARTs and a local bus/parallel port functionality are required.OXuPCI954 DATA SHEETIntegrated High Performance Quad UARTs,8-bit Local Bus/Parallel Port,3.3 V and 5 V (Universal Voltage) PCI Interface .Improvements of the OXuPCI954 over Discrete SolutionsHigher degree of integrationThe OXuPCI954 device offers four internal 16C950 high-performance UARTs and an 8-bit local bus or abi-directional parallel port.Multi-function deviceThe OXuPCI954 is a multi-function device to enable users to load individual device drivers for the internal serial ports, drivers for the peripheral devices connected to the local bus or drivers for the internal parallel port.Quad Internal OX16C950 UARTsThe OXuPCI954 device contains four ultra-high performance UARTs, which can increase driver efficiency by using features such as the 128-byte deep transmitter and receiver FIFOs, flexible clock options, automatic flow control, programmable interrupt and flow control trigger levels and readable FIFO levels. Data rates are up to 60 Mbps.Improved access timingAccess to the internal UARTs require zero or one PCI wait state. A PCI read transaction from an internal UART can complete within five PCI clock cycles and a write transaction to an internal UART can complete within four PCI clock cycles. Reduces interrupt latencyThe OXuPCI954 device offers shadowed FIFO levels and Interrupt status registers on the internal UARTs and the MIO pins. This reduces the device driver interrupt latency. Power managementThe OXuPCI954 device complies with the PCI Power Management Specification 1.1 and the Microsoft Communications Device-class Power Management Specification 2.0 (2000). Both functions offer the extended capabilities for Power Management. This achieves significant power savings by enabling device drivers to power down the PCI functions. For function 0, this is through switching off the channel clock, in power state D3. Wake-up (PME# generation) can be requested by either functions. For function 0, this is via the RI# inputs of the UARTs in the power-state D3 or any modem line and SIN inputs of the UARTs in power-state D2. For function 1, this is via the MIO[2] input.Optional EEPROMThe OXuPCI954 device can be reconfigured from an external EEPROM to the end-user’s requirements. However, this is not required in many applications as the default values are sufficient for typical applications. An overrun detection mechanism built into the EEPROM controller prevents the PCI system from ‘hanging’ due to an incorrectly programmed EEPROM.R EVISION H ISTORYRevision Modification May 2007 First publication.Sep 2007 Feature revision, including removal of D3coldT ABLE OF C ONTENTS1OXuPCI954 Device Modes (6)2Block Diagram (7)3Pin Information—176-Pin LQFP (8)3.1Mode ‘0’ Quad UARTs + 8-bit Local Bus (8)3.1.1Mode ‘1’ : Quad UARTs + Parallel Port (9)3.2Pin Descriptions (10)4Configuration and Operation (16)5PCI Target Controller (17)5.1Operation (17)5.2Configuration Space (17)5.2.1PCI Configuration Space Register Map (18)5.3Accessing Logical Functions (20)5.3.1PCI Access to Internal UARTs (21)5.3.2PCI Access to 8-bit Local Bus (22)5.3.3PCI Access to Parallel Port (22)5.4Accessing Local Configuration Registers (23)5.4.1Local Configuration and Control Register ‘LCC’ (Offset 0x00) (23)5.4.2Multi-purpose I/O Configuration Register ‘MIC’ (Offset 0x04) (24)5.4.3Local Bus Timing Parameter Register 1 ‘LT1’ (Offset 0x08) (26)5.4.4Local Bus Timing Parameter Register 2 ‘LT2’ (Offset 0x0C) (27)5.4.5UART Receiver FIFO Levels ‘URL’ (Offset 0x10) (28)5.4.6UART Transmitter FIFO Levels ‘UTL’ (Offset 0x14) (29)5.4.7UART Interrupt Source Register ‘UIS’ (Offset 0x18) (29)5.4.8Global Interrupt Status and Control Register ‘GIS’ (Offset 0x1C) (30)5.5PCI Interrupts (31)5.6Power Management (32)5.6.1Power Management of Function 0 (32)5.6.2Power Management of Function 1 (33)5.6.3Universal Voltage (34)5.7Unique Bar Option – for Function 0 (35)6Internal OX16C950 UARTs (36)6.1Operation – Mode Selection (36)6.1.1450 Mode (36)6.1.2550 Mode (36)6.1.3Extended 550 Mode (36)6.1.4750 Mode (36)6.1.5650 Mode (36)6.1.6950 Mode (37)6.2Register Description Tables (38)6.3UART Reset Configuration (41)6.3.1Hardware Reset (41)6.3.2Software Reset (41)6.4Transmitter and Receiver FIFOs (42)6.4.1FIFO Control Register ‘FCR’ (42)6.5Line Control and Status (43)6.5.1False Start Bit Detection (43)6.5.2Line Control Register ‘LCR’ (43)6.5.3Line Status Register ‘LSR’ (44)6.6Interrupts and Sleep Mode (45)6.6.1Interrupt Enable Register ‘IER’ (45)6.6.2Interrupt Status Register ‘ISR’ (46)6.6.3Interrupt Description (46)6.6.4Sleep Mode (47)6.7Modem Interface (47)6.7.1Modem Control Register ‘MCR’ (47)6.7.2Modem Status Register ‘MSR’ (48)6.8Other Standard Registers (48)6.8.1Divisor Latch Registers ‘DLL and DLM’ (48)6.8.2Scratch Pad Register ‘SPR’ (48)6.9Automatic Flow Control (49)6.9.1Enhanced Features Register ‘EFR’ (49)6.9.2Special Character Detection (50)6.9.3Automatic In-band Flow Control (50)6.9.4Automatic Out-of-band Flow Control (50)6.10Baud Rate Generation (51)6.10.1General Operation (51)6.10.2Clock Prescaler Register ‘CPR’ (51)6.10.3Times Clock Register ‘TCR’ (51)6.10.4External 1x Clock Mode (53)6.10.5Crystal Oscillator Circuit (53)6.11Additional Features (54)6.11.1Additional Status Register ‘ASR’ (54)6.11.2FIFO Fill Levels ‘TFL and RFL’ (54)6.11.3Additional Control Register ‘ACR’ (54)6.11.4Transmitter Trigger Level ‘TTL’ (55)6.11.5Receiver Interrupt. Trigger Level ‘RTL’ (55)6.11.6Flow Control Levels ‘FCL’ and ‘FCH’ (56)6.11.7Device Identification Registers (56)6.11.8Clock Select Register ‘CKS’ (56)6.11.9Nine-bit Mode Register ‘NMR’ (57)6.11.10Modem Disable Mask ‘MDM’ (57)6.11.11Readable FCR ‘RFC’ (58)6.11.12Good-data Status Register ‘GDS’ (58)6.11.13Port Index Register ‘PIX’ (58)6.11.14Clock Alteration Register ‘CKA’ (58)6.11.15RS485 Delay Enable ‘RS485_DLYEN’ (58)6.11.16RS485 Delay Count ‘RS485_DLYCNT’ (59)7Local bus (60)7.1Overview (60)7.2Operation (60)7.3Configuration and Programming (61)8Bidirectional Parallel Port (62)8.1Operation and Mode Selection (62)8.1.1SPP Mode (62)8.1.2PS2 Mode (62)8.1.3EPP Mode (62)8.1.4ECP Mode (62)8.2Parallel Port Interrupt (63)8.3Register Description (63)8.3.1Parallel Port Data Register ‘PDR’ (64)8.3.2ECP FIFO Address / RLE (64)8.3.3Device Status Register ‘DSR’ (64)8.3.4Device Control Register ‘DCR’ (64)8.3.5EPP Address register ‘EPPA’ (65)8.3.6EPP Data Registers ‘EPPD1-4’ (65)8.3.7ECP Data FIFO (65)8.3.8Test FIFO (65)8.3.9Configuration A Register (65)8.3.10Configuration B Register (65)8.3.11Extended Control Register ‘ECR’ (65)9Serial EEPROM (66)9.1Specification (66)9.1.1Zone 0: Header (67)9.1.2Zone 1: Local Configuration Registers (68)9.1.3Zone 2: Identification Registers (69)9.1.4Zone 3: PCI Configuration Registers (69)9.1.5Zone 4: Power Management DATA (and DATA_SCALE Zone) (70)9.1.6Zone 5: Function Access (70)10Operating Conditions (72)10.1DC Electrical Characteristics (72)11AC Electrical Characteristics (76)11.1PCI Bus Timings (76)11.2Local Bus (77)11.3Serial Ports (79)12Timing Waveforms (80)13Package Information (95)13.1176-Pin LQFP (95)14Ordering Information (96)1OX U PCI954D EVICE M ODESThe OXuPCI954 supports two modes of operation. These modes are summarized in the following table.Device Mode Mode Pin Selection Functionality0 MODE = 0 Function 0 : Quad UARTs Function 1 : 8-bit local bus1 MODE = 1 Function 0 : Quad UARTs Function 1 : Parallel Port* The OXuPCI954 is not pin-compatible with the OX16PCI954 or the OXmPCI954, but is the same in all other aspects.2B LOCK D IAGRAMFIFOSELMODEAD[31:0]C/BE[3:0]#PCI_CLKFRAME#DEVSEL#IRDY#TRDY#STOP#PARPERR#IDSELRST#INTA#PME#XTLIXTLOUART_Clk_Out Local_Bus ClkEE_DIEE_CSEE_CKEE_DOSOUT[3:0]SIN[3:0]RTS[3:0]DTR[3:0]CTS[3:0]DSR[3:0]DCD[3:0]RI[3:0]MIO[10:0]PD[7:0]ACK#PEBUSYSLCTERR#SLIN#INIT#AFD#STB#LBA[7:0]LBD[7:0]LBCS[3:0]LBWR#LBRD#LBRSTDATA_DIR OXuPCI954 Block DiagramOSCDIS XTLSEL3P IN I NFORMATION—176-P IN LQFP 3.1Mode ‘0’ Quad UARTs + 8-bit Local Bus7 NC. Do not connect these pins:23, 40, 41, 136, 137, 138, 1393.1.1Mode ‘1’ : Quad UARTs + Parallel Port15 NC. Do not connect these pins:23, 40, 41, 74, 112, 113, 114, 115, 116, 117, 124, 136, 137, 138, 1393.2Pin DescriptionsFor the actual pinouts of the OXuPCI954 device (for the various modes), refer to the Section 3, Pin Information. The I/O direction key table is on page 15.PCI Interface – All ModesPin Dir1Name Description149, 150, 151, 154, 155,157, 158, 160, 164, 165,167, 168, 169, 170, 171,174, 13, 14, 15, 17, 18, 20,24, 25, 27, 28, 31, 32, 33,34, 35, 39P_I/O AD[31:0] Multiplexed PCI Address/Data bus161, 175, 12, 26 P_I C/BE[3:0]# PCI Command/Byte enable146 P_I CLK PCI system clock (33MHz)176 P_IFRAME#CycleFrame5 P_ODEVSEL#DeviceSelect1 P_IIRDY#Initiatorready2 P_OTRDY#Targetready6 P_O STOP# Target Stop request10 P_I/OPAR Parity8 P_OSERR#Systemerror7 P_I/OPERR#Parityerror163 P_I IDSEL Initialization device select144 P_I RST# PCI system reset142 P_ODINTA# PCIinterrupt147 P_OD PME# Power management eventSerial Port Pins – All ModesPin Dir1Name Description50 I FIFOSEL FIFO select. For backward compatibility with 16C550,16C650 and 16C750 devices the UARTs’ FIFO depth is 16when FIFOSEL is low. The FIFO size is increased to 128when FIFOSEL is high. The unlatched state of this pin isreadable by software. The FIFO size may also be set to 128by setting FCR[5] when LCR[7] is set, or by putting thedevice into Enhanced mode.82, 81, 63, 62 O(h)SOUT[3:0]IrDA_Out[3:0] These four pins are present in all modes but they can serve one of two functions, as follows:UART serial data outputs.UART IrDA data output when MCR[6] of the corresponding channel is set in Enhanced mode.91, 73, 72, 55I(h) I(h) SIN[3:0]IrDA_In[3:0]These four pins are present in all modes but they can serveone of two functions, as follows:UART serial data inputs.UART IrDA data input when IrDA mode is enabled (seeabove).Serial Port Pins – All ModesPin Dir1Name Description89, 76, 71, 57 I(h) DCD[3:0]# Active-low modem data-carrier-detect input 84, 79, 65, 60O(h) O(h) O(h) DTR[3:0]#485_En[3:0]Tx_Clk_Out[3:0]These four pins are present in all modes but they can serveone of three functions, as follows:Active-low modem data-terminal-ready output. If automatedDTR# flow control is enabled, the DTR# pin is asserted anddeasserted if the receiver FIFO reaches or falls below theprogrammed thresholds, respectively.In RS485 half-duplex mode, the DTR# pin may beprogrammed to reflect the state of the transmitter empty bitto automatically control the direction of the RS485transceiver buffer (see register ACR[4:3]).Transmitter 1x clock (baud rate generator output). Forisochronous applications, the 1x (or Nx) transmitter clockmay be asserted on the DTR# pins (see register CKS[5:4]).83, 80, 64, 61 O(h) RTS[3:0]# Active-low modem request-to-send output. If automatedRTS# flow control is enabled, the RTS# pin is deassertedand reasserted whenever the receiver FIFO reaches or fallsbelow the programmed thresholds, respectively.85, 78, 67, 59 I(h) CTS[3:0]# Active-low modem clear-to-send input. If automated CTS#flow control is enabled, upon deassertion of the CTS# pin,the transmitter will complete the current character and enterthe idle mode until the CTS# pin is reasserted. Note: any in-band flow control characters are transmitted regardless ofthe state of the CTS# pin.86, 77, 66, 58I(h) I(h) DSR[3:0]#Rx_Clk_In[3:0]These four pins are present in all modes but they can serveone of two functions, as follows:Active-low modem data-set-ready input. If automated DSR#flow control is enabled, upon deassertion of the DSR# pin,the transmitter will complete the current character and enterthe idle mode until the DSR# pin is reasserted. Note: any in-band flow control characters are transmitted regardless ofthe state of the DSR# pin.External receiver clock for isochronous applications. TheRx_Clk_In is selected when CKS[1:0] = ‘01’.90, 75, 70, 56 I(h)I(h) RI[3:0]#Tx_Clk_In[3:0]Active-low modem Ring-Indicator inputExternal transmitter clock. This clock can be used by thetransmitter (and indirectly by the receiver) when CKS[6]=’1’.Clock Interface Pins – All ModesPin Dir 1 Name Description49 I/OXTLOCrystal oscillator output when OSCDIS = ‘0’.External clock source input when OSCDIS = ‘1’48 I XTLI Crystal oscillator input when OSCDIS = ‘0’, up to 20MHz.N/C when OSCDIS = ‘1’45 I OSCDIS Oscillator disable.When 0, the internal crystal oscillator is enabled and a crystal needs to be attached to XTLI/XTLO.XTLSEL must be set according to the crystal frequency that is used (up to 20Mhz).When 1, the internal crystal oscillator is disabled and an external oscillator source (up to 60MHz) can be input to XTLO. XTLI is N/C and XTLSEL must be 0130 I XTLSEL Defines the frequency of the crystal attached to XTLI/XTLO(when OSCDIS = ‘0’)0 = 1 MHz – 12 MHz 1 = 12 MHz – 20 MHz8-bit Local Bus – Mode 0Pin Dir 1 Name Description 111O UART_CLK_Out Buffered crystal output. This clock can drive external UARTsconnected to the local bus. Can be enabled / disabled by software.123 O(h) LBRST Local bus active-high reset. 124 O LBRST# Local bus active-low reset. 104 O LBDOUT Local bus data out enable. This pin can be used by externaltransceivers; it is high when LBD[7:0] are in output mode and low when they are in input mode.74 O LBCLK Buffered PCI clock. Can be enabled / disabled by software. 114, 115, 116, 117 O(h) O(h) LBCS[3:0]# LBDS[3:0]# Local bus active-low Chip-Select (Intel mode).Local bus active-low Data-Strobe (Motorola mode).112 O O LBWR# LBRDWR# Local bus active-low write-strobe (Intel mode).Local bus Read-not-Write control (Motorola mode).113 O Z LBRD# Hi-Z Local bus active-low read-strobe (Intel mode).Permanent high impedance (Motorola mode).105, 106, 108, 109 118, 119, 120, 122 O(h) LBA[7:0] Local bus address signals. 96, 97, 98, 99 100, 101, 102, 103I/O(h) LBD[7:0] Local bus data signals.Parallel Port – Mode 1Pin Dir 1 NameDescription123 I(h) I(h) ACK#INTR#Acknowledge (SPP mode). ACK# is asserted (low) by the peripheral to indicate that a successful data transfer has taken place.Identical function to ACK# (EPP mode).122 I(h) PEPaper Empty. Activated by printer when it runs out of paper. 120 I(h) I(h) BUSYWAIT#Busy (SPP mode). BUSY is asserted (high) by the peripheral when it is not ready to accept data.Wait (EPP mode). Handshake signal for interlocked IEEE 1284 compliant EPP cycles.109 OD(h) O(h) SLIN#ADDRSTB#Select (SPP mode). Asserted by host to select the peripheral.Address strobe (EPP mode) provides address read and write strobe.119 I(h) SLCT Peripheral selected. Asserted by peripheral when selected. 118 I(h) ERR#Error. Held low by the peripheral during an error condition. 108 OD(h) O(h) INIT#INIT#Initialize (SPP mode). Commands the peripheral to initialize.Initialize (EPP mode). Identical function to SPP mode. 106 OD(h) O(h) AFD#DATASTB# Auto Feed (SPP mode, open-drain).Data strobe (EPP mode) provides data read and write strobe.105 OD(h) O(h) STB#WRITE#Strobe (SPP mode). Used by peripheral to latch data currently available on PD[7:0].Write (EPP mode). Indicates a write cycle when low and a read cycle when high . 96, 97, 98, 99, 100, 101, 102, 103I/O(h) PD[7:0] Parallel data bus.104OPDOUTParallel port data out enable. This pin should be used by external transceivers for 5 V signaling; it is high when PD[7:0] are in output mode and low when they are in input mode.Multi-purpose and External Interrupt Pins – All ModesPin Dir1Name DescriptionMODE0 1135 --135I/O(h)OMIO0NCMulti-purpose I/O 0. Can drive high or low, or assert a PCIinterrupt.Output Driving ‘0’. Can be left as a No-connect.134 134 134134I/O(h)MIO1NCMulti-purpose I/O 1. Can drive high or low, or assert a PCIinterrupt (as long as LCC[6:5] = “00”).Output Driving ‘0’ (when LCC[6:5] ≠ ‘00’)Can be left as a No-Connect.133 133 133133I/O(h)IMIO2PME_InMulti-purpose I/O 2. When LCC[7] = 0, this pin can drive highor low, or assert a PCI interrupt.Input power management event. When LCC[7] is set thisinput pin can assert a function 1 PME#.93, 94, 95, 125, 126, 127, 128, 132 I/O(h) MIO[10:3] Multi-purpose I/O pins. Can drive high or low, or assert a PCIinterrupt.EEPROM Pins – All ModesPin Dir1Name Description53 OEE_CKEEPROMclock.52 O EE_CS EEPROM active-high Chip Select.54 IU(h) EE_DI EEPROM data in, with internal pull-up.When the serial EEPROM is connected, this pin should bepulled up using a 1-10k resistor. When the EEPROM is notused the internal pull-up is sufficient.Pin to be connected to the external EEPROM’s EE_DO pin(if used).51 O EE_DO EEPROM data out.Pin to be connected to the external EEPROM’s EE_DI pin(if used).Table 1: Pin DescriptionsI/O Direction Key P_I PCI input 3.3 V Only P_O PCI output / PCITristates 3.3 V Only P_I/O PCI bi-directional 3.3 V Only P_OD PCI open drain 3.3 V OnlyI Input LVTTL level I(h) Input LVTTL level, 5 V tolerant IU(h) Input with internal pull-up LVTTL level, 5 V tolerant I/O(h) Bi-Directional LVTTL level, 5 V tolerantO Output Standard Output O(h) Output 5 V tolerant (High Voltage BI-Direct in output mode) OD Open drain Standard Open-drain Output OD(h) Open drain 5 V tolerant (High Voltage BI-Direct in open-drain mode) NC No connectG Ground V VoltageMiscellaneous PinsPin Dir 1 NameDescription44 IMODEMode selector Pin0 : Function 0 : Quad UART. Function 1 : 8-bit local bus.1 : Function 0 : Quad UART. Function 1 : Parallel port.Power and GroundPinType Name Description19, 42, 47, 69, 88, 107, 131, 148VVDDPower Supply (3.3 V)11, 22, 36, 140, 156, 162, 173 V VIOPCI I/O Universal VoltageDefines the (clamping) voltage of the PCI I/O Buffers.To be connected to the VIO pin of the PCI connector. 3, 4, 9, 16, 21, 29, 30, 37, 38, 43, 46, 68, 87, 92, 110, 121, 129, 141, 143, 145, 152, 153, 159, 166, 172G GNDPower Supply Ground (0 V)4C ONFIGURATION AND O PERATIONThe OXuPCI954 is a multi-function, target-only PCI device, compliant with the PCI Local Bus Specification, Revision 3.0 and the PCI Power Management Specification, Revision 1.1.The OXuPCI954 affords maximum configuration flexibility by treating the internal UARTs, the local bus and the parallel port as separate logical functions. Each function has its own configuration space and is therefore recognized and configured by the PCI BIOS separately. The functions used are configured by the Mode Selection Pin as shown in Section 1 OXuPCI954 Device Modes.The OXuPCI954 is configured by system start-up software during the bootstrap process that follows bus reset. The system scans the bus and reads the vendor and device identification codes from any devices it finds. It then loads device-driver software according to this information and configures the I/O, memory and interrupt resources. Device drivers can then access the functions at the assigned addresses in the usual fashion, with the improved data throughput provided by PCI.Each function operates as though it was a separate device. However there are a set of Local Configuration Registers that can be used to enable signals and interrupts, configure timings, and improve the efficiency of multi-port drivers. This architecture enables separate drivers to be installed for each function. Generic port drivers can be hooked to use the functions individually, or more efficient multi-port drivers can hook both functions, accessing the Local Configuration Registers from either.All registers default after reset to suitable values for typical applications such a 4/8 port serial, or combo 4-port serial/1-port parallel add-in cards. However, all identification, control and timing registers can be redefined using an optional serial EEPROM.5PCI T ARGET C ONTROLLER5.1OperationThe OXuPCI954 responds to the following PCI transactions:-•Configuration access: The OXuPCI954 responds to type 0 configuration reads and writes if the IDSELsignal is asserted and the bus address is selecting theconfiguration registers for function 0 or 1. The devicewill respond to the configuration transaction by asserting DEVSEL#. Data transfer then follows. Anyother configuration transaction will be ignored by theOXuPCI954.•I/O reads/writes: The address is compared with the addresses reserved in the I/O Base Address Registers(BARs). If the address falls within one of the assignedranges, the device will respond to the I/O transactionby asserting DEVSEL#. Data transfer follows thisaddress phase. For the UARTs and 8-bit local buscontroller, only byte accesses are possible. For I/Oaccesses to these regions, the controller comparesAD[1:0] with the byte-enable signals as defined in thePCI specification. The access is always completed;however if the correct BE signal is not present thetransaction will have no effect.•Memory reads/writes: These are treated in the same way as I/O transactions, except that the memoryranges are used. Memory access to single-byte regions is always expanded to DWORDs in theOXuPCI954. In other words, OXuPCI954 reserves aDWORD per byte in single-byte regions. The deviceallows the user to define the active byte lane usingLCC[4:3] so that in Big-Endian systems the hardwarecan swap the byte lane automatically. For Memorymapped access in single-byte regions, the OXuPCI954 compares the asserted byte-enable withthe selected byte-lane in LCC[4:3] and completes theoperation if a match occurs, otherwise the access willcomplete normally on the PCI bus, but it will have noeffect on either the internal UARTs or the local buscontroller.•All other cycles (64-bit, special cycles, reserved encoding etc.) are ignored.The OXuPCI954 will complete all transactions as disconnect-with-data, i.e. the device will assert the STOP# signal alongside TRDY#, to ensure that the Bus Master does not continue with a burst access. The exception to this is Retry, which will be signaled in response to any access while the OXuPCI954 is reading from the serial EEPROM.The OXuPCI954 performs medium-speed address decoding as defined by the PCI specification. It asserts the DEVSEL# bus signal two clocks after FRAME# is first sampled low on all bus transaction frames which address the chip. The internal UARTs are accessed with zero wait states inserted. Fast back-to-back transactions are supported by the OXuPCI954 as a target, so a bus master can perform faster sequences of write transactions to the UARTs or local bus when an inter-frame turn-around cycle is not required.The device supports any combination of byte-enables to the PCI Configuration Registers and the Local Configuration Registers. If a byte-enable is not asserted, that byte is unaffected by a write operation and undefined data is returned upon a read.The OXuPCI954 performs parity generation and checking on all PCI bus transactions as defined by the standard. Note this is entirely unrelated to serial data parity which is handled within the UART functional modules themselves. If a parity error occurs during the PCI bus address phase, the device will report the error in the standard way by asserting the SERR# bus signal. However if that address/command combination is decoded as a valid access, it will still complete the transaction as though the parity check was correct.The OXuPCI954 does not support any kind of caching or data buffering in addition to that already provided within the UARTs by the transmit and receive data FIFOs. In general, registers in the UARTs and on the local bus can not be pre-fetched because there may be side-effects on read.5.2Configuration SpaceThe OXuPCI954 is a dual-function device, where each logical function has its own configuration space. All required fields in the standard header are implemented, plus the Power Management Extended Capability register set. The format of the configuration space is shown in the following tables.In general, writes to any registers that are not implemented are ignored, and all reads from unimplemented registers return 0.。
Extech CD Regulated Power Supply Modelos 382203 y
Manual del usuarioFuente de poder CD regulada con tres salidas Modelos 382203 (Análogo) y 382213 (Digital)IntroducciónFelicitaciones por seleccionar la Fuente de poder CD regulado Modelos 382203 (análogo) o 382213 (digital) de Extech. Los modelos 382203 y 382213 son fuentes de poder reguladas de estado sólido y compactos, apropiadas para muchas aplicaciones incluyendo pruebas de banco, servicio de campo, equipo de telecomunicaciones y diversión.Descripción del medidor1. Pantallas LCD Voltaje y Corriente2. LED indicador de estado de límite de corriente3. Interruptor de encendido con LED de estado4. Terminales de salida 5V y 12V fijo5. Terminales de salida alimentación variable6. Perillas de ajuste de voltaje y corriente variableNota: El Modelo 382213 (escalas LCD) se muestra arriba. El Modelo 382203 (mostrado en la portada) usa escala análoga.Operación1. La Fuente de poder debe ser alimentada con voltaje de línea nominal (110V ó 220V) dentro de+ 5%.2. Antes de encender, retire todas las cargas conectadas y fije la perilla de ajuste de voltajetotalmente contrarreloj (salida 0V CD).3. Para operar la fuente de alimentación como fuente de corriente constante, la salida de corrientedebe fijarse entre 10% y 100% del valor nominal (3A). El indicador de limitación de corriente se iluminará al activarse el circuito limitador de corriente.4. Use las perillas para ajuste de corriente y voltaje para fijar las salidas variables de corriente yvoltaje respectivamente. Use las terminales de salida variable para conexiones.5. Para las salidas de 5VCD y 12VCD, use las terminales de salida fija.6. Las pantallas análoga o digital indicaran las salidas reales de corriente y voltaje.7. Mantenga libre de obstrucciones las rejillas de ventilación del medidor (arriba y lados) paraprevenir sobrecalentamiento.Especificaciones382203382213Indicador Análogo doble conescalas Pantalla LCD doble de 3dígitosSalida de voltaje, CD0-30VSalida de corriente, CD0 - 3 amperiosIndicador de límite decorrienteLED de estadoPrecisión ± 7% de la escala total ± 1% de la escala total + 2dígitosOndulación y Ruido< 5mVRegulación de línea< 0,05% + 10mVVoltaje fijo de salida5V / 0,5A (Continuo); 1A (máx.)12V / 0,5A (Continuo); 1A (máx.)Tensión110/220VCA 50/60Hz (conmutable) Dimensiones152 x 142 x 242mm(6 x 5,6 x 9,5") (WxHxD)Peso4,5 kg (10 lbs.)Copyright (c)2012 Extech Instruments Corporation (a FLIR company) Reservados todos los derechos, incluyendo el derecho de reproducción total o parcial en cualquier medi o.。
温度传感器设置参数指南说明书
Cód.ParámetroU.M.TipoMín.Máx.VALOR/2Estabilidad de la medida -C 1154/3Deceleración visualización sonda-C 0150/4Sonda virtual-C 01000/5Selección °C o °F (0=°C, 1=°F)flag C 010/6Punto decimal (0=si 1=no)flag C 011/tI Visualización sobre el display -C 171/tE Visualización en terminal externo-C 060/P Selección tipo de sonda -C 020/A2Configuración de la sonda 2-C 042/A3Configuración de la sonda 3-C 040/A4Configuración de la sonda 4-C 040/A5Configuración de la sonda 5-C 040/c1Calibración de la sonda 1°C/°F C -20200/c2Calibración de la sonda 2°C/°F C -20200/c3Calibración de la sonda 3°C/°F C -20200/c4Calibración de la sonda 4°C/°F C -20200/c5Calibración de la sonda 5°C/°FC-2020St Set point (punto de consigna)°C/°F F r1r2-23rd Diferencial regulador°C/°F F 0.120 3.0rn Zona neutra°C/°F C 0604rr Diferencia inverso para control con zona neutra°C/°F C 0,1202r1SET mínimo admitido °C/°F C -50r2-23r2SET máximo admitido °C/°F C r120020TABLA DE PARÁMETROSCAREL: PUIFI0006 (MEMBRANA / ARMARIOS BT)/ PARÁMETROS SONDAr PARÁMETROS REGULADORr3Modalidad de funcionamientoflag C 020r4Variación automática del SET POINT nocturno °C/°F C -20200r5Habilitación de la monitorización de la temp.flag C 011rt Intervalo de monitorización de la temperaturahoras F 09990rH Máxima temperatura leída °C/°F F 000rLMínima temperatura leída°C/°FFc0Ret. arr. comp. y vent. en el mom. del encendido min C 0151c1Tiempo mínimo entre encendidos sucesivos min C 0151c2Tiempo mínimo de OFF del compresor min C 0150c3Tiempo mínimo de ON del compresormin C 0150c4Arranque forzado min C 01000cc Duración del ciclo continuohoras C 0150c6Tiempo exclusión de alarma después del ciclo continuohoras C 02502c7Tiempo máximo de Pump-Downs C 09000c8Retr. arr. comp. después de la ap. de la válvula PD s C 0605c9Habilitación función de autoarranque con func. en PDflag C 010c10Selección Pump-Down de tiempo o presiónflag C 010c11Retraso 2º compresorsC250d0Tipo de desescarche (0=resis. 1=gas 2=agua 3=gas a tiempo)flag C 041dI Intervalo entre dos desescarches horas F 02503dt1Temperatura fin desescarche evaporador °C/°F F -5020020dt2Temperatura fin desescarche evaporador auxiliar°C/°F F -5020020dt3Temperatura fin desescarche sonda 3°C/°F F -502004dP1Duración máx. del desescarche evaporador min F 125030dP2Duración máx. del desescarche evap. auxiliar min F 125030d3Retraso de activación del desescarche min C 02500d4Desescarche a la conexión del equipo flag C 010d5Retraso del desescarche a la conexion min C 02500d6Bloqueo del display durante el desescarche -C 021ddTiempo de goteo después del desescarcheminF154c PARÁMETROS COMPRESORd PARÁMETROS DE DESESCARCHEd8Exclusión alarmas después del desescarche horas F 02501d8d Tiempo exclusión de alarma tras puerta abierta min C 02500d9Prioridad del desescarche frente protecciones compresorflag C 010d/1Visualización de la sonda de desescarche °C/°F F 000d/2Visualización de la sonda de desescarche °C/°F F 000dC Base de los tiempos para desescarche flag C 010dC1Base de los tiempos para retardo de alarmas flag C 010d10Tiempo de funcionamiento del compresor min C 02500d11Umbral de temperatura para tiempo de funcionamiento°C/°F C -2020 1.0d12Desescarches avanzados -C 030dn Duración nominal del desescarche -C 110065dHFactor proporcional variación de ‘dI’-C10050A0Diferencial alarmas y ventiladores°C/°F C 0.120 1.0A1Tipo de umbral ‘AL’ y ‘AH’flag C 010AL Umbral de alarma de baja temperatura °C/°F F -5020010AH Umbral de alarma de alta temperatura °C/°F F -5020010Ad Retraso alarma baja y alta temperatura min F 0250120A4Configuración de la entrada digital 1-C 0120A5Configuración de la entrada digital 2-C 0120A6Bloqueo del compresor por alarma externa min C 01000A7Retraso de detección alarma externa min C 02500A8Habilitación alarmas ‘Ed1’ y ‘Ed2’ flag C 010A9Configuración salida digital 3flag C 0140Ado Configuración modo luz puerta flag C 010Ac Alarma alta temperatura del condensador °C/°F C 0.020070.0AE Difer. de la alarma de alta temp. cond.°C/°F C 0.12010Acd Retraso alarma alta temp. del condensadormin C 02500AF Tiempo apagado con sensor de luzseg C 02500ALF Umbral de alarma antihielo °C/°F C -50200-5AdFRetardo alarma antihielosegC250A PARÁMETROS DE ALARMAF0Control ventiladorflag C 022F1Temperatura encendido ventilador °C/°F F -50200 5.0F2Ventilador OFF con compresor OFFflag C 011F3Ventiladores en desescarche flag C 011Fd Ventiladores apagados después del goteo flag F 0150F4Temperatura ventilador condensador OFF°C/°F C -5020040F5Diferencial ventilador condensador°C/°FC0,1205Pw Contraseña -C 020022H0Dirección serial -C 02071H1Funcionalidad del relé 4flag C 0133H2Deshabilitación teclado/Infrared flag C 061H3Código habilitación telecomando -C 02550H4Deshabilitación zumbador flag C 010H5Funcionalidad del relé 5-C 0133H6Bloqueo teclas -C 025532H7Selección tecladoflag C 010H8Luz o salida aux conmutada con control horario-C 010H9Variación set point con control horario-C 010HPr Perfil de impresión-C 0150Hdn Num conjuntos de parámetros predeterminados disponibles-C 060Hdh Desfase de resistencia antivaho°C/°F C -502000HrL Control remoto de estado de relé de luz principal -C 010HrA Control remoto de estado de relé AUX principal -C 010HSA Control remoto de alarmas de controladores en ud principal-C 010In Tipo de unidad-C 060s_cLrH Orden baja humedad relativa-C 010s_cAUX Orden activar AUX -C 010s_cLUX Orden activar luz -C 010s_cONOFFOrden controlador ON/OFF-C1F PARÁMETROS VENTILADOR (solo para el modelo C)H OTRAS PREDISPOSICIONES。
MPI TITAN RF Probe Selection Guide
MPI Probe Selection GuideWith a critical understanding of the numerous measurement challenges associated with today’s RF ap-plications, MPI Corporation has developed TITAN™ RF Probes, a product series specifically optimized for these complex applications centered upon the requirements of advanced RF customers.TITAN™ Probes provide the latest in technology and manufacturing advancements within the field of RF testing. They are derived from the technology transfer that accompanied the acquisition of Allstron, then significantly enhanced by MPI’s highly experienced RF testing team and subsequently produced utilizing MPI’s world class MEMS technology. Precisely manufactured, the TITAN™ Probes include matched 50 Ohm MEMS contact tips with improved probe electrical characteristics which allow the realization of unmat -ched calibration results over a wide frequency range. The patented protrusion tip design enables small passivation window bond pad probing, while significantly reducing probe skate thus providing the out -standing contact repeatability required in today’s extreme measurement environments. TITAN TM Probes with all their features are accompanied by a truly affordable price.The TITAN™ Probe series are available in single-ended and dual tip configurations, with pitch range from 50 micron to 1250 micron and frequencies from 26 GHz to 110 GHz. TITAN™ RF Probes are the ideal choice for on-wafer S-parameter measurements of RF, mm-wave devices and circuits up to 110 GHz as well as for the characterization of RF power devices requiring up to 10 Watts of continuous power. Finally, customers can benefit from both long product life and unbeatable cost of ownership which they have desired foryears.Unique design of the MEMS coplanar contacttip of the TITAN™ probe series.DC-needle-alike visibility of the contact point and the minimal paddamage due to the unique design of the tipAC2-2 Thru S11 Repeatability. Semi-Automated System.-100-80-60-40-200 S 11 E r r o r M a g n i t u d e (d B )Frequency (GHz)Another advantage of the TITAN™ probe is its superior contact repeatability, which is comparable with the entire system trace noise when measured on the semi-automated system and on gold contact pads.CROSSTALKCrosstalk of TITAN™ probes on the short and the bare ceramic open standard of 150 micron spacing compared to conventional 110 GHz probe technologies. Results are corrected by the multiline TRL calibration. All probes are of GSG configuration and 100 micron pitch.-80-60-40-200Crosstalk on Open. Multiline TRL Calibration.M a g (S21) (d B )Frequency (GHz)-80-60-40-200Crosstalk on Short. Multiline TRL Calibration.M a g (S21) (d B )Frequency (GHz)The maximal probe c ontac t repeatability error of the c alibrate S11-parameter of the AC2-2 thru standard by T110 probes. Semi-automated system. Ten contact circles.Cantilever needle material Ni alloy Body materialAl alloy Contact pressure @2 mils overtravel 20 g Lifetime, touchdowns> 1,000,000Ground and signal alignment error [1]± 3 µm [1]Planarity error [1] ± 3 µm [1]Contact footprint width < 30 µm Contact resistance on Au < 3 mΩThermal range-60 to 175 °CMechanical CharacteristicsAC2-2 Thru S21 Repeatability. Manual TS50 System.-100-80-60-40-200S 21 E r r o r M a g n i t u d e (d B )Frequency (GHz)MECHANICAL CHARACTERISTICSThe maximal probe c ontac t repeatability error of the c alibrate S21-parameter of the AC2-2 thru standard by T50 probes. Manual probe system TS50.26 GHZ PROBES FOR WIRELESS APPLICATIONSUnderstanding customer needs to reduce the cost of development and product testing for the high competitive wireless application market, MPI offers low-cost yet high-performance RF probes. The specifically developed SMA connector and its outstanding transmission of electro-magnetic waves through the probe design make these probes suitable for applications frequencies up to 26 GHz. The available pitch range is from 50 micron to 1250 micron with GS/SG and GSG probe tip configurations. TITAN™ 26 GHz probes are the ideal choice for measurement needs when developing components for WiFi, Bluetooth, and 3G/4G commercial wireless applications as well as for student education.Characteristic Impedance 50 ΩFrequency rangeDC to 26 GHz Insertion loss (GSG configuration)1< 0.4 dB Return loss (GSG configuration)1> 16 dB DC current ≤ 1 A DC voltage ≤ 100 V RF power, @10 GHz≤ 5 WTypical Electrical Characteristics26 GHz Probe Model: T26Connector SMAPitch range50 µm to 1250 µm Standard pitch step from 50 µm to 450 µm from 500 µm to 1250 µm25 µm step 50 µm stepAvailable for 90 µm pitch Tip configurations GSG, GS, SG Connector angleV-Style: 90-degree A-Style: 45-degreeMechanical CharacteristicsT26 probe, A-Style of the connectorTypical Electrical Characteristics: 26 GHz GSG probe, 250 micron pitchPROBES FOR DEVICE AND IC CHARACTERIZATION UP TO 110 GHZTITAN™ probes realize a unique combination of the micro-coaxial cable based probe technology and MEMS fabricated probe tip. A perfectly matched characteristic impedance of the coplanar probe tips and optimized signal transmission across the entire probe down to the pads of the device under test (DUT) result in excellent probe electrical characteristics. At the same time, the unique design of the probe tip provides minimal probe forward skate on any type of pad metallization material, therefo -re achieving accurate and repeatable measurement up to 110 GHz. TITAN™ probes are suitable for probing on small pads with long probe lifetime and low cost of ownership.The TITAN™ probe family contains dual probes for engineering and design debug of RF and mm-wave IC’s as well as high-end mm-wave range probes for S-parameter characterization up to 110 GHz for modeling of high-performance microwave devices.Characteristic Impedance 50 ΩFrequency rangeDC to 40 GHz Insertion loss (GSG configuration)1< 0.6 dB Return loss (GSG configuration)1> 18 dB DC current ≤ 1 A DC voltage ≤ 100 V RF power, @10 GHz≤ 5 WTypical Electrical Characteristics40 GHz Probe Model: T40Connector K (2.92 mm)Pitch range50 µm to 500 µmStandard pitch step For GSG configuration:from 50 µm to 450 µm from 500 µm to 800 µmFor GS/SG configuration:from 50 µm to 450 µm 25 µm step 50 µm stepAvailable for 90 µm pitch25 µm stepAvailable for 90/500 µm pitch Tip configurations GSG, GS, SG Connector angleV-Style: 90-degree A-Style: 45-degreeMechanical CharacteristicsTypical Electrical Characteristics: 40 GHz GSG probe, 150 micron pitchT40 probe, A-Style of the connectorCharacteristic Impedance50 ΩFrequency range DC to 50 GHz Insertion loss (GSG configuration)1< 0.6 dB Return loss (GSG configuration)1> 17 dBDC current≤ 1 ADC voltage≤ 100 VRF power, @10 GHz≤ 5 W Typical Electrical Characteristics Connector Q (2.4 mm)Pitch range50 µm to 250 µm Standard pitch stepFor GSG configuration: from 50 µm to 450 µm For GS/SG configuration: from 50 µm to 450 µm 25 µm stepAvailable for 90/500/550 µm pitch 25 µm stepAvailable for 90/500 µm pitchTip configurations GSG, GS, SG Connector angle V-Style: 90-degreeA-Style: 45-degreeMechanical CharacteristicsT50 probe, A-Style of the connectorTypical Electrical Characteristics: 50 GHz GSG probe, 150 micron pitchCharacteristic Impedance50 ΩFrequency range DC to 67 GHz Insertion loss (GSG configuration)1< 0.8 dB Return loss (GSG configuration)1> 16 dBDC current≤ 1 ADC voltage≤ 100 VRF power, @10 GHz≤ 5 W Typical Electrical Characteristics Connector V (1.85 mm)Pitch range50 µm to 250 µm Standard pitch stepFor GSG configuration: from 50 µm to 400 µm For GS/SG configuration: from 50 µm to 250 µm 25 µm step Available for 90 µm pitch25 µm step Available for 90 µm pitchTip configurations GSG Connector angle V-Style: 90-degreeA-Style: 45-degreeMechanical CharacteristicsT67 probe, A-Style of the connectorTypical Electrical Characteristics: 67 GHz GSG probe, 100 micron pitchCharacteristic Impedance 50 ΩFrequency rangeDC to 110 GHz Insertion loss (GSG configuration)1< 1.2 dB Return loss (GSG configuration)1> 14 dB DC current ≤ 1 A DC voltage ≤ 100 V RF power, @10 GHz≤ 5 WTypical Electrical CharacteristicsMechanical CharacteristicsTypical Electrical Characteristics: 110 GHz GSG probe, 100 micron pitchT110 probe, A-Style of the connectorCharacteristic impedance50 ΩFrequency range DC to 220 GHz Insertion loss (GSG configuration)1< 5 dB Connector end return loss(GSG configuration)1> 9 dBTip end return loss(GSG configuration)1> 13 dBDC current≤ 1.5 ADC voltage≤ 50 V Typical Electrical CharacteristicsConnector Broadband interface Pitch range50/75/90/100/125 µm Temperature range -40 ~ 150 ºC Contact width15 µmquadrant compatible(allowing corner pads)Yes recommended pad size20 µm x 20 µm recommended OT (overtravel)15 µmcontact resistance(on Al at 20 ºC using 15 µm OT)< 45 mΩlifetime touchdowns(on Al at 20 ºC using 15 µm OT)> 200,000Mechanical CharacteristicsT220 probe, broadband interface Typical Performance (at 20 ºC for 100 µm pitch)BODY DIMENSIONS PROBES Single-Ended V-StyleT220 GHz Probe1.161.1628.328437.455.6512.5527.73Single-Ended A-StyleCALIBRATION SUBSTRATESAC-series of calibration standard substrates offers up to 26 standard sets for wafer-level SOL T, LRM probe-tip cali -bration for GS/SG and GSG probes. Five coplanar lines provide the broadband reference multiline TRL calibration as well as accurate verification of conventional methods. Right-angled reciprocal elements are added to support the SOLR calibration of the system with the right-angled configuration of RF probes. A calibration substrate for wide-pitch probes is also available.Material Alumina Elements designCoplanarSupported calibration methods SOLT, LRM, SOLR, TRL and multiline TRL Thickness 635 µmSizeAC2-2 : 16.5 x 12.5 mm AC3 : 16.5 x 12.5 mm AC5 : 22.5 x 15 mm Effective velocity factor @20 GHz0.45Nominal line characteristic impedance @20 GHz 50 ΩNominal resistance of the load 50 ΩTypical load trimming accuracy error ± 0.3 %Open standardAu pads on substrate Calibration verification elements Yes Ruler scale 0 to 3 mm Ruler step size100 µmCalibration substrate AC2-2Probe Configuration GSGSupported probe pitch100 to 250 µm Number of SOL T standard groups 26Number of verification and calibration lines5Calibration substrate AC-3Probe Configuration GS/SG Supported probe pitch50 to 250 µm Number of SOL T standard groups 26Number of verification and calibration lines5Calibration substrate AC-5Probe Configuration GSG, GS/SG Supported probe pitch250 to 1250 µm Number of SOL T standard groups GSG : 7GS : 7SG : 7Open standardOn bare ceramic Number of verification and calibration linesGSG : 2GS : 1Typical characteristics of the coplanar line standard of AC2-2 calibration substrate measured using T110-GSG100 probes, and methods recommended by the National Institute of Standard and Technologies [2, 3].2468(d B /c m )F requency (G Hz)α-6-4-202I m a g (Z 0) ()F requency (G Hz)AC2-2 W#006 and T110A-GSG100Ω2.202.222.242.262.282.30 (u n i t l e s s )F requency (G Hz)β/βо4045505560R e a l (Z 0) ()F requency (G Hz)ΩTypical Electrical CharacteristicsMPI QAlibria® RF CALIBRATION SOFTWAREMPI QAlibria® RF calibration software has been designed to simplify complex and tedious RF system calibration tasks. By implementing a progressive disclosure methodology and realizing intuitive touch operation, QAlibria® provides crisp and clear guidance to the RF calibration process, minimizing con-figuration mistakes and helping to obtain accurate calibration results in fastest time. In addition, its concept of multiple GUI’s offers full access to all configuration settings and tweaks for advanced users. QAlibria® offers industry standard and advanced calibration methods. Furthermore, QAlibria® is integrated with the NIST StatistiCal™ calibration packages, ensuring easy access to the NIST mul-tiline TRL metrology-level calibration and uncertainty analysis.MPI Qalibria® supports a multi-language GUI, eliminating any evitable operation risks and inconvenience.SpecificationsRF AND MICROWAVE CABLESMPI offers an excellent selection of flexible cables and acces-sories for RF and mm-wave measurement applications forcomplete RF probe system integration.CablesHigh-quality cable assemblies with SMA and 3.5 mm connectorsprovide the best value for money, completing the entry-level RFsystems for measurement applications up to 26 GHz. Phase stab-le high-end flexible cable assemblies with high-precision 2.92, 2.4, 1.85 and 1 mm connectors guarantee high stability, accuracy and repeatability of the calibration and measurement for DC applications up to 110 GHz.MPI offers these cable assemblies in two standard lengths of 120 and 80 cm, matching the probe system’s footprint and the location of the VNA.Cables Ordering InformationMRC-18SMA-MF-80018 GHz SMA flex cable SMA (male) - SMA (female), 80 cmMRC-18SMA-MF-120018 GHz SMA flex cable SMA (male) - SMA (female), 120 cmMRC-26SMA-MF-80026 GHz SMA flex cable SMA (male) - SMA (female), 80 cmMRC-26SMA-MF-120026 GHz SMA flex cable SMA (male) - SMA (female), 120 cmMRC-40K-MF-80040 GHz flex cable 2.92 mm (K) connector, male-female, 80 cm longMRC-40K-MF-120040 GHz flex cable 2.92 mm (K) connector, male-female, 120 cm longMRC-50Q-MF-80050 GHz flex cable 2.4 mm (Q) connector, male-female , 80 cm longMRC-50Q-MF-120050 GHz flex cable 2.4 mm (Q) connector, male-female , 120 cm longMRC-67V-MF-80067 GHz flex cable 1.85 mm (V) connector, male-female, 80 cm longMRC-67V-MF-120067 GHz flex cable 1.85 mm (V) connector, male-female, 120 cm longMMC-40K-MF-80040 GHz precision flex cable 2.92 mm (K) connector, male-female, 80 cm long MMC-40K-MF-120040 GHz precision flex cable 2.92 mm (K) connector, male-female, 120 cm long MMC-50Q-MF-80050 GHz precision flex cable 2.4 mm (Q) connector, male-female , 80 cm long MMC-50Q-MF-120050 GHz precision flex cable 2.4 mm (Q) connector, male-female , 120 cm long MMC-67V-MF-80067 GHz precision flex cable 1.85 mm (V) connector, male-female, 80 cm long MMC-67V-MF-120067 GHz precision flex cable 1.85 mm (V) connector, male-female, 120 cm long MMC-110A-MF-250110 GHz precision flex cable 1 mm (A) connector, male-female, 25 cm longMPI Global PresenceDirect contact:Asia region: ****************************EMEA region: ******************************America region: ********************************MPI global presence: for your local support, please find the right contact here:/ast/support/local-support-worldwide© 2023 Copyright MPI Corporation. All rights reserved.[1] [2][3] REFERENCESParameter may vary depending upon tip configuration and pitch.R. B. Marks and D. F. Williams, "Characteristic impedance determination using propagation constant measu -rement," IEEE Microwave and Guided Wave Letters, vol. 1, pp. 141-143, June 1991.D. F. Williams and R. B. Marks, "Transmission line capacitance measurement," Microwave and Guided WaveLetters, IEEE, vol. 1, pp. 243-245, 1991.AdaptersHigh-In addition, high-quality RF and high-end mm-wave range adapters are offered to address challenges ofregular system reconfiguration and integration with different type of test instrumentation. MRA-NM-350F RF 11 GHz adapter N(male) - 3.5 (male), straight MRA-NM-350M RF 11 GHz adapter N(male) - 3.5 (female), straightMPA-350M-350F Precision 26 GHz adapter 3.5 mm (male) - 3.5 mm (female), straight MPA-350F-350F Precision 26 GHz adapter 3.5 mm (female) - 3.5 mm (female), straight MPA-350M-350M Precision 26 GHz adapter 3.5 mm (male) - 3.5 mm (male), straight MPA-292M-240F Precision 40 GHz adapter 2.92 mm (male) - 2.4 mm (female), straight MPA-292F-240M Precision 40 GHz adapter 2.92 mm (female) - 2.4 mm (male), straight MPA-292M-292F Precision 40 GHz adapter 2.92 mm (male) - 2.92 mm (female), straight MPA-292F-292F Precision 40 GHz adapter 2.92 mm (female) - 2.92 mm (female), straight MPA-292M-292M Precision 40 GHz adapter 2.92 mm (male) - 2.92 mm (male), straight MPA-240M-240F Precision 50 GHz adapter 2.4 mm (male) - 2.4 mm (female), straight MPA-240F-240F Precision 50 GHz adapter 2.4 mm (female) - 2.4 mm (female), straight MPA-240M-240M Precision 50 GHz adapter 2.4 mm (male) - 2.4 mm (male), straight MPA-185M-185F Precision 67 GHz adapter 1.85 mm (male) -1.85 mm (female), straight MPA-185F-185F Precision 67 GHz adapter 1.85 mm (female) -1.85 mm (female), straight MPA-185M-185M Precision 67 GHz adapter 1.85 mm (male) -1.85 mm (male), straight MPA-185M-100FPrecision 67 GHz adapter 1.85 mm (male) -1.00 mm (female), straightDisclaimer: TITAN Probe, QAlibria are trademarks of MPI Corporation, Taiwan. StatistiCal is a trademark of National Institute of Standards and Technology (NIST), USA. All other trademarks are the property of their respective owners. Data subject to change without notice.。
无线充电QI协议数据编码格式
QI无线充通信协议数据包格式解析QI通信数据格式编码：协议规定时钟信号的频率应该是Fclk=2（4%）KHZ,所以每一位的传输时间约500us,如图所示：、/tCLK」ONE.I ZERO.I ONEZERO」ONE I ONE」ZERO.I ZERO.I数据0：500us的高电平，或者500us的低电平数据1：250us高电平+250us低电平，或者250us低电平+250us高电平电源接收端（移动设备端）采用11位异步串行格式传输数据字节数据包结构：数据包格式由四部分组成：序言（序言最小为11位，最大为25位，序言全部为1），报头，消息和校验和。
说明：序言使功率发射器同步输入数据并准确检测报头的起始位。
报头、消息和校验和由三个或更多字节组成的序列组成。
PreambLe Header Message Che匚ksum上图为数据包格式功率发射端在下列情况可视为正确接收到了数据包1、功率发射器检测到至少4个前导位，后面跟着一个起始位。
2、功率发射器没有在组成数据包的任何字节中检测到奇偶校验错误（这包括头字节、消息字节和校验和字节）。
3、功率发射器检测到校验和字节的停止位。
4、功率发射器确定校验和字节是一致的。
说明：如果功率发射机没有正确接收到数据包，功率发射机应丢弃包，不使用其中包含的任何信息，（在ping阶段以及标识和配置阶段，这通常会导致超时，它使功率发射机消除功率信号）。
报头的组成：报头应该由一个表示包类型的字节组成。
此外，报头是隐式的提供包中包含的消息的大小。
数据包类型:消息的组成：消息的第一个字节B0,直接跟在报头后面。
校验和的组成：校验和由一个字节组成，可使功率发送端能够检查传输数据错误。
功率变送器的校验和计算如下：说明：其中C 表示计算的校验和，H 表示报头，B0,B1,…，Blast 表示消息。
如果计算的校验和。
信号强度包（0x01）的组成:该字段中的无符号整数值应该用于表示发射端和接收端的耦合程度，功率接收端应该在Ping 期间监视适当变量的值，如整流电压，开路电压（在输出断开开关处测量），接收到的电源（如果在数字Ping 过程中，整流电压被主动或被动箝位），该值应该随着耦合程度的增加而增加。
SLG7NT4192_DS_r011_05272013
GreenPAK 3™Power Good Generator LogicGeneral Description Array Silego SLG7NT4192 is a low power and small formdevice. The SoC is housed in a 2mm x 3mm TQFNpackage which is optimal for using with smalldevices.Features• Low Power Consumption• Pb-Free / RoHS Compliant• Halogen-Free• TQFN-20 PackageOutput Summary• 9 Outputs – Open DrainPower Good Generator Logic Block DiagramPower Good Generator Logic Pin ConfigurationPin # Pin Name Type Pin Description1 VDD PWR Supply Voltage2 BC_ACOK_DSW Input Digital in without Schmitt trigger3 DPWROK Output Open Drain4 BC_ACOK_EC_IN Output Open Drain5 SUS_VR_PWRGD Input Digital in without Schmitt trigger6 V1 Input Analog Input7 PWRBTN_N Input Digital in without Schmitt trigger8 VCCST_PWRGD Output Open Drain9 PWRBTN_DSW_N Output Open Drain10 V2 Input Analog Input11 GND GND Ground12 SYS_PWROK Output Open Drain13 V3 Input Analog input14 PWRBTN_EC_IN Output Open Drain15 VBAT_MON Input Analog input16 RSMRST_PWRGD_N Output Open Drain17 V3.3A_DSW_PWRGD Input Digital in without Schmitt trigger18 ALL_SYS_PWRGD Output Open Drain19 DDR_VCCIO_PWRGD Input Digital in without Schmitt trigger20 PCH_PWROK Output Open DrainOrdering InformationPart Number Package TypeSLG7NT4192V V=TQFN-20SLG7NT4192VTR TQFN-20 – Tape and Reel (3k units)Power Good Generator Logic Absolute Maximum ConditionsParameter Min. Max. UnitV HIGH to GND -0.3 7 VVoltage at input pins -0.3 7 VCurrent at input pin -1.0 1.0 mAStorage temperature range -65 150 °CJunction temperature -- 150 °CElectrical Characteristics(@ 25°C, unless otherwise stated)Symbol Parameter Condition/Note Min. Typ. Max. Unit V DD Supply Voltage 3.135 3.3 3.465 V T A Operating Temperature -40 25 85 °CI Q Quiescent Current Static inputs and outputs -- 85 -- μAV IH HIGH-Level Input Voltage Logic Input 1.8 -- -- -- V IL LOW-Level Input Voltage Logic Input -- -- 1.3 VI IH HIGH-Level Input Current Logic Input Pins; V IN =3.3V -1.0 -- 1.0 μAI IL LOW-Level Input Current Logic Input Pins; V IN =0V -1.0 -- 1.0 μAV OL LOW-Level Output Voltage Open Drain,I OL = 3 mA, 1X Driver-- 0.080 0.15 VI OL LOW-Level Output Current Open Drain, V OL = 0.4 V, 1X Driver 7.3 12 -- mAV O Maximal Voltage Applied toany PIN in High-ImpedanceState-- -- VDD VV ACMP0 Analog Comparator ReferenceVoltageIncluding ACMP0 voltage reference T.B.D. 950 T.B.D. mVV ACMP1 Analog Comparator ReferenceVoltageIncluding ACMP1 voltage reference T.B.D. 950 T.B.D. mVV ACMP2Analog Comparator ReferenceVoltageIncluding ACMP2 voltage reference T.B.D. 950 T.B.D. mVV ACMP3Analog Comparator ReferenceVoltageIncluding ACMP3 voltage reference T.B.D. 950 T.B.D. mVV HYST Analog Comparator HysteresisVoltageACMP0, ACMP1, ACMP2, ACMP3 T.B.D. 50 T.B.D. mVV OFFSET Analog Comparator OffsetVoltageACMP0, ACMP1, ACMP2, ACMP3 -- ±5 -- mVT DLY0Delay0 Time T.B.D. 2.5 T.B.D. msPower Good Generator LogicPower Good Generator Logic SLG7NT4192 Functionality WaveformsInputs:D0 – Pin #15 (VBAT_MON)D1 – Pin #17 (V3.3A_DSW_PWRGD)D2 – Pin #7 (PWRBTN_N)D3 – Pin #6 (V1)D4 – Pin #10 (V2)D5 – Pin #13 (V3)D6 – Pin #2 (BC_ACOK_DSW)Outputs:D7 – Pin #3 (DPWROK) with external 5kΩ pull-up resistorD8 – Pin #16 (RSMRST_PWRGD_N) with external 5kΩ pull-up resistorD9 – Pin #14 (PWRBTN_EC_IN) with external 5kΩ pull-up resistorD10 – Pin #9 (PWRBTN_DSW_N) with external 5kΩ pull-up resistorD11 – Pin #8 (VCCST_PWRGD) with external 5kΩ pull-up resistorD12 – Pin #18 (ALL_SYS_PWRGD) with external 5kΩ pull-up resistorD13 – Pin #12 (SYS_PWROK) with external 5kΩ pull-up resistorD14 – Pin #20 (PCH_PWROK) with external 5kΩ pull-up resistorD15 – Pin #4 (BC_ACOK_EC_IN) with external 5kΩ pull-up resistor1. Chip functionality (Pin5 (SUS_VR_PWRGD), Pin19 (DDR_VCCIO_PWRGD) are always HIGH)Power Good Generator LogicPackage Top MarkingDatasheet Revision Programming Code NumberPart CodeRevisionDate 0.11 0205/27/2013Power Good Generator Logic Package Drawing and Dimensions20 Lead TQFN PackageJEDEC MO-220, Variation WCEEPower Good Generator LogicTape and Reel SpecificationPackage Type# of PinsNominal Package Size (mm)Max Units Reel & Hub Size(mm) Trailer A Leader BPocket (mm) per reelper boxPockets Length (mm) Pockets Length (mm)WidthPitchTQFN 20L2x3mm 0.4P Green20 2x3x0.75 3000 3000 178/60 42 168 42 168 8 4Carrier Tape Drawing and DimensionsPackageTypePocketBTMLength (mm)PocketBTM Width(mm)PocketDepth(mm) Index HolePitch(mm)Pocket Pitch (mm) Index Hole Diameter (mm)Index Hole to Tape Edge (mm) Index Hole to Pocket Center (mm)Tape Width (mm) A0B0K0P0P1D0EFWTQFN 20L 2x3mm 0.4P Green2.253.3 1.1 4 4 1.55 1.75 3.5 8Refer to EIA-481 SpecificationsRecommended Reflow Soldering ProfilePlease see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 4.50 mm 3(nominal).More information can be found at .Power Good Generator Logic Datasheet Revision HistoryDate Version Change05/20/2013 0.1 New design05/27/2013 0.11 Updated designSLG7NT4192Power Good Generator LogicSLG7NT4192_DS_r011PreliminaryPage 11 11 Silego Website & SupportSilego Technology WebsiteSilego Technology provides online support via our website at /.This website is used as a means to make files and information easily available to customers.For more information regarding Silego Green products, please visit://///Products are also available for purchase directly from Silego at the Silego Online Store at /.Silego Technical SupportDatasheets and errata, application notes and example designs, user guides, and hardware support documents and the latest software releases are available at the Silego website or can be requested directly at info@ .For specific GreenPAK design or applications questions and support please send email requests to GreenPAK@Users of Silego products can receive assistance through several channels:Contact Your Local Sales RepresentativeCustomers can contact their local sales representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. More information regarding your local representative is available at the Silego website or send a request to info@Contact Silego DirectlySilego can be contacted directly via e-mail at info@ or user submission form, located at the following URL: /Other InformationThe latest Silego Technology press releases, listing of seminars and events, listings of worldwide Silego Technology offices and representatives are all available at /THIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. SILEGO TECHNOLOGY DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. SILEGO TECHNOLOGY RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN, FUNCTIONS AND RELIABILITY WITHOUT NOTICE.。
Remote Terminal Units - Connections and Settings说明
Remote Terminal Units - Connections and Settings Binary output 520BOD01Application, characteristics and technical data have to be taken from the hardware data sheet:520BOD01 Data sheet1KGT 150 864OperationThe binary output module 520BOD01 can be usedfor the control of 8 binary process signals using relay contacts. The allocation of an output signal to the processing functions can be done according to the rules of configuration.Processing functionsThe module 520BOD01 is able to process the following types of signals:•Single or double commands (SCO or DCO) with 1 or2 pole output without (1 out of n) check•Single or double commands (SCO or DCO) with 1.5 or 2 pole output with (1 out of n) check •Regulation step command (RCO), 1 or 2 pole •Digital setpoints commands, 8 Bit without strobe (DSO8)•Bitstring output, 1 or 8 Bit (BSO1 or BSO8)The micro-controller on the module processes alltime critical tasks of the parameterized processing functions. Moreover it carries out the interactive communication with the RTU I/O bus. All configuration data and processing parameters are loaded by the communication unit via the RTU I/O bus.In connection with an I/O adapter (e. g. 520ADD01)or the RTU520 communication unit the module is interfaced to the RTU520 I/O bus.The binary output unit can execute the following processing functions on the individual signal types:•Control of the command output duration Command monitoring functions:•monitoring of the output bit patterns by reading back the output state•switching voltage monitoring (24 V DC coil voltage) before and during output only together with (1 out of n) control module•command output duration monitoringDuring initialization and operation the module carries out a number of tests. If a fault occurs it is reported to the communication unit. All fault conditions impairing the function of the module are displayed as common fault signal by a red LED. A failure of the module isdetected by the communication unit.Parameter name Default Parameter location Command pulse length 1 sec SCO, DCO, RCO - PDPparametersvalue range: 0.1... 25.5 secFor additional information on these configuration parameters in RTUtil500 refer to RTU500 series function description - part 5: SCADA functions (1KGT 150 797).SettingsThe device has no switches or jumpers.SignalingLED BO1... BO8The 520BOD01 has 8 yellow LED’s on the front plate indicating the state of the outputs.The LEDs are ON for the time an output is active (pulse or persistent).LED ERRThe module monitors and checks the own functionality as well as the dialog via the I/O bus. Detected errors are indicated by the red LED ERR on the front plate and transmitted via the I/O bus to the communication unit (CMU). Additional diagnostic messages are available using the Web-Server on the CMU.The LED ERR indicates module errors or I/O bus errors:•module runs initialization procedure•module is performing a cold or warm start •module has detected a memory error (RAM or Flash)•micro-controller is faulty•no dialog via the I/O bus for at least 2 minutes. The module is not polled by the CMU.ConnectionsI/O bus connectionThe module is connected to the RTU I/O bus via the connectors X1 and X2.Power supply U EThe electronic circuits on the process side are supplied by an external 24 V DC voltage input U E. The voltage input U Eis connected at X3.Process connectionThe process will be connected to the screw terminals X4 (see Fig. 2).The 1 pole connection is described in Fig. 7.For a 2 pole connection two relays (e.g. for double commands R01 and R03, R02 and R04) of the binary output board 520BOD01 are used (see Fig. 8 and Fig. 9).For the (1 out of n) check along with560CIG10/560CID11 the connection is shown in Fig. 10. Safety instructionsDangerous process voltagesEnvironmental conditionsFigure 1: 520BOD01front plateFigure 2: 520BOD01 labelFigure 3: RTU520 DIN rail mounting - step 1Figure 4: RTU520 DIN rail mounting - step 2Figure 5: RTU520 DIN rail mounting - step 31Insert upper edge into DIN rail and push downwards2Push lower edge towards DIN rail and snap in the module 3 + 4:Shift one module connector intothe other starting from right toleft5 + 6:Mount end stops at the left andright sideFigure 6: 520BOD01 connection diagramFigure 7: 1 pole process connection, single commandFigure 8: 2 pole process connection, single command1K G T 150 865 V 003 1Figure 9: 2 pole process connection, double commandX3-1X3-2+-Figure 10: (1 out of n) check, 1.5 pole connection, single commandABB AGPower Grids P.O. Box 10 03 5168128 Mannheim, Germany Tel. +49 621 381-3000/remote-terminal-units We reserve the right to make technical changes or modify the contents of this document without prior notice. With regard to purchase orders, the agreed particulars shall prevail. ABB AG does not accept any responsibility whatsoever for potential errors or possible lack of information in this document.We reserve all rights in this document and in the subject matter and illustrations contained therein. Any reproduction, disclosure to third parties or utilization of its contents – in whole or in parts – is forbidden without prior written consent of ABB AG. Copyright© 2019 ABB AG All rights reserved。
AT45DB021B-SI中文资料
1 Features•Single2.7V-3.6V Supply•Serial Peripheral Interface(SPI)Compatible•Page Program Operation–Single CycleReprogram(Erase and Program)–1024Pages(264Bytes/Page)Main Memory•Supports Page and Block Erase Operations•Two264-byte SRAM Data Buffers–Allows Receiving of Datawhile Reprogramming of Nonvolatile Memory•Continuous Read Capability through Entire Array–Ideal for Code Shadowing Applications•Low Power Dissipation–4mA Active Read Current Typical–2µA CMOS Standby Current Typical•20MHz Max Clock Frequency•Hardware Data Protection Feature•100%Compatible to AT45DB021and AT45DB021A• 5.0V-tolerant Inputs:SI,SCK,CS,RESET and WP Pins•Commercial and Industrial Temperature RangesDescriptionThe AT45DB021B is a2.7-volt only,serial interface Flash memory ideally suited fora wide variety of digital voice-,image-,program code-and data-storage applications.Its2,162,688bits of memory are organized as1024pages of264bytes each.In addi-tion to the main memory,the AT45DB021B also contains two SRAM data buffersof264bytes each.The buffers allow receiving of data while a page in the main mem-ory is being reprogrammed,as well as reading or writing a continuous data stream.Pin ConfigurationsCBGA Top Viewthrough PackageTSOP T op ViewT ype128-SOIC8-SOIC2AT45DB021B1937F –DFLSH –10/02EEPROM emulation (bit or byte alterability)is easily handled with a self-contained three step Read-Modify-Write operation.Unlike conventional Flash memories that are accessed randomly with multiple address lines and a parallel interface,the DataFlash uses a SPI serial interface to sequentially access its data.DataFlash supports SPI mode 0and mode 3.The simple serial interface facilitates hardware layout,increases system reliability,minimizes switching noise,and reduces package size and active pin count.The device is optimized for use in many commercial and industrial applications where high density,low pin count,low voltage,and low power are essential.The device oper-ates at clock frequencies up to 20MHz with a typical active read current consumption of 4mA.To allow for simple in-system reprogrammability,the AT45DB021B does not require high input voltages for programming.The device operates from a single power supply,2.7V to 3.6V,for both the program and read operations.The AT45DB021B is enabled through the chip select pin (CS)and accessed via a three-wire interface consisting of the Serial Input (SI),Serial Output (SO),and the Serial Clock (SCK).All programming cycles are self-timed,and no separate erase cycle is required before programming.When the device is shipped from Atmel,the most significant page of the memory array may not be erased.In other words,the contents of the last page may not be filled with FFH.Block DiagramMemory ArrayTo provide optimal flexibility,the memory array of the AT45DB021B is divided into three levels of granularity comprised of sectors,blocks and pages.The Memory Architecture Diagram illustrates the breakdown of each level and details the number of pages per sector and block.All program operations to the DataFlash occur on a page-by-page basis;however,the optional erase operations can be performed at the block or page level.3AT45DB021B1937F –DFLSH –10/02Memory Architecture DiagramDevice OperationThe device operation is controlled by instructions from the host processor.The list of instructions and their associated opcodes are contained in Tables 1through 4(pages 10and 11).A valid instruction starts with the falling edge of CS followed by the appropriate 8-bit opcode and the desired buffer or main memory address location.While the CS pin is low,toggling the SCK pin controls the loading of the opcode and the desired buffer or main memory address location through the SI (serial input)pin.All instructions,addresses,and data are transferred with the most significant bit (MSB)first.Buffer addressing is referenced in the datasheet using the terminology BFA8-BFA0to denote the nine address bits required to designate a byte address within a buffer.Main memory addressing is referenced using the terminology PA9-PA0and BA8-BA0where PA9-PA0denotes the 10address bits required to designate a page address and BA8-BA0denotes the nine address bits required to designate a byte address within the page.Read CommandsBy specifying the appropriate opcode,data can be read from the main memory or from either one of the two data buffers.The DataFlash supports two categories of read modes in relation to the SCK signal.The differences between the modes are in respect to the inactive state of the SCK signal as well as which clock cycle data will begin to be output.The two categories,which are comprised of four modes total,are defined as Inactive Clock Polarity Low or Inactive Clock Polarity High and SPI Mode 0or SPI Mode 3.A separate opcode (refer to Table 1on page 10for a complete list)is used to select which category will be used for reading.Please refer to the “Detailed Bit-level Read Timing ”diagrams in this datasheet for details on the clock cycle sequences for each mode.CONTINUOUS ARRAY READ:By supplying an initial starting address for the main memory array,the Continuous Array Read command can be utilized to sequentially read a continuous stream of data from the device by simply providing a clock signal;no additional addressing information or control signals need to be provided.The DataFlash incorporates an internal address counter that will automatically increment on every clock4AT45DB021B1937F –DFLSH –10/02cycle,allowing one continuous read operation without the need of additional address sequences.To perform a continuous read,an opcode of 68H or E8H must be clocked into the device followed by 24address bits and 32don ’t care bits.The first five bits of the 24-bit address sequence are reserved for upward and downward compatibility to larger and smaller density devices (see Notes under “Command Sequence for Read/Write Operations ”diagram).The next 10address bits (PA9-PA0)specify which page of the main memory array to read,and the last nine bits (BA8-BA0)of the 24-bit address sequence specify the starting byte address within the page.The 32don ’t care bits that follow the 24address bits are needed to initialize the read operation.Following the 32don ’t care bits,additional clock pulses on the SCK pin will result in serial data being output on the SO (serial output)pin.The CS pin must remain low during the loading of the opcode,the address bits,the don ’t care bits,and the reading of data.When the end of a page in main memory is reached during a Continuous Array Read,the device will continue reading at the beginning of the next page with no delays incurred during the page boundary crossover (the crossover from the end of one page to the beginning of the next page).When the last bit in the main memory array has been read,the device will continue reading back at the begin-ning of the first page of memory.As with crossing over page boundaries,no delays will be incurred when wrapping around from the end of the array to the beginning of the array.A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.The maximum SCK frequency allowable for the Continuous Array Read is defined by the f CAR specification.The Continuous Array Read bypasses both data buff-ers and leaves the contents of the buffers unchanged.MAIN MEMORY PAGE READ:A Main Memory Page Read allows the user to read data directly from any one of the 1024pages in the main memory,bypassing both of the data buffers and leaving the contents of the buffers unchanged.To start a page read,an opcode of 52H or D2H must be clocked into the device followed by 24address bits and 32don ’t care bits.The first five bits of the 24-bit address sequence are reserved bits,the next 10address bits (PA9-PA0)specify the page address,and the next nine address bits (BA8-BA0)specify the starting byte address within the page.The 32don ’t care bits which follow the 24address bits are sent to initialize the read operation.Following the 32don ’t care bits,additional pulses on SCK result in serial data being output on the SO (serial output)pin.The CS pin must remain low during the loading of the opcode,the address bits,the don ’t care bits and the reading of data.When the end of a page in main memory is reached during a Main Memory Page Read,the device will continue reading at the beginning of the same page.A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.BUFFER READ:Data can be read from either one of the two buffers,using different opcodes to specify which buffer to read from.An opcode of 54H or D4H is used to read data from buffer 1,and an opcode of 56H or D6H is used to read data from buffer 2.To perform a Buffer Read,the eight bits of the opcode must be followed by 15don ’t care bits,nine address bits,and eight don ’t care bits.Since the buffer size is 264-bytes,nine address bits (BFA8-BFA0)are required to specify the first byte of data to be read from the buffer.The CS pin must remain low during the loading of the opcode,the address bits,the don ’t care bits and the reading of data.When the end of a buffer is reached,the device will continue reading back at the beginning of the buffer.A low-to-high transition on the CS pin will terminate the read operation and tri-state the SO pin.5AT45DB021B1937F –DFLSH –10/02STATUS REGISTER READ:The status register can be used to determine the device ’s ready/busy status,the result of a Main Memory Page to Buffer Compare operation,or the device density.To read the status register,an opcode of 57H or D7H must be loaded into the device.After the last bit of the opcode is shifted in,the eight bits of the status register,starting with the MSB (bit 7),will be shifted out on the SO pin during the next eight clock cycles.The five most-significant bits of the status register will contain device information,while the remaining three least-significant bits are reserved for future use and will have undefined values.After bit 0of the status register has been shifted out,the sequence will repeat itself (as long as CS remains low and SCK is being tog-gled)starting again with bit 7.The data in the status register is constantly updated,so each repeating sequence will output new data.Ready/Busy status is indicated using bit 7of the status register.If bit 7is a 1,then the device is not busy and is ready to accept the next command.If bit 7is a 0,then the device is in a busy state.The user can continuously poll bit 7of the status register by stopping SCK at a low level once bit 7has been output.The status of bit 7will continue to be output on the SO pin,and once the device is no longer busy,the state of SO will change from 0to 1.There are eight operations that can cause the device to be in a busy state:Main Memory Page to Buffer Transfer,Main Memory Page to Buffer Compare,Buffer to Main Memory Page Program with Built-in Erase,Buffer to Main Memory Page Program without Built-in Erase,Page Erase,Block Erase,Main Memory Page Program,and Auto Page Rewrite.The result of the most recent Main Memory Page to Buffer Compare operation is indi-cated using bit 6of the status register.If bit 6is a 0,then the data in the main memory page matches the data in the buffer.If bit 6is a 1,then at least one bit of the data in the main memory page does not match the data in the buffer.The device density is indicated using bits 5,4,3and 2of the status register.For the AT45DB021B,the four bits are 0,1,0and 1.The decimal value of these four binary bits does not equate to the device density;the four bits represent a combinational code relating to differing densities of Serial DataFlash devices,allowing a total of sixteen dif-ferent density configurations.Program and Erase CommandsBUFFER WRITE:Data can be shifted in from the SI pin into either buffer 1or buffer 2.To load data into either buffer,an 8-bit opcode,84H for buffer 1or 87H for buffer 2,must be followed by 15don't care bits and nine address bits (BFA8-BFA0).The nine address bits specify the first byte in the buffer to be written.The data is entered following the address bits.If the end of the data buffer is reached,the device will wrap around back to the beginning of the buffer.Data will continue to be loaded into the buffer until a low-to-high transition is detected on the CS pin.BUFFER TO MAIN MEMORY PAGE PROGRAM WITH BUILT -IN ERASE:Data written into either buffer 1or buffer 2can be programmed into the main memory.To start the operation,an 8-bit opcode (83H for buffer 1or 86H for buffer 2)must be followed by the five reserved bits,10address bits (PA9-PA0)that specify the page in the main memory to be written,and nine additional don ’t care bits.When a low-to-high transition occurs on the CS pin,the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory.Both the erase and the programming of the page are internally self-timed and should takeStatus Register Format6AT45DB021B1937F –DFLSH –10/02place in a maximum time of t EP .During this time,the status register will indicate that the part is busy.BUFFER TO MAIN MEMORY PAGE PROGRAM WITHOUT BUILT-IN ERASE:A previ-ously erased page within main memory can be programmed with the contents of either buffer 1or buffer 2.To start the operation,an 8-bit opcode (88H for buffer 1or 89H for buffer 2)must be followed by the five reserved bits,10address bits (PA9-PA0)that specify the page in the main memory to be written,and nine additional don ’t care bits.When a low-to-high transition occurs on the CS pin,the part will program the data stored in the buffer into the specified page in the main memory.It is necessary that the page in main memory that is being programmed has been previously erased.The programming of the page is internally self-timed and should take place in a maximum time of t P .Dur-ing this time,the status register will indicate that the part is busy.Successive page programming operations without doing a page erase are not recom-mended.In other words,changing bytes within a page from a “1”to a “0”during multiple page programming operations without erasing that page is not recommended.PAGE ERASE:The optional Page Erase command can be used to individually erase any page in the main memory array allowing the Buffer to Main Memory Page Program without Built-in Erase command to be utilized at a later time.To perform a Page Erase,an opcode of 81H must be loaded into the device,followed by five reserved bits,ten address bits (PA9-PA0),and nine don ’t care bits.The ten address bits are used to spec-ify which page of the memory array is to be erased.When a low-to-high transition occurs on the CS pin,the part will erase the selected page to 1s.The erase operation is inter-nally self-timed and should take place in a maximum time of t PE .During this time,the status register will indicate that the part is busy.BLOCK ERASE:A block of eight pages can be erased at one time allowing the Buffer to Main Memory Page Program without Built-in Erase command to be utilized to reduce programming times when writing large amounts of data to the device.To perform a Block Erase,an opcode of 50H must be loaded into the device,followed by five reserved bits,seven address bits (PA9-PA3),and 12don ’t care bits.The seven address bits are used to specify which block of eight pages is to be erased.When a low-to-high transition occurs on the CS pin,the part will erase the selected block of eight pages to 1s.The erase operation is internally self-timed and should take place in a maximum time of t BE .During this time,the status register will indicate that the part is busy.Block Erase AddressingPA9PA8PA7PA6PA5PA4PA3PA2PA1PA0Block 0000000X X X 00000001X X X 10000010X X X 20000011X X X 3•••••••••••••••••••••••••••••••••1111100X X X 1241111101X X X 1251111110X X X 1261111111XXX1277AT45DB021B1937F –DFLSH –10/02MAIN MEMORY PAGE PROGRAM THROUGH BUFFER:This operation is a combina-tion of the Buffer Write and Buffer to Main Memory Page Program with Built-in Erase operations.Data is first shifted into buffer 1or buffer 2from the SI pin and then pro-grammed into a specified page in the main memory.To initiate the operation,an 8-bit opcode (82H for buffer 1or 85H for buffer 2)must be followed by the five reserved bits and 20address bits.The 10most-significant address bits (PA9-PA0)select the page in the main memory where data is to be written,and the next nine address bits (BFA8-BFA0)select the first byte in the buffer to be written.After all address bits are shifted in,the part will take data from the SI pin and store it in one of the data buffers.If the end of the buffer is reached,the device will wrap around back to the beginning of the buffer.When there is a low-to-high transition on the CS pin,the part will first erase the selected page in main memory to all 1s and then program the data stored in the buffer into the specified page in the main memory.Both the erase and the programming of the page are internally self-timed and should take place in a maximum of time t EP .During this time,the status register will indicate that the part is busy.Additional CommandsMAIN MEMORY PAGE TO BUFFER TRANSFER:A page of data can be transferred from the main memory to either buffer 1or buffer 2.To start the operation,an 8-bit opcode,53H for buffer 1and 55H for buffer 2,must be followed by the five reserved bits,10address bits (PA9-PA0)which specify the page in main memory that is to be trans-ferred,and nine don ’t care bits.The CS pin must be low while toggling the SCK pin to load the opcode,the address bits,and the don ’t care bits from the SI pin.The transfer of the page of data from the main memory to the buffer will begin when the CS pin transi-tions from a low to a high state.During the transfer of a page of data (t XFR ),the status register can be read to determine whether the transfer has been completed or not.MAIN MEMORY PAGE TO BUFFER COMPARE:A page of data in main memory can be compared to the data in buffer 1or buffer 2.To initiate the operation,an 8-bit opcode (60H for buffer 1and 61H for buffer 2)must be followed by 24address bits consisting of the five reserved bits,10address bits (PA9-PA0)which specify the page in the main memory that is to be compared to the buffer,and nine don ’t care bits.The CS pin must be low while toggling the SCK pin to load the opcode,the address bits and the don ’t care bits from the SI pin.On the low-to-high transition of the CS pin,the 264bytes in the selected main memory page will be compared with the 264bytes in buffer 1or buffer 2.During this time (t XFR ),the status register will indicate that the part is busy.On comple-tion of the compare operation,bit 6of the status register is updated with the result of the compare.AUTO PAGE REWRITE:This mode is needed only if multiple bytes within a page or multiple pages of data are modified in a random fashion.This mode is a combination of two operations:Main Memory Page to Buffer Transfer and Buffer to Main Memory Page Program with Built-in Erase.A page of data is first transferred from the main memory to buffer 1or buffer 2,and then the same data (from buffer 1or buffer 2)is programmed back into its original page of main memory.To start the rewrite operation,an 8-bit opcode (58H for buffer 1or 59H for buffer 2)must be followed by the five reserved bits,10address bits (PA9-PA0)that specify the page in main memory to be rewritten,and nine additional don ’t care bits.When a low-to-high transition occurs on the CS pin,the part will first transfer data from the page in main memory to a buffer and then program the data from the buffer back into same page of main memory.The operation is inter-nally self-timed and should take place in a maximum time of t EP .During this time,the status register will indicate that the part is busy.8AT45DB021B1937F –DFLSH –10/02If a sector is programmed or reprogrammed sequentially page-by-page,then the pro-gramming algorithm shown in Figure 1on page 26is recommended.Otherwise,if multiple bytes in a page or several pages are programmed randomly in a sector,then the programming algorithm shown in Figure 2on page 27is recommended.Each page within a sector must be updated/rewritten at least once within every 10,000cumulative page erase/program operations in that sector.Operation Mode SummaryThe modes described can be separated into two groups –modes which make use of the Flash memory array (Group A)and modes which do not make use of the Flash memory array (Group B).Group A modes consist of:1.Main Memory Page Read2.Main Memory Page to Buffer 1(or 2)Transfer3.Main Memory Page to Buffer 1(or 2)Compare4.Buffer 1(or 2)to Main Memory Page Program with Built-in Erase5.Buffer 1(or 2)to Main Memory Page Program without Built-in Erase6.Page Erase7.Block Erase8.Main Memory Page Program through Buffer 9.Auto Page Rewrite Group B modes consist of:1.Buffer 1(or 2)Read 2.Buffer 1(or 2)Write 3.Status Register ReadIf a Group A mode is in progress (not fully completed),then another mode in Group A should not be started.However,during this time in which a Group A mode is in progress,modes in Group B can be started.This gives the Serial DataFlash the ability to virtually accommodate a continuous data stream.While data is being programmed into main memory from buffer 1,data can be loaded into buffer 2(or vice versa).See application note AN-4(“Using Atmel ’s Serial DataFlash ”)for more details.Pin DescriptionsSERIAL INPUT (SI):The SI pin is an input-only pin and is used to shift data into the device.The SI pin is used for all data input,including opcodes and address sequences.SERIAL OUTPUT (SO):The SO pin is an output-only pin and is used to shift data out from the device.SERIAL CLOCK (SCK):The SCK pin is an input-only pin and is used to control the flow of data to and from the DataFlash.Data is always clocked into the device on the rising edge of SCK and clocked out of the device on the falling edge of SCK.CHIP SELECT (CS):The DataFlash is selected when the CS pin is low.When the device is not selected,data will not be accepted on the SI pin,and the SO pin will remain in a high-impedance state.A high-to-low transition on the CS pin is required to start an operation,and a low-to-high transition on the CS pin is required to end an operation.9AT45DB021B1937F –DFLSH –10/02WRITE PROTECT:If the WP pin is held low,the first 256pages of the main memory cannot be reprogrammed.The only way to reprogram the first 256pages is to first drive the protect pin high and then use the program commands previously mentioned.The WP pin is internally pulled high;therefore,connection of the WP pin is not necessary if this pin and feature will not be utilized.However,it is recommended that the WP pin be driven high externally whenever possible.RESET:A low state on the reset pin (RESET)will terminate the operation in progress and reset the internal state machine to an idle state.The device will remain in the reset condition as long as a low level is present on the RESET pin.Normal operation can resume once the RESET pin is brought back to a high level.The device incorporates an internal power-on reset circuit,so there are no restrictions on the RESET pin during power-on sequences.The RESET pin is also internally pulled high;therefore,connection of the RESET pin is not necessary if this pin and feature will not be utilized.However,it is recommended that the RESET pin be driven high exter-nally whenever possible.READY/BUSY:This open-drain output pin will be driven low when the device is busy in an internally self-timed operation.This pin,which is normally in a high state (through a 1k Ωexternal pull-up resistor),will be pulled low during programming operations,com-pare operations,and during page-to-buffer transfers.The busy status indicates that the Flash memory array and one of the buffers cannot be accessed;read and write operations to the other buffer can still be performed.Power-on/Reset StateWhen power is first applied to the device,or when recovering from a reset condition,the device will default to SPI Mode 3.In addition,the SO pin will be in a high-impedance state,and a high-to-low transition on the pin will be required to start a valid instruc-tion.The SPI mode will be automatically selected on every falling edge of by sampling the inactive clock state.10AT45DB021B1937F –DFLSH –10/02Note:In T ables 2and 3,an SCK mode designation of “Any ”denotes any one of the four modes of operation (Inactive Clock Polarity Low,Inactive Clock Polarity High,SPI Mode 0,or SPI Mode 3).Table 3.Additional Commands11AT45DB021B1937F –DFLSH –10/02P =Page Address BitB =Byte/Buffer Address Bit x =Don ’t Care12AT45DB021B1937F –DFLSH –10/02Note:1.After power is applied and V CC is at the minimum specified datasheet value,the system should wait 20ms before anoperational mode is started.Note:1.I cc1during a buffer read is 20mA maximum.Absolute Maximum Ratings*T emperature under Bias ................................-55°C to +125°C *NOTICE:Stresses beyond those listed under “Absolute Maximum Ratings ”may cause permanent dam-age to the device.This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied.Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Storage T emperature.....................................-65°C to +150°C All Input Voltages (including NC Pins)with Respect to Ground...................................-0.6V to +6.25V All Output Voltageswith Respect to Ground.............................-0.6V to V CC +0.6VDC and AC Operating RangeDC Characteristics13AT45DB021B1937F –DFLSH –10/02AC Characteristics14AT45DB021B1937F –DFLSH –10/02Input Test Waveforms and Measurement Levelst R ,t F <3ns (10%toOutput Test LoadACWaveformsTwo different timing diagrams are shown below.Waveform 1shows the SCK signal being low when CS makes a high-to-low transition,and Waveform 2shows the SCK sig-nal being high when CS makes a high-to-low transition.Both waveforms show valid timing diagrams.The setup and hold times for the SI signal are referenced to the low-to-high transition on the SCK signal.Waveform 1shows timing that is also compatible with SPI Mode 0,and Waveform 2shows timing that is compatible with SPI Mode 3.Waveform 1–Inactive ClockPolarity Low and SPI Mode 0Waveform 2–Inactive Clock Polarity High and SPI Mode 315AT45DB021B1937F –DFLSH –10/02Reset Timing (Inactive Clock Polarity Low Shown)Note:The signal should be in the high state before the signal is deasserted.Command Sequence for Read/Write Operations (except Status Register Read)Notes:1.“r ”designates bits reserved for larger densities.2.It is recommended that “r ”be a logical “0”for densities of 2M bits or smaller.3.For densities larger than 2M bits,the “r ”bits become the most significant Page Address bit for the appropriate density.16AT45DB021B1937F –DFLSH –10/02Write OperationsThe following block diagram and waveforms illustrate the various write sequences available.Main Memory Page Program through BuffersBuffer WriteBuffer to Main Memory Page Program (Data from Buffer Programmed into Flash Page)。
LT3094–20V,500mA,超低噪声,超高PSRR负线性稳压器演示手册 说明书
1UG-1386 Rev. ADESCRIPTIONLT3094–20V, 500mA, Ultralow Noise, Ultrahigh PSRRNegative Linear RegulatorDemonstration circuit 2624A features the LT ®3094, an ultralow noise, ultrahigh power supply rejection ratio (PSRR) negative low dropout (LDO) regulator . DC2624A operates over an input range of –3.8V to –20V, and can deliver up to 500mA output current. It features ultralow noise (0.8µV RMS from 10Hz to 100kHz) and very high PSRR (75dB at 1MHz).The LT3094 enable function (EN/UVLO pin) is bidirectional and can be controlled with either a positive or a negative voltage. The LT3094 also offers programmable current limit functionality by connecting a resistor from I LIM to GND. Current monitoring is also achieved by sensing the I LIM pin voltage. The V IOC tracking function controls an upstream switching converter to maintain a constant volt-age across the regulator and, hence, minimize power dis-sipation. The power good feedback (PGFB) pin is used to set a programmable power good threshold, and activatesAll registered trademarks and trademarks are the property of their respective owners.PERFORMANCE SUMMARYthe fast start-up circuitry. To use the power good func-tion, connect an external voltage source at V EXT . If power good and fast start-up functionality are not needed, tie PGFB to IN.Built-in protection includes reverse battery protection, reverse current protection, internal current limit with fold-back, and thermal limit with hysteresis.The LT3094 data sheet gives a complete description of the part, operation and applications information. The data sheet must be read in conjunction with this demo manual for demonstration circuit DC2624A. The LT3094 is assembled in 12-lead MSOP and 3mm × 3mm DFN packages with an exposed pad on the bottom-side of the IC. Proper board layout is essential for maximum ther-mal performance.Design files for this circuit board are available.Specifications are at T A = 25°CPARAMETERSCONDITIONSMIN TYPMAX UNITSInput Voltage Range (V IN )I OUT = 150mA, V OUT = –3.3V –20–3.8V Input Voltage Range (V IN )I OUT = 500mA, V OUT = –3.3V –7*–3.8V Output Voltage (V OUT )V IN = –5V, I OUT = 500mA –3.39–3.32–3.25V Shutdown Input Current (I IN )V EN = 0V, V IN = –5V5µA*The maximum input voltage for 500mA load current is set by the 60°C temperature rise of LT3094 on the demo circuit. Higher input voltages can be applied if a larger copper area and/or forced-air cooling is applied. The output current is also limited by the differential of input and output voltage. Please refer to the data sheet for details.QUICK START PROCEDUREDemonstration circuit 2624A is easy to set up to evaluate the performance of the LT3094EDD. Refer to Figure 1 for proper measurement equipment setup and follow the procedure below:1. Connect a load between the V OUT and GND terminals.2. With power off, connect the input power supply to the V IN and GND terminals.3. Apply –3.8V across V IN to GND. The output voltage should be –3.32V ± 3% (–3.39V to –3.25V).4. Vary V IN from –3.8V to –20V and vary the load current from 0mA to 500mA.Note: Make sure the power dissipation is below the thermal limit.5. Apply a power source at V EXT. The PG pin voltage should be approximately equal to V EXT.6. Refer to Application Notes AN70 and AN159 for mea-suring output noise and PSRR.Figure 1. Test Procedure Setup Drawing for DC2624A2UG-1386 Rev. A3UG-1386 Rev. APCB LAYOUTFigure 2. Bottom Layer of DC2624ABest PSRR Performance: PCB Layout for Input T race For applications utilizing the LT3094 for post-regulating switching converters, placing a capacitor directly at the LT3094 input results in AC current (at the switching fre-quency) flowing near the LT3094. Without careful atten-tion to PCB layout, this relatively high frequency switching current generates an electromagnetic field (EMF) that cou-ples to the LT3094 output, thereby degrading its effective PSRR. Highly dependent on the PCB, the switching prereg-ulator , and the input capacitor size, among other factors, the PSRR degradation can easily be 30dB at 1MHz. Thisdegradation is present even if the LT3094 is desoldered from the board, because it effectively degrades the PSRR of the PC board itself. While negligible for conventional low PSRR LDOs, LT3094’s ultrahigh PSRR requires care-ful attention to higher order parasitics in order to realize the full performance offered by the regulator .The LT3094 demo board alleviates this degradation in PSRR by using a specialized layout technique. In Figure 2, the input trace (V IN ) is highlighted in red together with input capacitor C1, and in Figure 3 the return path (GND) is also highlighted. Normally when4UG-1386 Rev. APCB LAYOUTan AC voltage is applied to the input of the board, AC current flows on this path, thus generating EMF . This EMF couples to output capacitor C2 and related traces, making the PSRR appear worse than it actu-ally is. With the input trace directly above the return path, the EMFs are in opposite directions, and con-sequently cancel each other out. Making sure these traces exactly overlap each other maximizes the can-cellation effect and thus provides the maximum PSRR offered by the regulator.Figure 3. Layer 3 of DC2624ABest AC Performance: PCB Layout for Output Capacitors C2For ultrahigh PSRR performance, the LT3094 bandwidth is quite high (~1MHz), making it very close to the output capacitor’s self-resonance frequency (~1.6MHz). There-fore, it is very important to avoid adding extra imped-ance (ESL & ESR) outside the feedback loop. To that end, minimize the effects of PCB trace and solder inductance by Kelvin connecting OUTS and SET pin capacitor GND directly to output capacitors (C2) terminals using split capacitor techniques as shown in Figure 4 and Figure 5. With only small AC current flowing through these connec-tions, the impact of solder joint/PCB trace inductance on stability is eliminated. While the LT3094 is robust enough not to oscillate if the recommended layout is not followed,phase/gain margin and stability will degrade.PCB LAYOUTFigure 4. C2 and C SET Connections for Best PerformanceDC2624a F05Figure 5. Split Pads for Output Capacitors on Top Layer of DC2624A5UG-1386 Rev. APARTS LISTITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBERRequired Circuit Components11CIN CAP, ALUM, 22µF, 35V, 5X5.4MM SUN ELECTRONIC INDUSTRIES CORP, 35CE22BSS 22C1, C4CAP, X7R, 4.7µF, 25V, 10% 1206MURATA, GRM31CR71E475KA88L31C2CAP, X5R, 10µF, 25V, 10% 1206MURATA, GJ831CR61E106KE83L41R1RES, CHIP, 200k, 1/10W, 5% 0603VISHAY, CRCW0603200KJNEA51R2RES, CHIP, 100k, 1/10W, 1% 0603VISHAY, CRCW0603100KFKEA61R3RES, CHIP, 33.2k, 1/10W, 1% 0603VISHAY, CRCW060333K2FKEA71R5RES, CHIP, 453k, 1/10W, 1% 0603VISHAY, CRCW0603453KFKEA81R6RES, CHIP, 49.9k, 1/10W, 1% 0603VISHAY, CRCW060349K9FKEA91R7RES, CHIP, 4.99k, 1/10W, 1% 0603VISHAY, CRCW06034K99FKEA101U1IC, LT3094EDD, 12DFN ANALOG DEVICES, LT3094EDD#PBFAdditional Demo Board Circuit Components10C3, C5 (OPT)CAP, OPTION, 120620R4 (OPT)RES, OPTION, 0603Hardware: For Demo Board Only18E1 TO E8TESTPOINT, TURRET, 0.094" PBF MILL-MAX, 2501-2-00-80-00-00-07-022J1, J2CONN, BNC, 5 PINS CONNEX, 11240434MH1 TO MH4STAND-OFF, NYLON 6.4mm WURTH ELEKTRONIK, 7029310006UG-1386 Rev. A7UG-1386 Rev. AInformation furnished by Analog Devices is believed to be accurate and reliable. However , no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.SCHEMATIC DIAGRAM8UG-1386 Rev. AANALOG DEVICES, INC. 2018-2019UG17053-0-02/19ESD CautionESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. 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IN NO EVENT WILL ADI AND ITS LICENSORS BE LIABLE FOR ANY INCIDENTAL, SPECIAL, INDIRECT , OR CONSEQUENTIAL DAMAGES RESUL TING FROM CUSTOMER’S POSSESSION OR USE OF THE EVALUATION BOARD, INCLUDING BUT NOT LIMITED TO LOST PROFITS, DELAY COSTS, LABOR COSTS OR LOSS OF GOODWILL. ADI’S TOTAL LIABILITY FROM ANY AND ALL CAUSES SHALL BE LIMITED TO THE AMOUNT OF ONE HUNDRED US DOLLARS ($100.00). EXPORT . Customer agrees that it will not directly or indirectly export the Evaluation Board to another country, and that it will comply with all applicable United States federal laws and regulations relating to exports. GOVERNING LAW . This Agreement shall be governed by and construed in accordance with the substantive laws of the Commonwealth of Massachusetts (excluding conflict of law rules). Any legal action regarding this Agreement will be heard in the state or federal courts having jurisdiction in Suffolk County, Massachusetts, and Customer hereby submits to the personal jurisdiction and venue of such courts. The United Nations Convention on Contracts for the International Sale of Goods shall not apply to this Agreement and is expressly disclaimed.。
CMX14Q20
121220
CMX14Q20
4. Schematic Drawing
20dB Directional Coupler
5. Port Configuration
Configuration Case 1. Case 2. Port 1 Input Output Port 2 Output Input Port 3 Isolated Coupling Port 4 Coupling Isolated
Avg. (Watt)
0.12 0.10 0.10 0.12 Operating Temp.
(℃)
1.40 1.15 1.25 1.40
20 20 20 20
Port1
200 200 200 200
Port2
-55 ~ 125 -55 ~ 125 -55 ~ 125 -55 ~ 125
3. Mechanical Specification
2. Electrical Specification
Freq.
(MHz)
Coupling
max (dB)
Insertion Loss
max (dB)
VSWR
Max
800-2200 800-1200 1200-1600 1600-2200 Directivity
min (dB)
22.0 ± 2.00 22.0 ± 2.00 21.0 ± 1.00 22.0 ± 2.00 Power Capacity
2
CMX14Q20 CEMAX
Port4 Port3
[Unit = mm]
RN2 Technologies Co., Ltd.
LTCC TOTAL SOLUTION (Ceramic Powder / Green Sheet / Component / Substrate)
Unicore UM4B0 Installation and Operation User Manu
U ni c o r e C o n f i dINSTALLATION AND OPERATIONUSER MANUALData subject to change without notice.Communications, Inc.Copyright© 2009-2021, Unicore RTK Positioning ModuleAll-constellation All-frequency GPS/BDS/GLONASS/Galileo U M 4B0DisclaimerInformation in this document is subject to change without notice and does not represent a commitment on the part of Unicore Communications, Inc. No part of this manual may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose without the express written permission of a duly authorized representative of Unicore Communications, Inc. The information contained within this manual is believed to be true and correct at the time of publication.© Copyright 2009-2021 Unicore Communications, Inc. All rights RSV.UM4B0 User Manual ForewordThis <User Manual> offers you information in the features of the hardware, the installation, specification and use of UNICORECOMM UM4B0 product.This manual is a generic version. Please refer to the appropriate part of the manual according to your purchased product configuration, concerning CORS, RTK and Heading.Readers it applies toThis <User Manual> is applied to the technicists who know GNSS Receiver to some extent but not to the general readers.Contents1INTRODUCTION (1)1.1O VERVIEW (1)1.2K EY F EATURES (1)1.3T ECHNICAL S PECIFICATIONS (2)1.4I NTERFACES (2)2HARDWARE (3)2.1D IMENSIONS (3)2.2P IN D EFINITION (T OP V IEW) (4)2.3E LECTRICAL S PECIFICATIONS (6)2.4O PERATIONAL C ONDITIONS (7)2.5P HYSICAL S PECIFICATIONS (7)3HARDWARE DESIGN (8)3.1D ESIGN IN C ONSIDERATIONS (8)3.2UM4B0R EFERENCE D ESIGN (9)3.3P INS (10)3.4PCB P ACKAGING (11)3.5R ESET S IGNAL (12)3.6A NTENNA (12)3.7E XTERNAL A NTENNA F EED D ESIGN (12)4INSTALLATION AND CONFIGURATION (14)4.1ESD H ANDLING P RECAUTIONS (14)4.2H ARDWARE I NSTALLATION (14)4.3S TART U P (17)4.4C ONFIGURATION AND O UTPUT (17)4.4.1Operation Procedures (18)5CONFIGURATION COMMANDS (19)5.1RTK R EFERENCE S TATION C ONFIGURATION (20)5.2RTK R OVER C ONFIGURATION (21)5.3M OVING B ASE C ONFIGURATIONS (21)5.4H EADING C ONFIGURATION (21)6ANTENNA DETECTION (22)7FIRMWARE UPGRADE (22)8PRODUCTION REQUIREMENT (24)9PACKAGING (25)1Introduction1.1OverviewUM4B0 is a high precision positioning and heading RTK module developed by Unicore Communications, targeting light robots, UAVs, intelligent vehicles, GIS information collection, etc.By employing a single UC4C0 (432 channel tracking) baseband chip and a single RF chip, using single-sided SMD packaging, UM4B0 has achieved the smallest size(30x40mm) in this industry with high accuracy heading and positioning output. It can simultaneously track BDS B1I/B2I/B3I/B1C/B2a + GPS L1/L2/L5 + GLONASSL1/L2+Galileo E1/E5a/E5b.Figure 1-1 UM4B0 Module1.2Key Features•30*40mm, the smallest multi-system multi-frequency high precision module •Support GPS L1/L2/L5+GLONASS L1/L2+BDS B1I/B2I/B3I/B1C/B2a+Galileo E1/E5a/E5b•Based on 432 channel NebulasII GNSS SoC•20Hz update rate•Instant RTK initialization and long-distance RTK•Enhanced multi-system multi-frequency RTK technology, JamShield adaptive narrow-band anti-interference and U-AutoAlign multi-path mitigation •Support odometer input and external high-performance IMU interface* •SMD packagingUM4B0 User Manual 1.3Technical SpecificationsTable 1-1 Performance SpecificationsTable 1-2 Functional Ports1.4InterfacesFigure 1-2 Block Diagram1.RF PartThe receiver gets filtered and enhanced GNSS signal from the antenna via a coaxial cable. The RF part converts the RF input signals into the IF signal, and converts IF analog signal into digital signals required for NebulasII (UC4C0) digital processing.2.NebulasII SoC (UC4C0)The UM4B0 incorporates the processing from the NebulasII (UC4C0), UNICORECOMM’s new generation high precision GNSS SoC with 55nm low power design, which supports up to 12 digital intermediate frequency or 8 analog intermediate frequency signals and can track 12 navigation signals with 432 channels.3.1PPSUM4B0 outputs 1 PPS with adjustable pulse width and polarity.4.EventUM4B0 provides 1 Event Mark Input with adjustable pulse width and polarity.2Hardware2.1DimensionsUM4B0 User ManualFigure 2-1 Mechanical Dimensions2.2Pin Definition (Top View)Figure 2-2 UM4B0 Pin DiagramTable 2-2 Pin DefinitionUM4B0 User Manual2.3Electrical SpecificationsTable 2-3 Absolute Maximum Ratings2.4Operational ConditionsTable 2-4 Operational ConditionsNOTE: Since the product contains capacitors at the input, inrush current will occur during power-on. Evaluate in the actual environment in order to check the effect of the supply voltage drop due to the inrush current.2.5Physical SpecificationsTable 2-5 Physical Specifications3Hardware Design3.1Design in ConsiderationsTo make UM4B0 work properly, you need to properly connect the following:The module VCC power-on behavior is repeatable, the initial level is lower than0.4V, and the undershoot and ringing should be guaranteed to be within 5% VCC Provide stable power to the VCC pinConnect all the GND pins to groundConnect VBAT pin to a 3.0V power supplyConnect ANT_IN signal to the antenna, and ensure the 50-ohm impedance matchingConnect ANT_PWR to +3.3~5.5 V voltage, then supply +3.3~5.5 V feed to the antenna through ANT_INEnsure COM1 is connected to a PC or an external processor, and users can use this serial port to receive position data. COM1 is also necessary for firmwareupgradesProperly connect the module’s reset pin FRESET_N to ensure complete reset of the module. It will restore the module to the manufacturing configuration.When ANT_NLOD, ANT_FFLG and antenna detection indication signal are connected, the IO without any pull-up/down of the client MCU terminal isrequired at the input.In order to obtain proper performance, special concerns should be paid during the design:Power supply: A table and low ripple power supply is necessary for good performance. Make sure the peak-to-peak voltage ripple does not exceed50mVpp. It is recommended to use a power chip with current output capacity greater than 2A to power the board.-Use LDO to ensure the purity of power supply-Try to place LDO close to the module in layout-Widen the tracks of power circuit or use copper pour surface to transmit current-Avoid walking through any high-power or high inductance devices such as a magnetic coilInterfaces: Ensure that the signals and baud rate of the main equipment match those of the UM4B0 moduleAntenna interface: Make sure the antenna impedance matches, and the cable is short without any kinks, try to avoid all acute anglesTry to avoid designing in any circuits underneath UM4B0This module is a temperature sensitive device, so dramatic changes in temperature will result in reduced performance. Keep it away as far as possible from any high-power high-temperature air and heating devices3.2UM4B0 Reference DesignFigure 3-1 Minimum Reference DesignFigure 3-2 UM4B0 Reference Design 3.3PinsTable 3-1 Pin Notes3.4 PCB PackagingFigure 3-3 UM4B0 recommended PCB Packaging (unit: mil, in brackets: mm)3.5Reset SignalUM4B0 module can’t work properly unless it is correctly reset after power on. To ensure effective reset, the reset pin (RST) and power supply pin (VCC) must meet the following time sequence requirement. To reset UM4B0 during normal operation, please pull RST pin to low level for more than 5ms.Figure 3-4 UM4B0 RST3.6AntennaThe module has the antenna input pin ANT_IN, which provides a +3.3V antenna feed. When an active antenna of +3.3~5V is adopted, please make sure the 50 Ω antenna impedance is matched.Figure 3-5 UM4B0 Active Antenna Connection3.7External Antenna Feed DesignUM4B0 feeds the antenna signals to the required circuits internally, but in order to effectively prevent damage from lightning and surges, circuit protection should be installed externally to protect the module.High voltage and high-power protection chips should be used to feed the antenna from the outside of the module. A gas discharge tube, varistor, TVS tube and other high-power protective devices may also be used in the antenna circuit to effectively improve the prevention against lightning stroke and surge.ANTFigure 3-6 UM4B0 External Antenna Feed Reference CircuitRemarks:a)L1, feed inductor, 68nH RF inductor in 0603 package is recommended;b)C1, decoupling capacitor, it is recommended to connect two capacitors of 100nF/100pFin parallel;c)C2, DC blocking capacitor, recommended 100pF capacitor.4Installation and Configuration4.1ESD Handling PrecautionsUM4B0 Module is an Electrostatic Sensitive Device (ESD) and special precautions when handling are required.Electrostatic discharge may cause damages to the device. All operations mentioned in this chapter should be carried out on an antistatic workbench, wearing an antistatic wrist strap and using a conductive foam pad. If anantistatic workbench is not available, wear an antistatic wrist strap and connect the other end to a metal frame to avoid the effects of static electricity.Hold the edge of the module, not in direct contact with the componentsPlease check carefully whether the module has obviously loose or damaged components.Figure 4-1 Typical Installation of UM4B0Please check the contents of the package carefully after receiving the package of UM4B0.UM4B0 EVK suite (or evaluation board)User manualUPrecise softwareQualified antennaMMCX antenna cablePC or Laptop with serial ports (Win7 or above), with UPrecise installed4.2Hardware InstallationAfter the above preparation, please follow the steps below to install:Step 1: Make sure to take all the anti-static measures, such as wearing an anti-static wrist strap, grounding the workbench;Step 2: Align UM4B0 transfer board positioning holes and pins with EVK, and fix it in the EVK. EVK provides power supply and standard communication interface for the module to communicate with peripheral devices;NOTE: The RF connector of the board is MMCX, and the suitable connecting wire should be selected according to the package. The input signal gain at the antenna interface is optimal between 20 and 36 dB. Please select the appropriate antenna, antenna cable and online LNA accordingly.Figure 4-2 Installation InstructionStep 3: Select the GNSS antenna with appropriate gain, and fix it in a stable, non-block area, using the coaxial radio frequency cable to connect the antenna to UM4B0 EVK;Step 4: Connect the PC to the EVK serial port through direct serial cable;Figure 4-3 Connect the Serial PortStep 5: Connect a 12V adapter to the EVK power input, and switch on to powerthe device;Figure 4-4 Connect the AntennaStep 6: Open the UPrecise software on the PC;Step 7: Control the receiver through UPrecise to send commands or to log data.4.3Start UpThe power supply for UM4B0 is 3.3VDC. Before powering on the device, please connect UM4B0 serial port to the GNSS antenna. The receiver is started and the communication is connected after powering up. Testing tools are provided for module testing.4.4Configuration and OutputUNICORECOMM UPrecise software provides a user-friendly graphical interface to control and display the operation of your receiver. The features of Uprecise include: Logging Control View: Graphic interface for data loggingConsole window for sending command to the receiver (Console View)Displaying the receiver’s output in ASCII-format (ASCII View)Graphic window for displaying Position of satellite, PRN, and Signal/Noise Ratio (Constellation View)Historical and present Trajectory of the receiver (Trajectory View)Position/Velocity/Time of the receiver (PVT View)Apart from the basic functions above, UPrecise offers advanced functions as follows: Selecting and recording the logSending commands to the receiverOperating and configuration of the ASCII viewThe trajectory view for displaying the present point and the past point of the receiverSwitching Views over the tracking windowSwitching between Constellation ViewsResetting the receiverReplaying the GGA logFigure 4-5 UPrecise SoftwareUM4B0 User Manual 4.4.1Operation ProceduresStep 1. Follow 4.2 Installation Guide to connect the power source, antenna to the board, and turn on the EVK switchStep 2. Click file - > connect the serial port, and set the baud rate; the default baud rate of UB4B0M is 115200bpsFigure 4-6 Connect the Serial PortStep 3. Click the receiver settings button to configure the NMEA message output. Itis recommended to configure GPGGA, GPGSV, and other messages.Figure 4-7 NMEA Data OutputStep 4. Click the receiver settings button to configure the NMEA message output, then click send. It is recommended to configure GPGGA, GPGSV, and other messages. Step 5.In the data session window, click “Send all Message” to complete all the NMEA message output (update rate 1Hz). Right click in the data session window to adjust: output log font size, stop / resume log output, or clear log content, etc.Step 6. Use various views of UPrecise to configure or input commands as required.5Configuration CommandsUM4B0 supports abbreviated ASCII format. Simplified ASCII format without check bit is more accessible to user commands. All commands are composed of a log heading and configuration parameters (If parameters are null, there will be only one heading in the command). Header field contains the command name or message headers. UM4B0 is simple to use, and common instructions are shown in the following table:UM4B0 User Manual5.1RTK Reference Station ConfigurationIf the precise coordinates are known, the precise coordinates could be set as in this example:Mode base 40.07898324818 116.23660197714 60.4265 // set lat lon heightrtcm1033 com2 10 // RTCM1033 input from com2rtcm1006 com2 10rtcm1074 com2 1rtcm1084 com2 1rtcm1094 com2 1rtcm1124 com2 1saveconfigIf precise coordinates are unknown:Mode base time 60 1.5 2.0 // 60 seconds position averagertcm1033 com2 10rtcm1006 com2 10rtcm1074 com2 1rtcm1084 com2 1rtcm1094 com2 1rtcm1124 com2 1saveconfig5.2RTK Rover ConfigurationRTK Rover stations (rover station) receive differential correction data sent from reference stations and receive satellite signals to provide an RTK positioning solution and realize RTK high-precision positioning with cm or mm-level accuracy. Common instructions for configuring RTK rover are as follows:gngga 1saveconfig5.3Moving Base ConfigurationsRTK reference station provides precisely known coordinates of a fixed station. Unlike the RTK reference station, moving base station is in motion, at the same time receives the satellite information, and sends it to the rover station receiver (to be determined) directly or after processing. The rover station receiver receives satellite observations as well as information from the moving base station, to make relative positioning and determine the position of the rover station. Commonly used instructions to set the moving base station are as follows:Mode movingbasertcm1006 com2 1rtcm1074 com2 1rtcm1084 com2 1rtcm1094 com2 1rtcm1124 com2 1saveconfig5.4Heading ConfigurationGNSS heading refers to the clockwise angle between true North and the baseline vector constituted by the two GNSS antennas. Commonly used instructions are as follows:Mode headinggphdt com1 1saveconfigUM4B0 User Manual6Antenna Detection1The UM4B0 module offers antenna open/short detection. The corresponding pins are ANT_NLOAD and ANT_FFLG.•The current monitoring chip outputs 2 bit high and low voltage; the software portion sets 2 bit IO of corresponding NII as input pull-up, and then queries the status of 2 bit IO to check the antenna state.•If ANT_PWR malfunctions, the query result is invalid.•If the antenna is not fed by ANT_PWR but by other means, the query result is invalid.7Firmware UpgradeUprecise software is used for the remote update of UM4B0. Please follow the steps below to upgrade the device:Figure 7-1 Update InterfaceClick “…” to browse the firmware update package, and click“Start” to start the firmware upgrading process (uncheck software reset):1 Optional by FirmwareFigure 7-2 Update StepsWaiting for the process to complete 100% (the upgrade time is normally within 5min):Figure 7-3 Update StepsPlease use COM1 only to update firmware.UM4B0 User Manual8Production RequirementRecommended thermal cycle curve is as follows:Figure 8-1 Soldering TemperatureTemperature rising stage∙Rising slope: Max. 3℃/s∙Rising temperature range:50℃-150℃Preheating stage∙Preheating time: 60 – 120 s∙Preheating temperature range: 150 - 180℃Reflux Stage∙Over melting temperature (217℃) time: 40 – 60 s∙Peak temperature: no higher than 245℃Cooling Stage∙Cooling slope: Max. 4℃ / sNotes：In order to prevent fall off during soldering of the modules, please avoid soldering the module in the back of the Board during design, that is, better not to go through soldering cycle twice.The setting of temperature depends on many factors, such as type of Board, solder paste type, solder paste thickness, etc. Please also refer to the relevant IPC standards and indicators for solder paste.Since the lead soldering temperatures are relatively low, if using this soldering method, please give priority to other components on the Board.9PackagingUM4B0 modules are delivered in trays, which is suitable for mainstream SMT equipment. Each box contains 5 trays, so there are 150 UM4B0 modules in the box. Table 9-1 Package Informationw 。
【IBM BIOS】错误代码说明书
【IBM BIOS】错误代码说明书.txt真正的好朋友并不是在一起有说不完的话题，而是在一起就算不说话也不会觉得尴尬。
你在看别人的同时，你也是别人眼中的风景。
要走好明天的路，必须记住昨天走过的路，思索今天正在走着的路。
【IBM BIOS】错误代码说明书错误码及提示出错部件及解决方法10X101: 中断失败102: 时钟失败103: 时间中断失败104: 保护模式失败105: 最后的 8042命令未接受107: NMI 检测失败108: 时钟总线检测失败109: Low meg芯片选择检测系统主板.nm110平面奇偶检测内存内存插槽如果有接到电脑的扩展部件移除系统主板111I/O奇偶检测内存扩展部件或端口复制器系统主板.11XX1101: A类设备检测失败串口设备通讯接线系统主板12XX1201: B类检测失败系统主板 (红外)158即设置了SuperVisor密码但没有设置硬盘密码设置硬盘密码159硬盘密码与SuperVisor密码不相同设置硬盘密码与SuperVisor密码相同161电池失效检测备用电池备用电池系统主板.163时间和日期未设置设置时间和日期系统主板.173设备数据丢失在屏幕上选择OK，然后设置时间和日期备用电池系统主板.174设置错误：先进行检测安装的设备列表再改变FRU部件检测设备配置硬盘驱动器系统主板.0175CRC1错, 停止了 POST任务. EEPROM 校验错. 系统主板0177SuperVisor密码检验错系统主板0178EEPROM 失效系统主板17XX1701: 硬盘控制器失败1780, 1790: 硬盘0出错1781, 1791: 硬盘1出错硬盘驱动器系统主板183提示输入SuperVisor密码时输入错误输入正确的SuperVisor密码184开机密码检验错进入BIOS设置中重置开机密码185非法的启动顺序进入BIOS设置中重置启动顺序186 1系统主板0187EAIA 数据读取错误。
1ED020I12FTA
EiceDRIVER™1ED020I12FTA Single IGBT Driver ICData Sheet Version 2.1, 2013-05-21Edition 2013-05-21Published byInfineon Technologies AG81726 Munich, Germany© 2013Infineon Technologies AGAll Rights Reserved.Legal DisclaimerThe information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.InformationFor further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office ().WarningsDue to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office.Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.Revision HistoryPage or Item Subjects (major changes since previous revision)Version 2.1, 2013-05-21Trademarks of Infineon Technologies AGAURIX™, BlueMoon™, C166™, CanPAK™, CIPOS™, CIPURSE™, COMNEON™, EconoPACK™, CoolMOS™, CoolSET™, CORECONTROL™, CROSSAVE™, DAVE™, EasyPIM™, EconoBRIDGE™, EconoDUAL™, EconoPIM™, EiceDRIVER™, eupec™, FCOS™, HITFET™, HybridPACK™, I²RF™, ISOFACE™, IsoPACK™, MIPAQ™, ModSTACK™, my-d™, NovalithIC™, OmniTune™, OptiMOS™, ORIGA™, PRIMARION™, PrimePACK™, PrimeSTACK™, PRO-SIL™, PROFET™, RASIC™, ReverSave™, SatRIC™, SIEGET™, SINDRION™, SIPMOS™, SMARTi™, SmartLEWIS™, SOLID FLASH™, TEMPFET™, thinQ!™, TRENCHSTOP™, TriCore™, X-GOLD™, X-PMU™, XMM™, XPOSYS™.Other TrademarksAdvance Design System™ (ADS) of Agilent Technologies, AMBA™, ARM™, MULTI-ICE™, KEIL™, PRIMECELL™, REALVIEW™, THUMB™, µVision™ of ARM Limited, UK. AUTOSAR™ is licensed by AUTOSAR development partnership. Bluetooth™ of Bluetooth SIG Inc. CAT-iq™ of DECT Forum. COLOSSUS™, FirstGPS™ of Trimble Navigation Ltd. EMV™ of EMVCo, LLC (Visa Holdings Inc.). EPCOS™ of Epcos AG. FLEXGO™ of Microsoft Corporation. FlexRay™ is licensed by FlexRay Consortium. HYPERTERMINAL™ of Hilgraeve Incorporated. IEC™ of Commission Electrotechnique Internationale. IrDA™ of Infrared Data Association Corporation. ISO™ of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLAB™ of MathWorks, Inc. MAXIM™ of Maxim Integrated Products, Inc. MICROTEC™, NUCLEUS™ of Mentor Graphics Corporation. Mifare™ of NXP. MIPI™ of MIPI Alliance, Inc. MIPS™ of MIPS Technologies, Inc., USA. muRata™of MURATA MANUFACTURING CO., MICROWAVE OFFICE™ (MWO) of Applied Wave Research Inc., OmniVision™ of OmniVision Technologies, Inc. Openwave™ Openwave Systems Inc. RED HAT™ Red Hat, Inc. RFMD™ RF Micro Devices, Inc. SIRIUS™ of Sirius Satellite Radio Inc. SOLARIS™ of Sun Microsystems, Inc. SPANSION™ of Spansion LLC Ltd. Symbian™ of Symbian Software Limited. TAIYO YUDEN™ of Taiyo Yuden Co. TEAKLITE™ of CEVA, Inc. TEKTRONIX™ of Tektronix Inc. TOKO™ of TOKO KABUSHIKI KAISHA TA. UNIX™ of X/Open Company Limited. VERILOG™, PALLADIUM™ of Cadence Design Systems, Inc. VLYNQ™of Texas Instruments Incorporated. VXWORKS™, WIND RIVER™ of WIND RIVER SYSTEMS, INC. ZETEX™ of Diodes Zetex Limited.Last Trademarks Update 2010-10-26Table of ContentsTable of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.3Internal Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.1Undervoltage Lockout (UVLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.2READY Status Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.3Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.3.4Active Shut-Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.4Non-Inverting and Inverting Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.5Driver Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.6Two-Level Turn-Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.7Minimal On Time / Off Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8External Protection Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8.1Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8.2Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.8.3Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.9RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 5.2Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.3Recommended Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5.4Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4.1Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5.4.2Logic Input and Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4.3Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4.4Active Miller Clamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.4.5Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.6Dynamic Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.4.7Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.4.8Active Shut Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5.4.9Two-level Turn-off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 6Insulation Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.1Certified according to DIN EN 60747-5-2 (VDE 0884 Teil 2): 2003-01. Basic Insulation . . . . . . . . . . 26 6.2Recognized under UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329Application Notes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.1Reference Layout for Thermal Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 9.2Printed Circuit Board Guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33List of FiguresFigure1Typical Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure2Block Diagram 1ED020I12FTA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure3Pin Configuration PG-DSO-20 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure4Application Example Bipolar Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure5Application Example Unipolar Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure6Propagation Delay, Rise and Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure7Principle Switching Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure8Typical Switching Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure9DESAT Switch-OFF Behavior. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure10Short Switch ON Pulses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure11Short Switch OFF Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure12Short Switch OFF Pulses, Ringing Surpression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Figure13VCC2 Ramp Up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure14VCC2 Ramp Down and VCC2 Drop. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure15Typical T TLSET Time over C TLSET Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Figure16PG-DSO-20 (Plastic (Green) Dual Small Outline Package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Figure17Reference Layout for Thermal Data (Copper thickness 102μm). . . . . . . . . . . . . . . . . . . . . . . . . . 33List of TablesTable1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table2Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table3Operating Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Table4Recommended Operating Parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Table5Voltage Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table6Logic Input and Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Table7Gate Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table8Active Miller Clamp. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table9Short Circuit Clamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table10Dynamic Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table11Desaturation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Table12Active Shut Down. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table13Two-level Turn-off. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Table14Certified according to DIN EN 60747-5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table15Recognized under UL 1577 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Product Name Gate Drive Current Package 1ED020I12FTA ±2APG-DSO-20EiceDRIVER™Single IGBT Driver IC1ED020I12FTA1OverviewMain Features •Single channel isolated IGBT Driver •For 600V/1200V IGBTs •2A rail-to-rail output •Vcesat-detection •Active Miller Clamp •Two level turn offProduct Highlights •Coreless transformer isolated driver•Basic insulation according to DIN EN 60747-5-2•Basic insulation recognized under UL1577•Integrated protection features•Suitable for operation at high ambient temperature •Automotive QualifiedTypical Application •Drive inverters for HEV and EV •Auxilliary inverters for HEV and EV •High Power DC/DC invertersDescriptionThe 1ED020I12FTA is a galvanic isolated single channel IGBT driver in PG-DSO-20 package that provides an output current capability of typically 2A.All logic pins are 5V CMOS compatible and could be directly connected to a microcontroller.The data transfer across galvanic isolation is realized by the integrated Coreless Transformer Technology.The 1ED020I12FTA provides several protection features like IGBT two level turn off, desaturation protection,active Miller clamping and active shut down.OverviewBlock Diagram 2Block Diagram3Pin Configuration and Functionality 3.1Pin ConfigurationTable1Pin ConfigurationPin Function1VEE2Negative power supply output side2VEE2Negative power supply output side3DESAT Desaturation protection4GND2Signal ground output side5TLSET Two level set6VCC2Positive power supply output side7OUT Driver output8CLAMP Miller clamping9VEE2Negative power supply output side10VEE2Negative power supply output side11GND1Ground input side12GND1Ground input side13IN+Non inverted driver input14IN-Inverted driver input15RDY Ready output16FLT Fault output, low active17RST Reset input, low active18VCC1Positive power supply input side19GND1Ground input side20GND1Ground input side3.2Pin FunctionalityGND1Ground connection of the input side.IN+ Non Inverting Driver InputIN+ control signal for the driver output if IN- is set to low. (The IGBT is on if IN+ = high and IN- = low)A minimum pulse width is defined to make the IC robust against glitches at IN+. An internal Pull-Down-Resistor ensures IGBT Off-State.IN- Inverting Driver InputIN- control signal for driver output if IN+ is set to high. (IGBT is on if IN- = low and IN+ = high)A minimum pulse width is defined to make the IC robust against glitches at IN-. An internal Pull-Up-Resistor ensures IGBT Off-State./RST Reset InputFunction 1: Enable/shutdown of the input chip. (The IGBT is off if /RST = low). A minimum pulse width is defined to make the IC robust against glitches at /RST.Function 2: Resets the DESAT-FAULT-state of the chip if /RST is low for a time T RST. An internal Pull-Up-Resistor is used to ensure /FLT status output./FLT Fault OutputOpen-drain output to report a desaturation error of the IGBT (FLT is low if desaturation occurs)RDY Ready StatusOpen-drain output to report the correct operation of the device (RDY = high if both chips are above the UVLO level and the internal chip transmission is faultless).VCC15V power supply of the input chipVEE2Negative power supply pins of the output chip. If no negative supply voltage is available, all VEE2 pins have to be connected to GND2.DESAT Desaturation Detection InputMonitoring of the IGBT saturation voltage (V CE) to detect desaturation caused by short circuits. If OUT is high, V CE is above a defined value and a certain blanking time has expired, the desaturation protection is activated and the IGBT is switched off. The blanking time is adjustable by an external capacitor.CLAMP Miller ClampingTies the gate voltage to ground after the IGBT has been switched off at a defined voltage to avoid a parasitic switch-on of the IGBT.During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes below 2V below VEE2.GND2 Reference GroundReference ground of the output chip.OUT Driver OutputOutput pin to drive an IGBT. The voltage is switched between VEE2 and VCC2. In normal operating mode Vout is controlled by IN+, IN- and /RST. During error mode (UVLO, internal error or DESAT) Vout is set to VEE2 independent of the input control signals.VCC2Positive power supply pin of the output side.TLSET Two Level Turn Off AdjustCircuitry at TLSET adjust the two level turn off time with an external capacitor to GND2 and the two level voltage with an external Zener diode to GND2, for wave forms please see Figure9.Functional DescriptionIntroduction 4Functional Description4.1IntroductionThe 1ED020I12FTA is an advanced IGBT gate driver for motor drives typical greater 10kW. Control and protection functions are included to make possible the design of high reliability systems.The device consists of two galvanic separated parts. The input chip can be directly connected to a standard 5V DSP or microcontroller with CMOS in/output and the output chip is connected to the high voltage side.An effective active Miller clamp function avoids the need of negative gate driving in some applications and allows the use of a simple bootstrap supply for the high side driver.A rail-to-rail driver output enables the user to provide easy clamping of the IGBTs gate voltage during short circuit of the IGBT. So an increase of short circuit current due to the feedback via the Miller capacitance can be avoided. Further, a rail-to-rail output reduces power dissipation.The device also includes an IGBT desaturation protection with a FAULT status output.A two-level turn-off feature with adjustable delay protects against excessive overvoltage at turn-off in case of overcurrent or short circuit condition. The same delay is applied at turn-on to prevent pulse width distortion.A READY status output reports if the device is supplied and operates correctly.4.2SupplyThe driver 1ED020I12FTA is designed to support two different supply configurations, bipolar supply and unipolar supply.In bipolar supply the driver is typically supplied with a positive voltage of 15V at VCC2 and a negative voltage of -8V at VEE2, refer to Figure4. Negative supply prevents a dynamic turn on due to the additional charge which is generated from IGBT input capacitance times negative supply voltage. If an appropriate negative supply voltage is used, connecting CLAMPxx to IGBT gate is redundant and therefore typically not necessary.For unipolar supply configuration the driver is typically supplied with a positive voltage of 15V at VCC2. Erratically dynamic turn on of the IGBT could be prevented with active Miller clamp function, so CLAMP output is directly connected to IGBT gate, refer to Figure5.Functional DescriptionInternal Protection Features4.3Internal Protection Features4.3.1Undervoltage Lockout (UVLO)To ensure correct switching of IGBTs the device is equipped with an undervoltage lockout for both chips, refer to Figure13 and Figure14.If the power supply voltage V VCC1 of the input chip drops below V UVLOL1 a turn-off signal is sent to the output chip before power-down. The IGBT is switched off and the signals at IN+ and IN- are ignored as long as V VCC1 reaches the power-up voltage V UVLOH1.If the power supply voltage V VCC2 of the output chip goes down below V UVLOL2 the IGBT is switched off and signals from the input chip are ignored as long as V VCC2 reaches the power-up voltage V UVLOH2. VEE2 is not monitored, otherwise negative supply voltage range from 0V to -12V would not be possible.4.3.2READY Status OutputThe READY output at pin /RDY shows the status of three internal protection features.•UVLO of the input chip•UVLO of the output chip after a short delay•Internal signal transmission after a short delayIt is not necessary to reset the READY signal since its state only depends on the status of the former mentioned protection signals.4.3.3Watchdog TimerDuring normal operation the internal signal transmission is monitored by a watchdog timer. If the transmission fails for a given time, the IGBT is switched off and the READY output reports an internal error.4.3.4Active Shut-DownThe Active Shut-Down feature ensures a safe IGBT off-state if the output chip is not connected to the power supply, IGBT gate is clamped at OUT to VEE2.Functional DescriptionNon-Inverting and Inverting Inputs4.4Non-Inverting and Inverting InputsThere are two possible input modes to control the IGBT. At non-inverting mode IN+ controls the driver output while IN- is set to low. At inverting mode IN- controls the driver output while IN+ is set to high, refer to Figure7. A minimum input pulse width is defined to filter occasional glitches.4.5Driver OutputThe output driver section uses only MOSFETs to provide a rail-to-rail output. This feature permits that tight control of gate voltage during on-state and short circuit can be maintained as long as the drivers supply is stable. Due to the low internal voltage drop, switching behaviour of the IGBT is predominantly governed by the gate resistor. Furthermore, it reduces the power to be dissipated by the driver.4.6Two-Level Turn-OffThe Two-Level Turn-OFF introduces a second turn off voltage level at the driver output in between ON- and OFF-level, refer to Figure8. This additional level ensures lower V CE overshoots at turn off by reducing gate emitter voltage of the IGBT at short circuits or over current events. The V GE level is adjusting the current of the IGBT at the end two level turn off interval, the required timing is depending on stray inductance and over current at beginning of two level turn off interval.Reference voltage level and hold up time could be adjusted at TLSET pin. The reference voltage is set by the required Zener diode connected between pin TLSET and GND2. The holdup time is set by the capacitor connected to the same pin TLSET and GND2.The hold time can be adjusted during switch on using the whole capacitance connected at pin TLSET including capacitor, parasitic wiring capacitance and junction capacitance of Zener diode. When a switch on signal is given the IC starts to discharge C TLSET. Discharging C TLSET is stopped after 500ns. Then Ctlset is charged with an internal charge current I TLSET. When the voltage of the capacitor C TLSET exceeds 7V a second current source starts charging C TLSET up to V ZDIODE. At the end of this discharge-charge cycle the gate driver is switched on.The time between IN initiated switch-on signal (minus an internal propagation delay of approximately 200ns) and switch-on of the gate drive is sampled and stored digitally. It represents the two level turn off set time T TLSET during switch-off. Due to digitalization the tpdon time can vary in time steps of 50ns.If switch off is initiated from IN+, IN- or /RST signal, the gate driver is switched off immediately after internal propagation delay of approximately 200ns and V OUT begins to decrease to the second gate voltage level.For switch off initiated by DESAT, the gate driver switch off is delayed by desaturation sense to OUT delay, afterwards V OUT begins to decrease to the second gate voltage level.For reaching second gate voltage level the output voltage V OUT is sensed and compared with the Zener voltage V ZDIODE. When V OUT falls below the reference voltage V ZDIODE of the Zener diode the switch off process is interrupted and V OUT is adjusted to V ZDIODE. OUT is switched to VEE2 after the holdup time has passed.The Two-Level Turn-OFF function cannot be disabled.Functional DescriptionMinimal On Time / Off Time4.7Minimal On Time / Off TimeThe 1ED020I12FTA driver requires minimal on and off time for proper operation in the application. Minimal on time must be greater than the adjustable two level plateau time T TLSET, shorter on times will be suppressed by generating of the plateau time refer to Figure10. Due to the short on time, the voltage at TLSET pin does not reach the comparator threshold; therefore the driver does not turn on. A similar principle takes place for off time. Minimal off time must be greater than T TLSET; shorter off times will be suppressed, which means OUT stays on refer to Figure11. A two level turn off plateau cannot be shortened by the driver. If the driver has entered the turn off sequence it cannot switch off due to the fact, that the driver has already entered the shut off mode. But if the driver input signal is turned on again, it will leave the lower level after T TLSET time by switching OUT to high, refer to Figure12.4.8External Protection Features4.8.1Desaturation ProtectionA desaturation protection ensures the protection of the IGBT at short circuit. When the DESAT voltage goes up and reaches 9V, the output is driven low, refer to Figure9. Further, the FAULT output is activated. A programmable blanking time is used to allow enough time for IGBT saturation. Blanking time is provided by a highly precise internal current source and an external capacitor.4.8.2Active Miller ClampIn a half bridge configuration the switched off IGBT tends to dynamically turn on during turn on phase of the opposite IGBT. A Miller clamp allows sinking the Miller current across a low impedance path in this high dV/dt situation. Therefore in many applications, the use of a negative supply voltage can be avoided.During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes below typical 2 V (related to VEE2). The clamp is designed for a Miller current up to 2 A.4.8.3Short Circuit ClampingDuring short circuit the IGBTs gate voltage tends to rise because of the feedback via the Miller capacitance. An additional protection circuit connected to OUT and CLAMP limits this voltage to a value slightly higher than the supply voltage. A current of maximum 500mA for 10μs may be fed back to the supply through one of this paths. If higher currents are expected or a tighter clamping is desired external Schottky diodes may be added.4.9RESETThe reset input has two functions.Firstly, /RST is in charge of setting back the FAULT output. If /RST is low longer than a given time, /FLT will be cleared at the rising edge of /RST, refer to Figure9; otherwise, it will remain unchanged. Moreover, it works as enable/shutdown of the input logic, refer to Figure7.。
TFS246B中文资料
______________________________________________________________________________________________________VI TELEFILTER Vectron International, Inc.Potsdamer Straße 18 267 Lowell Road D 14 513 TELTOW / Germany Hudson, NH 03051 / USA Tel: (+49) 3328 4784-52 / Fax: (+49) 3328 4784-30 Tel: (603) 598-0070 Fax: (603) 598-0075E-Mail: tft@ E-Mail: vti@Measurement conditionAmbient temperature:23°C Input power level:0dBmTerminating impedance: 340 Ohms || -5 pF External coil: 100 nHConstruction and pin connectionsee page 2CharacteristicsRemark:Reference level for the relative attenuation a rel of the TFS 246 B is the minimum of the pass band attenuation a min . The minimum of the pass band attenuation a min is defined as the insertion loss a e . The centre frequency f o is the arithmetic mean value of the upper and lower frequencies at the 3 dB filter attenuation level relative to the insertion loss a e . The nominal frequency f N is fixed on 246,0 MHz without tolerance. The given values for the relative attenuation a rel and for the group delay ripple have to be reached at the frequencies given below also if the centre frequency f o is shifted due to the temperature coefficient of frequency TC f in the operating temperature range and due to a production tolerance for the centre frequency f o .D a t atyp. value tolerance / limit______________________________________________________________________________________________________Insertion lossa e = a min 6dB max8dB (Reference level)______________________________________________________________________________________________________Centre frequencyf o 246,0MHz -______________________________________________________________________________________________________Relative attenuation a rel246,0 MHz ±80kHz -max 3dB 246,0 MHz ±200kHz ...246,0 MHz ±400kHz 12dB min 2dB 246,0 MHz ±400kHz ...246,0 MHz ±600kHz 34dB min 25dB 246,0 MHz ±600kHz ...246,0 MHz ±1,6MHz 40dB min 35dB 246,0 MHz ±1,6MHz ...246,0 MHz ±3MHz 50dB min 45dB 246,0 MHz ±3MHz ...246,0 MHz ±25MHz> 50dBmin 50dBNarrowband spurious resonances (1dB-bandwith < 35 kHz in f 0 + 600 kHz to f 0 + 1 MHz) min 32dB ______________________________________________________________________________________________________Group delayGD 3,6µs -Group delay ripple 246,0 MHz ±50kHz 1µs max 1,2µs______________________________________________________________________________________________________Operating temperature range - 20 °C ... + 85 °C______________________________________________________________________________________________________Temperature coefficient of frequency TCca. - 0,036 ppm/K²______________________________________________________________________________________________________Frequency inversion temperature + 20 ... + 30 °C______________________________________________________________________________________________________generated:checked / approved:Construction, pin connection and 50 Ω - matching networkTFS246Btft H3______________________________________________________________________________________________________ VI TELEFILTER Vectron International, Inc.Potsdamer Straße 18 267 Lowell RoadD 14 513 TELTOW / Germany Hudson, NH 03051 / USATel: (+49) 3328 4784-52 / Fax: (+49) 3328 4784-30 Tel: (603) 598-0070 Fax: (603) 598-0075 E-Mail: tft@ E-Mail: vti@______________________________________________________________________________________________________VI TELEFILTER Vectron International, Inc.Potsdamer Straße 18 267 Lowell Road D 14 513 TELTOW / Germany Hudson, NH 03051 / USA Tel: (+49) 3328 4784-52 / Fax: (+49) 3328 4784-30 Tel: (603) 598-0070 Fax: (603) 598-0075E-Mail: tft@ E-Mail: vti@Stability characteristicsAfter the following tests the filter shall meet the whole specification:1. Shock:30g, 18 ms, half sine wave, 3 shocks each plane;DIN IEC 68 T2 - 272. Vibration:10 Hz to 150 Hz, 0.35 mm amplitude, 5g; 2 hours for 3 planes;DIN IEC 68 T2 - 63. Damp heat:90 % to 95 % rel. humidity, 40 °C, 10 days;IEC Pub. 68 - 2 - 34. Resistance tosolder heat (Reflow):260 °C for 10 sec;PackingTape & Reel:DIN IEC 286 - 3, with exception of value for N and minimum bending radius;tape type II , embossed carrier tape with top cover tape on the upper side;max. pieces of filters per reel: 2300COVER TAPETape (all dimensions in mm)W : 16 ± 0,3Po : 4 ± 0,1Do : 1,5 + 0,5 E : 1,75 ± 0,1F : 7,5 ± 0,1G (min) : 0,75P2 : 2 ± 0,1P1 : 12 ± 0,1D1(min) : 1,5Ao : 7,6 ± 0,1Bo : 9,6 ± 0,1D1 : 1,5 + 0,5 NW 1W 2Reel (all dimensions in mm):A : 330W1 : 16,4 +2W2 (max) : 22,4N (min) : >= 90C : 13 ± 0,25The minimum bending radius is 45 mm. The mounting surface of the filters faces the bottom side of the embossed carrier tape.The marking of the filters is able to read if the view is directed on the upper side of the carrier tape with the sprocket holes on the right side of the tape.Air reflow temperature conditions1st and 2nd air reflow profileName:pre-heating periods main-heating periods peak temperatureTemperature:150 °C - 170 °C over 200 °C 255 °C ± 5 °CTime:60 sec. - 90 sec.20 sec. - 25 sec.Tolerance of temperatures: ± 5 °Ctime / sec. temperature / °C time / sec. temperature / °C02314016010341501612046160164306017017040801801805010319020560121195230701342002558014320523090150210205100154215180110156220165120158230140130159240120______________________________________________________________________________________________________ VI TELEFILTER Vectron International, Inc.Potsdamer Straße 18 267 Lowell RoadD 14 513 TELTOW / Germany Hudson, NH 03051 / USATel: (+49) 3328 4784-52 / Fax: (+49) 3328 4784-30 Tel: (603) 598-0070 Fax: (603) 598-0075 E-Mail: tft@ E-Mail: vti@。
Q4B_Annex_12_R1__Step_4
ICH地区所用药典内容评估和推荐分析筛分法通则Q4B 附件12现行第四版本，2010年6月9日发布Q4B 附件12文件历史编码历史日期Q4B 附件12 指导委员会批准进入第二阶段，公开征求意见。
2009年10月29日现行第四版本Q4B 附件12 指导委员会批准进入第四阶段，并推荐给ICH三方地区法规机2010年6月9日构采纳。
目录1. 介绍 (2)2. Q4B结果 (2)2.1 分析程序 (2)2.2可接受标准 (2)3. 附录实施时间 (2)4. 实施的考虑 (2)4.1 一般考虑 (2)4.2 FDA考虑 (2)4.3 EU考虑 (2)4.4 MHLW考虑 (2)4.5加拿大卫生部考虑 (2)5. 此次Q4B评估所引用文献 (3)分析筛分法1. 介绍本附件为Q4B“分析筛分法”通则评估的结果，由药典讨论组（PDG）递交草案。
2. Q4B结果2.1 分析程序ICH指导委员会基于Q4B专家工作组的评估，推荐官方药典文本，即欧洲药典通则2.9.38.“分析筛分方法评估粒度分布”、日本药典3.04“粒度测定法---第二法：分析筛分法”及美国药典通则<786>“分析筛分方法评估粒度分布”作为ICH地区间可互换应用的指导文本。
2.2可接受标准无可接受标准。
3. 附录实施时间本附件在区域内实施（结合法规进度ICH第5阶段），即可用于该区域。
实施时间因区域不同。
4. 实施的考虑4.1 一般考虑：在申请人或生产商将现有方法变更为Q4B 本附件2.1部分中评估过的药典正文时，应根据已有的当地包括药典变更的药政原理进行变更申明、差异，和/或预批准程序。
4.2 FDA的考虑：基于上述推荐，与本附件中设定条件一致时，在本附件2.1部分中引用的药典正文应作为是可互换的。
但是，FDA可能会要求企业证明所选择的方法是可以接受的，适用于特定的物料或产品，而不考虑方法的来源。
4.3 EU的考虑：对于欧盟地区，欧洲药典各论是强制实行的。
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Turn over P40132A©2012 Pearson Education Ltd.1/1/1/*P40132A0124*Instructionst Use black ink or ball-point pen.t Fill in the boxes at the top of this page with your name,centre number and candidate number.t Answer all questions.t Answer the questions in the spaces provided– there may be more space than you need.t Show all the steps in any calculations and state the units.Informationt The total mark for this paper is 120.t The marks for each question are shown in brackets– use this as a guide as to how much time to spend on each question.Advicet Read each question carefully before you start to answer it.t Keep an eye on the time.t Write your answers neatly and in good English.t Try to answer every question.t Check your answers if you have time at the end.2*P40132A0224*3*P40132A0324*Turn over4*P40132A0424*5*P40132A0524*Turn over(b) John varied the temperature of the water bath between 15 °C and 65 °C. Hemeasured the rate of carbon dioxide production by counting the number ofbubbles per minute.(i) Sketch the shape of the graph that John would obtain on the axes below.(3)(ii) Give the dependent variable in this experiment.(1).................................................................................................................................................................................................................................................................................... (iii) Give the independent variable in this experiment.(1).................................................................................................................................................................................................................................................................................... (c) Give two variables that John would need to keep the same in his experiment.(2)1 ...............................................................................................................................................................................................................................................................................2 ...............................................................................................................................................................................................................................................................................rate ofcarbon dioxideproductionin bubblesper minutetemperaturein °C6*P40132A0624*(d) Suggest one way that John could improve the reliability of his experiment.(1)................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ (e) Suggest how John could improve the accuracy of his measurement of the rate ofcarbon dioxide production.(1)................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ (f) Yeast is used to produce beer.Write the word equation for the respiration of yeast that occurs during theproduction of beer.(3)....................................................................................................................................................................................................................................................................................(Total for Question 3 = 14 marks)7*P40132A0724*Turn over8*P40132A0824*5 Crop plants are often grown in glasshouses where conditions can be carefully controlled.This is done in order to get the greatest crop yield.(a) Explain how the following factors could affect crop yield.(i) Increasing the temperature of the glasshouse(3).................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... (ii) Providing a supply of fertiliser to the crop plants(3)....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................9*P40132A0924*Turn over(b) Sometimes a farmer needs to control an insect pest that might damage his crops. He can do this by using either biological control or a chemical pesticide.(i) Describe one example of the use of biological control.(2).................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... (ii) Give three advantages of using biological control instead of a chemical pesticide.(3)1 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................2 ...................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................3 ....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................(Total for Question 5 = 11 marks)10*P40132A01024*6 The photographs show an adult insect called an ash borer and an adult insect calleda wasp.ash borer waspAsh borers reproduce by laying eggs which develop into maggots. The maggots eat theirway into ash trees and feed on carbohydrates in the trees. This can kill the trees becausethe root cells lack the carbohydrate needed to release energy for the absorption ofmineral ions.(a) (i) Suggest why the maggots need to feed on carbohydrate.(1)........................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................ (ii) Name and describe the process used by root cells to absorb mineral ions.(2).................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................... (iii) Describe how magnesium ions are used to help trees to grow.(2)....................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................(b) Wasps defend themselves from predators by using a sting. This means that predatorsavoid attacking wasps.Ash borers look very similar to wasps.Use your knowledge of natural selection to explain why ash borers have evolvedto look like wasps.(4) .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... ....................................................................................................................................................................................................................................................................................(Total for Question 6 = 9 marks)7Achondroplasia is an inherited condition in humans. Adults with achondroplasia are much shorter than average height.This condition is controlled by a gene with two alleles. The dominant allele (A) codes for shorter than average height and the recessive allele (a) codes for average height.(a) Two parents both had achondroplasia. They had a child who grew up to be ofaverage height.Use a genetic diagram to show:x the genotype of each parentx the gametes they producedx the genotypes of all the possible offspringx the phenotypes of all the possible offspring(4)(b) The parents had a second child.State the probability that this child grew up to be of average height.(1) ....................................................................................................................................................................................................................................................................................(c) Achondroplasia is caused by a dominant allele.(i) Explain what is meant by the term dominant allele.(2) .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... ....................................................................................................................................................................................................................................................................................(ii) Suggest why the number of people with achondroplasia is low, even though it is a dominant condition.(2) .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... ....................................................................................................................................................................................................................................................................................(Total for Question 7 = 9 marks)(c) Some scientists think that the release of greenhouse gases has contributed to thesechanges in temperature.(i) Name a greenhouse gas.(1) ....................................................................................................................................................................................................................................................................................(ii) What is meant by the term greenhouse gas?(1) .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... ....................................................................................................................................................................................................................................................................................(iii) Suggest how human activities could be responsible for the change in temperature between 1970 and 1995.(3) .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... .................................................................................................................................................................................................................................................................................... ....................................................................................................................................................................................................................................................................................(Total for Question 8 = 12 marks)。