pichiapink_strain_secsig_media_man
Bosch NDC-265-P 720p IP Dome Camera 说明书
The Bosch NDC-265-P 720p IP dome camera is a ready-to-use, complete network video surveillance system inside a compact camera. This camera brings Bosch’s high-performance technology into the realm of small office and retail businesses by offering a cost-effective solution for a broad range of applications.To use the camera as a stand-alone video surveillance system, simply take it out of the box, assemble it according to the quick installation guide, start it, and walk away – it’s already recording. In this mode, no additional equipment is required.For medium-to-large-scale or growing systems, the camera easily integrates with the Bosch Divar 700 Series recorder. It uses H.264 compression technology to give clear images while reducing bandwidth and storage by up to 30%.FunctionsBest-in-class HD 720p image performanceThe camera delivers the clearest HD 720p images and most accurate colors within its class. Progressive scan ensures moving objects are always sharp.Tri-streaming videoTri-streaming allows a data stream to be encoded simultaneously according to different, customized settings. Two types of streams can serve different purposes. For example, use H.264 stream for local recording and viewing, and the M-JPEG stream to provide compatibility with legacy DVRs.Efficient recordingA removable microSD/SDHC card offers edge recording inside the IP dome camera. This card not only saves network bandwidth but also reduces the requirement for a high-capacity hard disk or DVR. When used with a microSD/SDHC card, the camera is a complete, self-contained surveillance system without the need for additional equipment.The camera can also be used with an iSCSI server connected via the network to store long-term recordings. 16-channel PC surveillance softwareThe bundled PC surveillance software offers a user-friendly interface to support easy installation and configuration. A wizard allows the configuration of multiple cameras simultaneously using an auto detection device. Multiple cameras can be monitored in one screen and video clips on microSD/SDHC cards can be archived, searched, and exported in a single application.NDC-265-P HD 720p IP Dome Camera▶Complete network video surveillance system inside adome camera▶HD 720p progressive scan for sharp images of movingobjects▶Tri-streaming: Dual H.264 and M-JPEG simultaneously▶Removable microSD/SDHC card offers days ofstorage inside camera▶PC surveillance software supports multiple cameramonitoring▶Two-way audio and audio alarm▶Power over Ethernet (IEEE 802.3af compliant)▶ONVIF conformant2ONVIF 1.0 conformantThe latest Open Network Video Interface Forum (ONVIF) standard ensures compatibility with other surveillance products. This will contribute to a reduction in future upgrade or migration costs.Two-way audio and audio alarmTwo-way audio allows remote users to listen in on an area and communicate messages to visitors or intruders via an external loudspeaker (not included). Audio detection can be used to generate an alarm, if needed.Tamper and motion detectionA wide range of configuration options is available for alarms signaling camera tampering. A built-in algorithm for detecting movement in the video can also be used for alarm signaling.Power-over-EthernetPower for the camera can be supplied via a Power-over-Ethernet (IEEE 802.3af) compliant network cable connection. With this configuration, only a single cable connection is required to view, power, and control the camera.Certifications and ApprovalsSafety EU: EN 60950-1: 2006,Reference IEC 60950-1:2005US: UL 60950-1:1st edition dated October 31, 2007Canada: CAN/CSA-C22.2 NO. 60950-1-03EMC EN 50130-4:1995 + A1:1998 + A2:2003FCC Part15 Subpart B, Class BEMC directive 2004/108/ECEN 55022 class BEN 61000-3-2 :2006EN 61000-3-3 : 1995+A1 :2001+A2 :2005EN 55024AS/NZS CISPR 22 (equal to CISPR 22)ICES-003 Class BEN 50121-4:2006Product Certifica-tionsCE, FCC, UL, cUL, C-tick, CB, VCCIPower supply CE, UL, cUL, PSE, CCC Installation/Configuration NotesConnections1I/O2Power 12 VDC3Ethernet RJ454Audio Line-out5Audio Line-inDimensionsmm (in)Parts IncludedQuantity Component1NDC-265-P 720p IP Dome camera1Quick Installation Guide1Installation paper sticker1Torx screwdriver for Dome cover1CD ROM1Camera fixing screw kit1MicroSDHC card (warranty provided by card manufacturer) 1Universal power supply with US, EU and UK plug3Technical SpecificationsPowerInput voltage+12 VDC orPower-over-EthernetPower consumption 4.2 W (max)VideoSensor type¼-inch CMOSSensor pixels1280 x 800Sensitivity 1.0 lxVideo resolution720p, 4CIF/D1, VGA, CIF, QVGA Video compression H.264 MP (Main Profile); H.264 BP+(Baseline Profile Plus); M-JPEGMax. frame rate30 fps (M-JPEG frame rate can vary de-pending on system loading)LensLens type Varifocal 2.7 to 9 mm, DC Iris F1.2 tocloseLens mount Board mountedConnectionAnalog video out 2.5 mm jack for installation onlyAlarm input Short or DC 5V activationRelay out Input rating Maximum 1 A 24 VAC/VDC AudioAudio input Built-in microphoneLine in jack connectorAudio output Line out jack connectorAudio communication Two-way, full duplexAudio compression G.711, L16 (live and recording)Local StorageMemory card slot Supports up to 32 GB microSD/SDHCcard(An SD card of Class 4 or higher is recom-mended for HD recording) Recording Continuous recording, ring recording.alarm/events/schedule recording Software ControlUnit configuration Via web browser or PC surveillance soft-wareNetworkProtocols HTTP, HTTPs, SSL, TCP, UDP, ICMP,RTSP, RTP, Telnet, IGMPv2/v3, SMTP,SNTP, FTP, DHCP client, ARP, DNS,DDNS, NTP, SNMP, UPnP, 802.1X, iSCSI Ethernet10/100 Base-T, auto-sensing, half/full du-plex, RJ45PoE IEEE 802.3af compliant MechanicalDimensions Diameter: 135 mm (5.32 in)Height: 102 mm (4 in)Weight568 g (1.25 lb) approx. EnvironmentalOperating temperatureCamera-10 ºC to +50 ºC (14 ºF to +122 ºF)Operating temperatureUniversal Power Supply Unit0 ºC to +40 ºC (+32 ºF to +104 ºF) Storage temperature-20 ºC to +70 ºC (-4 ºF to +158 ºF) Humidity10% to 80% relative humidity (non con-densing)Ordering InformationNDC-265-P 720p IP Dome CameraHD 720p IP Dome Camera System includingvarifocal lens and power supplyNDC-265-P4Americas:Bosch Security Systems, Inc. 130 Perinton Parkway Fairport, New York, 14450, USA Phone: +1 800 289 0096 Fax: +1 585 223 9180***********************.com Europe, Middle East, Africa:Bosch Security Systems B.V.P.O. Box 800025600 JB Eindhoven, The NetherlandsPhone: + 31 40 2577 284Fax: +31 40 2577 330******************************Asia-Pacific:Robert Bosch (SEA) Pte Ltd, Security Systems11 Bishan Street 21Singapore 573943Phone: +65 6258 5511Fax: +65 6571 2698*****************************Represented by© Bosch Security Systems Inc. 11 | Data subject to change without notice T7233796747 | Cur: en-US, V2, 5 Jan 2011。
SDIO spec
f in eo nIn fio nI n fTechnical Committee SD Card Associationf in eo nIn fi ne o n I nf in eo nIRevision HistoryDate Version Changes compared to previous issueApril 3, 2006 1.10 Simplified Version Initial ReleaseFebruary 8, 20072.00(1) Added method to change bus speed (Normal Speed up to 25MHzand High Speed up to 50 MHz)(2) Operational Voltage Requirement is extended to 2.7-3.6V(3) Combine sections 12 (Physical Properties) and 13 (MechanicalExtensions) and add miniSDIO to the new section 13 (Physical Properties)(4) Add Embedded SDIO ATA Standard Function Interface Code (5) Reference of Physical Ver2.00 supports SDHC combo card. (6) Some typos in Ver1.10 are fixed.f in eo nIn fi ne o n I nf in eo nI Release of SD Simplified SpecificationThe following conditions apply to the release of the SD simplified specification ("Simplified Specification") by the SD Card Association. The Simplified Specification is a subset of the complete SD Specification which is owned by the SD Card Association.Publisher:SD Association2400 Camino Ramon, Suite 375 San Ramon, CA 94583 USA Telephone: +1 (925) 275-6615 Fax: +1 (925) 886-4870 E-mail: office@Copyright Holder: The SD Card AssociationNotes:This Simplified Specification is provided on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified Specification may require a license from the SD Card Association or other third parties.Disclaimers:The information contained in the Simplified Specification is presented only as a standard specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any representations or warranties of any kind. No responsibility is assumed by the SD Card Association for any damages, any infringements of patents or other right of the SD Card Association or any third parties, which may result from its use. No license is granted by implication, estoppel or otherwise under any patent or other rights of the SD Card Association or any third party. Nothing herein shall be construed as an obligation by the SD Card Association to disclose or distribute any technical information, know-how or other confidential information to any third party.f in eo nIn fi ne o n I nf in eo nConventions Used in This DocumentNaming ConventionsSome terms are capitalized to distinguish their definition from their common English meaning. Words not capitalized have their common English meaning.Numbers and Number BasesHexadecimal numbers are written with a lower case “h” suffix, e.g., FFFFh and 80h. Binary numbers are written with a lower case “b” suffix (e.g., 10b).Binary numbers larger than four digits are written with a space dividing each group of four digits, as in 1000 0101 0010b.All other numbers are decimal.Key WordsMay: Indicates flexibility of choice with no implied recommendation or requirement.Shall: Indicates a mandatory requirement. Designers shall implement such mandatory requirements to ensure interchangeability and to claim conformance with the specification.Should: Indicates a strong recommendation but not a mandatory requirement. Designers should give strong consideration to such recommendations, but there is still a choice in implementation.Application NotesSome sections of this document provide guidance to the host implementers as follows: Application Note:This is an example of an application note.f in eo nIn fi ne o n I nf in eo nTable of Contents1. General Description.................................................................................................................................1 1.1 SDIO Features....................................................................................................................................1 1.2 Primary Reference Document.............................................................................................................1 1.3 Standard SDIO Functions....................................................................................................................1 2. SDIO Signaling Definition........................................................................................................................2 2.1 SDIO Card Types................................................................................................................................2 2.2 SDIO Card modes...............................................................................................................................2 2.2.1 SPI (Card mandatory support).....................................................................................................2 2.2.2 1-bit SD Data Transfer Mode (Card Mandatory Support).............................................................2 2.2.3 4-bit SD Data Transfer Mode (Mandatory for High-Speed Cards, Optional for Low-Speed).........2 2.3 SDIO Host Modes...............................................................................................................................2 2.4 Signal Pins..........................................................................................................................................3 3. SDIO Card Initialization............................................................................................................................4 3.1 Differences in I/O card Initialization.....................................................................................................4 3.2 The IO_SEND_OP_COND Command (CMD5).................................................................................10 3.3 The IO_SEND_OP_COND Response (R4)........................................................................................11 3.4 Special Initialization considerations for Combo Cards.......................................................................12 3.4.1 Re-initialize both I/O and Memory..............................................................................................12 3.4.2 Using a Combo Card as SDIO only or SD Memory only after Combo Initialization....................12 3.4.3 Acceptable Commands after Initialization..................................................................................12 3.4.4 Recommendations for RCA after Reset.....................................................................................12 3.4.5 Enabling CRC in SPI Combo Card.............................................................................................14 4. Differences with SD Memory Specification..........................................................................................15 4.1 SDIO Command List.........................................................................................................................15 4.2 Unsupported SD Memory Commands...............................................................................................15 4.3 Modified R6 Response......................................................................................................................16 4.4 Reset for SDIO..................................................................................................................................16 4.5 Bus Width..........................................................................................................................................16 4.6 Card Detect Resistor.........................................................................................................................17 4.7 Timings..............................................................................................................................................17 4.8 Data Transfer Block Sizes.................................................................................................................18 4.9 Data Transfer Abort...........................................................................................................................18 4.9.1 Read Abort.................................................................................................................................18 4.9.2 Write Abort.................................................................................................................................18 4.10 Changes to SD Memory Fixed Registers..........................................................................................18 4.10.1 OCR Register.............................................................................................................................19 4.10.2 CID Register...............................................................................................................................19 4.10.3 CSD Register.............................................................................................................................19 4.10.4 RCA Register.............................................................................................................................19 4.10.5 DSR Register.............................................................................................................................19 4.10.6 SCR Register.............................................................................................................................19 4.10.7 SD Status...................................................................................................................................19 4.10.8 Card Status Register..................................................................................................................19 5. New I/O Read/Write Commands............................................................................................................21 5.1 IO_RW_DIRECT Command (CMD52)..............................................................................................21 5.2 IO_RW_DIRECT Response (R5)......................................................................................................22 5.2.1 CMD52 Response (SD modes)..................................................................................................22 5.2.2 R5, IO_RW_DIRECT Response (SPI mode).............................................................................23 5.3 IO_RW_EXTENDED Command (CMD53). (24)f in eo nIn fi ne o n I nf in eo nI 5.3.2 Special Timing for CMD53 Multi-Block Read..............................................................................25 6. SDIO Card Internal Operation................................................................................................................26 6.1 Overview...........................................................................................................................................26 6.2 Register Access Time........................................................................................................................26 6.3 Interrupts...........................................................................................................................................26 6.4 Suspend/Resume..............................................................................................................................27 6.5 Read Wait..........................................................................................................................................27 6.6 CMD52 During Data Transfer............................................................................................................27 6.7 SDIO Fixed Internal Map...................................................................................................................27 6.8 Common I/O Area (CIA)....................................................................................................................28 6.9 Card Common Control Registers (CCCR).........................................................................................28 6.10 Function Basic Registers (FBR)........................................................................................................35 6.11 Card Information Structure (CIS).......................................................................................................37 6.12 Multiple Function SDIO Cards...........................................................................................................37 6.13 Setting Block Size with CMD53.........................................................................................................37 6.14 Bus State Diagram............................................................................................................................38 7. Embedded I/O Code Storage Area (CSA).............................................................................................39 7.1 CSA Access.......................................................................................................................................39 7.2 CSA Data Format..............................................................................................................................39 8. SDIO Interrupts.......................................................................................................................................40 8.1 Interrupt Timing.................................................................................................................................40 8.1.1 SPI and SD 1-bit Mode Interrupts ..............................................................................................40 8.1.2 SD 4-bit Mode............................................................................................................................40 8.1.3 Interrupt Period Definition ..........................................................................................................40 8.1.4 Interrupt Period at the Data Block Gap in 4-bit SD Mode (Optional)..........................................40 8.1.5 Inhibited Interrupts (Removed Section)......................................................................................40 8.1.6 End of Interrupt Cycles...............................................................................................................40 8.1.7 Terminated Data Transfer Interrupt Cycle ..................................................................................41 8.1.8 Interrupt Clear Timing.................................................................................................................41 9. SDIO Suspend/Resume Operation........................................................................................................42 10. SDIO Read Wait Operation.....................................................................................................................43 11. Power Control.........................................................................................................................................44 11.1 Power Control Overview....................................................................................................................44 11.2 Power Control support for SDIO Cards.............................................................................................44 11.2.1 Master Power Control ................................................................................................................44 11.2.2 Power Selection.........................................................................................................................45 11.2.3 High-Power Tuples.....................................................................................................................45 11.3 Power Control Support for the SDIO Host.........................................................................................45 11.3.1 Version 1.10 Host.......................................................................................................................45 11.3.2 Power Control Operation............................................................................................................46 12. High-Speed Mode...................................................................................................................................47 12.1 SDIO High-Speed Mode....................................................................................................................47 12.2 Switching Bus Speed Mode in a Combo Card...................................................................................47 13. SDIO Physical Properties......................................................................................................................48 13.1 SDIO Form Factors...........................................................................................................................48 13.2 Full-Size SDIO ..................................................................................................................................48 13.3 miniSDIO...........................................................................................................................................48 14. SDIO Power.............................................................................................................................................48 14.1 SDIO Card Initialization Voltages......................................................................................................48 14.2 SDIO Power Consumption................................................................................................................48 15. Inrush Current Limiting..........................................................................................................................50 16. CIS Formats.. (51)f in eo nIn fi ne o n I nf in eo nI 16.2 Basic Tuple Format and Tuple Chain Structure.................................................................................51 16.3 Byte Order Within Tuples ..................................................................................................................51 16.4 Tuple Version ....................................................................................................................................52 16.5 SDIO Card Metaformat......................................................................................................................52 16.6 CISTPL_MANFID: Manufacturer Identification String Tuple..............................................................53 16.7 SDIO Specific Extensions..................................................................................................................53 16.7.1 CISTPL_FUNCID: Function Identification Tuple.........................................................................53 16.7.2 CISTPL_FUNCE: Function Extension Tuple..............................................................................54 16.7.3 CISTPL_FUNCE Tuple for Function 0 (common).......................................................................54 16.7.4 CISTPL_FUNCE Tuple for Function 1-7....................................................................................55 16.7.5 CISTPL_SDIO_STD: Function is a Standard SDIO Function.....................................................58 16.7.6 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards...............................................................58 Appendix A.....................................................................................................................................................59 A.1 SD and SPI Command List....................................................................................................................59 Appendix B.....................................................................................................................................................61 B.1 Normative References...........................................................................................................................61 Appendix C.....................................................................................................................................................62 C.1 Abbreviations and Terms...................................................................................................................62 Appendix D.. (64)f in eo nIn fi ne o n I nf in eo nI Table of TablesTable 3-1 OCR Values for CMD5.....................................................................................................................10 Table 4-1 Unsupported SD Memory Commands.............................................................................................16 Table 4-2 R6 response to CMD3.....................................................................................................................16 Table 4-3 SDIO R6 Status Bits.........................................................................................................................16 Table 4-4 Combo Card 4-bit Control................................................................................................................17 Table 4-5 Card Detect Resistor States.............................................................................................................17 Table 4-6 is blanked.........................................................................................................................................17 Table 4-7 SDIO Status Register Structure .......................................................................................................20 Table 5-1 Flag data for IO_RW_DIRECT SD Response..................................................................................23 Table 5-2 IO_RW_ EXTENDED command Op Code Definition.......................................................................24 Table 5-3 Byte Count Values ...........................................................................................................................25 Table 6-1 Card Common Control Registers (CCCR).......................................................................................29 Table 6-2 CCCR bit Definitions........................................................................................................................34 Table 6-3 Function Basic Information Registers (FBR)....................................................................................35 Table 6-4 FBR bit and field definitions.............................................................................................................36 Table 6-5 Card Information Structure (CIS) and reserved area of CIA.............................................................37 Table 11-1 Reference Tuples by Master Power Control and Power Select......................................................45 Table 16-1 Basic Tuple Format........................................................................................................................51 Table 16-2 Tuples Supported by SDIO Cards..................................................................................................52 Table 16-3 CISTPL_MANFID: Manufacturer Identification Tuple.....................................................................53 Table 16-4 CISTPL_FUNCID Tuple.................................................................................................................53 Table 16-5 CISTPL_FUNCE Tuple General Structure.....................................................................................54 Table 16-6 TPLFID_FUNCTION Tuple for Function 0 (common)....................................................................54 Table 16-7 TPLFID_FUNCTION Field Descriptions for Function 0 (common).................................................54 Table 16-8 TPLFID_FUNCTION Tuple for Function 1-7..................................................................................55 Table 16-9 TPLFID_FUNCTION Field Descriptions for Functions 1-7.............................................................57 Table 16-10 TPLFE_FUNCTION_INFO Definition...........................................................................................57 Table 16-11 TPLFE_CSA_PROPERTY Definition...........................................................................................57 Table 16-12 CISTPL_SDIO_STD: Tuple Reserved for SDIO Cards................................................................58 Table 16-13 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards.................................................................58 Table A-14 SD Mode Command List................................................................................................................59 Table A-15 SPI Mode Command List (60)f in eo nIn fi ne o n I nf in eo nI Table of FiguresFigure 2-1 Signal connection to two 4-bit SDIO cards.......................................................................................3 Figure 3-1 SDIO response to non-I/O aware initialization..................................................................................4 Figure 3-2 Card initialization flow in SD mode (SDIO aware host)....................................................................7 Figure 3-3 Card initialization flow in SPI mode (SDIO aware host)....................................................................9 Figure 3-4 IO_SEND_OP_COND Command (CMD5).....................................................................................10 Figure 3-5 Response R4 in SD mode...............................................................................................................11 Figure 3-6 Response R4 in SPI mode..............................................................................................................11 Figure 3-7 Modified R1 Response....................................................................................................................11 Figure 3-8 Re-Initialization Flow for I/O Controller...........................................................................................13 Figure 3-9 Re-Initialization Flow for Memory controller ...................................................................................13 Figure 5-1 IO_RW_DIRECT Command...........................................................................................................21 Figure 5-2 R5 IO_RW_DIRECT Response (SD modes)..................................................................................22 Figure 5-3 IO_RW_DIRECT Response in SPI Mode.......................................................................................23 Figure 5-4 IO_RW_EXTENDED Command.....................................................................................................24 Figure 6-1 SDIO Internal Map..........................................................................................................................28 Figure 6-2 State Diagram for Bus State Machine (38)f in eo nIn fi ne o n I nf in eo nI 1. General DescriptionThe SDIO (SD Input/Output) card is based on and compatible with the SD memory card. This compatibility includes mechanical, electrical, power, signaling and software. The intent of the SDIO card is to provide high-speed data I/O with low power consumption for mobile electronic devices. A primary goal is that an SDIO card inserted into a non-SDIO aware host shall cause no physical damage or disruption of that host or it’s software. In this case, the SDIO card should simply be ignored. Once inserted into an SDIO aware host, the detection of the card proceeds via the normal means described in this specification with some extensions. In this state, the SDIO card is idle and draws a small amount of power (15 mA averaged over 1 second). During the normal initialization and interrogation of the card by the host, the card identifies itself as an SDIO card. The host software then obtains the card information in a tuple (linked list) format and determines if that card’s I/O function(s) are acceptable to activate. This decision is based on such parameters as power requirements or the availability of appropriate software drivers. If the card is acceptable, it is allowed to power up fully and start the I/O function(s) built into it.1.1 SDIO Features• Targeted for portable and stationary applications• Minimal or no modification to SD Physical bus is required • Minimal change to memory driver software• Extended physical form factor available for specialized applications • Plug and play (PnP) support• Multi-function support including multiple I/O and combined I/O and memory • Up to 7 I/O functions plus one memory supported on one card. • Allows card to interrupt host• Operational Voltage range: 2.7-3.6V (Operational Voltage is used for Initialization) • Application Specifications for Standard SDIO Functions. • Multiple Form Factors:• Full-Size SDIO • miniSDIO1.2 Primary Reference DocumentThis specification is based on and refers extensively to the SDA document:SD Memory Card SpecificationsPart 1 PHYSICAL LAYER SPECIFICATION Version 2.00 May 9, 2006The reader is directed to this document for more information on the basic operation of SD cards. In addition, other documents are referenced in this specification. A complete list can be found in appendix B.1.This specification can apply to any released versions of Physical Layer Specification after Version 2.00.1.3 Standard SDIO FunctionsAssociated with the base SDIO specification, there are several Application Specifications for Standard SDIO Functions. These common functions such as cameras, Bluetooth cards and GPS receivers have a standard register interface, a common operation method and a standard CIS extension. Implementation of the standard interfaces are optional for any card vendor, but compliance with the standard allows the use of standard drivers and applications which will increase the appeal of these cards to the consumer. Full information on these standard interfaces can be found in the Application Specifications for Standard SDIO Functions maintained by the SDA.。
Cisco UCS B200 M4 Blade Server 产品概述说明书
Data SheetCisco UCS B200 M4 Blade ServerProduct OverviewThe Cisco Unified Computing System ™ (Cisco UCS ®) combines Cisco UCS B-Series Blade Servers and C-SeriesRack Servers with networking and storage access into a single converged system with simplified managemen t,greater cost efficiency and agility, and increased visibility and control. One of the newest servers in the Cisco UCSportfolio is the Cisco UCS B200 M4 Blade Server.The UCS B200 M4 Blade Server (Figure 1) delivers performance, flexibility and optimiza tion for data centers andremote sites. This enterprise-class server offers market-leading performance, versatility, and density withoutcompromise for workloads ranging from web infrastructure to distributed databases. The Cisco UCS B200 M4server can quickly deploy stateless physical and virtual workloads, with the programmable ease of use of theCisco UCS Manager software and simplified server access with Cisco ®SingleConnect technology. Based on theIntel ® Xeon ® processor E5-2600 v4 and v3 product family, it offers up to 1.5 TB of total memory when using 64 GBDIMMs, up to two drives, and up to 80 Gbps I/O throughput. The Cisco UCS B200 M4 offers exceptional levels ofperformance, flexibility, and I/O throughput to run your most demanding applications.In addition, Cisco UCS has the architectural advantage of not having to power and cool excess switches, NICs andHBAs in each blade server chassis. Having a larger power budget per blade server provides uncompromisedexpandability and capabilities, as in the new Cisco UCS B200 M4 server with its leading memory-slot and drivecapacity.Figure 1.Cisco UCS B200 M4 Blade ServerCisco UCS B200 M4 OverviewThe Cisco UCS B200 M4 provides:●Up to two multicore Intel Xeon processor E5-2600 v4 and v3 series CPUs for up to 44 processing cores. ● 24 DIMM slots for industry-standard DDR4 memory at speeds up to 2400 MHz and it offers up to 1.5 TB oftotal memory when using 64 GB DIMMs.● Two optional, hot-plug, SAS and SATA hard disk drives (HDDs) or solid-state drives (SSDs).●Cisco UCS Virtual Interface Card (VIC) 1340: a 2-port, 40 Gigabit Ethernet, Fibre Channel over Ethernet(FCoE)-capable modular LAN on motherboard (mLOM) mezzanine adapter. ◦ 2x ports - 40 Gbps Unified I/O portsor2 sets of 4 x 10-Gbps unified I/O ports◦ Delivers 80 Gbps to the server◦ Adapts to either 10 Gbps or 40 Gbps fabric connections●Cisco FlexStorage local drive storage subsystem provides flexible boot and local storage capabilities. Itallows you to:◦Support for optional NVIDIA M6 GPU◦Configure the Cisco UCS B200 M4 to meet your local storage requirements without having to buy,power and cool components that you do not need.◦Choose an enterprise-class RAID controller, or go without any controller or drive bays if not utilizing local drives◦Easily add, change, or remove Cisco FlexStorage modules●The Cisco UCS B200 M4 server is a half-width blade. Up to eight can reside in the 6-rack-unit (6RU) CiscoUCS 5108 Blade Server Chassis, offering one of the highest densities of servers per rack unit of bladechassis in the industry.OverviewThe Cisco UCS B200 M4 server is suited for a broad spectrum of IT workloads, including:●IT and web infrastructure●Virtualized workloads●Consolidating applications●Virtual desktops●Middleware●ERP and CRM applications●Single-instance and distributed databasesThe Cisco UCS B200 M4 Blade Server is one member of the Cisco UCS B-Series Blade Servers platform.As part of Cisco UCS, Cisco UCS B-Series servers incorporate many innovative Cisco technologies to help customers handle their most challenging workloads. Cisco UCS B-Series servers within a Cisco UCSmanagement framework incorporate a standards-based unified network fabric, Cisco Data Center VM-FEX virtualization support, Cisco UCS Manager, Cisco UCS Central, Cisco UCS Director software, and Cisco fabric extender architecture (Figure 2)Figure 2. Cisco UCS Server Innovations Change the E conomics of the Data Center by E nabling Customer Workloads to Benefit from Cisco UCS Simplification and Operational E fficienciesFeatures and Benefits of the Cisco UCS B200 M4 ServerTable 1 lists the main features and benefits of the Cisco UCS B200 M4.Table 1. Main Features and BenefitsSpecificationsTable 2 provides specifications for the Cisco UCS B200 M4. Table 2. P roduct SpecificationsTable 3. Regulatory Standards ComplianceWarranty InformationFind warranty information at on the Product Warranties page.Cisco Unified Computing ServicesUsing a unified view of data center res ources, Cisco and our industry-leading partners deliver services that accelerate your transition to a unified computing environment. Cisco Unified Computing Services can help you create an agile infrastructure that accelerates time to value, reduces costs and risks, and maintains availability during deployment and migration. After deployment, our services can help you improve performance, availability, and resiliency as your business needs evolve, and mitigate risk further. Quickly deploy your data center r esources and optimize ongoing operations to better meet your business needs. For more information about these and other Cisco Data Center Services offerings, visit /go/unifiedcomputingservices or/go/dcservices.Cisco CapitalFinancing to Help You Achieve Your ObjectivesCisco Capital can help you acquire the technology you need to achieve your objective s and stay competitive. We can help you reduce CapEx. Accelerate your growth. Optimize your investment dollars and ROI. Cisco Capital financing gives you flexibility in acquiring hardware, software, services, and complementary third-party equipment. And th ere’s just one predictable payment. Cisco Capital is available in more than 100 countries. Learn more.For More InformationFor more information about Cisco UCS B-Series Blade Servers, visit/en/US/products/ps10280/index.html or contact your local Cisco representative.Printed in USA C78-732434-04 11/16。
PCI-E 标准
PCI Express™Card Electromechanical SpecificationRevision 1.1March 28, 2005Revision RevisionHistory Daterelease. 7/22/021.0 Initial1.0a Incorporated WG Errata C1-C7 and E1. 4/15/031.1 Incorporated approved Errata and ECNs. 03/28/05PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does PCI-SIG make a commitment to update the information contained herein.Contact the PCI-SIG office to obtain the latest revision of the specification.Questions regarding this specification or membership in PCI-SIG may be forwarded to:Membership ServicesE-mail: administration@Phone: 503-291-2569Fax: 503-297-1090Technical Supporttechsupp@DISCLAIMERThis PCI Express Card Electromechanical Specification is provided “as is” with nowarranties whatsoever, including any warranty of merchantability, noninfringement,fitness for any particular purpose, or any warranty otherwise arising out of any proposal,specification, or sample. PCI-SIG disclaims all liability for infringement of proprietaryrights, relating to use of information in this specification. No license, express or implied,by estoppel or otherwise, to any intellectual property rights is granted herein.PCI Express is a trademark of PCI-SIG.All other product names are trademarks, registered trademarks, or service marks of theirrespective owners.Copyright © 2002-2005 PCI-SIGContents1.INTRODUCTION (7)1.1.TERMS AND DEFINITIONS (7)1.2.REFERENCE DOCUMENTS (9)1.3.SPECIFICATION CONTENTS (9)1.4.OBJECTIVES (10)1.5.ELECTRICAL OVERVIEW (10)1.6.MECHANICAL OVERVIEW (11)2.AUXILIARY SIGNALS (13)2.1.REFERENCE CLOCK (14)2.1.1.Low Voltage Swing, Differential Clocks (14)2.1.2.Spread Spectrum Clocking (SSC) (15)2.1.3.REFCLK AC Specifications (16)2.1.4.REFCLK Phase Jitter Specification (19)2.2.PERST# SIGNAL (20)2.2.1.Initial Power-Up (G3 to L0) (20)2.2.2.Power Management States (S0 to S3/S4 to S0) (21)2.2.3.Power Down (22)2.3.WAKE# SIGNAL (24)2.4.SMBUS (OPTIONAL) (27)2.4.1.Capacitive Load of High-power SMBus Lines (27)2.4.2.Minimum Current Sinking Requirements for SMBus Devices (28)2.4.3.SMBus “Back Powering” Considerations (28)2.4.4.Power-on Reset (28)2.5.JTAG PINS (OPTIONAL) (29)2.6.AUXILIARY SIGNAL PARAMETRIC SPECIFICATIONS (30)2.6.1.DC Specifications (30)2.6.2.AC Specifications (31)3.HOT INSERTION AND REMOVAL (33)3.1.SCOPE (33)3.2.PRESENCE DETECT (33)4.ELECTRICAL REQUIREMENTS (35)4.1.POWER SUPPLY REQUIREMENTS (35)4.2.POWER CONSUMPTION (36)4.3.POWER SUPPLY SEQUENCING (37)4.4.POWER SUPPLY DECOUPLING (38)4.5.ELECTRICAL TOPOLOGIES AND LINK DEFINITIONS (38)4.5.1.Topologies (38)4.5.2.Link Definition (40)4.6.ELECTRICAL BUDGETS (41)4.6.1.AC Coupling Capacitors (42)4.6.2.Insertion Loss Values (Voltage Transfer Function) (42)4.6.3.Jitter Values (44)4.6.4.Crosstalk (46)ne-to-Lane Skew (46)4.6.6.Equalization (47)4.6.7.Skew within the Differential Pair (47)4.7.EYE DIAGRAMS AT THE ADD-IN CARD INTERFACE (47)4.7.1.Add-in Card Transmitter Path Compliance Eye-Diagram (48)4.7.2.Add-in Card Minimum Receiver Path Sensitivity Requirements (49)4.7.3.System Board Transmitter Path Compliance Eye Diagram (50)4.7.4.System Board Minimum Receiver Path Sensitivity Requirements (52)5.CONNECTOR SPECIFICATION (53)5.1.CONNECTOR PINOUT (53)5.2.CONNECTOR INTERFACE DEFINITIONS (58)5.3.SIGNAL INTEGRITY REQUIREMENTS AND TEST PROCEDURES (62)5.4.CONNECTOR ENVIRONMENTAL AND OTHER REQUIREMENTS (65)5.4.1.Environmental Requirements (65)5.4.2.Mechanical Requirements (67)5.4.3.Current Rating Requirement (68)5.4.4.Additional Considerations (69)6.ADD-IN CARD FORM FACTORS AND IMPLEMENTATION (71)6.1.ADD-IN CARD FORM FACTORS (71)6.2.CONNECTOR AND ADD-IN CARD LOCATIONS (81)6.3.CARD INTEROPERABILITY (87)ACKNOWLEDGEMENTS (89)FiguresFIGURE 1-1: VERTICAL EDGE-CARD CONNECTOR (11)FIGURE 1-2: EXAMPLE SERVER I/O BOARD WITH PCI EXPRESS SLOTS ON A RISER (12)FIGURE 2-1: DIFFERENTIAL REFCLK WAVEFORM (14)FIGURE 2-2: EXAMPLE REFERENCE CLOCK SOURCE TERMINATION (15)FIGURE 2-3: SINGLE-ENDED MEASUREMENT POINTS FOR ABSOLUTE CROSS POINT AND SWING (17)FIGURE 2-4: SINGLE-ENDED MEASUREMENT POINTS FOR DELTA CROSS POINT (17)FIGURE 2-5: SINGLE-ENDED MEASUREMENT POINTS FOR RISE AND FALL TIME MATCHING (18)FIGURE 2-6: DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE AND PERIOD18 FIGURE 2-7: DIFFERENTIAL MEASUREMENT POINTS FOR RISE AND FALL TIME (18)FIGURE 2-8: DIFFERENTIAL MEASUREMENT POINTS FOR RINGBACK (18)FIGURE 2-9: REFERENCE CLOCK SYSTEM MEASUREMENT POINT AND LOADING (19)FIGURE 2-10: POWER UP (21)FIGURE 2-11: POWER MANAGEMENT STATES (22)FIGURE 2-12: OUT-OF-TOLERANCE THRESHOLD WINDOWS (23)FIGURE 2-13: POWER DOWN (23)FIGURE 2-14: WAKE# RISE AND FALL TIME MEASUREMENT POINTS (31)FIGURE 3-1: PRESENCE DETECT IN A HOT-PLUG ENVIRONMENT (34)FIGURE 4-1: PCI EXPRESS ON THE SYSTEM BOARD (39)FIGURE 4-2: PCI EXPRESS CONNECTOR ON SYSTEM BOARD WITH AN ADD-IN CARD.39 FIGURE 4-3: PCI EXPRESS CONNECTOR ON A RISER CARD WITH AN ADD-IN CARD (40)FIGURE 4-4: LINK DEFINITION FOR TWO COMPONENTS (41)FIGURE 4-5: EXAMPLE INTERCONNECT TERMINATED AT THE CONNECTOR INTERFACE (42)FIGURE 4-6: INSERTION LOSS BUDGETS (43)FIGURE 4-7: JITTER BUDGET (44)FIGURE 4-8: ADD-IN CARD TRANSMITTER PATH COMPLIANCE EYE DIAGRAM (48)FIGURE 4-9: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR ADD-IN CARD RECEIVER PATH COMPLIANCE (49)FIGURE 4-10: SYSTEM BOARD TRANSMITTER PATH COMPOSITE COMPLIANCE EYE DIAGRAM (50)FIGURE 4-11: TWO-PORT MEASUREMENT MODEL (51)FIGURE 4-12: REPRESENTATIVE COMPOSITE EYE DIAGRAM FOR SYSTEM BOARD RECEIVER PATH COMPLIANCE (52)FIGURE 5-1: CONNECTOR FORM FACTOR (58)FIGURE 5-2: RECOMMENDED FOOTPRINT (59)FIGURE 5-3: ADD-IN CARD EDGE-FINGER DIMENSIONS (60)FIGURE 5-4: ILLUSTRATION OF ADJACENT PAIRS (65)FIGURE 5-5: CONTACT RESISTANCE MEASUREMENT POINTS (66)FIGURE 6-1: STANDARD HEIGHT PCI EXPRESS ADD-IN CARD WITHOUT THE I/O BRACKET (72)FIGURE 6-2: STANDARD HEIGHT PCI EXPRESS ADD-IN CARD WITH THE I/O BRACKET AND CARD RETAINER (73)FIGURE 6-3: ADDITIONAL FEATURE AND KEEPOUTS ON THE X16 GRAPHICS CARD (74)FIGURE 6-4: STANDARD ADD-IN CARD I/O BRACKET (75)FIGURE 6-5: BRACKET DESIGN WITH THE MOUNTING TABS MOUNTED ON THE PRIMARY SIDE OF THE ADD-IN CARD (76)FIGURE 6-6: ADD-IN CARD RETAINER (77)FIGURE 6-7: LOW PROFILE PCI EXPRESS ADD-IN CARD WITHOUT THE I/O BRACKET.78 FIGURE 6-8: LOW PROFILE PCI EXPRESS ADD-IN CARD WITH THE I/O BRACKET (79)FIGURE 6-9: LOW PROFILE I/O BRACKET (80)FIGURE 6-10: EXAMPLE OF A PC SYSTEM IN MICROATX FORM FACTOR (81)FIGURE 6-11: INTRODUCTION OF A PCI EXPRESS CONNECTOR IN A MICROATX SYSTEM (82)FIGURE 6-12: MORE PCI EXPRESS CONNECTORS ARE INTRODUCED ON A MICROATX SYSTEM BOARD (83)FIGURE 6-13: PCI EXPRESS CONNECTOR LOCATION IN A MICROATX SYSTEM WITH ONE PCI EXPRESS CONNECTOR (84)FIGURE 6-14: PCI EXPRESS CONNECTOR LOCATION IN A MICROATX SYSTEM WITH TWO PCI EXPRESS CONNECTORS (85)FIGURE 6-15: CARD ASSEMBLED IN CONNECTOR (86)TablesTABLE 2-1: REFCLCK DC SPECIFICATIONS AND AC TIMING REQUIREMENTS (16)TABLE 2-2: MAXIMUM ALLOWED PHASE JITTER WHEN APPLIED TO FIXED FILTER CHARACTERISTIC (20)TABLE 2-3: AUXILIARY SIGNAL DC SPECIFICATIONS - PERST#, WAKE#, AND SMBUS30 TABLE 2-4: POWER SEQUENCING AND RESET SIGNAL TIMINGS (31)TABLE 4-1: POWER SUPPLY RAIL REQUIREMENTS (35)TABLE 4-2: ADD-IN CARD POWER DISSIPATION (36)TABLE 4-3: ALLOCATION OF INTERCONNECT PATH INSERTION LOSS BUDGET (43)TABLE 4-4: TOTAL SYSTEM JITTER BUDGET (45)TABLE 4-5: ALLOCATION OF INTERCONNECT JITTER BUDGET (45)TABLE 4-6: ALLOWABLE INTERCONNECT LANE-TO-LANE SKEW (47)TABLE 4-7: ADD-IN CARD TRANSMITTER PATH COMPLIANCE EYE REQUIREMENTS..48 TABLE 4-8: ADD-IN CARD MINIMUM RECEIVER PATH SENSITIVITY REQUIREMENTS49 TABLE 5-1: PCI EXPRESS CONNECTORS PINOUT (53)TABLE 5-2: SIGNAL INTEGRITY REQUIREMENTS AND TEST PROCEDURES (63)TABLE 5-3: TEST DURATIONS (66)TABLE 5-4: MECHANICAL TEST PROCEDURES AND REQUIREMENTS (67)TABLE 5-5: END OF LIFE CURRENT RATING TEST SEQUENCE (68)TABLE 5-6: ADDITIONAL REQUIREMENTS (69)TABLE 6-1: ADD-IN CARD SIZES (71)TABLE 6-2: CARD INTEROPERABILITY (87)11. IntroductionThis specification is a companion for the PCI Express Base Specification, Revision 1.1. Its primary focus is the implementation of an evolutionary strategy with the current PCI desktop/server mechanical and electrical specifications. The discussions are confined to ATX or ATX-based form factors.Other form factors, such as PCI Express Mini Card are covered in other separate specifications.51.1. TermsDefinitionsandAdd-in card A card that is plugged into a connector and mounted in a chassisslot.ATX A system board form factor. Refer to the ATX Specification,2.2.Revision.10ATX-based form factor Refers to the form factor that does not exactly conform to theATX specification, but uses the key features of the ATX, such asthe slot spacing, I/O panel definition, etc.Auxiliary signals Signals not required by the PCI Express architecture but necessaryfor certain desired functions or system implementation, for15example, the SMBus signals.Basic bandwidth Contains one PCI Express Lanex1, x4, x8, x16 x1 refers to one PCI Express Lane of basic bandwidth; x4 refers to acollection of four PCI Express Lanes; etc.Down-plugging Plugging a larger Link card into a smaller Link connector; for example, 20plugging a x4 card into a x1 connectorDown-shifting Plugging a PCI Express card into a connector that is not fullyrouted for all of the PCI Express Lanes; for example, plugginga x4 card into a x8 capable connector with only four Lanesroutedbeing25Evolutionary strategy A strategy to develop the PCI Express connector and card formfactors within today’s chassis and system board form factorconstraints.infrastructureHigh bandwidth Supports larger number of PCI Express Lanes, such as a x16 cardconnector.or30Hot-Plug Insertion and/or removal of a card into an active backplane orsystem board as defined in PCI Standard Hot-Plug Controller andSubsystem Specification, Revision. 1.0. No special card support is required.Hot swap Insertion and/or removal of a card into a passive backplane. Thecard must satisfy specific requirements to support Hot swap.5Interoperability Ability to plug a PCI Express card into different Link connectorsand the system works, for example, plugging a x1 PCI ExpressI/O card into a x16 graphics slot.Link A collection of one or more PCI Express LanesLow profile card An add-in card whose height is no more than 68.90 mm10(2.731 inches)microATX An ATX-based system board form factor. Refer to the microATXMotherboard Interface Specification, Revision 1.2.PCI Express Mini Card PCI Express for mobile form factor, similar to Mini PCIPCI Express Lane One PCI Express Lane contains two differential lines for15Transmitter and two differential lines for Receiver. A by-N Linkis composed of N Lanes.sideband signaling A method for signaling events and conditions using physicalsignals separate from signals forming the Link between twocomponents.20Standard height card An add-in card whose height is no more than 111.15 mminches)(4.376Up-plugging Plug a smaller Link card into a larger Link connector; forexample, plugging a x1 card into a x4 connectorwakeup A mechanism used by a component to request the reapplication of25main power when in the L2 Link state. Two such mechanisms aredefined in the PCI Express Base Specification, Revision 1.1: Beacon andWAKE#. This specification requires the use of WAKE# on any add-incard or system board that supports wakeup functionality.Documents1.2. ReferenceThis specification references the following documents:PCI Express Base Specification, Revision 1.1PCI Local Bus Specification, Revision 3.0PCI Express Jitter Modeling5PCI Express Jitter and BERATX Specification, Revision 2.2microATX Motherboard Interface Specification, Revision 1.2SMBus Specification, Revision 2.0JTAG Specification (IEEE1149.1)10PCI Standard Hot-Plug Controller and Subsystem Specification, Revision 1.0Compact PCI Hot Swap SpecificationEIA-364-1000.01: Environmental Test Methodology for Assessing the Performance of Electrical Connectors and Sockets Used in Business Office ApplicationsEIA-364: Electrical Connector/Socket Test Procedures Including Environmental Classifications15Contents1.3. SpecificationThis specification contains the following information:Auxiliary signalsAdd-in card hot insertion and removalPower delivery20Add-in card electrical budgetConnector specificationCard form factors and implementation1.4. ObjectivesThe objectives of this specification are:Support 2.5 Gb/s data rate (per direction) with headroom for future bandwidth increasesEnable Hot-Plug and hot swap where they are neededLeverage desktop and server commonality5Facilitate smooth transitionsAllow co-existence of both PCI and PCI Express add-in cardsNo chassis or other PC infrastructure changesForward looking for future scalabilityExtensible for future bandwidth needs10Allows future evolution of PC architectureMaximize card interoperability for user flexibilityLow cost1.5. Electrical OverviewThe electrical part of this specification covers auxiliary signals, hot insertion and removal, power15delivery, and add-in card interconnect electrical budgets for the evolutionary strategy. The PCIExpress Transmitter and Receiver electrical requirements are specified in the PCI Express BaseSpecification, Revision 1.1.Besides the signals that are required to transmit/receive data on the PCI Express interface, there arealso signals that may be necessary to implement the PCI Express interface in a system environment, 20or to provide certain desired functions. These signals are referred to as the auxiliary signals. They include:Reference clock (REFCLK), must be supplied by the system (see Section 2.1.1)Add-in card presence detect pins (PRSNT1# and PRSNT2#), requiredPERST#, required25JTAG, optionalSMBus, optionalWake (WAKE#), required only if the device/system supports wakeup+3.3Vaux, optionalREFCLK, JTAG, SMBus, PERST#, and WAKE# are described in Chapter 2; +3.3Vaux is30described in Chapter 4; and PRSNT1# and PRSNT2# are described in Chapter 3.Both Hot-Plug and hot swap of PCI Express add-in cards are supported, but their implementation isoptional. Hot-Plug is supported with the evolutionary add-in card form factor. Hot swap issupported with other form factors and will be described in other specifications.To support Hot-Plug, presence detect pins (PRSNT1# and PRSNT2#) are defined in each end of the connectors and add-in cards. Those presence detect pins are staggered on the add-in cards such 5that they are last-mate and first-break, detecting the presence of the add-in cards. Chapter 3discusses the detailed implementation of PCI Express Hot-Plug.Chapter 4 specifies the PCI Express add-in card electrical requirements, which include powerdelivery and interconnect electrical budgets. Power is delivered to the PCI Express add-in cards viaadd-in card connectors, using three voltage rails: +3.3V, +3.3Vaux, and +12V. Note that the10+3.3Vaux voltage rail is not required for all platforms (refer to Section 4.1 for more information on the required usage of 3.3Vaux). The maximum add-in card power definitions are based on the card size and Link widths, and are described in Section 4.2. Chapter 4 describes the interconnectelectrical budgets, focusing on the add-in card loss and jitter requirements.Overview1.6. MechanicalPCI Express can be used in many different applications in desktop, mobile, server, as well as15networking and communication equipment. Consequently, multiple variations of form factors and connectors will exist to suit the unique needs of these different applications.Figure 1-1 shows an example of the vertical edge-card PCI Express connector to be used in ATX or ATX-based systems. There will be a family of such connectors, containing one to 16 PCI ExpressLanes. The basic bandwidth (BW) version supports one PCI Express Lane and could be used as the 20replacement for the PCI connector. The high bandwidth version will support 16 PCI Express Lanes and will be used for applications that require higher bandwidth, such as graphics.OM14739Figure 1-1: Vertical Edge-Card ConnectorVertical edge card connectors also have applications in the server market segment. Figure 1-2 shows an example of a server configuration using a PCI Express riser card.OM14740Figure 1-2: Example Server I/O Board with PCI Express Slots on a Riser Mobile applications require a right angle edge card connector. The definition of such a connector will be covered in a separate document.For certain server and network applications there may also be a need for a Compact PCI-like PCI Express connector, or other backplane-type PCI Express connectors.PCI Express cable connectors may also be needed for within-system applications, both internally 5(inside the chassis) and externally (outside the chassis).While the reality of multiple variations of PCI Express connectors and form factors is recognized, no attempt will be made to define every possible PCI Express connector and form factor variation in this specification. They will be defined later as the need arises in other specifications. Thisspecification, instead, focuses on the vertical edge card PCI Express connectors and form factor 10requirements by covering the following:Connector mating interfaces and footprintsElectrical, mechanical, and reliability requirements of the connectors, including the connector testing proceduresAdd-in card form factors15Connector and add-in card locations, as well as keep-outs on a typical desktop system board (ATX/microATX form factor)Connector definitions and requirements are addressed in Chapter 5 and add-in card form factors and implementation are discussed in Chapter 6.2. Auxiliary SignalsThe auxiliary signals are provided on the connector to assist with certain system level functionality or implementation. These signals are not required by the PCI Express architecture. The high-speed signal voltage levels are compatible with advanced silicon processes. The optional low speed signals are defined to use the +3.3V or +3.3Vaux supplies, as they are the lowest common voltage available. 5Most ASIC processes have high voltage (thick gate oxide) I/O transistors compatible with 3.3 V. Use of the 3.3 V supply allows PCI Express signaling to be used with existing control bus structures, avoiding a buffered set of signals and bridges between the buses.The PCI Express connector and add-in card interfaces support the following auxiliary signals:REFCLK-/REFCLK+ (required): low voltage differential signals.10 PERST# (required): indicates when the applied main power is within the specified tolerance andstable. PERST# goes inactive after a delay of T PVPERL time from the power rails achieving specified tolerance on power up.WAKE#: an open-drain, active low signal that is driven low by a PCI Express function to re-activate the PCI Express Link hierarchy’s main power rails and reference clocks. It is required 15on any add-in card or system board that supports wakeup functionality compliant with this specification.SMBCLK (optional): the SMBus interface clock signal. It is an open-drain signal. SMBDAT (optional): the SMBus interface address/data signal. It is an open-drain signal. JTAG (TRST#, TCLK, TDI, TDO, and TMS) (optional): the pins to support IEEE Standard201149.1, Test Access Port and Boundary Scan Architecture (JTAG). They are included as an optional interface for PCI Express devices. IEEE Standard 1149.1 specifies the rules and permissions for designing an 1149.1-compliant IC.PRSNT1# (required): Add-in card presence detect pin. See Chapter 3 for a detailed description.PRSNT2# (required): Add-in card presence detect pin. See Chapter 3 for a detailed description.25Note that the SMBus interface pins are collectively optional for both the add-in card and the system board. If the optional management features are implemented, SMBCLK and SMBDAT are both required. Similarly, the JTAG pins are collectively optional. If this test mode is implemented, all the JTAG pins are required. Refer to the PCI Local Bus Specification, Revision. 3.0, Section 4.3.3 for additional system requirements related to these signals.3022.1. Reference Clock2.1.1. Low Voltage Swing, Differential ClocksTo reduce jitter and allow for future silicon fabrication process changes, low voltage swing,differential clocks are being used, as illustrated in Figure 2-1. The nominal single-ended swing for each clock is 0 to 0.7 V and a nominal frequency of 100 MHz ±300 PPM. The clock has a defined 5crossover voltage range and monotonic edges through the input threshold regions as specified in Chapter 4.REFCLK–REFCLK+OM14741Figure 2-1: Differential REFCLK WaveformThe reference clock pair is routed point-to-point to each connector from the system boardaccording to best-known clock routing rules. The reference clock distribution to all devices must be matched to within 15 inches on the system board. The phase delay between the transmitter and 10receiver clock is assumed to be less than 10 ns. The combination of the maximum reference clock mismatch and the maximum channel length will contribute approximately 7-8 ns and the remaining time is allocated to the difference in the insertion delays of the Tx and Rx devices. The routing of each signal in any given clock pair between the clock source and the connector must be well matched in length (< 0.005 inch) and appropriately spaced away from other non-clock signals to 15avoid excessive crosstalk.The add-in card is not required to use the reference clock on the connector. However, the add-in card is required to maintain the 600-ppm data rate matching specified in Section 4.3.1.1 of the PCI Express Base Specification, Revision 1.1.Any terminations required by the clock are to be on the system board. An example termination 20topology for a current-mode clock generator is shown in Figure 2-2. EMI emissions will be reduced if clocks to open sockets are shut down at the clock source. The method for detecting the presence of a card in a slot and controlling the clock gating is platform specific and is not covered in this specification.A-0439Figure 2-2: Example Reference Clock Source Termination Termination on the add-in card is allowed, but is not covered by the specifications in Section 2.1.3.While the same measurement techniques can be used as specified in that section, receivertermination will reduce the nominal swing and rise and fall times by half. The low input swing and low slew rates need to be validated against the clock receiver requirements as they can causeexcessive jitter in some clock input buffer designs.5The reference clock timings are based on nominal 100 Ω, differential pair routing withapproximately 5-mil trace widths. This timing budget allows for a maximum add-in card tracelength of 4.0 inches. No specific trace geometry, however, is explicitly defined in this specification.2.1.2. Spread Spectrum Clocking (SSC)The reference clocks may support spread spectrum clocking. Any given system design may or may 10not use this feature due to platform-level timing issues. The minimum clock period cannot beviolated. The preferred method is to adjust the spread technique to not allow for modulation above the nominal frequency. This technique is often called “down-spreading.” The requirements for spread spectrum modulation rate and magnitude are given in the PCI Express Base Specification,Revision 1.1.152.1.3. REFCLK AC SpecificationsAll specifications in Table 2-1 are to be measured using a test configuration as described in Note 11 with a circuit as shown in Figure 2-9.Table 2-1: REFCLCK DC Specifications and AC Timing Requirements100 MHz Input Unit Note Symbol ParameterMin MaxRise Edge Rate Rising Edge Rate 0.6 4.0 V/ns 2, 3Fall Edge Rate Falling Edge Rate 0.6 4.0 V/ns 2, 3V IH Differential Input High Voltage +150 mV 2V IL Differential Input Low Voltage -150 mV 2V CROSS Absolute crossing point voltage +250 +550 mV 1,4,5V CROSS DELTA Variation of V CROSS over all risingclock edges+140 mV 1,4,9V RB Ring-back Voltage Margin -100 +100 mV 2,12 T STABLE Time before V RB is allowed 500 ps 2,12 T PERIOD AVG Average Clock Period Accuracy -300 +2800 ppm 2,10,13T PERIOD ABS Absolute Period (including Jitterand Spread Spectrum)9.847 10.203 ns 2,6T CCJITTER Cycle to Cycle jitter 150 ps 2 V MAX Absolute Max input voltage +1.15 V 1,7 V MIN Absolute Min input voltage - 0.3 V 1,8 Duty Cycle Duty Cycle 40 60 % 2Rise-Fall Matching Rising edge rate (REFCLK+) tofalling edge rate (REFCLK-)matching20 % 1,14Z C-DC Clock source DC impedance 40 60 Ω1,11Notes:1. Measurement taken from single ended waveform.52. Measurement taken from differential waveform.3. Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minusREFCLK-). The signal must be monotonic through the measurement region for rise and fall time.The 300 mV measurement window is centered on the differential zero crossing. See Figure 2-7.4. Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+10equals the falling edge of REFCLK-. See Figure 2-3.5. Refers to the total variation from the lowest crossing point to the highest, regardless of which edgeis crossing. Refers to all crossing points for this measurement. See Figure 2-3.6. Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cyclejitter, relative PPM tolerance, and spread spectrum modulation. See Figure 2-6.157. Defined as the maximum instantaneous voltage including overshoot. See Figure 2-3. 8. Defined as the minimum instantaneous voltage including undershoot. See Figure 2-3.9. Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-.This is the maximum allowed variance in VCROSS for any particular system. See Figure 2-4. 10. Refer to Section 4.3.2.1 of the PCI Express Base Specification, Revision 1.1 for information5regarding PPM considerations.11. System board compliance measurements must use the test load card described in Figure 2-9.REFCLK+ and REFCLK- are to be measured at the load capacitors CL. Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or differential probe can be used for differential measurements. Test load C L = 2 pF.1012. T STABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage afterrising/falling edges before it is allowed to droop back into the V RB ±100 mV differential range. See Figure 2-8.13. PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is1/1,000,000thof 100.000000 MHz exactly or 100 Hz. For 300 PPM then we have a error budget of 15100 Hz/PPM * 300 PPM = 30 kHz. The period is to be measured with a frequency counter with measurement window set to 100 ms or greater. The ±300 PPM applies to systems that do not employ Spread Spectrum or that use common clock source. For systems employing SpreadSpectrum there is an additional 2500 PPM nominal shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2800 PPM2014. Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It ismeasured using a ±75 mV window centered on the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of REFCLK-, the maximum allowed difference should not exceed 2520% of the slowest edge rate. See Figure 2-5.REFCLK–A-0437REFCLK+V MAX = 1.15 VV MIN = -0.30 VV CROSS MAX = 550 mV V CROSS MIN = 250 mVFigure 2-3: Single-Ended Measurement Points for Absolute Cross Point and SwingREFCLK–A-0438REFCLK+VFigure 2-4: Single-Ended Measurement Points for Delta Cross Point。
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Rising to the challenges of modern smart home demands, this new standard of WiFi is ready to support more devices with better reliability and faster speeds.CapacityWiFi 6 gives you improved network capacity for more WiFi devices. Have more fun with the uninterrupted 4K streaming, gaming, and the smart home experience. SpeedGet ultra-fast wireless speeds with moreconnections for all devices with lesscongestion. You’ll get some blazingconnection speeds of more thanone Gigabit per second or more,4K streaming, & VR/AR gaming.RangeExperience reliable and stronger WiFicoverage indoors and outdoors for allyour devices. High-performance antennas,pre-optimized for best peformance, on therouter amplify WiFi signals for maximizedrange and reliable coverage.4-Stream WiFi 6Stream HD & 4K UHD content to more devices at the same time.Faster Upload & Download SpeedsFaster WiFi download & upload speeds at the same time.Greater than 1Gbps WiFi SpeedsUnimaginable speeds now delivered. Capable of greater than 1Gbps WiFi speeds to newer mobile devices.4Powerful Triple-Core 1.5GHz ProcessorMore processing power increases the overall performance of your network.TRIPLEGet ultra-fast wireless speeds for better 4K UHD streaming, gaming or video conferencing experience.SpeedUP TO 3GBPS † SPEEDS —600Mbps + 2400Mbps with 4-stream connectivity **AX OPTIMIZED POWERFUL PROCESSOR—1.5GHz triple-coreprocessor ensures smooth 4K UHD streamingM ORE WIFI FOR MORE DEVICES— Allows efficient data transmission to devices simultaneously.§160MHZ CHANNEL SUPPORT ***—Doubles the speeds as offered by 80MHz channels to provide Gigabit speeds for compatible mobile devices and laptops1024-QAM—25% increased data efficiency and faster speeds than a 256-QAM router5 GIGABIT PORTS—Connect more wired devices for faster file transferand uninterrupted connections with 1 WAN & 4 LAN Ethernet portsSUPERSPEED USB 3.0 PORT —Up to 10X faster than USB 2.025%5G CapacityGet better performance for all your smart home devices even when your family is busy streaming videos or uploading media files during the Internet rush hour.U LTIMATE RANGE—WiFi coverage throughout small to medium homesWiFi RangeHIGH-PERFORMANCE ANTENNAS—Two (2) external antennasextend strong and reliable WiFi signals over larger areaFaster and expanded coverage throughout your home and for all your devices.There’s nothing more frustrating than lost connections! With NETGEAR’s advanced features & best-in-class technology, you’ll reduce interference & enjoy more reliable WiFi connectivity.Reliable ConnectionsSIMULTANEOUS DUAL BAND WIFI—Supports two WiFi bands simultaneously to double the available bandwidth and provide a reliable, dedicated WiFi network for smooth online gamingwithout any network congestionBEAMFORMING+—Improve range and performance for both 2.4 and 5GHz devicesStart enjoying your new device faster than ever. NETGEAR wants to make sure installation and management is simple & easy, so you can connect quickly & make sure you stay that way!Ease Of UseNIGHTHAWK ® APP —Easily set up your router and get more out of your WiFi. Includes access from anywhere to manage your network away from homeAX WIFI SUPPORTS ALL CURRENT WIFI DEVICES —WiFi 6 supports all current WiFi device and is backward compatible with WiFi 5 and earlier generation devicesVOICE CONTROLLED BY AMAZON ALEXA ® & THE GOOGLEASSISTANT ™— Control your NETGEAR WiFi network with simplevoice commandsWith NETGEAR, sharing across yournetwork is fun and easy, such as accessing stored photos & music.USB 3.0 PORT—Faster streaming, backup and easy accessto your stored mediaSharingADDITIONAL DFS CHANNELS—Reduce interference fromneighboring networksMaintain high security across your network to ensure your privacy & family is safe while online. Whether it’s preventing phishing & spyware or just limiting access for kids & guests, NETGEAR has you covered.SecurityV PN SUPPORT —On PC, MAC, & now also with OpenVPN Connect app on iOS & Android, securely access your home network & Internet connection from your mobile device remotelySTANDARDS-BASED WIFI SECURITY (802.11i, 128-bit AES encryption with PSK)GUEST NETWORK—Separate and secure network for your guests AUTOMATIC FIRMWARE UPDATE —Delivers latest security patches to the routerL ATEST SECURITY STANDARD—Supports WPA3 the latest and cutting-edge WiFi security protocolNETGEAR ARMOR ™—Cybersecurity for your home ††. Advanced cyber threat protection for your home network and your connected devices Powerful Triple-core ProcessorNighthawk AX4 WiFi Router is powered by a powerful triple-core processor designed to transfer multi-Gigs of data. Full-packet processing offload means zero load on the CPU. Enjoy smoother Ultra-HD 4K video streaming and gaming without interruptions.Gigabit WiFi to Mobile DevicesSupport for 160MHz channel allows the Nighthawk AX4 WiFi 6 Router to stream at Gigabit speeds to supported mobile devices, which are increasingly used for video streaming or gaming.Nighthawk AppThe NETGEAR Nighthawk® App makes it easy to set up your router and get more out of your WiFi. With the app, you can install your router in a few steps—just connect your mobile device to the router network and the app will walk you through the rest. Once set up, you can use the intuitive dashboard to pause the Internet on your connected devices, run a quick Internet speed test, and much more!• Anywhere Access—Easily monitor your home networkanytime, anywhere• Internet Speed Test—Check the broadband speeds fromyour service provider• Pause Internet—Pause the Internet to any device• Traffic Meter—Track Internet data usage• Guest Networks—Set up separate WiFi access for guests• Quick Setup—Get connected in just minutes• Get it at NETGEAR Armor ™identifies network s STAY SAFE EVEN WHEN AWAY FROM HOME WIFI — Stay in the know with Nighthawk App. Anywhere, anytime—Encrypts your internet connection toConnection DiagramInternetLEDon/off USB portPower on/offPackage Contents• NETGEAR ® Nighthawk ® AX4/4-Stream AX3000 WiFi Router (RAX40v2)• Ethernet cable • Quick start guide • Power adapterPhysical Specifications• Dimensions: 13.38 x 8.11 x 2.24 in (340 x 206 x 57 mm)• Weight: 1.32 lb (600 g)Technical Specifications• WiFi 6 (802.11ax) Dual Band WiFi (AX3000) - 2.4GHz AX: 2x2 (Tx/Rx) 1024/256-QAM20/40MHz, up to 600Mbps - 5GHz AX: 2x2 (Tx/Rx) 1024-QAM20/40/80/160MHz, up to 2.4Gbps - B ackwards compatible with 802.11a/b/g/n/ac WiFi • One (1) USB 3.0 port• 1024-QAM—25% data efficiency and faster speeds than a 256-QAM router • Powerful 1.5GHz triple-core processor • Memory: 256MB flash and 512MB RAM • 160MHz channel support• Additional DFS channels reduce interference from neighboring networks • Longer range with 2 high-performance antennas• Five (5) 10/100/1000Mbps Gigabit Ethernet ports - 1 WAN & 4 LAN • O n/off LED light switchKey Features• 2.5X better performance than an AC router—4-stream WiFi with up to 600 + 2400Mbps † for ultra-fast wireless speeds **• 160MHz channel support ***—Doubles the speeds as offered by 80MHz channels to provide Gigabit speeds for compatible mobile devices and laptops• Powerful processor—Dual-core processor ensures smooth 4K UHD streaming & gaming• 4 Gigabit Ethernet LAN ports—Connect more wired devices for faster file transfer and uninterrupted connections• Nighthawk ® App—Easily set up your router and get more out of your WiFi. Includes a ccess from anywhere to manage your network away from home• WiFi 6 supports all current WiFi devices and is backward compatible with WiFi 5 and earlier generation devices• NETGEAR Armor ™—Advanced cyber threat protection for your home network and your connected devices ††• Works with Amazon Alexa ® & the Google Assistant ™—Control your NETGEAR WiFi network with simple voice commandsSupport• 90-day complimentary technical supportfollowing purchase from a NETGEAR authorized reseller• J oin the NETGEAR Community Forum. Visit System Requirements• Microsoft ® Windows 7, 8, 10, Vista ®, XP ®, 2000, Mac OS ®, UNIX ®, or Linux ®• Microsoft ® Internet Explorer ® 11 or higher, Microsoft Edge, Google Chrome ® 55 or higher, Firefox ® 45 or higher, Safari ® 10 or higherSecurity• Standards-based WiFi Security (802.11i, 128-bit AES encryption with PSK)• Automatic firmware update delivers latest security patches to the router• Guest network access—separate & secure • VPN Support—Secure access to your home network away from home• S upports WPA3, the latest and cutting-edge WiFi security protocol• NETGEAR Armor ™—Advanced cyber threat protection for your home network and your connected devices ††Warranty• /warranty• Extend your warranty & technical support within 90 days of product purchase [US only]. Visit: /homeThis product comes with a limited warranty that is valid only if purchased from a NETGEAR authorized reseller.*90-day complimentary technical support following purchase from a NETGEAR authorized reseller.†Maximum wireless signal rate derived from IEEE 802.11 specifications. Actual data throughput and wireless coverage will vary and may be lowered by network and environmentalconditions, including network traffic volume and building construction. NETGEAR makes no representations or warranties about this product's compatibility with AX standards. Up to 3000Mbps wireless speeds achieved when connecting to other 802.11ax 3000Mbps devices.**When working with 160MHz clients as compared to a 2x2 AC router that does not support 160MHz.***Requires client device that supports 160MHz bandwidth on WiFi.§ Requires compatible AX clients with DL-OFDMA and UL-OFDMA support.‡As compared to an AC1200 2x2 router.††NETGEAR Armor requires a paid subscription after the initial introductory period.For indoor use only.NETGEAR, the NETGEAR Logo, NETGEAR Armor and Nighthawk are trademarks of NETGEAR, Inc. Mac, Mac OS, iPhone, and the Mac logo are trademarks of Apple Inc. App Store is a service mark of Apple Inc., registered in the U.S. and other countries. Google Play and the Google Play logo are trademarks of Google LLC. Any other trademarks mentioned herein are for reference purposes only. ©2020 NETGEAR, Inc.NETGEAR, Inc. 350 E. Plumeria Drive, San Jose, CA 95134-1911 USA, /supportD-RAX40v2-21。
Espressif Systems (Shanghai) Co.,Ltd.产品说明书
EMITIDO POR / ISSUED BYLGAI TECHNOLOGICAL CENTER - No. 0370 (APPLUS)SOLICITANTE / APPLICANTEspressif Systems (Shanghai) Co.,Ltd.FABRICANTE (Nombre, Dirección)MANUFACTURER (Name, Address) Espressif Systems (Shanghai) Co.,Ltd.Suite 204, Block 2, 690 Bibo Road, Zhang Jiang Hi-Tech Park, Shanghai, China COMERCIALIZADO POR (marca)COMMERCIALISED BY (Brand) ESPRESSIFPRODUCTOPRODUCT Wi-Fi & Bluetooth Internet of Things Module TIPOSTYPESESP32-S3-MINI-1U Versión HW / FMWHW / FMW versionSW: V1.1.3.0HW: V1.0DIRECTIVA APLICABLEAPPLICABLE DIRECTIVEDIRECTIVA 2014/53/UE DEL PARLAMENTO EUROPEO Y DEL CONSEJO, DE 16 DE ABRIL DE 2014, RELATIVA A LA ARMONIZACIÓN DE LAS LEGISLACIONES DE LOS ESTADOS MIEMBROS SOBRE LA COMERCIALIZACIÓN DE EQUIPOS RADIOELÉCTRICOSDIRECTIVE 2014/53/EU OF THE EUROPEAN PARLIAMENT AND OF THE COUNCILOF 16 APRIL 2014 ON THE HARMONISATION OF THE LAWS OF THE MEMBER STATES RELATING TO THE MAKING AVAILABLE ON THE MARKET OF RADIO EQUIPMENTDESCRIPCIÓNDESCRIPTIONThe device is a Wi-Fi & Bluetooth Internet of Things Module with Wi-Fi 2.4G and Bluetooth.CUMPLE CON LOS REQUISITOS ESENCIALESMEET ESSENTIAL REQUIREMENTSArt.3.1a Salud y Seguridad / ☒Art.3.1a Health & SafetyArt. 3.2 Uso eficiente del espectro radioeléctrico / ☒Art.3.2 Efficient use of Radio spectrumArt.3.1b EMC / ☒Art.3.1b EMC Art 3.3 Características especiales / ☐Art.3.3 Special characteristicsEste documento carece de validez sin su anexo, cuyo número coincide con el del presente certificado. // This document in not valid without its technical annex, whosenumber coincides with the number of the certificate.La evaluación de la documentación técnica entregada se encuentran recogidos en el expediente técnico número: 22/36400865The evaluation of the technical documentation delivered is included in the technical file number: 22/36400865Restricciones (si aplican) / Restrictions (if apply):Bellaterra, 17 de marzo de 2022 // 17th March 2022José Luis Medina DirectorElectrical & Electronics - SpainEste Certificado es válido mientras no se produzcan cambios en el estado de la técnica que indiquen que el equipo radioeléctrico aprobado ya no puede cumplir los requisitos esenciales de la Directiva 2014/53/UE y no haya notificaciones en el tipo aprobado que puedan afectar a la conformidad con los requisitos esenciales de la Directiva 2014/53/UEThis Certificate is valid as long as there are no changes in the prior art indicating that the approved radio equipment can no longer meet the essential requirements of Directive 2014/53/EU and No.0370-RED-5007LGAI Technological Center, S.A. (APPLUS)Campus UAB - Ronda de la Font del Carme s/n 08193 Bellaterra (Barcelona) T +34 93 567 20 00 F +34 93 567 20 01 No.CERTIFICADO DE EXAMEN UE DE TIPOEU-TYPE EXAMINATION CERTIFICATEF +34 93 567 20 01Anexo técnico Ed. 117/03/2022ANEXO TÉCNICOTECHNICAL ANNEX0370-RED-5007L G A I T e c h n o l o g i c a l C e n t e r , S .A . C .I .F A 63207492A. MODEL DESCRIPTIONA.1. GENERAL INFORMATION ON THE RADIO EQUIPMENT:Manufacturing country: China Brand: ESPRESSIFCommercial designation: ESPRESSIFCountry of commercialization: European UnionRadio service: Wi-Fi 2.4G and BluetoothApplication: Wi-Fi & Bluetooth Internet of Things ModuleA.1.1 TRADE VERSIONS/VARIANTS: ESP32-S3-MINI-1UA.2. FEATURES: Wi-Fi & Bluetooth Internet of Things ModuleA.3. SOFTWARE VERSION(S): V1.1.3.0A.4. HARDWARE VERSION(S): V1.0A.5. OTHER COMPONENTS- Disposable antenna YES ☐ NO ☒o Antenna gain (dBi)*:(*) only in case of YESF +34 93 567 20 01Anexo técnico Ed. 117/03/2022ANEXO TÉCNICOTECHNICAL ANNEX0370-RED-5007L G A I T e c h n o l o g i c a l C e n t e r , S .A . C .I .F A 63207492A.6. OPERATING FREQUENCIES AND MAXIMUM POWER EMITTED BY BANDN/A: Not applicable N/D: Not defined* Conducted power for mobile technologies and EIRP for other technologies.A.7. OTHER PARAMETERS OF RADIO INTERFACE SPECIFICATIONS (RI)Requires license/Use authorization: YES ☐ NO ☒BAND SERVICEOPERATIONAL FREQUENCY(TX)MAX POWER* CNAF IR CNAF/ UN-XXX Band 1 BLE F_min: 2402MHz F_max: 2480MHz 9.25 dBm IR-163 UN-85 Band 2WiFi 2.4GHzF_min: 2412MHz F_max: 2472MHz19.95 dBmIR-163UN-85F +34 93 567 20 01Anexo técnico Ed. 117/03/2022ANEXO TÉCNICOTECHNICAL ANNEX0370-RED-5007L G A I T e c h n o l o g i c a l C e n t e r , S .A . C .I .F A 63207492B. TEST PROTOCOLREQUIREMENT STANDARDLaboratory Report no. Health and Safety (Article 3.1a) EN IEC 62368-1:2020+A11:2020 TA Technology(Shanghai) Co., Ltd. R2112A1105-L1 EN 50665:2017 R2112A1105-M1 EN IEC 62311:2020 EMC (Article 3.1b) EN 301 489-1 V2.2.3 TA Technology(Shanghai) Co., Ltd.R2112A1105-E1EN 301 489-17 V3.2.4EN 55032:2015+A11:2020 EN 55035:2017+A11:2020 Radio Aspects (Article 3.2) EN 300 328 V2.2.2TA Technology(Shanghai) Co., Ltd.R2112A1105-R1C. RESTRICTIONSRestrictions: YES ☐ NO ☒ Describe restrictions: N/AF +34 93 567 20 01Anexo técnico Ed. 117/03/2022ANEXO TÉCNICOTECHNICAL ANNEX0370-RED-5007L G A I T e c h n o l o g i c a l C e n t e r , S .A . C .I .F A 63207492D. ACTIVITIES CARRIED OUT BY THE NBTechnical Documentation Review☐ Assembly drawings(s) ☒ Block diagram ☒ Circuit diagram/schematics ☒ External photographs ☒ Label drawing/location ☒ User manual ☒ Internal photographs ☒ Operational description ☒ Risk Assessment☒ Test set-up photographs☒ Test reports ☒ EU declaration of conformity ☒ Bill of materials☒ PCB layout☐ Installation diagrams and explanations☒ List of applied (harmonized and non-harmonized) standardsOther activities☒ RIS☒ EFIS/CNAF☒ Review Technical Justifications ☒ Analysis report☒ EU type certification issuedE.ADDITIONAL INFORMATION:Radio Equipment Directive 2014/53/EU, Article 10.4: Manufacturers shall keep the technical documentation and the EU declaration of conformity for 10 years after the radio equipment has been placed on the market.Radio Equipment Directive 2014/53/EU, Annex III, Module B.7: The manufacturer shall inform the notified body that holds the technical documentation relating to the EU-type examination certificate of all modifications to the approved type that may affect the conformity of the radio equipment with the essential requirements of this Directive or the conditions for validity of that certificate. Such modifications shall require additional approval in the form of an addition to the original EU-type examination certificate.This review includes draft standards, deviations from the standards and technical justification for compliance.。
AXIS P13网络摄像头系列说明书
FICHE TECHNIQUELa série de caméras réseau AXIS P13 comporte des caméras fixes pour l’intérieur et pour l’extérieur qui offrent une qualité d’image exceptionnelle avec une compression H.264. Ces caméras sont idéales pour une surveillance hautes performances. Les modèles mégapixel offrent également une video HDTV 720p/1080p.Série de caméras réseau AXIS P13Superbe qualité d’image pour la vidéosurveillance dans tous types d’environnements.> Superbe qualité vidéo incluant la HDTV et 5 megapixels > Contrôle P-Iris > Multiples flux vidéo H.264> PTZ numérique et flux de vues multiples > Modèles utilisables à l’extérieurLa série des AXIS P13 offre des caméras supportant toute éten-due de résolutions allant jusqu’à 5 mégapixels, notamment avec les caméras AXIS P1347 et AXIS P1347-E. Les modèles sont dis-ponibles à la fois dans les versions intérieur et extérieur ”-E ”. Les caméras fournissent une large gamme dynamique, une fonc-tionnalité jour et nuit avec une superbe qualité d’images dans des conditions de luminosité comme d’obscurité.Les caméras 3- et 5-megapixel proposent également un contrôle P-I ris unique et révolutionnaire, qui leur permet de contrôler avec précision la position de l’iris afin d’optimiser la profondeur du champ et la résolution de l’objectif pour obtenir une qualité d’image optimale.Toutes les caméras AXIS P13 prennent en charge plusieurs flux de données vidéo au format H.264 et Motion JPEG. La techno-logie H.264 réduit de manière significative les exigences en bande passante et en stockage sans affecter la qualité de l’image.Les modèles SVGA et mégapixels ont une fonction de mise au point arrière à distance qui permet à la mise au point d’êtreajustée depuis un ordinateur. Ces mêmes modèles offrent égale-ment une fonction panoramique/inclinaison/zoom numérique, tandis que les caméras AXI S P1346/-E sont en plus équipées d’un flux à vues multiples. Les caméras AXI S P13 prennent en charge l’alimentation par Ethernet (PoE), ce qui facilite leur installation. Les modèles ex-térieurs sont alimentés par Ethernet et par High PoE et fonc-tionnent à des températures comprises entre -40 ºC et 50 ºC .La série AXIS P13 comprend des caméras réseau fixes conçues pour l’intérieur et l’extérieur qui conviennent à un large éventail d’applications de vidéosurveillance, bâtiments publics ou industriels, commerces, aéroports, gares et écoles. Caméras hautes performances pour l’intérieur/l’extérieurInstallation facile grâce à l’assistance à la mise au point, la mise au point à distance et le compteur de pixelsL’assistance à la mise au point simplifie le réglage de la mise au point de toutes les caméras AXIS P13, grâce au clignotement d’un voyant vert lorsqu’une image est au point après un réglage manuel de l’objectif. De plus, les modèles SVGA et mégapixel/HDTV sont équipés d’une fonction de mise au point à distance du foyer arrière qui permet l’ajustement de la mise au point à partir d’un ordina-teur. Le compteur de pixels permet de vérifier que la résolution en pixels d’un objet est conforme aux règlementations en vigueur ou aux besoins du client (ex. : reconnaissance faciale).Modèles utilisables àl’extérieurLes caméras réseau AXI S P13-E permet-tent de gagner du temps et de réaliser deséconomies puisqu’elles sont immédiate-ment prêtes pour un montage en exté-rieur. Certifiées IP66, elles sont protégéescontre la poussière, la pluie, la neige et lesrayons du soleil et peuvent fonctionnerjusqu’à une température de -40 °C. Lescaméras sont alimentées par Ethernet, cequi facilite l’installation puisqu’elles nenécessitent pas de câble d’alimentation séparé. Une membrane de déshumidifi-cation intégrée permet d’éliminer toute l’humidité le boîtier de la caméra lors de l’installation. Ces caméras permettent l’installation facile d’une lampe à infrarouge sous le boîtier. Ils arrivent avec un support de montage mural, un pare-soleil et les presse-étoupes.PTZ numérique et flux à vue multipleLes modèles de caméras SVGA et mégapixel sont dotés de fonctions pan-oramiques, d’inclinaison et de zoom numériques qui permettent de sélectionnerune vue détourée de la vue d’ensemble pour l’afficher ou l’enregistrer, ce quiréduit ainsi le débit binaire et l’espace de stockage requis. Les caméras 3- et5-megapixel sont également dotées de la fonction de flux à vues multiplesqui permet de transmettre simultanément plusieurs zones détourées de la vuecomplète, simulant jusqu’à huit caméras virtuelles.Flux à vues multiples avec les cameras réseau AXIS P1346/-E et AXIS P1347/-EUne caméra Vue panoramique complète offrant des zonesdétourées de la vue complètePlusieurs champs de vision virtuels dela caméra (jusqu’à huit vues possibles)Contrôle P-IrisLes cameras 3-megapixel AXI S P1346/-E et 5-megapixel AXI S P1347/-E of-frent un nouveau contrôle précis de l’iris avancé, P-Iris, qui établit de nouvelles normes de qualité d’image pour les caméras fixes. Ce contrôle comporte un objectif P-Iris spécial associé à un logiciel spécialisé de la caméra qui fournit la meilleure position de l’iris pour un contraste, une clarté, une résolution et une profondeur de champ améliorés de l’image. Une bonne profondeur de champ, où des objets situés à différentes distances de la caméra sont simultanément mis au point, permet d’obtenir une meilleure visibilité de scène.Le P-Iris est particulièrement utile aux caméras mégapixel/HDTV, car il permet de continuer à obtenir des images haute résolution nettes, même dans des conditions d’éclairage difficiles. Il utilise le même type de connecteur et de câble que l’iris DC classique qui est également pris en charge par les caméras 3- et 5-megapixel pour la rétrocompatibilité.Pour en savoir plus sur P-Iris et ses contrôles, cliquez sur le lien :/corporate/corp/tech_papers.htmAXIS P1343/P1344/P1346/P1347 :Microphone intégréPour plus d’informations, visitez le site ** Ce produit inclut un logiciel développé par le projet OpenSSLpour une utilisation dans la boîte à outils OpenSSL. ()©2012 Axis Communications AB. AXIS COMMUNICATIONS, AXIS, ETRAX, ARTPEC et VAPIX sont des marques déposées d’Axis AB ou en cours de dépôt par Axis AB dans différentes juridictions. Tous les autres noms, produits ou services sont la propriété de leurs détenteurs respectifs. Document sujet à modification sans préavis.A x i s C o m m u n i c a t i o n s S A S -R C S B 4 0 8 9 6 9 9 9 8 4 7 2 9 2 / F R / R 1 / 1 2 0 4AXIS T8123 à 1 port。
96- 和 176 层 3d NAND 闪存的单事件影响响应说明书
Single-Event Effects Response of96-and176-Layer3D NAND Flash Memories Edward P.Wilcox,Member,IEEE,Matthew B.Joplin,Member,IEEE,Melanie D.Berg,Member,IEEEAbstract—Single-event effects testing(heavy-ion and proton)is presented for96-and176-layer commercially-available3D NAND flash memory,with emphasis on SEFI detection and recovery.Index Terms—Flash memory,proton,heavy ion,single-event upset,three-dimensional NAND,single-event functional interruptI.I NTRODUCTIONS TATE-OF-THE-ART3D NAND flash memories[1],[2] are characterized for single-event effects(SEE)response, including single-event upset(SEU),single-event latchup (SEL),and single-event functional interrupt(SEFI).With limited options for high-density radiation-hardened-by-design (RHBD)memories available,commercial parts are likely candidates for use in space,whether as-is or with significant aftermarket vendor screening and/or repackaging.These de-vices have well-known susceptibilities to multiple single-event effects phenomena[3]–[6].In this work,the SEE responses of three off-the-shelf devices are characterized and compared with heavy-ion and proton[7]irradiation,along with some exploration of the necessary mitigation steps to recover from complex error modes.II.D EVICES U NDER T ESTThe three commercial off-the-shelf(COTS)NAND flash devices tested are Micron96-and176-layer3D NAND flash, and SK Hynix176-layer3D NAND flash,further described in Table I.Throughout this document they are generally referred to based on the manufacturer and number of layers for convenience,e.g.,Micron96-layer flash.All are nominally triple-level cell(TLC)memories with the capability to operate in a classical single-level cell(SLC)mode for improved performance and endurance.Each device was prepared for heavy-ion testing by laser-chemical decapsulation to expose a single die as shown in Fig.1,Fig.2,and Fig.3.For proton testing,no decapsulation was performed.Submitted for publication on July14,2023.This work was funded by the NASA Electronic Parts and Packaging(NEPP)program.Authors acknowledge the support of Mike Wojtczak,Jeff Cassidy,and MEMKOR;the NASA GSFC Radiation Effects and Analysis Group(REAG);the Lawrence Berkeley National Laboratory;and Ethan Cascio of the Massachusetts General Hospital.E.P.Wilcox is with NASA Goddard Space Flight Center,Greenbelt,MD 20771USA(e-mail:*******************).M.B.Joplin is with NASA Goddard Space Flight Center,Greenbelt,MD 20771USA(e-mail:*************************).M.D.Berg is with SSAI,Inc.contracted by NASA Goddard Space Flight Center,Greenbelt,MD20771USA(e-mail:***********************).Fig.1.Decapsulated Micron96-layer flashmemoryFig.2.Decapsulated Micron176-layer flash memoryIII.T ESTING D ESCRIPTIONAll three devices were tested under heavy-ion irradiation at the Lawrence Berkeley National Laboratory’s(LBNL)88”Cyclotron[8];the Micron96-layer device in August of2022, and all three devices in November2022.Testing was per-formed with the16MeV/amu cyclotron tune using ions with incident linear energy transfer(LET)of approximately1.2to 56MeV·cm2/mg.All testing was performed in air.Testing at elevated temperature,where indicated,used resistive heating elements adhered to the printed circuit board;temperature was monitored by use of integrated on-chip temperature sensors within the NAND devices.High-energy proton testing was subsequently performed at the Massachusetts General Hospital’s Francis H.Burr Proton Therapy Center[9]in December2022.All three devices were characterized in varying degree to SEU and SEFI with125-and200-MeV protons.Some limited multi-die test results areTABLE ID EVICES U NDER T ESTPart Number MT29F8T08EWLGEM5MT29F8T08EWLKEM5H25G9TC18CX488ManufacturerMicronMicronSK Hynix3D NAND Technology 96Layers,SLC/TLC Floating Gate176Layers,SLC/TLC Replacement Gate176Layers,SLC/TLC Charge Trap(B27C)(B47T)(V7)Advertised Die Capacity512Gb TLC 512Gb TLC 512Gb TLC Total Capacity 8Tb TLC (16die)8Tb TLC (16die)512Gb TLC (1die)Lot Date Code IYG222PK22212TTested V oltageVCC:2.5V -3.3V VCC:2.5V -3.3V VCC:2.5V -3.3V VCCQ:1.25V VCCQ:1.25V VCCQ:1.25V Package132LBGA132LBGA152BGAFig.3.Decapsulated SK Hynix 176-layer flash memorypresented for the high-energy proton testing,but in general,testing was still based on a single die at a time.The airgap was 81cm and aperture size 3.5cm at 200MeV ,and the airgap 51cm and aperature size 2.5cm at 125MeV .A radiochromic film verified that the proton beam spot covered the flash memory device.Practical considerations of available beam time and test infrastructure generally preclude the complete testing of multi-terabit high-density memories.Instead,a representative sample of the array is characterized and assumptions made regarding the response of the entire device.A more thorough test is certainly appropriate when a specific application is targeted.In this work,the results sections indicate the size of memory tested,and test configuration,for each condition.In the case of heavy-ion testing at LBNL,it is only possible to test the top-most device in the stack due to ion range constraints.Heavy-ion SEFI testing included a fast (∼10ms)shutter mechanism in front of the device (Fig.4)to ensure that beam was only applied during specific operations [11],and that it could be immediately blocked from the device when a SEFI was detected.The fully-autonomous SEFI test detects anomalous device operation (or lack of any device response)and attempts recovery by RESET command,HARD RESET command,and finally by power cycle.RESET and HARD RESET are standard NAND flash commands documented by the manufacturer and communicated by the normal parallel databus.A power cycle physically pulls all device pins (both power and data)to 0V .Larger sample sizes are possible without the need to manually reconfigure the test between each event,and a more precise fluence-to-failure estimationFig.4.External shutter inserted in between facility and DUTis achieved by eliminating any manual response time.IV.H EAVY I ON R ESULTSA.Single-Event UpsetsAll SEU data were gathered with powered-off testing to isolate memory cell upsets from peripheral circuitry effects.The August 2022heavy ion data for the 96-layer Micron flash (Fig.7)represents four blocks (one per plane)totaling about 72MB of single-level cell (SLC)flash,and two blocks totaling about 108MB of triple-level cell (TLC)flash.The November heavy ion data (Fig.5)represents ten SLC blocks.It was observed initially that the SLC response was notice-ably better than expected at low LET compared to previously-published data for flash memories of generally-similar tech-nologies [5].After further investigation,the parts were tested again (Fig.5),but this time with adjustments made to the internal voltage threshold used to discriminate programmed cells (‘0’)from erased cells (‘1’)as provided in the man-ufacturer datasheet.Because NAND flash single-event upsets result in programmed (‘0’)cells turning into erased (‘1’)cells,it follows that adjusting the read offset setting towards theFig.5.Micron96-layer flash heavy-ion SEU responseerased state might increase the resistance to SEU,especially at lower LET where deposited charge is insufficient to fully shift a cell from0to1.See Fig.9for a generic illustration of this effect.Other tradeoffs(e.g.,long-term data retention) are possible.The black line in Fig.5is the original SLC data from Fig.7 with the default threshold voltages.The dashed line is a repeat of that test with zero offset explicitly set for confirmation of prior results.A clear trend of increased SEU hardness with lowered(i.e.,more negative)voltage threshold offset is present,as predicted by the effect of Fig.9.Similar test results are available for the176-layer Micron device in Fig.6.The Hynix device did not include a published mechanism to adjust the voltage threshold offsets and such testing was not performed in this study;a comparison of TLC and SLC SEU data is in Fig.8.B.Single-Event Functional InterruptsEach device was tested for susceptibility to single-event functional interrupts(SEFI),which are non-destructive(re-coverable)events caused by an upset in a critical element of control or peripheral circuitry that causes anomalous behavior. NAND flash SEFI are most easily grouped into those that cause a total loss of functionality requiring a power cycle, and those that cause malfunction within a portion of the memory array(e.g.,block-level SEFI that prevent successful READ,ERASE,or PROGRAM operations).The SEFI that completely disrupt functionality are detected in this test by frequent polling of the device with a READID command; this can be easily automated to collect statistically-significant volumes of events with accurate fluence-to-failure recorded. Additionally,the tester autonomously recovered from each of these SEFI and recorded whether a simple RESET orHARD Fig.6.Micron176-layer flash heavy-ion SEUresponseFig.7.Micron96-layer flash comparison of SLC and TLC modes RESET command was sufficient,or if the device required a power cycle to restore communications.Necessary and sufficient recovery steps for the Micron96-layer device are in Table II,for the Micron176-layer flash in Table III,those for the Hynix176-layer device are in Table IV, and breakdown of operational mode SEFI vulnerability in Table V.In Table V,a secondary shutter system was used to ensure the device was only exposed directly to the beam when the operational modes desired were active.Fig.8.SK Hynix 176-layer flash comparison of SLC and TLCmodesFig.9.Graphical diagram of the effect of varying LET on programmed flashcell threshold voltages.Green dashed lines are the programmed settings used to discriminate between programmed and erased SLC cells.SEFI testing of individual device operational modes was performed on all three memories.However,such testing is inherently time-consuming and not all combinations of device and operational mode were extensively characterized at all LET of interest;lack of data at any given LET does not imply a zero-error result.Data available are in Fig.10.Each device type is identified by marker shape,and each operational type during irradiation is indicated by color.Filled shapes indicateTABLE IISEFIRECOVERY STEPS NECESSARY FORM ICRON 96-LAYERDEVICELET (MeV·Fluence Count of READID SEFI resettable by -cm 2/mg)/cm 2RESET HARD RESET Pow.Cycle 18.02.01∗10610(77%)3(23%)0(0%)29.02.61∗10610(71%)1(7%)3(21%)56.08.58∗10689(77%)20(17%)6(5%)79.21.05∗107132(70%)40(21%)16(9%)Fig.10.Cross-section vs LET data for heavy-ion SEFI results in all three memories.TABLE IIISEFIRECOVERY STEPS NECESSARY FORM ICRON 176-LAYER DEVICELET Fluence Count of READID SEFI resettable by MeV·cm 2/mg/cm 2RESET HARD RESET Power Cycle 3.05.00∗1063008.02.01∗10620018.01.01∗10620029.01.00∗106700limiting cross-sections where no errors were observed during testing,and are computed as the inverse of the total tested fluence at that LET.SEFI operational testing was always performed with erase,program,read,and idle operations as typical of a data recorder-type application.In the case of an ERASE mode test,errors were detected in the erase or program stages by verifying the NAND status register flag was correctly set by the device indicating a successful operation after each erase or program command.Errors detected during readback were by means of an unrealistically-high error count at the block level.Following the erase-program-read-idle process,the device was reset and power cycled before restarting and re-opening the shutter.If a SEFI was observed during the active phase (e.g.,a failure to erase while under active irradiation)the beam was immediately blocked to minimize the probability of multiple events occurring during one cycle.In the case of a PROGRAM mode test,a single operational cycle was erase-program-read-idle-erase,such that the effects of a SEFI induced while programming could be evaluatedTABLE IVSEFIRECOVERY STEPS NECESSARY FORH YNIX 176-LAYERDEVICELETFluence Count of READID SEFI resettable by MeV·cm 2/mg/cm 2RESET HARD RESET Power Cycle 8.01.15∗10600029.01.0∗106010TABLE VSEFISUSCEPTIBILITY OFH YNIX 176-LAYER FLASH TO BLOCK -LEVEL ERASURE ,PROGRAMMING ,AND READBACK FAILURESLET Fluence Operational State While IrradiatingCount of block SEFI detected as failure to:MeV·cm 2/mg/cm 2ERASE PROGRAM READ 8.02.23∗105ERASE 39013858.02.23∗105PROGRAM 391818.02.23∗105READ 2503529.02.23∗105ERASE 4933829.02.23∗105PROGRAM 1676633129.02.23∗105READ200113144during all subsequent phases.Similarly,a READ mode testis constructed of erase-program-read-idle-erase-program,with only the read portion exposed to beam;subsequent SEFI observed during erase and program were fully evaluated prior to restarting the next test.These operational phases are similar to those described graphically and in more detail by [11].The total number of program-erase cycles did not approach the datasheet limits for these devices in either SLC or TLC mode.C.Single-Event LatchupTesting with 16MeV/amu Xe (incident LET 56.0MeV·cm 2/mg)revealed no single-event latchup (SEL)in any of the devices tested when irradiated at 85°C to a fluence of 1*107/cm 2at V CC of 3.3V .When irradiated at 45°angle (effective LET of 79.2MeV·cm 2/mg at die surface)no SEL was observed in the two Micron devices to a fluence of 1.05*107/cm 2.The Hynix 176-layer device had an anomalous high-current condition at this LET that reached power supply compliance and required a power cycle.This may be single-event latchup.Functionality was successfully recovered on-site,but further evaluation for latent damage has not been performed.The control circuitry for these devices is implemented under the flash memory stack (on the order of 10-20um below die surface).Beams used for this experiment had sufficient range to reach these circuits before the Bragg peak.However,precise estimation of tested LET requires construction analyses and will have the effect of raisingthe LET in the sensitive volume.V.P ROTON R ESULTSA.Single-Event UpsetsProton testing at the Massachusetts General Hospital’s Francis H.Burr Proton Therapy Center used 125-and 200-MeV proton irradiation to explore the proton sensitivity of the devices.Basic single-event upset test results are in Fig.11and represent test results with a 0x00repeating data pattern.To investigate any cumulative dose-related effects,one experiment included a series of exposures with intermediate measurement points to a total fluence of 1*1011p/cm 2.In Fig.12,four tests were performed without re-programming the memory.Then,a single test to the same fluence was performed for comparison.Proton testing also allowed the opportunity to explore the responses of individual die within the stacked part,rather than only a top-level die as in heavy-ion testing.In Fig.13,theFig.11.SEU data for all three devices with high-energy protons.Fig.12.Cumulative measurement of proton-induced upsets compared to a single measurement.125-and 200-MeV proton responses of all sixteen die are compared.The fluence for each energy was 1*1011p/cm 2.The actual physical order of the sixteen die is unknown.B.Single-Event Functional InterruptsSome 200-MeV proton SEFI test data is also available,though the overall sensitivity to SEFI with protons was rel-atively low.Testing was only performed with READID-style testing,in which the device ID is rapidly polled to verify basic functionality of the device.Results are in Table VI.BlockTABLE VISEFISUSCEPTIBILITY WITH200M E V PROTONS .Energy Device Total Fluence Observed Cross-sectionRecovery (MeV)(/cm 2)SEFI (cm 2)200SK Hynix 1761*101100N/A200Micron 964*101125.0*10−12Recovered with RESETMicron 176Not TestedFig.13.Proton-induced upsets in all sixteen die of the stacked device.SEFI events affecting memory integrity were not evaluated with protons.While the Micron 176layer device was not tested for SEFI with proton due to time constraints,it should be noted that this device had no READID SEFI (SEFI that resulted in loss of communications with the device)requiring more than a RESET command during heavy ion testing.VI.A CKNOWLEDGMENTSThe authors wish to thank additional colleagues at NASA GSFC for assistance with heavy ion testing and data analy-sis,including Michael Campola,Megan Casey,and Rebekah Austin,and wish to acknowledge Martha O’Bryan’s assistance with publication.R EFERENCES[1]K.Parat and A.Goda,“Scaling Trends in NAND Flash,”IEEE In-ternational Electron Devices Meeting ,San Francisco,CA,2018,pp.2.1.1-2.1.4.[2]L.Heineck and J.Liu,”3D NAND Flash Status and Trends,”2022IEEEInternational Memory Workshop (IMW),Dresden,Germany,2022,pp.1-4.[3]M.Bagatin et al.,”Single Event Effects in 3-D NAND Flash MemoryCells With Replacement Gate Technology,”in IEEE Transactions on Nuclear Science,vol.70,no.4,pp.308-313,April 2023[4]M.Bagatin et al.,”Effects of Heavy-Ion Irradiation on Vertical 3-DNAND Flash Memories,”in IEEE Transactions on Nuclear Science,vol.65,no.1,pp.318-325,Jan.2018.[5] E.P.Wilcox and M.J.Campola,”A TID and SEE Characterization ofMulti-Terabit COTS 3D NAND Flash,”2019IEEE Radiation Effects Data Workshop,San Antonio,TX,USA,2019,pp.238-244.[6] F.Irom,D.N.Nguyen and G.R.Allen,”Single Event Effect and TotalIonizing Dose Results of Highly Scaled Flash Memories,”2013IEEE Radiation Effects Data Workshop (REDW),San Francisco,CA,2013,pp.113-116.[7] D.Chen et al.,”Heavy Ion and Proton-Induced Single Event UpsetCharacteristics of a 3-D NAND Flash Memory,”in IEEE Transactions on Nuclear Science,vol.65,no.1,pp.19-26,Jan.2018.[8]M.K.Covo et al.,”88-Inch Cyclotron:The one-stop facility forelectronics radiation testing,”2017IEEE International Workshop on Metrology for AeroSpace (MetroAeroSpace),Padua,Italy,2017,pp.484-488.[9] E.W.Cascio,”A Five-Year Compendium of Proton Test Usage Patternsat the Francis H.Burr Proton Therapy Center,”2018IEEE Radiation Effects Data Workshop (REDW),Waikoloa,HI,USA,2018,pp.1-5.[10] F.Irom,D.N.Nguyen,G.R.Allen and S.A.Zajac,”Scaling Effectsin Highly Scaled Commercial Nonvolatile Flash Memories,”2012IEEE Radiation Effects Data Workshop,Tucson,AZ,2012,pp.103-108.[11] E.P.Wilcox,”Risk-Driven and Mitigation-Focused SEFI Testing ofNAND Flash Devices,”2022Single-Event Effects Symposium and Military &Aerospace Programmable Logic Device (SEEMAPLD)Workshop,La Jolla,CA,2022.。
Matrox Odyssey Xpro与Hitachi KP-FD202SCL相关的摄像头接口应用指
HITACHI KP-FD202SCL October 22, 2008 Basics about thecameraCamera Descriptions▪ Effective resolution: 1620 ⨯ 1220 ⨯ 12-bit @ 30 fps.▪ Camera Link MEDIUM interface (RGB).▪ Progressive scan.▪ Internal sync.▪ Internal or external exposure control.▪ 72 MHz pixel clock rate.Mode of operations as per Matrox Imaging (in parentheses as per camera manufacturer)Interface Mode▪ Continuous▪ Pseudo-continuous (Trigger Mode 1Trigger) ▪ Asynchronous reset (Trigger Mode 1Trigger)Basics about theinterface modesCamera Interface BriefsMode 1: Continuous▪ 1620 ⨯ 1220 ⨯ 12-bit @ 30 fps.▪ Camera Link MEDIUM interface (RGB).▪ Progressive scan.▪ Matrox Odyssey Xpro receiving LVAL, FVAL, PCLK and video signal fromcamera.▪ DCF used: KPFD202SCL1620x1220_8bitCon.DCFMode 2: Pseudo-continuous▪ 1620 ⨯ 1220 ⨯ 12-bit.▪ Camera Link MEDIUM interface (RGB).▪ Progressive scan.▪ Matrox Odyssey Xpro sending periodic TIMER1 OUT (CC1) signal tocamera to initiate and control exposure time.▪ Matrox Odyssey Xpro receiving LVAL, FVAL, PCLK and video signal fromcamera.Continued…HITACHI KP-FD202SCL October 22, 2008 Basics about theCamera Interface Briefs (cont.)interface modesMode 2: Pseudo-continuous▪ DCF used: KPFD202SCL1620x1220_8bitPcon.DCF▪ 1620 ⨯ 1220 ⨯ 12-bit.▪ Camera Link MEDIUM interface (RGB).▪ Progressive scan.▪ Matrox Odyssey Xpro receiving external trigger signal.▪ Matrox Odyssey Xpro sending TIMER1 OUT (CC1) signal to camera toinitiate and control exposure time.▪ Matrox Odyssey Xpro receiving LVAL, FVAL, PCLK and video signal fromcamera.▪ DCF used: KPFD202SCL1620x1220_8bitAsync.DCFCamera Interface Detailsinterface modesMode 1: Continuous▪Frame Rate: Matrox Odyssey Xpro receives the continuous video fromthe camera at 30 frames per second.▪Exposure time: Exposure time is set using the integration time settingin the Camera Configuration Utility. Refer to the camera manual for moreinformation.▪Camera control settings: The camera mode is set to Trigger modeOFF in the Camera Configuration Utility. Refer to the camera manual formore information.Matrox Odyssey XproCamera Interface Application NoteHITACHI KP-FD202SCL October 22, 2008 Specifics about theCamera Interface Details (cont.)interface modesMode 2: Pseudo-continuous▪Frame rate: The frame rate is determined by the frequency of theTIMER1 OUT (CC1) signal.▪Exposure time: The width (rising edge to falling edge) of the TIMER1OUT (CC1) signal is the exposure time, which can be modified in the DCFusing Matrox Intellicam, the ONL imCamControl() or imDigControl()function, or with the MIL MdigControl() function. Consult the respectivemanual for more information.▪Camera Configuration: The camera mode is set to Trigger mode 1Trigger in the Camera Configuration Utility. Refer to the camera manualfor more information.Mode 3: Asynchronous Reset▪Frame rate: The frame rate is determined by the frequency of theexternal trigger signal.▪Exposure time: Same as in Mode 2: Pseudo-continuous.▪Camera Configuration: Same as in Mode 2: Pseudo-continuous.Cabling details for theCabling Requirementsinterface modesModes 1 and 2: Continuous and Pseudo-continuous▪Cable and Connection: Two Mini-Camera Link Cables.Mode 3: Asynchronous reset▪Cable and Connection: Two Mini-Camera Link cable.▪External trigger: External trigger should be connected to the OPTO TRIGinput of the 9-pin connector on the Expanded I/O adapter bracket.EXPANDED I/O BRACKET(9-pin connector) External Trigger SourceOPTOTRIG + 07 ←SIGNAL --OPTOTRIG - 02 ←GROUND --The DCFs mentioned in this application note are also attached (embedded) to this PDF file – use the Adobe Reader’s View File Attachment to access the DCF files. The information furnished by Matrox Electronics System, Ltd. is believed to be accurate and reliable. Please verify all interface connections with camera documentation or manual. Contact your local sales representative or Matrox Sales office or Matrox Imaging Applications at 514-822-6061 for assistance. © Matrox Electronic Systems Ltd, 2008-2011.Matrox Electronic Systems Ltd.1055 St. Regis Blvd.Dorval, Quebec H9P 2T4CanadaTel: (514) 685-2630Fax: (514) 822-6273。
Research_Development_on_Sodium-Ion_Batteries
Research Development on Sodium-Ion Batteries
Naoaki Yabuuchi,†,‡,§ Kei Kubota,†,‡ Mouad Dahbi,†,‡ and Shinichi Komaba*pplied Chemistry, Tokyo University of Science, 1-3 Kagurazaka, Shinjuku, Tokyo 162-8061, Japan Elements Strategy Initiative for Catalysts and Batteries (ESICB), Kyoto University, Katsura, Kyoto 615-8520, Japan
Review
Figure 1. Elemental abundance in the Earth’s crust. Data derived from ref 3.
Li2CO3) was steeply increased during the first decade of this century.4 Moreover, lithium resources are unevenly distributed (mainly in South America); therefore, production of LIBs depends on the import of lithium from South America. In contrast to lithium, sodium resources are unlimited everywhere, and sodium is one of the most abundant elements in the Earth’s crust. The infinite sodium resources are also found in the ocean. Additionally, sodium is the second-lightest and -smallest alkali metal next to lithium as shown in Table 1. On the basis of material abundance and standard electrode potential, rechargeable sodium batteries (or Na-ion battery, NIB, if we follow the terminology of LIB) are the ideal alternative to LIBs.4−6 NIBs are operable at ambient temperature, and metallic sodium is not used as the negative electrode, which is different
SRD-1656D 16CH CIF 实时DVR用户手册说明书
SRD -1656D16CH CIF (1280H available) Real-time DVRKey FeaturesSRD-1656DDIsplay Video Inputs 16 Composite video 0.5-1 Vpp, 75 ohm automatic termination Resolution NTSC : 1280 x 480, 720 x 480 / PAL : 1280 x 576, 720 x 576liveFrame Rate NTSC : 480fps / PAL : 400fpsResolutionNTSC : 1280 x 480, 720 x 480 / PAL : 1280 x 576, 720 x 576Multi screen Display1 / 4 / 7 / 9 / 13 / 16 / 16A / Sequence / PIP peRFoRManCeoperating system embeddedLinux RecordingCompressionH.264Record RateNTSC : Up to 120fps@1280 x 480 / PAL : Up to 100fps@1280 x 576NTSC : Up to 120fps@704 x 480 / PAL : Up to 100fps@704 x 576NTSC : Up to 240fps@704 x 240 / PAL : Up to 200fps@704 x 288NTSC : Up to 480fps@352 x 240 / PAL : Up to 400fps@352 x 288ModeNTSC : Manual, Schedule (Continuous / Event), Event (Pre / Post), Time lapse (1~30 fps)PAL : Manual, Schedule (Continuous / Event), Event (Pre / Post), Time lapse (1 ~ 25fps)eventVideo loss, Motion (Level 1 ~ 10), Alarm, Tampering (Level 1 ~ 3)overwrite Modes Selectable (Stop / Continuous)pre-alarm Up to 30sec (5, 10, 20, 30sec)post-alarm Up to 6hour (5,10, 20, 30sec, 1, 3, 5, 10, 20min, 1, 2, 3, 4, 5, 6hour)search &playbacksearch ModeDate/Time, Event, Back up, POS, Motion (*All search include preview function)playback FunctionFast forward / backward (2x, 4x, 8x, 16x, 32x, 64x) *Backward play with i-frame only Slow forward / backward (1/2x, 1/4x, 1/8x)Step forward / backward *Backward play with i-frame onlynetwork (Ipv4)Transmission speed4CIF / 2CIF / CIF (NTSC : 120 / 240 / 480fps, PAL : 100 / 200 / 400fps)BandwidthUp to 32Mbps Bandwidth ControlSelectablestreamH.264 (4CIF / 2CIF / CIF selectable)Max. Remote Users Search 3 / Live unicast 10 / Live multicast 20protocol support TCP/IP , DHCP , PPPoE, SMTP , NTP , HTTP , HTTPS, DDNS, RTP , RTSP , SNMP Monitoring SmartViewer, Webviewer, SSM (CMS)smart phone platformAndroid, iOSprotocol supportRTP , RTSP , HTTP , CGI Max. Remote Users Live 2, Search 1storage Internal HDDUp to 4 SATA HDDsexternal (e-saTa Interface)2 External SATA ports (*Expansion bay, Model : SVS-5R/5E) DVD Writer (Back up)YesUsB (Back up)2 USB portsFile Format (Back up)BU (DVR player), EXE (Include player), AVI securitypassword protection1 Admin, 10 Group, 10 User per 1 group Data authenticationWatermark* The latest product information / specification can be found at • 16CH CIF real-time DVR• Up to 480(NTSC) / 400(PAL)fps recording rate • HDMI / VGA video output• 16CH audio inputs / 1CH audio output • Max. 4 internal HDDs• PTZ control via coaxial cable (Samsung CCVC, Pelco-C)• DVD-RW, Smart phone support (Android / iOS)• Accurate still image (De-Interlace support each channel)• Enhanced Network Bandwidth up to 32Mbps。
NVIDIA nForce 590 SLI系列产品说明说明书
Características y ventajasMCP NVIDIA nForce® 590 SLIPensado para entusiastasLos procesadores de comunicaciones y contenidos multimedia (MCP) NVIDIA nForce® 590 SLI™ proporcionan todas las herramientas y el rendimiento que necesitan los frikis del PC. Si se combinan con determinadas tarjetas gráficas NVIDIA GeForce y otros componentes del sistema, la velocidad del bus aumenta de forma dinámica. Además, ofrecen funciones de overclocking y mayor rapidez en la transmisión de datos.Tecnología NVIDIA LinkBoost™El MCP nForce 590 SLI incrementa automáticamente el ancho de banda cuando detecta la presencia de determinadas tarjetas gráficas NVIDIA® GeForce®.Diseñado para NVIDIA® SLI™La tecnología NVIDIA SLI es una innovación revolucionaria que permite aumentar drásticamente el rendimiento gráfico combinando varias GPU NVIDIA en un mismo sistema dotado de un MCP NVIDIA nForce SLI.Componentes con certificación NVIDIA SLICuando se combinan ciertos componentes (como determinadas GPU NVIDIA® GeForce® y memorias del sistema) con placas basadas en el MCP nForce 590 SLI, se incrementa automáticamente la velocidad del bus del sistema. Si quieres información sobre los componentes con certificación SLI, visita \nForce.Dos enlaces PCI Express SLI x16El ancho de banda de los dos enlaces PCI Express de 16 vías garantiza el máximo rendimiento gráfico para los juegos y las GPU de última generación. Multiplica por dos el ancho de banda de las soluciones PCI Express SLI x8.Almacenamiento MediaShield™ de NVIDIAConjunto de funciones que mantiene a salvo la información digital. Siempre fiable, escalable y accesible. Incluye soporte de configuraciones RAID y unidades de disco SATA.Configuración de varios discosUn sencillo asistente ayuda a configurar fácilmente las unidades de disco para obtener mayor protección de los datos, un acceso más rápido a los discos o máxima capacidad de almacenamiento.MediaShield selecciona automáticamente la configuración RAID 0, 1, 0+1 o 5 en función de tus necesidades. Los más expertos pueden manejar las opciones RAID directamente si lo prefieren.Sistema de alerta de discosSi falla alguno de los discos, MediaShield presenta una imagen en la que señala el disco defectuoso para facilitar su identificación, sustitución y recuperación.Migración de nivel RAID (morphing)MediaShield ofrece al usuario la posibilidad de cambiar la configuración RAID existente por otra configuración en un solo paso denominado cambio de nivel o morphing. Esto elimina la necesidad de hacer la copia de seguridad de los datos y efectuar los numerosos pasos que conllevaría el proceso manual.Matriz de discos de arranqueLas funciones MediaShield permiten utilizar una matriz de discos para cargar el sistema operativo al arranque.Seis unidades de disco SATA 3Gb/sPosibilidad de combinar hasta 6 unidades SATA en un volumen para obtener configuraciones RAID más rápidas y de mayor capacidad. La presencia de más discos significa más opciones de configuración, lo que incluye, por ejemplo, dos matrices RAID 5 o 6 unidades RAID 0 (striping) para obtener máxima velocidad de acceso a los datos. Además, el soporte de unidades SATA-2 3Gb/s permite aprovechar ventajas como las funciones de conexión en caliente y reordenación de colas de comandos (Native Command Queuing y Tagged Command Queuing). Las colas de comandos nativas aumentan la eficacia del acceso a los discos en entornos multithread porque permiten mantener las operaciones de lectura/escritura en espera para ejecutarlas en el orden más conveniente.Comunicación en red con NVIDIA nForceLa tecnología de red de NVIDIA proporciona la máxima velocidad de transmisión con el menor índice de utilización de la CPU. Además de ser extraordinariamente estable y manejable, esta solución facilita la administración de la red y reduce el coste total de propiedad. Sólo NVIDIA integra este nivel de funcionalidad de red para llevar la comunicación online a otra dimensión.Gigabit Ethernet nativo de NVIDIALa máxima velocidad existente en conexiones Gigabit Ethernet. Elimina los cuellos de botella y mejora la eficacia global del sistema.Tecnología NVIDIA FirstPacket™Conviértete en el “rey del ping” con la tecnología FirstPacket de NVIDIA. Tendrás la mejor calidad de comunicación en tus llamadas telefónicas y todo el rendimiento que necesitas al jugar online.FirstPacket garantiza que los datos de los juegos, las comunicaciones de voz sobre IP (VoIP) y las transferencias de archivos de gran tamaño se gestionarán de acuerdo con las preferencias que tú establezcas a través de un sencillo asistente de configuración.Tecnología NVIDIA DualNet®Duplica la capacidad de tus comunicaciones en red con las dos conexiones Gigabit Ethernet integradas en el MCP NVIDIA nForce 500.Combinación de las dos conexiones Gigabit EthernetLa combinación de ambas conexiones permite sumar su capacidad para duplicar el ancho de banda Ethernet y, de esta forma, poder transferir grandes cantidades de datos desde el servidor de archivos a otros PC. Además, proporciona redundancia gracias al cambio automático de enlace en caso de fallo (failover).Aceleración de las funciones TCP/IPOfrece el máximo rendimiento del sistema al realizar mediante hardware el trabajo de filtrado de paquetes normalmente reservado a la CPU, lo que proporciona un entorno de red más rápido. Utilidad NVIDIA nTune™ 4.0La nueva versión de esta utilidad Windows incluye más opciones para optimizar el rendimiento. nTune permite ajustar manual o automáticamente los parámetros del sistema para conseguir el rendimiento deseado. Una vez realizada la configuración, la utilidad elige automáticamente los parámetros adecuados para la aplicación que se ejecute basándose en las reglas personales y los perfiles definidos por el usuario.PCI ExpressDiseñado para funcionar con el bus PCI Express. Este bus duplica el ancho de banda del bus AGP 8X, lo que proporciona una velocidad superior a 4 GB/s en las transferencias de datos en ambas direcciones.Audio de alta definición (HDA)El audio de alta definición introduce en el PC la calidad de sonido de los equipos electrónicos de consumo. Con HDA, los sistemas pueden proporcionar un extraordinario sonido de 192 kHz/32 bits a través de ocho canales que admiten los nuevos formatos de audio.USB 2.0Interfaz estándar que proporciona conexión inmediata con los dispositivos USB.。
毕赤酵母手册
Pichia expression vectors for selection on Zeocin™ and purification of secreted, recombinant proteins
Cat. no. V195-20 Rev. Date: 7 July 2010 Manual part no. 25-0150
MAN0000035
User Manual
ii
Table of Contents
Important Information................................................................................................................................ v Accessory Products ................................................................................................................................... vii Introduction ................................................................................................................................................. 1 Overview .......................................................................................................................................................1 Methods........................................................................................................................................................ 2 Cloning into pPICZ A, B, and C...............................................................................................................2 Multiple Cloning Site of pPICZ A ...........................................................................................................5 Multiple Cloning Site of pPICZ B ............................................................................................................6 Multiple Cloning Site of pPICZ C............................................................................................................7 Pichia Transformation ..................................................................................................................................9 Expression in Pichia ....................................................................................................................................13 Purification ...........................................................................................................................15 Appendix .................................................................................................................................................... 17 Recipes .........................................................................................................................................................17 Zeocin™ ........................................................................................................................................................19 pPICZ Vector ............................................................................................................................................21 Lithium Chloride Transformation Method.............................................................................................23 Construction of In Vitro Multimers..........................................................................................................25 Technical Support.......................................................................................................................................33 Purchaser Notification ...............................................................................................................................34 References....................................................................................................................................................35
Symphony Enterprise Management和控制系统的Cnet高速数据通信网络说明
Features and Benefits Overview Control ITHarmony RackCommunications Control Network, Cnet, is a high-speed data communicationhighway between nodes in the Symphony™ Enterprise Man-agement and Control System. Cnet provides a data pathamong Harmony control units (HCU), human system inter-faces (HSI), and computers. High system reliability andavailability are key characteristics of this mission-criticalcommunication network. Reliability is bolstered by redun-dant hardware and communication media in a way that thebackup automatically takes over in the event of a fault in theprimary. Extensive use of error checking and messageacknowledgment assures accurate communication of criticalprocess data.Cnet uses exception reporting to increase the effective band-width of the communication network. This method offers theuser the flexibility of managing the flow of process data andultimately the process. Data is transmitted only when it haschanged by an amount which can be user selected, or when apredetermined time-out period is exceeded. The system pro-vides default values for these parameters, but the user cancustomize them to meet the specific needs of the processunder control.TC00895A■Fast plant-wide communication network: Cnet provides fastresponse time to insure timelyinformation exchange.■Efficient data transfer: Message packing and multiple address-ing increase data handlingefficiency and throughput.■Plant-wide time synchronization: Time synchronization of Cnetnodes throughout the entirecontrol process insures accuratedata time-stamping.■Independent node communica-tion: Each Cnet node operatesindependently of other nodes.Requires no traffic directors;each node is its owncommunication manager.■Accurate data exchange: Multi-ple self-check features including positive message acknowledg-ment, cyclic redundancy checks(CRC), and checksums insuredata integrity.■Automatic communications recovery: Rack communicationmodules provide localized start-up/shutdown on power failurewithout operator intervention.Each type of interface supportsredundancy.Harmony Rack CommunicationsOverviewHarmony rack communications encompasses various communication interfaces as shown inFigure1: Cnet-to-Cnet communication, Cnet-to-HCU communication, and Cnet-to-computercommunication.Figure 1. Harmony Rack Communications ArchitectureThe communication interface units transfer exception reports and system data, control, and con-figuration messages over Cnet. Exception reported data appears as dynamic values, alarms, and state changes on displays and in reports generated by human system interfaces and other system nodes. Exception reporting is automatic at the Harmony controller level. Specifically, the control-ler generates an exception report periodically to update data, after a process point reaches adefined alarm limit or changes state, or after a significant change in value occurs.Harmony Rack Communications Control NetworkCnet is a unidirectional, high speed serial data network that operates at a 10-megahertz or two-megahertz communication rate. It supports a central network with up to 250 system node connec-tions. Multiple satellite networks can link to the central network. Each satellite network supports up to 250 system node connections. Interfacing a maximum number of satellite networks gives a system capacity of over 62,000 nodes.On the central network, a node can be a bridge to a satellite network, a Harmony control unit, a human system interface, or a computer, each connected through a Cnet communication interface.On a satellite network, a node can be a bridge to the central network, a Harmony control unit, a human system interface, or a computer.Harmony Control UnitThe Harmony control unit is the fundamental control node of the Symphony system. It connects to Cnet through a Cnet-to-HCU interface. The HCU cabinet contains the Harmony controllers and input/output devices. The actual process control and management takes place at this level. HCU connection to Cnet enables Harmony controllers to:■Communicate field input values and states for process monitoring and control.■Communicate configuration parameters that determine the operation of functions such asalarming, trending, and logging on a human system interface.■Receive control instructions from a human system interface to adjust process field outputs.■Provide feedback to plant personnel of actual output changes.Human System InterfaceA human system interface such as a Signature Series workstation running Maestro or ConductorSeries software provides the ability to monitor and control plant operations from a single point. It connects to Cnet through a Cnet-to-computer interface. The number of workstations in a Sym-phony system varies and depends on the overall control plan and size of a plant. The workstation connection to Cnet gives plant personnel access to dynamic plant-wide process information, and enables monitoring, tuning, and control of an entire plant process from workstation color graphics displays and a pushbutton keyboard.ComputerA computer can access Cnet for data acquisition, system configuration, and process control. It con-nects to Cnet through a Cnet-to-computer interface. The computer connection to Cnet enablesplant personnel, for example, to develop and maintain control configurations, manage the system database, and create HSI displays remotely using Composer™engineering tools. There are addi-tional Composer and Performer series tools and applications that can access plant informationthrough a Cnet-to-computer interface.Cnet-to-Cnet Communication InterfaceThe Cnet-to-Cnet interfaces are the INIIR01 Remote Interface and the INIIL02 Local Interface.Figure2 shows the remote interface and Figure 3 shows the local interface.Harmony Rack CommunicationsFigure 2. Cnet-to-Cnet Remote Interface (INIIR01)Figure 3. Cnet-to-Cnet Local Interface (INIIL02)Harmony Rack Communications INIIR01 Remote InterfaceThe INIIR01 Remote Interface consists of the INNIS01 Network Interface Module and the INIIT12 Remote Transfer Module (Fig.2). This interface is a node on a central network that can communi-cate to an interface node on a remote satellite network. In this arrangement, two interfaces arerequired: one for the central network, and the other for the satellite network. Bidirectional commu-nication from the central network to the remote satellite network is through standard RS-232-Cports.The remote interface supports hardware redundancy. Redundancy requires a full set of duplicate modules (two INNIS01 modules and two INIIT12 modules on each network). The secondaryINIIT12 module continuously monitors the primary over dedicated Controlway. A failover occurs when the secondary module detects a primary module failure. When this happens, the secondary interface takes over and the primary interface is taken offline.INIIL02 Local InterfaceThe INIIL02 Local Interface consists of two INNIS01 Network Interface modules and the INIIT03 Local Transfer Module (Fig.3). This interface acts as a bridge between two local Cnets. One of the INNIS01 modules operates on the central network side and the other operates on the satellite net-work side. Bidirectional communication from the central network to the local satellite network is through cable connection to the NTCL01 termination unit. The maximum distance betweentermination units on the two communication networks is 45.8 meters (150feet).The local interface supports hardware redundancy. Redundancy requires a full set of duplicatemodules (four INNIS01 modules and two INIIT03 modules). The secondary INIIT03 module con-tinuously monitors the primary over dedicated Controlway. A failover occurs when the secondary detects a primary module failure. When this happens, the secondary assumes responsibility and the primary is taken offline.Cnet-to-HCU Communication InterfaceThe Harmony control unit interface consists of the INNIS01 Network Interface Module and the INNPM12 or INNPM11 Network Processing Module (Fig. 4). This interface can be used for a node on the central network or on a satellite network (Fig.1). Through this interface the Harmony con-trol unit has access to Cnet and to Controlway at the same time. Controlway is an internal cabinet communication bus between Harmony rack controllers and the communication interfacemodules.The HCU interface supports hardware redundancy. Redundancy requires a full set of duplicate modules (two INNIS01 modules and two INNPM12 or INNPM11 modules). The secondary net-work processing module (INNPM12 or INNPM11) continuously monitors the primary through a direct ribbon cable connection. A failover occurs when the secondary detects a primary module failure. When this happens, the secondary assumes responsibility and the primary is taken offline. Cnet-to-Computer Communication InterfaceThe Cnet-to-computer interfaces are the INICI03 and INICI12 interfaces. The INICI03 interfaceconsists of the INNIS01 Network Interface Module, the INICT03A Computer Transfer Module,and the IMMPI01 Multifunction Processor Interface Module (Fig. 5). The INICI12 interface con-sists of the INNIS01 Network Interface Module and the INICT12 Computer Transfer Module(Fig6).Harmony Rack CommunicationsFigure 4. Cnet-to-HCU InterfaceFigure 5. Cnet-to-Computer Interface (INICI03)Figure 6. Cnet-to-Computer Interface (INICI12)Harmony Rack CommunicationsA computer interface can be used for a node on the central network or on a satellite network (Fig.1). It gives a host computer access to point data over Cnet. The computer connects through either an RS-232-C serial link at rates up to 19.2 kilobaud or through a SCSI parallel port when using an INICI03 interface. The computer connects through an RS-232-C serial link at rates up to 19.2 kilobaud when using an INICI12 interface. Each interface is command driven through soft-ware on the host computer. It receives a command from the host computer, executes it, then replies to the host computer.Note: A workstation running Conductor VMS software does not use an INICI03 or INICI12 Cnet-to-Computer Interface but instead has its own dedicated version of the Cnet-to-computer interface (IIMCP02 and IIMLM01).Communication ModulesTable 1 lists the available Harmony rack communication modules. These modules, in certain combinations, create the various Cnet communication interfaces.Network Interface ModuleThe INNIS01 Network Interface Module is the front end for all the different Cnet communication interfaces. It is the intelligent link between a node and Cnet. The INNIS01 module works in con-junction with the transfer modules and the network processing module. This allows any node to communicate with any other node within the Symphony system.The INNIS01 module is a single printed circuit board that occupies one slot in the module mount-ing unit (MMU). The circuit board contains microprocessor based communication circuitry that enables it to directly communicate with the transfer modules and network processing module, and to interface to Cnet.The INNIS01 module connects to its Cnet communication network through a cable connected to an NTCL01 termination unit. Communication between nodes is through coaxial or twinaxial cables that connect to the termination units on each node.Cnet-to-Cnet Remote Transfer ModuleThe INIIT12 Remote Transfer Module supports bidirectional communication through twoRS-232-C ports. Port one passes system data only. Port two passes system data or can be used as a diagnostic port. The central network INIIT12 module can use a variety of means to link to the sat-ellite network INIIT12 module such as modems, microwave, and transceivers. The INIIT12Table 1. Harmony Rack Communication Modules ModuleDescription Cnet-to-Cnet Cnet-to-HCU Cnet-to-Computer INIIR01 INIIL02 INICI03INICI12 IMMPI01Multifunction processor interface •INICT03ACnet-to-computer transfer •INICT12Cnet-to-computer transfer •INIIT03Cnet-to-Cnet local transfer •INIIT12Cnet-to-Cnet remote transfer •INNIS01Network interface •••••INNPM11 or INNPM12Network processing•Harmony Rack Communicationsmodule directly communicates with an INNIS01 module. Many of the operating characteristics of the INIIT12 module are determined by function code202 (INIIT12 executive) specifications.The INIIT12 module is a single printed circuit board that occupies one slot in the module mount-ing unit. The circuit board contains microprocessor based communication circuitry that enables it to serially communicate with another INIIT12 module, to directly communicate with its INNIS01 module, and to interface to Controlway.The INIIT12 module connects through a cable to an NTMP01 termination unit. The two RS-232-C ports are located on the termination unit.Cnet-to-Cnet Local Transfer ModuleThe INIIT03 Local Transfer Module serves as the bridge between two local Cnet communication networks. It holds the node database and is responsible for transferring all messages between net-works. Messages include exception reports, configuration data, control data, and system status.This module directly communicates with the INNIS01 module of the central network and of the satellite network simultaneously.The INIIT03 module is a single printed circuit board that occupies one slot in the module mount-ing unit. The circuit board contains microprocessor based communication circuitry that enables it to directly communicate with its two INNIS01 modules and to interface to Controlway.Cnet-to-Computer Transfer ModuleThe INICT03A Computer Transfer Module and INICT12 Computer Transfer Module handle all communication with a host computer. These modules are command driven through software on the host computer. The module receives a command from the host computer, executes it, thenreplies. Its firmware enables the host computer to issue commands for data acquisition, process monitoring, and process control, and to perform system functions such as security, timesynchronization, status monitoring, and module configuration.The INICT03A and INICT12 modules are single printed circuit boards that occupy one slot in the module mounting unit. Their capabilities and computer connection methods differ. The INICT03A module can store up to 30,000 point definitions (depending on point types). The INICT12 module can store up to 10,000 point definitions.For the INICT03A module, the circuit board contains microprocessor based communication cir-cuitry that enables it to directly communicate with its INNIS01 module and to directlycommunicate with an IMMPI01 module. It communicates with the IMMPI01 module through a ribbon cable connection. The IMMPI01 module handles the actual host computer interface andsupports RS-232-C or SCSI serial communication.For the INICT12 module, the circuit board contains microprocessor based communication cir-cuitry that enables it to directly communicate with its INNIS01 module and to directlycommunicate with a host computer using RS-232-C serial communication. The module cable con-nects to an NTMP01 termination unit. Two RS-232-C ports are located on the termination unit. The NTMP01 jumper configuration determines DTE or DCE operation.Multifunction Processor Interface ModuleThe IMMPI01 Multifunction Processor Interface Module handles the I/O interface between thehost computer and the INICT03A Computer Transfer Module. The IMMPI01 module supportseither a SCSI or RS-232-C computer interface. When communicating through the RS-232-C port, the module can act as data communication equipment (DCE) or data terminal equipment (DTE).Harmony Rack Communications The IMMPI01 module is a single printed circuit board that occupies one slot in the module mount-ing unit. The circuit board contains microprocessor based communication circuitry that enables it to communicate with its INICT03A module through a ribbon cable connection.For RS-232-C computer interface, the module cable connects to an NTMP01 termination unit. Two RS-232-C ports are located on the termination unit. The NTMP01 jumper configuration determines DTE or DCE operation. The SCSI port is located at the module faceplate. In this case, notermination unit is required.Network Processing ModuleThe INNPM12 or INNPM11 Network Processing Module acts as a gateway between Cnet andControlway. The module holds the Harmony control unit database and handles the communica-tion between controllers residing on Controlway and the INNIS01 module.The INNPM12 or INNPM11 module is a single printed circuit board that occupies one slot in the module mounting unit. The circuit board contains microprocessor based communication circuitry that enables it to directly communicate with its INNIS01 module and to interface to Controlway.Rack Communications PowerHarmony rack communication modules are powered by 5, 15, and -15VDC logic power. Modular Power System II supplies the logic power. These operating voltages are distributed from thepower system through a system power bus bar mounted in the cabinet. A module mounting unit connects to this bus bar then routes the power to individual modules through backplaneconnectors.Rack Communications Mounting HardwareHarmony rack communication modules and their termination units mount in standard ABB cabi-nets. The option for small cabinet mounting is provided. The number of modules that can bemounted in a single cabinet varies. Modules of an interface are always mounted in adjacent slots.An IEMMU11, IEMMU12, IEMMU21, or IEMMU22 Module Mounting Unit and an NFTP01 Field Termination Panel are used for module and termination unit mounting respectively (Fig. 7). The mounting unit and termination panel both attach to standard 483-millimeter (19-inch) width side rails. Front mount and rear mount MMU versions are available to provide flexibility in cabinetmounting.A module mounting unit is required to mount and provide power to rack mounted modules. Theunit is for mounting Harmony rack controllers, I/O modules, and communication interfacemodules. The MMU backplane connects and routes:■Controlway.■I/O expander bus.■Logic power to rack modules.The Controlway and I/O expander bus are internal cabinet, communication buses. Communica-tion between rack controllers and HCU communication interface modules is over Controlway. The Cnet-to-Cnet interfaces use dedicated Controlway for redundancy communication. This dedicated Controlway is isolated from all other modules.Harmony Rack CommunicationsFigure 7. Rack I/O Mounting HardwareRelated DocumentsNumber Document TitleWBPEEUD250001??Harmony Rack Communications, Data SheetHarmony Rack Communications WBPEEUS250002C111Harmony Rack CommunicationsWBPEEUS250002C1Litho in U.S.A.May 2003Copyright © 2003 by ABB, All Rights Reserved® Registered Trademark of ABB.™ Trademark of ABB.For more information on the Control IT suiteofproducts,***************************.comFor the latest information on ABB visit us on the World Wide Web at /controlAutomation Technology Products Mannheim, Germany www.abb.de/processautomation email:*********************************.com Automation Technology ProductsWickliffe, Ohio, USA/processautomation email:****************************.com Automation Technology Products Västerås, Sweden /processautomation email:************************.com ™Composer, Control IT , and Symphony are trademarks of ABB.。
我最喜欢的卡通人物小公主苏菲英语作文
My Favorite Cartoon Character: LittlePrincess SophieIn the vast realm of cartoon characters, there is one who holds a special place in my heart - Little Princess Sophie. She is not just a fictional creation but a symbolof courage, kindness, and perseverance. Her story, filled with adventure and magic, has captivated my imagination and left a lasting impression on my childhood memories.Sophie, the titular character of the cartoon series, is a young girl with a big heart and an even bigger dream. She lives in a enchanted kingdom where mysteries and wonders abound. Despite being a princess, Sophie's life is far from the typical fairytale portrayal. She faces challenges and obstacles that test her mettle and her resolve.What makes Sophie so endearing is her unwavering spirit. She is not afraid to take risks or face her fears. Whetherit's battling a dragon or solving a puzzle that couldunlock the secrets of her kingdom, Sophie approaches each task with a determined smile and a can-do attitude. Her courage is not just physical; it's also emotional. She iswilling to stand up for what she believes in, even when it means going against the grain or challenging authority.Sophie's kindness is another trait that resonates deeply with me. She is always ready to lend a helping hand to those in need, whether it's a friend in trouble or a stranger in distress. Her compassion is not limited to humans; she treats all creatures, from the smallest bug to the largest beast, with respect and care. This empathy and understanding make her a true role model for young viewers. The cartoon series also explores Sophie's relationship with her family and friends. These interactions provide a window into her character, revealing her loyalty, love, and a sense of humor. Her bond with her parents and siblings is particularly heartwarming, showing how family ties can be a source of strength and comfort in times of trouble.What I admire most about Sophie is her perseverance. She never gives up, even when faced with seemingly insurmountable obstacles. She learns from her mistakes, adapts to new situations, and finds creative solutions to problems. This resilience and adaptability are qualities that I strive to emulate in my own life.In conclusion, Little Princess Sophie is not just a cartoon character; she is a hero in my eyes. Her story teaches valuable lessons about courage, kindness, and perseverance. She inspires me to be brave, to be kind, andto never give up on my dreams. For these reasons and many more, Little Princess Sophie remains my favorite cartoon character to this day.**我最喜欢的卡通人物:小公主苏菲**在众多的卡通人物中,有一个角色在我心中占据了特殊的位置——小公主苏菲。
介绍八寻宁宁的英语作文
介绍八寻宁宁的英语作文Amidst the vast universe of anime characters, Yotsuba Nanami stands out as a beacon of uniqueness and charm. Her journey through the world of the supernatural, as portrayed in the anime "Uzumaki: Whirlpool of Dreams," is not just a thrilling adventure but a testament to her resilience and courage.Yotsuba Nanami is a girl with a mysterious past and an even more enigmatic future. Her eyes are windows to a different world, a world where the supernatural and the ordinary coexist, where dreams and nightmares blend into a tapestry of infinite possibilities. Her hair, a cascade of deep indigo, flows behind her like a river of night, complementing her pale skin and intense gaze.Her personality is a complex tapestry of contradictions. She is both strong and vulnerable, wise and naive, a seeker of truth and a runner from her own destiny. This contradiction is what makes her so charming. She is not a two-dimensional character; she is a three-dimensional being with layers of depth and nuance that make her relatable and engaging.Yotsuba's relationship with her friends and foes is another layer of her charm. She is a loyal friend, willing to sacrifice herself for the ones she cares about. But she is also a fierce opponent, unafraid to face her fears and challenges head-on. This balance of kindness and courage is what makes her stand out in a world full of characters.The anime "Uzumaki: Whirlpool of Dreams" is not just about Yotsuba's adventures in the supernatural world. It is also about her journey of self-discovery, about finding her place in the world and understanding her own powers. This journey is fraught with danger and uncertainty, but Yotsuba's unwavering determination and courage guide her through it.Yotsuba Nanami is not just a character in an anime; she is a symbol of hope and courage. She represents the idea that even in the face of impossible odds, one can find strength within oneself and emerge stronger and wiser. Her story is an inspiration to us all, a reminder that no matter what challenges we face, we have the power to overcome them.In conclusion, Yotsuba Nanami is a character who captivates and inspires. Her journey, her challenges, and her triumphs are all part of her charm. She is a beacon of hope in a dark world, a reminder that with courage and determination, we can all find our own path and shine brightly in our own way.**八寻宁宁的魅力**在众多的动漫人物中,八寻宁宁以其独特和迷人的魅力脱颖而出。
Raspberry Pi Pico与Arducam SPI摄像头快速入门指南说明书
QUICK START GUIDESPI Camera On Raspberry Pi Pico(Arducam Mini 2MP)INTRODUCTIONAs an alternative to Arduino, Raspberry Pi Pico lacks pro-cessing power, memory, and a CSI interface, which makes it impossible for Pico to work with the official or any MIPI CSI -2 camera modules. Thankfully, Pico has a wide range of flexible I/O options includes SPI, which enables the Ar-ducam SPI camera to work with Pico.Now, the Arducam team has solved the compatibility of our SPI camera with Raspberry Pi Pico. Get the camera working for the Person Detection demo!KEY SPECSFEATURES• M12 mount or CS mount lens holder with changeable lens options• I2C interface for the sensor configuration• SPI interface for camera commands and data stream • All IO ports are 5V/3.3V tolerant•Support JPEG compression mode, single and multiple shoot mode, one time capture multiple read operation, burst read operation, low power mode and etc.PINOUTTYPICAL WIRINGNOTE: Arducam Mini 2MP camera module is a general -purpose solution compatible with multiple platforms, include Arduino, ESP32, Micro:bit and the Raspberry Pi Pico we ’re using. For the wring and software on other platforms, please refer to the product page: https:///product/arducam -2mp -spi -camera -b0067-arduino/If you need our help or want to customize other models of Pico cameras, feel free to contact us at sup-****************SOFTWARE SETUPTo facilitate copying, please refer to doc page: https:///docs/pico/arducam -camera -module -for -raspberry -pi -pico/spi -camera -for -raspberry -pi -pico/ We will keep online up -to -date continuously.1. Get the driver2. How to access SPI Camera using C2.1 Cameras supported by the driver • OV2640 2MP_Plus JPEG format•OV5642 5MP_Plus JPEG format2.2 Demos provided2.3 Compile the driver libraryNote: Refer to the official manual for the development environment: https:///documentation/rp2040/getting -started/#getting -started -with -cChoose the demo and input the following code to compile it. (default is Arducam_MINI_2MP_Plus_Videostreaing )2.4 Run the .uf2 file•Copy the PICO_SPI_CAM/C/build/Examples/Arducam_MINI_2MP_Plus_Videostreaing/Arducam_mini_2mp_plus_videostreaming.uf2 file to Pico to run the test.•Open HostApp.exe under PICO_SPI_CAM/HostApp file path, configure the port number, and click Image to view the image.3. How to access Camera using Python (on Windows)3.1 Download and install developing software Thonny Refer to the official manual: https:///3.2 Configure the IDERefer to the official manual: https:///3.3 Run Thonny• Copy all the files except boot.py under PI-CO_SPI_CAM/Python/ file path to Pico .• Open Thonny software ->Select Interpreter ->Select Circuit Python(generic)-> Press OK•Open Device Manager to check the Ports(COM & LPT) of Pico and then configure port number of Circuit Python(generic)• Copy all the boot.py file under PICO_SPI_CAM/Python/ file path to Pico.•Reboot Pico and then check the new port number under Ports(COM & LPT), it ’s used to USB communica-tion.• Open the camera drive program CircuitPython device via opening file on Thonny•Click Run , and it appears [48], CameraType is OV2640, SPI Interface OK means that the initialization of the camera is completed. Note [48] refers to the I2C device address of OV2640 camera.•Open HostApp.exe under PICO_SPI_CAM/HostApp file path, select the port number used for USB communi-cation, and click Image to view the image.If you need our help or the API detailed information, feel free to contact us. Email: ******************* Web: Doc Page: https:///docs/pico/arducam -camera -module -for -raspberry -pi -pico/spi -camera -for -raspberry -pi -pico/。
屏幕前的小姐们英语作文
Ladies sitting in front of the screens,The world is at your fingertips as you navigate through the digital realm, a place where information flows like a river, and connections are made with the click of a button. As you engage with this vast expanse of knowledge and interaction, here are some reflections and insights to consider.Empowerment Through Technology:The screen before you is not just a portal to entertainment but a tool for empowerment. It allows you to learn new skills, access educational resources, and stay informed about global events. Embrace the power of technology to broaden your horizons and enhance your capabilities.The Importance of Digital Literacy:Being proficient in the digital world means understanding how to use technology effectively and responsibly. It involves critical thinking about the information you consume and the impact of your online presence. Cultivate digital literacy to protect yourself and contribute positively to the online community.Balancing Screen Time:While screens offer endless opportunities, its essential to find a balance. Too much time in front of a screen can lead to physical and mental fatigue. Make sure to take breaks, engage in physical activities, and maintain social connections outside the digital sphere. Cybersecurity Awareness:As you interact with the digital world, be aware of the potential risks. Protect your personal information, use strong passwords, and be cautious about the websites you visit and the apps you download. Cybersecurity is a shared responsibility, and your vigilance plays a crucial role.The Impact of Your Online Presence:Remember that your online actions can have farreaching effects. Be mindful of the content you share, the comments you post, and how you interact with others. Use your online presence to inspire, educate, and uplift others.Lifelong Learning:The screen is a gateway to a wealth of knowledge. Make a commitment to lifelong learning. Whether its mastering a new language, understanding complex scientific concepts, or exploring artistic expressions, the opportunities are endless.Supporting Others:Use your digital presence to support and uplift others. Share resources, engage in meaningful discussions, and be a voice for those who may not be heard. The digital world can be a powerful platform for advocacy and change.Creativity and Expression:The screen is also a canvas for your creativity. Whether youre writing, designing, coding, or creating digital art, let your unique voice shine through. The digital world thrives on diversity and originality.Staying Connected:While the screen can sometimes create a sense of isolation, it can also be a powerful tool for staying connected. Reach out to friends and family, join online communities that share your interests, and participate in virtual events.The Future is Bright:As you sit in front of the screen, remember that you are part of a rapidly evolving digital landscape. Embrace the changes, adapt to new technologies, and look forward to the exciting possibilities that lie ahead.In conclusion, the screen is more than a window to the digital world its a mirror reflecting your potential, your creativity, and your impact. Use it wisely, and let it be a catalyst for your growth and the betterment of society.Warm regards,Your Name。
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PichiaPink™ Expression Strain, Secretion Signal, and Media KitsProduct Catalog No. StoragePichiaPink™ Expression Strain Kit A11154 –80°CPichiaPink™ Secretion Signal Kit A11155 –20°CPichiaPink™ Media Kit A11156 Room temperatureIntroductionThis product information sheet is supplied with the PichiaPink™ Expression Strain, PichiaPink™ Secretion Signal, and PichiaPink™ Media Kits, and provides guidelines and general instructions for high-level and large-scale expression and secretion of bioactive recombinant proteins using these kits. For detailed experimental protocols, refer to the PichiaPink™Expression System manual (A10984) available online at or by contacting Technical Support. PichiaPink™ System OverviewThe PichiaPink™ System is a eukaryotic protein expression system based on the eukaryote Pichia pastoris, which can be used for high-level (g/liter) and large-scale (1000+ liter) production of secreted recombinant proteins. The PichiaPink™ System offers the following advantages over existing Pichia pastoris based protein expression systems:•Easy selection of expression clones using ADE2 complementation (i.e., complementation of adenine auxotrophy) rather than antibiotic resistance.•Essentially all transformants in the PichiaPink™ system express the protein of interest.•Three protease knockout PichiaPink™ strains to help reduce the impact of proteases and the need for heavy protease inhibitor use during expression, as well as a “protease wild-type” strain.•ADE2 complementation ensures higher stability of transformants during scale-up of protein expression.•Choice between three expression vectors (pPinkα-HC, pPink-HC, and pPink-LC; available separately from Invitrogen) allowing high- and low-copy number secreted or intracellular expression.•Eight secretion signal sequences for optimization of secreted protein expression.•Simpler media growth conditions for screening and convenient PichiaPink™ media pouches.SelectionThe ADE2 gene encodes phosphoribosylaminoimidazole carboxylase, which catalyzes the sixth step in the de novo biosynthesis of purine nucleotides (Jones & Fink, 1982). In Saccharomyces cerevisiae, Pichia pastoris and other yeast strains, mutations in ADE2 lead to the accumulation of purine precursors in the vacuole, which causes the colony to be red in color.All PichiaPink™ strains are ade2 auxotrophs that are unable to grow in the absence of adenine due to the full deletion of the ADE2 gene and part of its promoter, and display a slow-growth phenotype on rich medium. Transformation of the PichiaPink™ strains with an expression plasmid containing the ADE2 gene enable the strains to grow again on medium lacking adenine (Ade dropout medium or minimal medium). Further, the color of the transformant colonies indirectly indicates the relative expression levels of your protein of interest. For more information on PichiaPink™ vector kits available from Invitrogen, visit our website at or contact Technical Support.Secreted ExpressionHeterologous expression in Pichia pastoris can be intracellular or secreted. Secretion requires the presence of a signal sequence on the expressed protein to target it to the secretory pathway. While several different secretion signal sequences have been used successfully, including the native secretion signal present on some heterologous proteins, success has been variable. The PichiaPink™ Secretion Signal Kit enables you to screen multiple signal sequences with your gene of for optimal expression and secretion of your recombinant protein (see PichiaPink™ Secretion Signal Kit, page 3).Protease Knock-outs prb1 and pep4Proteases are known to be secreted into the medium during Pichia fermentations, which can result in the degradation of the desired protein product. To help reduce the impact of proteases and the need for heavy protease inhibitor use, PichiaPink™System offers three protease knockout strains along with the “protease wild-type” PichiaPink™ Strain 1.The PichiaPink™ Strain 2 is a pep4 knockout, which prevents it from synthesizing proteinase A, a vacuolar aspartyl protease capable of self-activation. Since proteinase A also plays a role in the subsequent activation of additional vacuolar proteases, pep4 knockout strains have a diminished proteinase B activity and lack carboxypeptidase Y activity altogether.PichiaPink™ Strain 3 is a prb1 knockout, which prevents it from synthesizing proteinase B, a vacuolar serine protease of the subtilisin family.PichiaPink™ Strain 4 is double knock-out for both proteinases A and B (i.e.,pep4 and prb1), therefore has the lowest protease activity amongst the PichiaPink™ strains.Part no. A11237 MAN0001701 Rev. Date: 7 March 2012Page 2 PichiaPink™ Expression Strain KitThe PichiaPink™ Expression Strain Kit (Cat. no. A11154) is also included in the PichiaPink™ Secretion Optimization and PichiaPink™ Secreted Protein Expression Kits (Cat. nos. A11150 and A11151, respectively). The PichiaPink™ Expression Strain Kit components are described below. The PichiaPink™ Expression Strains are supplied frozen in YPD medium containing 15% glycerol. Upon receipt,streak the strains on YPD agar and prepare glycerol stocks. Store the strains at –80°C.Note: The ade2 deletion is a full deletion of the ADE2 gene and part of its promoter.IntroductionPichiaPink™ strains are mutants of Pichia pastoris designed for high-level (g/liter) and large-scale (1000+ liter) production of secreted bioactive recombinant proteins. Their general growth conditions and handling requirements are quite similar to Saccharomyces cerevisiae; however, we recommend that you familiarize yourself with basic microbiological and sterile techniques, as well as with basic molecular biology and protein chemistry, before attempting to grow and manipulate any microorganism. Some general references to consult are Recombinant Protein Expression in Pichia pastoris (Cregg et al., 2000),and Pichia Protocols: Methods in Molecular Biology (Higgins & Cregg, 1998).For detailed protocols on transforming PichiaPink™ strains, expressing recombinant strains, optimizing protein expression and secretion, and scaling-up protein expression, as well as for guidelines on PichiaPink™ fermentation, refer to the PichiaPink™ Expression System manual (A10984) available at or by contacting Technical Support. Growth of PichiaPink™ Expression StrainsThe growth temperature of PichiaPink™ strains is 24–30°C for liquid cultures, plates, and slants. Growth above 32°C during induction can be detrimental to protein expression and can even lead to cell death.Note: Growth characteristics of PichiaPink™ strains may vary depending on the recombinant protein expressed.•Doubling time of log phase untransformed PichiaPink™ strains (i.e., ade2) in YPD is ~6 to 8 hours•Untransformed prb1 PichiaPink™ strains (i.e., PichiaPink™ Strains 3 and 4) grow slightly slower than PichiaPink™ strains expressing functional PRB1 gene product.•Doubling time of log phase transformed PichiaPink™ strains (i.e., expressing ADE2 gene product) in BMGY is ~4 hours •Doubling time of log phase transformed PichiaPink™ strains in BMMY is ~16 hours•The protease deficient Pichia pastoris strains (i.e., PichiaPink™ strains 2, 3, and 4) are not as robust as wild-type Pichia pastoris, and require greater care in growth and storage, especially during fermentative growth.•One OD600 = ~5 × 107 cells/mL.•When using plates or medium containing methanol as growth medium, we recommend that you add methanol every day to compensate for loss because of evaporation or consumption. For plates, add 100 µL of 100% methanol to the lid of the inverted plate. For liquid medium, add 100% methanol to a final concentration of 0.5%.Note: Some researchers have had success adding methanol to up to 3% for Mut+ strains similar to PichiaPink™ without any negative effect to their liquid culture.Storing PichiaPink™ Expression StrainsWe recommend that you prepare frozen stocks of all four PichiaPink™ strains for long term storage. Although transformed PichiaPink™ strains are very stable, we recommend that you check your cells for correct phenotype and protein expression after extended storage at 4°C or –80°C.To store cells for weeks to months, use YPD medium and YPD agar slants (see page 4).1.Streak each strain to obtain single colonies on YPD agar plates. Grow 3–5 days at 24–30°C.2.Transfer one colony to a YPD stab and grow for 3–5 days at 30°C.3.You can store the cells on YPD for several weeks at 4°C.To store cells for months to years, store frozen at –80°C.1.Day1: Culture a single colony of each strain in 10 mL of YPD medium for 16–20 hours at 24–30°C, shaking at 300 rpm.This is your starter culture.Note: It is important to have adequate aeration for growth. Always use 1:5 ratio of media to flask volume.2.Day 2: Seed 200 mL of YPD medium with the starter culture to an OD600 of 0.2. Grow shaking for 1–2 days at 24–30°C toan OD600 of 2–3.3.Day 3 or 4: Harvest the cells by centrifuging at 1,500 × g for 5 minutes. Remove the supernatant and resuspend the cellsin YPD medium containing 25% glycerol to a final OD600 of 50–100 (approximately 2.5 × 109–5.0 × 109 cells/mL).4.Aliquot the cells in cryovials (1 mL aliquots) and freeze in liquid nitrogen or a dry ice/ethanol bath and store at –80°C.Cells will be pink in color.Page 3 PichiaPink™6HFUHWLRQ 6LJQDO KitThe secretion signal sequences included in the PichiaPink™ Secretion Signal Kit (Cat. no. A11155) are supplied as phosphorylated duplex oligomers in 40 pmol aliquots lyophilized in TE Buffer, pH 8 (10 mM Tris-HCl, 1 mM EDTA, pH 8.0). The sequence underlined in each signal sequence corresponds to the Kozak sequence taken from the native AOX1 gene. For detailed instructions on cloning the secretion signals, refer to the PichiaPink™ Expression System manual (part no. A10984), available on our website at (). Resuspend the duplexes in 40 µL TE Buffer, pH 8 before use.α-mating factor pre-sequenceSource: Saccharomyces cerevisiae, Length: 19 aa (amino acids), MW (Molecular Weight): 2000.3 DaNucleotide sequence of oligo 1:AATTCGAAACG ATG AGATTTCCTTCAATTTTTACTGCTGTTTTATTCGCAGCATCCTCCGCATTAGCTComplement nucleotide sequence of oligo 2: AGCTAATGCGGAGGATGCTGCGAATAAAACAGCAGTAAAAATTGAAGGAAATCTCATCGTTTCGα-amylase signal sequenceSource: Aspergillus niger, Length: 20 aa, MW: 2207.6 DaNucleotide sequence of oligo 1:AATTCGAAACG ATG GTCGCTTGGTGGTCTTTGTTTCTGTACGGTCTTCAGGTCGCTGCACCTGCTTTGGCTComplement nucleotide sequence of oligo 2: AGCCAAAGCAGGTGCAGCGACCTGAAGACCGTACAGAAACAAAGACCACCAAGCGACCATCGTTTCGGlucoamylase signal sequenceSource: Aspergillus awamori, Length: 18 aa, MW: 1825.2 DaNucleotide sequence of oligo 1:AATTCGAAACG ATG TCTTTTAGATCCTTGTTGGCTTTGTCTGGTTTGGTTTGTTCTGGTTTGGCTComplement nucleotide sequence of oligo 2: AGCCAAACCAGAACAAACCAAACCAGACAAAGCCAACAAGGATCTAAAAGACATCGTTTCGSerum albumin signal sequenceSource: Homo sapiens, Length: 18 aa, MW: 2140.5 DaNucleotide sequence of oligo 1:AATTCGAAACG ATG AAGTGGGTTACCTTTATCTCTTTGTTGTTTCTTTTCTCTTCTGCTTACTCTComplement nucleotide sequence of oligo 2: AGAGTAAGCAGAAGAGAAAAGAAACAACAAAGAGATAAAGGTAACCCACTTCATCGTTTCGInulinase signal sequenceSource: Kluyveromyces maxianus, Length: 16 aa, MW: 1647.0 DaNucleotide sequence of oligo 1:AATTCGAAACG ATG AAGTTAGCATACTCCTTGTTGCTTCCATTGGCAGGAGTCAGTGCTComplement nucleotide sequence of oligo 2: AGCACTGACTCCTGCCAATGGAAGCAACAAGGAGTATGCTAACTTCATCGTTTCGInvertase signal sequenceSource: Saccharomyces cerevisiae, Length: 19 aa, MW: 2025.5 DaNucleotide sequence of oligo 1:AATTCGAAACG ATG CTTTTGCAAGCTTTCCTTTTCCTTTTGGCTGGTTTTGCAGCCAAAATATCTGCAComplement nucleotide sequence of oligo 2: TGCAGATATTTTGGCTGCAAAACCAGCCAAAAGGAAAAGGAAAGCTTGCAAAAGCATCGTTTCGKiller protein signal sequenceSource: Saccharomyces cerevisiae, Length: 26 aa, MW: 2926.6 DaNucleotide sequence of oligo 1:AATTCGAAACG ATG ACTAAGCCAACCCAAGTATTAGTTAGATCCGTCAGTATATTATTTTTCATCACATTACTACATCTAGTCGTAGCT Complement nucleotide sequence of oligo 2: AGCTACGACTAGATGTAGTAATGTGATGAAAAATAATATACTGACGGATCTAACTAATACTTGGGTTGGCTTAGTCATCGTTTCG Lysozyme signal sequenceSource: Gallus gallus, Length: 26 aa, MW: 2686.4 DaNucleotide sequence of oligo 1:AATTCGAAACG ATG CTGGGTAAGAACGACCCAATGTGTCTTGTTTTGGTCTTGTTGGGATTGACTGCTTTGTTGGGTATCTGTCAAGGT Complement nucleotide sequence of oligo 2: ACCTTGACAGATACCCAACAAAGCAGTCAATCCCAACAAGACCAAAACAAGACACATTGGGTCGTTCTTACCCAGCATCGTTTCGPichiaPink ™ Media KitThe PichiaPink ™ Media Kit (Cat. no. A11156) is also included in the PichiaPink ™ Secretion Optimization and PichiaPink ™Secreted Protein Expression Kits (Cat. nos. A11150 and A11151, respectively). It includes the following prepackaged media for your convenience. Keep the media dry and store at room temperature.Preparing Media for PichiaPink ™ ExperimentsFollow the instructions below to prepare the media for your PichiaPink ™ experiments using the PichiaPink ™ Media Kit. For additional media and buffers used in PichiaPink ™ experiments, refer to the PichiaPink ™ Expression System manual (A10984) available online at or by contacting Technical Support.20% Dextrose (10X)To prepare 1 liter of 20% Dextrose (10X) stock solution:1. Dissolve the contents of the Dextrose pouch from the PichiaPink ™ Media Kit in 1000 mL of distilled water.2. Autoclave for 15 minutes, or filter sterilize.Store at room temperature. The shelf life of this solution is approximately one year.YPD MediumYPD medium is used for growing PichiaPink ™ strains prior to transformation. To prepare 1 liter of YPD, use only one pouch of YP from the PichiaPink ™ Media Kit.1. Dissolve the contents of the YP pouch from the PichiaPink ™ Media Kit in 900 mL of distilled water.2. Autoclave for 20 minutes on liquid cycle.3. Add 100 mL of sterile 20% Dextrose (see above).Store the YPD medium at room temperature. The shelf life for YPD medium is several months.YPD AgarYPD agar is used for streaking glycerol stocks of PichiaPink ™ strains. To prepare 1 liter, use only one pouch of YP agar. 1. Dissolve the contents of the YP agar pouch from the PichiaPink ™ Media Kit in 900 mL of distilled water. 2. Autoclave for 20 minutes on liquid cycle.3. Add 100 mL of sterile 20% Dextrose (see above).Store the YPD agar slants or plates at 4°C. The shelf life for YPD agar is several months.YPDS MediumYPDS medium is used for recovery of cells after electroporation. To prepare 0.2 liters of YPDS, use only one pouch of YPS. 1. Dissolve the contents of the YPS pouch from the PichiaPink ™ Media Kit in 180 mL of distilled water. 2. Autoclave for 20 minutes on liquid cycle.3. Add 20 mL of sterile 20% Dextrose (see above).Store the YPD medium at room temperature. The shelf life for YPDS medium is several months.PAD AgarPAD (Pichia Adenine Dropout) agar lacks adenine, and is used for selecting transformed PichiaPink ™ strains. To prepare 1 liter of PAD agar, use only one pouch of PAD agar from the PichiaPink ™ Media Kit.1. Dissolve the contents of the PAD agar pouch from the PichiaPink ™ Media Kit in 900 mL of distilled water.2. Autoclave for 20 minutes on liquid cycle.3. Add 100 mL of sterile 20% Dextrose (see above).Store the PAD agar plates at 4°C. The shelf life for PAD agar is several months.Purchaser NotificationThese products are covered by Limited Use Label License No. 334: PichiaPink ™ (see the Invitrogen catalog or our website, ). By the use of this product you accept the terms and conditions of all applicable Limited Use Label Licenses.For research use only. Not intended for any animal or human therapeutic or diagnostic use. 2012 Life Technologies Corporation. All rights reserved.。