SDmini_spec_rev1.02

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SDIO spec

f in eo nIn fio nI n fTechnical Committee SD Card Associationf in eo nIn fi ne o n I nf in eo nIRevision HistoryDate Version Changes compared to previous issueApril 3, 2006 1.10 Simplified Version Initial ReleaseFebruary 8, 20072.00(1) Added method to change bus speed (Normal Speed up to 25MHzand High Speed up to 50 MHz)(2) Operational Voltage Requirement is extended to 2.7-3.6V(3) Combine sections 12 (Physical Properties) and 13 (MechanicalExtensions) and add miniSDIO to the new section 13 (Physical Properties)(4) Add Embedded SDIO ATA Standard Function Interface Code (5) Reference of Physical Ver2.00 supports SDHC combo card. (6) Some typos in Ver1.10 are fixed.f in eo nIn fi ne o n I nf in eo nI Release of SD Simplified SpecificationThe following conditions apply to the release of the SD simplified specification ("Simplified Specification") by the SD Card Association. The Simplified Specification is a subset of the complete SD Specification which is owned by the SD Card Association.Publisher:SD Association2400 Camino Ramon, Suite 375 San Ramon, CA 94583 USA Telephone: +1 (925) 275-6615 Fax: +1 (925) 886-4870 E-mail: office@Copyright Holder: The SD Card AssociationNotes:This Simplified Specification is provided on a non-confidential basis subject to the disclaimers below. Any implementation of the Simplified Specification may require a license from the SD Card Association or other third parties.Disclaimers:The information contained in the Simplified Specification is presented only as a standard specification for SD Cards and SD Host/Ancillary products and is provided "AS-IS" without any representations or warranties of any kind. No responsibility is assumed by the SD Card Association for any damages, any infringements of patents or other right of the SD Card Association or any third parties, which may result from its use. No license is granted by implication, estoppel or otherwise under any patent or other rights of the SD Card Association or any third party. Nothing herein shall be construed as an obligation by the SD Card Association to disclose or distribute any technical information, know-how or other confidential information to any third party.f in eo nIn fi ne o n I nf in eo nConventions Used in This DocumentNaming ConventionsSome terms are capitalized to distinguish their definition from their common English meaning. Words not capitalized have their common English meaning.Numbers and Number BasesHexadecimal numbers are written with a lower case “h” suffix, e.g., FFFFh and 80h. Binary numbers are written with a lower case “b” suffix (e.g., 10b).Binary numbers larger than four digits are written with a space dividing each group of four digits, as in 1000 0101 0010b.All other numbers are decimal.Key WordsMay: Indicates flexibility of choice with no implied recommendation or requirement.Shall: Indicates a mandatory requirement. Designers shall implement such mandatory requirements to ensure interchangeability and to claim conformance with the specification.Should: Indicates a strong recommendation but not a mandatory requirement. Designers should give strong consideration to such recommendations, but there is still a choice in implementation.Application NotesSome sections of this document provide guidance to the host implementers as follows: Application Note:This is an example of an application note.f in eo nIn fi ne o n I nf in eo nTable of Contents1. General Description.................................................................................................................................1 1.1 SDIO Features....................................................................................................................................1 1.2 Primary Reference Document.............................................................................................................1 1.3 Standard SDIO Functions....................................................................................................................1 2. SDIO Signaling Definition........................................................................................................................2 2.1 SDIO Card Types................................................................................................................................2 2.2 SDIO Card modes...............................................................................................................................2 2.2.1 SPI (Card mandatory support).....................................................................................................2 2.2.2 1-bit SD Data Transfer Mode (Card Mandatory Support).............................................................2 2.2.3 4-bit SD Data Transfer Mode (Mandatory for High-Speed Cards, Optional for Low-Speed).........2 2.3 SDIO Host Modes...............................................................................................................................2 2.4 Signal Pins..........................................................................................................................................3 3. SDIO Card Initialization............................................................................................................................4 3.1 Differences in I/O card Initialization.....................................................................................................4 3.2 The IO_SEND_OP_COND Command (CMD5).................................................................................10 3.3 The IO_SEND_OP_COND Response (R4)........................................................................................11 3.4 Special Initialization considerations for Combo Cards.......................................................................12 3.4.1 Re-initialize both I/O and Memory..............................................................................................12 3.4.2 Using a Combo Card as SDIO only or SD Memory only after Combo Initialization....................12 3.4.3 Acceptable Commands after Initialization..................................................................................12 3.4.4 Recommendations for RCA after Reset.....................................................................................12 3.4.5 Enabling CRC in SPI Combo Card.............................................................................................14 4. Differences with SD Memory Specification..........................................................................................15 4.1 SDIO Command List.........................................................................................................................15 4.2 Unsupported SD Memory Commands...............................................................................................15 4.3 Modified R6 Response......................................................................................................................16 4.4 Reset for SDIO..................................................................................................................................16 4.5 Bus Width..........................................................................................................................................16 4.6 Card Detect Resistor.........................................................................................................................17 4.7 Timings..............................................................................................................................................17 4.8 Data Transfer Block Sizes.................................................................................................................18 4.9 Data Transfer Abort...........................................................................................................................18 4.9.1 Read Abort.................................................................................................................................18 4.9.2 Write Abort.................................................................................................................................18 4.10 Changes to SD Memory Fixed Registers..........................................................................................18 4.10.1 OCR Register.............................................................................................................................19 4.10.2 CID Register...............................................................................................................................19 4.10.3 CSD Register.............................................................................................................................19 4.10.4 RCA Register.............................................................................................................................19 4.10.5 DSR Register.............................................................................................................................19 4.10.6 SCR Register.............................................................................................................................19 4.10.7 SD Status...................................................................................................................................19 4.10.8 Card Status Register..................................................................................................................19 5. New I/O Read/Write Commands............................................................................................................21 5.1 IO_RW_DIRECT Command (CMD52)..............................................................................................21 5.2 IO_RW_DIRECT Response (R5)......................................................................................................22 5.2.1 CMD52 Response (SD modes)..................................................................................................22 5.2.2 R5, IO_RW_DIRECT Response (SPI mode).............................................................................23 5.3 IO_RW_EXTENDED Command (CMD53). (24)f in eo nIn fi ne o n I nf in eo nI 5.3.2 Special Timing for CMD53 Multi-Block Read..............................................................................25 6. SDIO Card Internal Operation................................................................................................................26 6.1 Overview...........................................................................................................................................26 6.2 Register Access Time........................................................................................................................26 6.3 Interrupts...........................................................................................................................................26 6.4 Suspend/Resume..............................................................................................................................27 6.5 Read Wait..........................................................................................................................................27 6.6 CMD52 During Data Transfer............................................................................................................27 6.7 SDIO Fixed Internal Map...................................................................................................................27 6.8 Common I/O Area (CIA)....................................................................................................................28 6.9 Card Common Control Registers (CCCR).........................................................................................28 6.10 Function Basic Registers (FBR)........................................................................................................35 6.11 Card Information Structure (CIS).......................................................................................................37 6.12 Multiple Function SDIO Cards...........................................................................................................37 6.13 Setting Block Size with CMD53.........................................................................................................37 6.14 Bus State Diagram............................................................................................................................38 7. Embedded I/O Code Storage Area (CSA).............................................................................................39 7.1 CSA Access.......................................................................................................................................39 7.2 CSA Data Format..............................................................................................................................39 8. SDIO Interrupts.......................................................................................................................................40 8.1 Interrupt Timing.................................................................................................................................40 8.1.1 SPI and SD 1-bit Mode Interrupts ..............................................................................................40 8.1.2 SD 4-bit Mode............................................................................................................................40 8.1.3 Interrupt Period Definition ..........................................................................................................40 8.1.4 Interrupt Period at the Data Block Gap in 4-bit SD Mode (Optional)..........................................40 8.1.5 Inhibited Interrupts (Removed Section)......................................................................................40 8.1.6 End of Interrupt Cycles...............................................................................................................40 8.1.7 Terminated Data Transfer Interrupt Cycle ..................................................................................41 8.1.8 Interrupt Clear Timing.................................................................................................................41 9. SDIO Suspend/Resume Operation........................................................................................................42 10. SDIO Read Wait Operation.....................................................................................................................43 11. Power Control.........................................................................................................................................44 11.1 Power Control Overview....................................................................................................................44 11.2 Power Control support for SDIO Cards.............................................................................................44 11.2.1 Master Power Control ................................................................................................................44 11.2.2 Power Selection.........................................................................................................................45 11.2.3 High-Power Tuples.....................................................................................................................45 11.3 Power Control Support for the SDIO Host.........................................................................................45 11.3.1 Version 1.10 Host.......................................................................................................................45 11.3.2 Power Control Operation............................................................................................................46 12. High-Speed Mode...................................................................................................................................47 12.1 SDIO High-Speed Mode....................................................................................................................47 12.2 Switching Bus Speed Mode in a Combo Card...................................................................................47 13. SDIO Physical Properties......................................................................................................................48 13.1 SDIO Form Factors...........................................................................................................................48 13.2 Full-Size SDIO ..................................................................................................................................48 13.3 miniSDIO...........................................................................................................................................48 14. SDIO Power.............................................................................................................................................48 14.1 SDIO Card Initialization Voltages......................................................................................................48 14.2 SDIO Power Consumption................................................................................................................48 15. Inrush Current Limiting..........................................................................................................................50 16. CIS Formats.. (51)f in eo nIn fi ne o n I nf in eo nI 16.2 Basic Tuple Format and Tuple Chain Structure.................................................................................51 16.3 Byte Order Within Tuples ..................................................................................................................51 16.4 Tuple Version ....................................................................................................................................52 16.5 SDIO Card Metaformat......................................................................................................................52 16.6 CISTPL_MANFID: Manufacturer Identification String Tuple..............................................................53 16.7 SDIO Specific Extensions..................................................................................................................53 16.7.1 CISTPL_FUNCID: Function Identification Tuple.........................................................................53 16.7.2 CISTPL_FUNCE: Function Extension Tuple..............................................................................54 16.7.3 CISTPL_FUNCE Tuple for Function 0 (common).......................................................................54 16.7.4 CISTPL_FUNCE Tuple for Function 1-7....................................................................................55 16.7.5 CISTPL_SDIO_STD: Function is a Standard SDIO Function.....................................................58 16.7.6 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards...............................................................58 Appendix A.....................................................................................................................................................59 A.1 SD and SPI Command List....................................................................................................................59 Appendix B.....................................................................................................................................................61 B.1 Normative References...........................................................................................................................61 Appendix C.....................................................................................................................................................62 C.1 Abbreviations and Terms...................................................................................................................62 Appendix D.. (64)f in eo nIn fi ne o n I nf in eo nI Table of TablesTable 3-1 OCR Values for CMD5.....................................................................................................................10 Table 4-1 Unsupported SD Memory Commands.............................................................................................16 Table 4-2 R6 response to CMD3.....................................................................................................................16 Table 4-3 SDIO R6 Status Bits.........................................................................................................................16 Table 4-4 Combo Card 4-bit Control................................................................................................................17 Table 4-5 Card Detect Resistor States.............................................................................................................17 Table 4-6 is blanked.........................................................................................................................................17 Table 4-7 SDIO Status Register Structure .......................................................................................................20 Table 5-1 Flag data for IO_RW_DIRECT SD Response..................................................................................23 Table 5-2 IO_RW_ EXTENDED command Op Code Definition.......................................................................24 Table 5-3 Byte Count Values ...........................................................................................................................25 Table 6-1 Card Common Control Registers (CCCR).......................................................................................29 Table 6-2 CCCR bit Definitions........................................................................................................................34 Table 6-3 Function Basic Information Registers (FBR)....................................................................................35 Table 6-4 FBR bit and field definitions.............................................................................................................36 Table 6-5 Card Information Structure (CIS) and reserved area of CIA.............................................................37 Table 11-1 Reference Tuples by Master Power Control and Power Select......................................................45 Table 16-1 Basic Tuple Format........................................................................................................................51 Table 16-2 Tuples Supported by SDIO Cards..................................................................................................52 Table 16-3 CISTPL_MANFID: Manufacturer Identification Tuple.....................................................................53 Table 16-4 CISTPL_FUNCID Tuple.................................................................................................................53 Table 16-5 CISTPL_FUNCE Tuple General Structure.....................................................................................54 Table 16-6 TPLFID_FUNCTION Tuple for Function 0 (common)....................................................................54 Table 16-7 TPLFID_FUNCTION Field Descriptions for Function 0 (common).................................................54 Table 16-8 TPLFID_FUNCTION Tuple for Function 1-7..................................................................................55 Table 16-9 TPLFID_FUNCTION Field Descriptions for Functions 1-7.............................................................57 Table 16-10 TPLFE_FUNCTION_INFO Definition...........................................................................................57 Table 16-11 TPLFE_CSA_PROPERTY Definition...........................................................................................57 Table 16-12 CISTPL_SDIO_STD: Tuple Reserved for SDIO Cards................................................................58 Table 16-13 CISTPL_SDIO_EXT: Tuple Reserved for SDIO Cards.................................................................58 Table A-14 SD Mode Command List................................................................................................................59 Table A-15 SPI Mode Command List (60)f in eo nIn fi ne o n I nf in eo nI Table of FiguresFigure 2-1 Signal connection to two 4-bit SDIO cards.......................................................................................3 Figure 3-1 SDIO response to non-I/O aware initialization..................................................................................4 Figure 3-2 Card initialization flow in SD mode (SDIO aware host)....................................................................7 Figure 3-3 Card initialization flow in SPI mode (SDIO aware host)....................................................................9 Figure 3-4 IO_SEND_OP_COND Command (CMD5).....................................................................................10 Figure 3-5 Response R4 in SD mode...............................................................................................................11 Figure 3-6 Response R4 in SPI mode..............................................................................................................11 Figure 3-7 Modified R1 Response....................................................................................................................11 Figure 3-8 Re-Initialization Flow for I/O Controller...........................................................................................13 Figure 3-9 Re-Initialization Flow for Memory controller ...................................................................................13 Figure 5-1 IO_RW_DIRECT Command...........................................................................................................21 Figure 5-2 R5 IO_RW_DIRECT Response (SD modes)..................................................................................22 Figure 5-3 IO_RW_DIRECT Response in SPI Mode.......................................................................................23 Figure 5-4 IO_RW_EXTENDED Command.....................................................................................................24 Figure 6-1 SDIO Internal Map..........................................................................................................................28 Figure 6-2 State Diagram for Bus State Machine (38)f in eo nIn fi ne o n I nf in eo nI 1. General DescriptionThe SDIO (SD Input/Output) card is based on and compatible with the SD memory card. This compatibility includes mechanical, electrical, power, signaling and software. The intent of the SDIO card is to provide high-speed data I/O with low power consumption for mobile electronic devices. A primary goal is that an SDIO card inserted into a non-SDIO aware host shall cause no physical damage or disruption of that host or it’s software. In this case, the SDIO card should simply be ignored. Once inserted into an SDIO aware host, the detection of the card proceeds via the normal means described in this specification with some extensions. In this state, the SDIO card is idle and draws a small amount of power (15 mA averaged over 1 second). During the normal initialization and interrogation of the card by the host, the card identifies itself as an SDIO card. The host software then obtains the card information in a tuple (linked list) format and determines if that card’s I/O function(s) are acceptable to activate. This decision is based on such parameters as power requirements or the availability of appropriate software drivers. If the card is acceptable, it is allowed to power up fully and start the I/O function(s) built into it.1.1 SDIO Features• Targeted for portable and stationary applications• Minimal or no modification to SD Physical bus is required • Minimal change to memory driver software• Extended physical form factor available for specialized applications • Plug and play (PnP) support• Multi-function support including multiple I/O and combined I/O and memory • Up to 7 I/O functions plus one memory supported on one card. • Allows card to interrupt host• Operational Voltage range: 2.7-3.6V (Operational Voltage is used for Initialization) • Application Specifications for Standard SDIO Functions. • Multiple Form Factors:• Full-Size SDIO • miniSDIO1.2 Primary Reference DocumentThis specification is based on and refers extensively to the SDA document:SD Memory Card SpecificationsPart 1 PHYSICAL LAYER SPECIFICATION Version 2.00 May 9, 2006The reader is directed to this document for more information on the basic operation of SD cards. In addition, other documents are referenced in this specification. A complete list can be found in appendix B.1.This specification can apply to any released versions of Physical Layer Specification after Version 2.00.1.3 Standard SDIO FunctionsAssociated with the base SDIO specification, there are several Application Specifications for Standard SDIO Functions. These common functions such as cameras, Bluetooth cards and GPS receivers have a standard register interface, a common operation method and a standard CIS extension. Implementation of the standard interfaces are optional for any card vendor, but compliance with the standard allows the use of standard drivers and applications which will increase the appeal of these cards to the consumer. Full information on these standard interfaces can be found in the Application Specifications for Standard SDIO Functions maintained by the SDA.。

MICRO SD 3.0 SPEC

MicroSD3.0 UHS-I SpecificationRev B2Sep-23-2014NOTE: INFORMATION IN THIS PRODUCT SPECIFICATION IS SUBJECT TO CHANGE AT ANYTIME WITHOUT NOTICE, ALL PRODUCT SPECIFICATIONS ARE PROVIDED FOR REFERENCE ONLY.TO ANY INTELLECTUAL, PROPERTY RIGHTS IN LONGSYS ELECTRONICS CO.,LTD. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED.Contents1. Overview (4)1.1 Product Description (4)1.2 Features Summary (4)2. Pin Assignment (5)3. Product List (5)4. Current Consumption (7)5. Operational Environment (7)6. Card Registers (7)6.1 Card Identification Register (CID) (7)6.2 Card-Specific Data Register (CSD) (8)7. Bus Operation Conditions (9)7.1 For 3.3V Signaling (9)7.1.1 Threshold Level for High Voltage Range (9)7.1.2 Peak Voltage and Leakage Current (9)7.1.3 Bus Signal Line Load (10)7.1.4 Bus Signal Levels (10)7.1.5 Bus Timing(Default) (10)7.1.6 Bus Timing(High-Speed Mode) (12)7.2 For 1.8V Signaling (13)7.2.1 Threshold Level for High Voltage Range (13)7.2.2 Peak Voltage and Leakage Current (13)7.2.3 Bus Timing Specification in SDR12 (13)7.2.3.1 Clock Timing (14)7.2.3.2 Card Input Timing (14)7.2.3.3 Card Output Timing (14)7.2.3.3.1 Output Timing of Fixed Data Window (15)7.2.3.3.2 Output Timing of Variable Window (SDR104) (15)8. Physical Dimension (15)1. Overview1.1 Product DescriptionThe Longsys MicroSD3.0 Cards are fully compatible with Physical Layer Specification, Version 3.0 (this specification is available from the SDA), support Ultra High Speed(UHS), provides high write/read speed and high IOPS, It was designed to meet the security, high capacity, high performance and environmental requirements inherent in next generation consumer electronic devices.The MicroSD3.0 card system is a new mass-storage system based on innovations in semiconductor technology. It has been developed to provide an inexpensive, mechanically robust storage medium in card form for multimedia consumer applications. MicroSD card allows the design of inexpensive players and drivers without moving parts. A low power consumption and a wide supply voltagerange favors consumer electronic devices.Ultra High Speed (UHS) CardIt provides up to 104MB/s* performance. UHS cards are backward compatible on non-UHS hosts. *Based on internal testing; performance may vary depending upon host device.1 megabyte(MB)=1,000,000bytes.1.2 Features Summary-Capacity: 4GB/8GB/16GB/32GB/64GB/128GB-Complies to SD specifications version 3.00-Voltage operating: 2.7~3.6V.-Targeted for portable and stationary applications-Greater Performance Choices-Bus Speed Mode:DS-Default Speed mode: 3.3V signaling, frequency up to 25MHz, up to 12.5MB/secHS-High Speed mode: 3.3V signaling, frequency up to 50MHz, up to 25MB/secSDR12-1.8V signaling, frequency up to 25MHz, up to 12.5MB/secSDR25-1.8V signaling, frequency up to 50MHz, up to 25MB/secSDR50-1.8V signaling, frequency up to 100MHz, up to 50MB/secSDR104-1.8V signaling, frequency up to 208MHz, up to 104MB/secDDR50-1.8V signaling, frequency up to 50MHz, sampled on both clock edges, up to 50MB/s-Switch function command supports Bus Speed Mode, Command System, Drive Strength, and future functions.-password protection (CMD42-LOCK_UNLOCK)-Sophisticated system for error recovery including a powerful ECC-Global Wear Leveling-Power management for low power operation-Add TF card adapter can be used in SD card socket.2. Pin AssignmentPin No.SD ModeName Type Description 1 Dat2 I/O/PP Data Line [Bit 2]2CD/DAT3I/O/PP3Card Detect / Data Line [Bit 3]3 CMD PP Command/Response4 VDD S Supply voltage5 CLK I Clock6 VSS S Supply voltage ground7 DAT0 I/O/PP Data Line [Bit 0] 8DAT1I/O/PPData Line [Bit 1]S: power supply; I: input; O: output; PP: I/O using push-pull driversTable 1: Pin Assignment3. Product ListPart NumberCapacityActual Size（Min ） (note2)Speed Class (note1) Write Speed (Typical) (note1) UHS-I (note1)TypeNCIX4XX-004G 4GB 3.6GB Class4 4 MB/S SDR50/SDR104 SDHC NCIX6XX-004G 4GB 3.6GB Class6 6 MB/S SDR50/SDR104 SDHC NCIXAXX-004G 4GB 3.6GB Class10 10 MB/S SDR50/SDR104 SDHC NCIX4XX-008G 8GB 7.3GB Class4 4 MB/S SDR50/SDR104 SDHC NCIX6XX-008G8GB7.3GBClass66 MB/SSDR50/SDR104SDHCNCIXAXX-008G 8GB 7.3GB Class10 10 MB/S SDR50/SDR104 SDHC NCIXBXX-008G 8GB 7.3GB Class10 133X SDR104 SDHC NCIXCXX-008G 8GB 7.3GB Class10 150X SDR104 SDHC NCIXAXX-016G 16GB 14.7GB Class10 10 MB/S SDR50/SDR104 SDHC NCIXBXX-016G 16GB 14.7GB Class10 133X SDR104 SDHC NCIXCXX-016G 16GB 14.7GB Class10 150X SDR50/SDR104 SDHC NCIXDXX-016G 16GB 14.7GB Class10 233X SDR104 SDHC NCIXEXX-016G 16GB 14.7GB Class10 266X SDR104 SDHC NCIXFXX-016G 16GB 14.7GB Class10 300X SDR104 SDHC NCIXAXX-032G 32GB 29.4GB Class10 10 MB/S SDR50/SDR104 SDHC NCIXBXX-032G 32GB 29.4GB Class10 133X SDR104 SDHC NCIXCXX-032G 32GB 29.4GB Class10 150X SDR104 SDHC NCIXDXX-032G 32GB 29.4GB Class10 233X SDR50/SDR104 SDHC NCIXEXX-032G 32GB 29.4GB Class10 266X SDR104 SDHC NCIXFXX-032G 32GB 29.4GB Class10 300X SDR104 SDHC NCIXGXX-032G 32GB 29.4GB Class10 333X SDR104 SDHC NCIXHXX-032G 32GB 29.4GB Class10 400X SDR104 SDXC NCIXAXX-064G 64GB 58.9GB Class10 10 MB/S SDR50/SDR104 SDXC NCIXHXX-064G 64GB 58.9GB Class10 333X SDR104 SDXC NCIXHXX-064G 64GB 58.9GB Class10 400X SDR104 SDXC NCIXBXX-128G 128GB 118GB Class10 150X SDR104 SDXCTable 2: Product Listnote1:*Measurement based on VTE3100 TestMetrix device, SW 3.2A software or up version, test script:SD_Card(Spec3.0_High&Extended-Capacity_UHS-I and Non-UHS-I)_Compliance [rev31R].vte*SDR50@SDR50-100MHzSDR104@SDR104-208MHz.*1X=150KByte/snote2: *1Gigabyte (GB) = 1 billion bytes. Some capacity not available for data storage*Maximum speed differs from the bus I/F speed. It varies depending upon the card performance. The average speed that a device writes to a MicroSD memory card may vary depending upon the device and the operation it is performing. The speed may also depend on how other data is stored on the MicroSD memory card. Normal and high-speed cards can also be used with UHS-I host devices, but the high performance enabled by a UHS-I host device can only be achieved with a UHS-I memory card.4. Current ConsumptionStandby current: 500uA（Maximum value）Standby current: 150uA（average value）Operating current: 250mA（Maximum value）Operating current: 100mA（average value）*Test condition: Realtek5308 card reader (Voltage 3.3V), Fluke289C multi-meter.5. Operational EnvironmentParameter RangeTemperatureOperating 0℃~ 70℃Non-Operating -40℃~ 85℃HumidityOperating 25% to 85%, non-condensing Non-Operating 25% to 85%, non-condensingDurability insertion/removal cycles 10,000 Data Retention10yearsTable 3: Operational Environment6. Card Registers6.1 Card Identification Register (CID)The Card Identification (CID) register is 128 bit wide. It contains the card identification information used during the card identification phase. Every individual flash card shall have a unique identification number.The structure of the CID register is defined in the following table.CID Bit Width Name Field[127:120] 8 ManufactureID MID [119:104] 16 OEM/ApplicationID OID [103:64] 40 ProductName PNM [63:56] 8 ProductRevision PRV [55:24] 32 Product Serial Number PSN[23:20] 4 Reserved ---[19:8] 12 ManufacturingDate MDT [7:1] 7 CRC7 check sum CRC[0] 1 Notused,always”1 ---Table 4: CID Table- All contents in the CID table are programmable; Manufacturers can update the CID data through utility.- Manufacturers should license MID and OID field form the SD Card Association(SDA)6.2 Card-Specific Data Register (CSD)The Card-Specific Data register provides information on how to access the card contents. The defines the data format, error correction type, maximum data access time, data transfer speed, whether the DSR register can be used etc. The programmable part of the register can be changed by CMD27.The CSD Table Version 2.0(as shown below) is applied to SDHC and SDXC Cards. Note that bits [15:0] are programmable by the host side. Refer to the SD specification for detailed information CSD BitWidth NameFieldValueNote [127:126] 2 CSD structureCSD_STRUCTURE 01bV2.0(>2GB Card) [125:120] 6 Reserved --- --- --- [119:112]8Data read access-time 1 (TAAC)0E h[111:104] 8 Data read access-time2 in CLK cycles(NSA*100)(NSAC) 00 h[103:96] 8 Max data transfer rate (TRAN_SPEED)32 h5A h 0B h 2B h[95:84] 12 Card command classes CCC5B5 h[83:80] 4 Max. read data block length (READ_BL_LEN) 9 h 512 Byte[79] 1 Partial block read allowed (READ_BL_PARTIA L)[78]1Write block misalignment(WRITE_BLK_MISA LIGN)[77] 1 Read block misalignment(READ_BLK_MISAL IGN) 0[76] 1 DSR implemented DSR_IMP x[75:70] 6 Reserve --- --- [69:48] 22 Device size C_SIZE xxxxxxh[47] 1 Reserved --- 0 [46] 1 Erase single block enable (ERASE_BLK_EN) 1[45:39] 7 Erase sector size (SECTOR_SIZE) 7F h [38:32] 7 Write protect group size C_SIZE0 b[31] 1 Write protect group enable --- 0 [30:29] 2 Reserved(ERASE_BLK_EN) 0 b [28:26] 3 Write speed factor(SECTOR_SIZE)010 b [25:22]4Max. write data block (WP_GRP_SIZE)9 hlength[21] 1 Partial block write allowed (WP_GRP_ENABLE)[20:16] 5 Reserved --- ---[15] 1Fileformatgroup (FILE_FORMAT_GRP)[14] 1Copyflag COPY x[13] 1Permanentwriteprotection PERM_WRITE_PROTECTx[12] 1 Temporary write protection TMP_WRITE_PROTECTx[11:10] 2 File format (FILE_FORMAT) 00 b[9:8] 2 Reserved --- 00b[7:1] 7 CRC CRC ---[0] 1Notused,always’1’ --- 1Table 5: CSD (Version 2.0) Table7. Bus Operation Conditions7.1 For 3.3V Signaling7.1.1 Threshold Level for High Voltage RangeParameter Symbol Min Max Unit Remark Supply Voltage V DD 2.7 3.6 VOutput High Voltage V OH 0.75*V DD V I OH=2mA V DD min Output Low Voltage V OL0.125*V DD V I OL=2mA V DD min Input High Voltage V IH 0.625*V DD V DD+0.3 VInput Low Voltage V IL V ss-0.3 0.25*V DD VPower Up Time 250 ms From 0V to V DD minTable 6: Threshold Level for High Voltage7.1.2 Peak Voltage and Leakage CurrentParameter Symbol Min Max Unit Remark Peak voltage on all lines VAll InputsInput Leakage Current -10 10 uAAll OutputsOutput Leakage Current -10 10 uATable 7: Peak Voltage and Leakage Current7.1.3 Bus Signal Line LoadParameter SymbolMin Max Unit RemarkPull-up resistance R CMDR DAT10 100 KΏTo prevent bus floatingTotal bus capacitance for each signal line C L40 pF1 card C HOST+C BUS shall notexceed 30pFCard capacitance foreach signal pinC CARD10 pFMaximum signalinductance16 nHPull-up resistance insidecard(pin1)R DAT3 10 90 KΏMay be used for card detectionCapacity Connected toPower Line C C 5 uF To prevent inrush currentTable 8: Bus Operating Conditions - Signal Line's Load7.1.4 Bus Signal LevelsAs the bus can be supplied with a variable supply voltage,all sigelnal levels are related to the supply valtage.Figure 1: Bus Signal LevelsTo meet the requirements of the the JEDEC specification JESD8-1A and JESD8-7,the card input and output voltages shall be within the specifide ranges shown in Table 6 for any V DD of the allowed valtage range.7.1.5 Bus Timing(Default)Figure 2:Card input Timing(Default Speed Card)Figure 3:Card Output Timing(Default Speed Mode)Unit RemarkParameter Symbo Min. MaxClock CLK （All values are referred to min（V IH）and max（V IL））Clock frequency data transfer fpp 0 25 MHz C≤ 10pF (1 card)CARDClock frequency Identification f0(1)/100 400 KHz C CARD≤ 10pF (1 card)ODClock low time t WL 10 ns C CARD≤ 10pF (1 card) Clock high time t WH 10 ns C CARD≤ 10pF (1 card) Clock rise time t TLH10 ns C CARD≤ 10pF (1 card) Clock fall time t THL10 ns C CARD≤ 10pF (1 card) Inputs CMD, DAT (referenced to CLK)Input set-up time t ISU 5 ns C CARD≤ 10pF (1 card)Input hold time t TH 5 nsC CARD≤ 10pF (1 card) Outputs CMD, DAT (referenced to CLK)Output Delay time during Datat ODLY 0 14 ns C L≤ 40pF (1 card) Transfer ModeOutput Hold time t OH 0 50 ns C L≤ 40pF (1 card) (1)0 Hz means to stop the clock.The given minimum frequency range is for cases were continuesclock is required (refer to Chapter 4.4-Clock Control)Table 9:Bus Timing-Parameters Values (Default Speed)7.1.6 Bus Timing(High-Speed Mode)Figure 4: Card Input Timing(High Speed Card)Figure5: Card Output Timing(High Speed Mode)Parameter Symbo Min. Max Unit RemarkClock CLK （All values are referred to min（V IH）and max（V IL））Clock frequency data transfer fpp 0 50 MHz CCARD≤ 10pF (1 card) Clock low time t WL 7 ns C CARD≤ 10pF (1 card) Clock high time t WH 7 ns C CARD≤ 10pF (1 card) Clock rise time t TLH 3 ns C CARD≤ 10pF (1 card) Clock fall time t THL 3 ns C CARD≤ 10pF (1 card) Inputs CMD, DAT (referenced to CLK)Input set-up time t ISU 6 ns C CARD≤ 10pF (1 card) Input hold time t TH 2 nsC CARD≤ 10pF (1 card) Outputs CMD, DAT (referenced to CLK)Output Delay time during DataTransfer Modet ODLY14 ns C L≤ 40pF (1 card) Output Hold time t OH 2.5 ns C L≥ 15pF (1 card)Total System capacitance for each line1C L40 pF1card1)In order to satisty sever timing , host shall drive only one card.Table 10 :Bus Tinming – Parameters Values(High Speed)7.2 For 1.8V Signaling7.2.1 Threshold Level for High Voltage RangeParameter Symbol Min Max Unit Remark Supply Voltage V DD 2.7 3.6 VRegulator Voltage V DDIO 1.7 1.95 V Generated by V DD Output High Voltage V OH 1.4 V I OH=2mA V DD min Output Low Voltage V OL0.45 V I OL=2mA V DD min Input High Voltage V IH 1.27 2.0 VInput Low Voltage V IL V ss-0.3 0.58 VTable 11: Threshold Level for High Voltage7.2.2 Peak Voltage and Leakage CurrentParameter Symbol Min Max Unit Remark Input Leakage Current -2 2 uA DAT3 pull-up isdisconnectedTable 12: Peak Voltage and Leakage Current7.2.3 Bus Timing Specification in SDR12, SDR25, SDR50 and SDR104 Modes7.2.3.1 Clock TimingFigure 6: Clock Signal TimingSymbolMinMaxUnitRemarkt CLK 4.8 - ns208MHz (Max.), Between rising edge,V CT =0.975Vt CR , t CF - 0.2* t CLK nst CR , t CF < 2.00ns (max.) at 208MHz, C CARD =10pF t CR , t CF < 2.00ns (max.) at 100MHz, C CARD =10pFThe absolute maximum value of t CR , t CF is 10ns regardless of clock frequence. Clock Duty3070%Table 13:Clock Signal Timing7.2.3.2 Card Input TimingFigure 7: Card Input TimingSymbolMinMaxUnitSDR104 modet IS 1.40 - ns C CARD = 10pF , V CT = 0.975V t IH 0.80 ns C CARD = 5pF , V CT = 0.975V SymbolMinMaxUnitSDR12, SDR25 and SDR50 modest IS 3.00 - ns C CARD = 10pF , V CT = 0.975V t IH 0.80 - nsC CARD = 5pF , V CT = 0.975V Table 14: SDR50 and SDR104 Input Timing7.2.3.3 Card Output Timing7.2.3.3.1 Output Timing of Fixed Data Window (SDR12, SDR25 and SDR50)Figure 8:Output Timing of Fixed Date WindowSymbolMinMaxUnitRemarkt ODLY - 7.5 nst CLK ≥10.0ns, CL=30pF, using driver Type B,for SDR50. t ODLY 14 nst CLK ≥20.0ns, CL=40pF, using driver Type B,for SDR25 and SDR12. t OH1.5-nsHold time at the t ODLY (min.). CL=15pFTable 15: Output Timing of Fixed Data Window7.2.3.3.2 Output Timing of Variable Window (SDR104)Figure 9: Output Timing of Variable Data WindowSymbol Min Max Unit Remarkt OP -2UICard Output Phase△t OP-350 +1550 psDelay variation due to temperature change after tuningt ODW 0.60 - UIt ODW = 2.88ns at 208MHz Table 16: Output Timing of Variable Data Window8. Physical DimensionType MeasurementLength15mm+/-0.1mm(B)Width11mm+/-0.1mm(A)Thickness 1.0mm+/-0.1mm(C)0.7mm+/-0.1mm(C1)Weight 0.33gram MaxTable 17: MicroSD card physical dimension (Unit in mm) Mechanical form factor as follows: (Unit in mm)Figure 10: Bottom ViewFigure 11: TOP View。

博世安全系统-法拉登VIVIDIO应用程序步骤配置说明书

From Nuremberg BT-VS/MKP-XPT Product Management 20.04.2023Release LetterProduct: VIDEOJET decoder 7000 VJD-7513Version: Firmware 10.40.0055This letter contains latest information about the above-mentioned product.1. GeneralThis firmware release 10.40.0055 is a feature release based on FW 10.31.0005.Changes since last release FW 10.31.0005 are marked in blue.VIDEOJET decoder 7000 uses robust, fan-less technology designed for ambitious environmental conditions while providing maximum performance on minimum space in a nicely designed industrial housing.VIDEOJET decoder 7000 displays video from Standard Definition (SD), High Definition (HD), 4K Ultra High Definition (UHD), and Megapixel (MP) cameras and encoders using H.265, H.264 or MPEG-4 encoding at up to 60 frames per second over IP networks.VIDEOJET decoder 7000 is the successor of VIDEOJET decoder 8000 (VJD-8000, VJD-8000-N). It is using the same housing but comes with different video output interfaces and provides improved performance and functionality.Notes:•Firmware update may take several minutes due to a large cumulative Microsoft patch.•This firmware includes OpenSSL.From NurembergBT-VS/MKP-XPT Product Management 20.04.20232. Applicable products•VIDEOJET decoder 7000, VJD-75133. New Features•SRTP for encrypted multicast traffic is supported. This allows fully secured communication with and video streaming from CPP13 and CPP14 cameras in multicast environments.•SNMPv3 trap service has been added, including the support of SNMP-related RCP+ commands for configuration.• A JPEG snapshot is now possible from each of the displays, including JPEG quality settings parameter.•Display order can be re-arranged in case Windows display detection differs from mechanical order.•The default layout is depending on the display number to simplify the identification of display order. The number of video windows per display increases as square of the display number.•The web interface of the decoder has been updated to the latest style guide and re-structured to ease usage for installation, licensing, and integration purposes.o The new web pages provide links to documentation and include a live preview.o Maintenance log file creation and download is supported by a workflow mechanism.o A keyboard emulator supports initial setup for IP Matrix even without keyboard connected.From NurembergBT-VS/MKP-XPT Product Management 20.04.20234. Changes•The Video SDK as one of the core components for the decoder firmware has been updated to latest version 6.40, providing a great number of improvements and fixes, mainly aroundONVIF and RTSP support, increasing the overall robustness.•An issue is fixed for banner upload when banners are activated.•An issue is fixed for zooming out in client dewarping mode of panoramic camera streams.•An issue is fixed where client dewarping was not working on line 1 of a panoramic camera in onboard dewarping mode. Onboard dewarping is only available for lines 2 and higher, line 1 always provides the full warped image circle.•An issue with DNS server configuration is fixed.•An issue is fixed where CPP13 and CPP14 cameras were not correctly connected in camera sequences.•Maintenance log file download is improved, supported by the new web interface structure.•An issue is fixed where daylight saving time was incorrectly reflected in time zone offset calculation.5. System RequirementsFor configuration purposes:•Configuration Manager 7.61 or newerFor operation purposes:•Bosch Video Management System 12.0 or higherNote that not all features may be supported by BVMS yet.Please refer to BVMS release notes.From NurembergBT-VS/MKP-XPT Product Management 20.04.20236. Restrictions; Known Issues•Connecting encrypted streams without proper signalling may result in crashing the software decoder instance, resulting in black video displayed.•Alarms will not be signaled with a red border around the cameo if connection was established using CONNECT_PRIMITIVE.•Using CONNECT_PRIMITIVE via TCP is not possible.•CONNECT_PRIMITIVE does not support "first available" feature.•Audio may remain audible despite layout change to other than single view.•RCP+ command CONF_ALARM_CONNECT_TO_IP is not supported.•Alarm connection does not support audio, nor does it include metadata.•Maximum password length is 19 characters.•With “Reconnect last devices” active camera connections are stored and automatically reconnected after reboot. To avoid deadlock in case of an overload situation the automaticreconnect will be deactivated after the decoder was forced into reboot for ten times within 10 minutes.•Monitors may be swapped after update. Swap back is possible using Configuration Manager.•IP Matrix pre-requisites for multi-decoder clustering:o Fixed IP addresses must be assigned; DHCP configuration is not functional.o Passwords for service level must be same on all clustered decoders.o Passwords for user level must be same on all clustered decoders.•After removing a slave decoder from the IP Matrix master, both decoders must be restarted.•Camera sequences are paused when picture-in-picture mode is activated.•Time related settings may appear in Configuration Manager only with delay or after a reboot.•Monitors connected to the Display Port via USB-C may not always be detected during booting.In this case, unplug and reconnect the adapter or cable to the monitor. If only one monitor isused it is recommended to connect to the direct HDMI output.•Log file download stability may be affected by workload of decoder. As a workaround, the download may need to be repeated, or the workload of the decoder may need to be reduced (disconnect all camera streams).•Time zone configuration is only supported via TIME_ZONE_STRING.•The KBD-DIGITAL keyboard is locked automatically during start-up of the decoder, or with re-connect. It will be unlocked after entering the PIN but the lock screen will remain until the next action on the keyboard.•Certificates used with the decoder must not have any Windows policies defined.•DNS resolution is not implemented yet, thus time server entry only works with IP addresses.•Dewarping zoom does not work correctly for panoramic cameras in on-board dewarping mode for camera line 1.•Overload messages and traps may appear too sensitive in cases where display refresh rates are lower than video stream frame rates.From NurembergBT-VS/MKP-XPT Product Management 20.04.20237. Previous Revisions7.1. New Features with 10.31.0005•Support for HOST_NAME to get and set the device’s hostname; only supported in extended configuration mode.•Support for DNS_SERVER_IP_STRING to get and set primary and secondary DNS server IPv4 addresses.7.2. Changes with 10.31.0005•Optimized transparent data processing time to allow adequate transparent data pass-through for serial PTZ keyboard.•An issue is fixed to apply e-PTZ presets correctly in camera sequences.•Feature loss due to suppressing encrypted UDP multicast connections for Bosch IP cameras with firmware 8 and higher, and fall back to TCP, tunneled via HTTPS control connection.(This feature will be added again with FW 10.40.)From NurembergBT-VS/MKP-XPT Product Management 20.04.20237.3. New Features with 10.30.0005•The default setting for Automatic IPv4 address assignment is set to “DHCP plus Link-Local”.Though this might seem a small change, it may have an impact:The former default IP address 192.168.0.200 will virtually become obsolete.Instead, the camera will assign itself an auto-IP address out of the range 169.254.1.0 to169.254.254.255 as long as there is no other IP address assigned by a DHCP server.(https:///wiki/Link-local_address)The advantage is that there are no more duplicate IP addresses, which is consideredprohibited in a network.•Network authentication 802.1x with EAP/TLS has been added.Please note that the server certificate needs to get the usages ‘Trust’ and ‘EAP_TLS_Trusted’ assigned.The client certificate will get the necessary usages assigned automatically.•The possibility of large banner overlays has been introduced.o Banners can be uploaded as images that can be displayed over three areas: top, center and bottom. The images are scaled to fill the area and cropped wherenecessary.o Banners can be sequenced with a configurable dwell time.o Configuration Manager 7.60 is supporting this with upload and banner sequence configuration, including banner previews.•Set and recall prepositions for moving cameras (AUTODOME, MIC) as well as for ONVIF PTZ cameras via keyboard has been added to the IP Matrix functionality.•Images can be uploaded to the decoder for two purposes, using Configuration Manager. The images shall be in JPG format and must be named as follows:o‘monitor background’ image, shown as background of an empty video window: ‘Logo.jpg’o‘’no camera’ image, shown on connection failure: ‘NoCamLogo.jpg’7.4. Changes with 10.30.0005•An issue was fixed where uploading a new video loss image did not break the software seal.From NurembergBT-VS/MKP-XPT Product Management 20.04.20237.5. Changes with 10.23.0002• A security vulnerability has been fixed where a crafted configuration packet sent by an authenticated administrative user can be used to execute arbitrary commands in systemcontext (CVE-2021-23862).For more details refer to our Security Advisory BOSCH-SA-043434-BT, published at ourSecurity Advisory web pagehttps:///xc/en/support/product-security/security-advisories.htmlor visit our PSIRT website at https://.7.6. New Features with 10.22.0038•APIPA (link-local address, Auto-IP) is used instead of a default IP address when DHCP is on and no DHCP server responded.•Transparent data pass-through for serial PTZ keyboard (SERIAL_PORT_APP_VAL and TRANSFER_TRNSPARENT_DATA) has been added.•Support of RCP+ via CGI (including WRITE commands) has been added.•HTTP digest authentication is supported for RCP+ via CGI.•Display orientation can be changed per line via RCP+.•RCP+ WRITE command MONITOR_NAME now supported for custom monitor names.•Updated RCP+ documentation is now available via the VIDEOJET decoder webpage.•Download of screen and tile snapshots via snap.jpg is now supported (requires at least user privileges).•Firmware update on-screen countdown dialog now shows a heartbeat whenever a single update step takes longer.•Support of CONNECT_URL read queries to get current video connection details, including current digital and dewarping zoom settings, has been added.•Support of various digital and dewarping zoom persistence modes(DIGITAL_ZOOM_PERSISTENCE_MODE) has been added.•Support of SYSTEM_DATETIME_V2 to read/write UTC system time has been added.•Support for new Sentinel RMS licenses has been added. Legacy licenses can now also be based on new installation code (lock code from Sentinel RMS).From NurembergBT-VS/MKP-XPT Product Management 20.04.20237.7. Changes with 10.22.0038•IP Matrix initialization is now working also for camera lines larger than 1.•RCP+ response for query on connected cameras is now working correctly.•URL extension for camera configuration in IP Matrix is no longer truncated.•An issue with an unexpected application restart has been fixed.•The DECODER_GROUP command is no longer supported when decoder IP address is not static. This disables the whole IP matrix configuration pages in Configuration Manager until a static IP is configured in the decoder’s network settings.•Improvements were made for log export via webpage and via Configuration Manager.•KBD-DIGITAL keyboard PIN is now used immediately without application restart.•KBD-DIGITAL keyboard PIN is now required whenever keyboard is attached and at application start.•Display orientation is now working for further monitor types.•Support of further USB to serial COM port adapters for KBD-DIGITAL keyboard connectivity.o Current: Prolific PL2303 [hardware ID USB\VID_067B&PID_2303]o New: Prolific PL2303GT [hardware ID USB\VID_067B&PID_23C3]o New: ATEN UC232A [hardware ID USB\VID_0557&PID_2008]o New: Unitek Y-108 [hardware ID FTDIBUS\VID_0403+PID_6001]o CableCreation CD0489 (PL2303) [hardware ID USB\VID_067B&PID_2303] is compatible to the already supported Prolific PL2303 adapter.Please note that the KBD-DIGITAL keyboard connectivity requires continuous maintenance, since new or not listed USB-to-serial COM port adapters typically require the installation of a suitable driver on the VIDEOJET decoder and an adaption of the hardware ID filter in thekeyboard detection software module. Newer USB adapters may require a firmware update to become supported.From NurembergBT-VS/MKP-XPT Product Management 20.04.20237.8. New Features with 10.01.0036Security• A protected configuration mode has been implemented, allowing too enable SSD encryption (BitLocker) and too disable USB ports, e.g. for installation of the decoder in public areas.•The configuration of the decoder can be protected by Software Sealing, similar to IP cameras.•The latest Microsoft Windows security updates have been included.Miscellaneous• A dewarped cutout from panoramic cameras can be defined with PTZ coordinates.• A new way to control and integrate the decoder into a management system has been added by a JSON RPC API. This allows to send commands and retrieve status information via JSON remote procedure calls. The API documentation is added to the distribution package.• A video output capture service (VOCS) has been implemented which could be activated via a license, applicable per display output. This service captures the memory of the video outputand encodes it into a camera-like video stream, which can be recorded via Video StreamingGateway (VSG) onto iSCSI storage.• A time server can be added to synchronize the decoder.•Decoder log file can be downloaded via Configuration Manager. This is especially recommended when download of the log file is not working correctly via web browser.7.9. Changes with 10.01.0036•Upload of background image and connection loss image to the decoder and reverting them to default is now also possible with service password set. The former restriction is obsolete.•Various minor bug fixes.From NurembergBT-VS/MKP-XPT Product Management 20.04.20237.10. New Features with 9.60.0017IP Matrix enhancements•KBD-DIGITAL is supported in addition to KBD-UNIVERSAL XF.This keyboard requires a serial-to-USB adapter to connect to the decoder.Both keyboards can be mixed in a clustered multi-decoder IP Matrix, one keyboard perdecoder.•Playback from local recording is supported.Permission is configured via Configuration Manager for the whole IP Matrix, valid for all users.•Buttons for next and previous camera have been added to the KBD-UXF functions.•Audio can be switched on or off via keyboard.•Camera channels can be extended via license up to 64 cameras per decoder unit.Note:IP Matrix manual is now separated intoo One configuration manual for IP Matrixo One operation manual for IP Matrix using KBD-UXFo One operation manual for IP Matrix using KBD-DIGITALSecurity•The latest Microsoft Windows security updates have been included.Miscellaneous•Background image and connection loss image can be uploaded to the decoder, replacing the default images. Reverting them to default is done by uploading an empty image.Note: Upload is only possible in conjunction with an empty service password.7.11. Changes with 9.60.0017•Temperature control margin increased to improve maximum performance at the specified maximum temperature, covering component tolerances, and to ensure that all productsadhere fully to their specification.•Various minor bug fixes.Security SystemsFromNuremberg BT-VS/MKP-XPT Product Management 20.04.202311BOSCH and the symbol are registered trademarks of Robert Bosch GmbH, Germany 7.12. Features with initial release 9.51• VIDEOJET decoder 7000 displays video from Standard Definition (SD), High Definition (HD),4K Ultra High Definition (UHD), and Megapixel (MP) cameras and encoders using H.264 or MPEG -4 encoding at up to 60 frames per second over IP networks.• VIDEOJET decoder 7000 provides an HDMI and a DisplayPort (via USB-C connector) output, both capable of driving up to 4K UHD displays simultaneously.• Display settings are automatically discovered and set for optimal display performance. • Monitor layouts can be switched independently for each display.• Upright monitors (portrait mode) are supported.• Video window (cameo) aspect ratio can be set to 16:9, 9:16, 3:4, or 1:1.• Active camera connections and layout are stored and automatically reconnected after reboot if configured. To avoid deadlock in case of an overload situation the automatic reconnect will be deactivated after VIDEOJET decoder 7000 was forced into reboot for 3 times within 10 minutes.• Video smoothing can be configured.• RTSP connections are supported, enabling connectivity to 3rd party and ONVIF cameras. • Discovery port is configurable.• Cameo distance is configurable.• VIDEOJET decoder 7000 supports IP Matrix application as built-in feature.• VIDEOJET decoder 7000 is able to display VCA metadata.• VIDEOJET decoder 7000 provides bi-directional G.711 audio for the video stream shown in single view on the first monitor.• Configuration is done using the Configuration Manager.• The number of decoders presented in capabilities is configurable to regulate the consumption of VMS licenses. Default value is 30.• System access is password-protected with two levels.• The system firmware can be upgraded remotely.• System API is compatible to predecessor VIDEOJET decoder 8000 for easy plug-and-play integration.• Operating temperature iso 0 °C to +50 °C (+32 °F to +122 °F) ambient temperature, with airflow o 0 °C to +40 °C (+32 °F to +104 °F) ambient temperature, still airFor detailed functional description of inherited firmware features, please refer to the VIDEOJET decoder 8000 firmware 9.51 release notes.For detailed technical specification, please refer to the datasheet.。

iSee mini升级指南

iSee mini升级指导1.下载升级包a)下载升级包“iSee mini升级工具包”解压得到如下文件三个文件夹（SD-CardMaker、Format Flash、Auto update）2.制作升级卡a)使用读卡器将SD卡(推荐使用256MB以上，8GB以下的Micro SD卡)连接电脑；b)打开SD-CardMaker文件夹，运行 SDcardMaker.exe（操作系统推荐使用windows XP，windows 7请以管理员身份运行,不支持windows 8），选择SD卡所指向的可移动磁盘，勾选“是否重新分区并格式化”后面的“是”，点击打开选择SD-CardMaker文件夹里的u-boot.bin文件。

如图所示点击“制作启动卡”弹出分区完成窗口，点击确定，在弹出的格式化窗口里选择开始，如图所示格式化完毕后点击关闭，弹出制作完成窗口，点击确定即可。

3.清除iSee mini内部数据a)将Format Flash文件夹内的“wsot_factory_format.wst”文件复制到SD卡里面。

b)在iSee mini关机状态下插入SD卡，用遥控开机，观察两侧喇叭处有蓝灯以1Hz的频率交替闪烁（此过程很快大约2秒钟），此时，内部数据清空完毕。

c)用适配器圆形插头顶一下iSee mini背部的复位孔，使其断电关机（若有外部其它设备对其充电请先断开），弹出SD卡。

4.刷入新的升级包刷入新的升级包前请务必确认你的iSee mini的版本，否则导致升级失败。

这里以双频WiFi版演示，单频WiFi版本操作一样只是ROM不一样。

单双频可以查看iSee mini的包装盒查看，若参数栏标有双频WiFi即为双频版否则为单频版本（寄回厂家做过硬件升级的是双频版的）。

a)将SD卡连接电脑删除SD卡内的所有文件，复制Auto update文件夹下的“双频WiFi版”里的“factory_update_param.aml、ISEEMINI_20140812_HA_NO_6330、recovery”三个文件到SD卡里面。

STMicroelectronics DfuSe USB设备固件升级用户手册说明书

UM0412User manual Getting started with DfuSe USB device firmware upgradeSTMicroelectronics extensionIntroductionThis document describes the demonstration user interface that was developed to illustrateuse of the STMicroelectronics device firmware upgrade library. A description of this library,including its application programming interface, is contained in the “DfuSe applicationprogramming interface” document and installed with the DfuSe software.July 2009Doc ID 13379 Rev 41/22Contents UM0412Contents1Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1System requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.2Package contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3DfuSe demonstration installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3.1Software installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3.2Hardware installation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2DFU file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123User interface description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.1DfuSe demonstration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2DFU file manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2.1“Want to do” dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2.2File generation dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.2.3File extraction dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174Step-by-step procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.1DfuSe demonstration procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.1.1How to upload a DFU file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.1.2How to download a DFU file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.2DFU file manager procedures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2.1How to generate DFU files from S19/Hex/Bin files . . . . . . . . . . . . . . . . 204.2.2How to extract S19/Hex/Bin files from DFU files . . . . . . . . . . . . . . . . . . 20 5Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212/22 Doc ID 13379 Rev 4UM0412List of tables List of tablesTable 1.DfuSe demo dialog box description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 2.File generation dialog box description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 3.Multi bin injection dialog box description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 4.File extraction dialog box description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 5.Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Doc ID 13379 Rev 43/22List of figures UM0412 List of figuresFigure 1.System properties dialog box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2.Selecting the installation location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3.Driver selection option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4.Driver selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Figure 5.Installation from disk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 6.Progress message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 7.Warning message. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 8.Installation finish. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 9.DfuSe demo dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 10.Edit option byte dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 11.“Want to do” dialog box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 12.“Generation” dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 13.“Multi bin injection” dialog box . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 14.“Extract” dialog box. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4/22 Doc ID 13379 Rev 4UM0412Getting started Doc ID 13379 Rev 45/221 Getting started1.1 System requirementsIn order to use the DfuSe demonstration with the Windows operating system, a recentversion of Windows, such as Windows 98SE, Millennium, 2000, XP or VISTA, must beinstalled on the PC.The version of the Windows OS installed on your PC may be determined by right-clicking onthe “My Computer” icon in the desktop, then clicking on the “Properties” item in thedisplayed PopUpMenu. The OS type is displayed in the “System properties” dialog boxunder the “System” label in the “General” tabsheet (see Figure 1).Figure 1.System properties dialog boxGetting started UM04126/22 Doc ID 13379 Rev 41.2 Package contentsThe following items are supplied in this package:Software contents1. STTube driver consisting of the two following files:–STTub30.sys: Driver to be loaded for demo board.–STDFU.inf: Configuration file for driver.2. DfuSe_Demo_V3.0_Setup.exe: Installation file which installs the DfuSe applicationsand source code on your computer.Hardware contentsThis tool is designed to work with all STMicroelectronics devices which supports the Device Firmware Upgrade via an USB interface. For more details, please contact your STrepresentative or visit the ST web site ( ).1.3 DfuSe demonstration installation1.3.1 Software installationRun DfuSe_Demo_V3.0_Setup.exe file: the InstallShield Wizard will guide you to installDfuSe applications and source code on your computer. When the software is successfullyinstalled, click the “Finish” button. Y ou can then explore the driver directory.The driver files are located in the “Driver” folder in your install path (C:\Programfiles\STMicroelectronics\DfuSe).The source code for the Demo application and DfuSe library is located in the “C:\ProgramFiles\STMicroelectronics\DfuSe\Sources” folder.Documentation is located in the “C:\Program Files\STMicroelectronics\DfuSe\Sources\Doc”folder.1.3.2 Hardware installation●Connect the device to a spare USB port on your PC.●The “Found New Hardware Wizard” then starts. Select the “Install from a list or specific location” as shown below and then click “Next”.UM0412Getting startedDoc ID 13379 Rev 47/22Figure 2.Selecting the installation location ●Select “Don’t search. I will choose the driver to install” as shown below and then click“Next”.Getting started UM04128/22 Doc ID 13379 Rev 4Figure 3.Driver selection option ●If a driver is already installed, the model list will show the compatible hardware models, else click “Have Disk...” to locate the driver files.UM0412Getting startedDoc ID 13379 Rev 49/22Figure 4.Driver selection ●In the “Install From Disk” dialog box, click “Browse...” to specify the driver files location,the driver directory is located in your install path (C:\Programfiles\STMicroelectronics\DfuSe\Driver), then click “OK”.The PC autoselects the correct INF file, in this case STDFU.INF . Once Windows has found the required driver .INF file, the compatible hardware model will be displayed in the model list. Click “Next” to proceed.Getting started UM041210/22 Doc ID 13379 Rev 4Figure 5.Installation from disk●When Windows is performing the driver installation, a warning dialog will be displayed indicating that the driver has not passed Windows logo testing, click “continue Anyway”to continue.Figure 6.Progress messageUM0412Getting startedDoc ID 13379 Rev 411/22Figure 7.Warning message●Windows should then display a message indicating that the installation was successful. Click “Finish” to complete the installation.Figure 8.Installation finishDFU file UM041212/22 Doc ID 13379 Rev 42 DFU fileUsers that have purchased DFU devices require the ability to upgrade the firmware of thesedevices. Traditionally, firmware is stored in Hex, S19 or Binary files, but these formats do not contain the necessary information to perform the upgrade operation, they contain only the actual data of the program to be downloaded. However, the DFU operation requires more information, such as the product identifier, vendor identifier, Firmware version and the Alternate setting number (Target ID) of the target to be used, this information makes the upgrade targeted and more secure. To add this information, a new file format should be used, to be called DFU file format. For more details refer to the “DfuSe File Format Specification” document (UM0391).3 User interface descriptionThis section describes the different user interfaces available in the DfuSe package, andexplains how to use them to perform DFU operations such as Upload, Download andfirmware file management.demonstration3.1 DfuSeFirmware upgrades need to be able to be performed without any special training, even bynovice users. Hence, the user interface was designed to be as robust and simple to use aspossible (see Figure9). The numbers in Figure9 refer to the description in Table1 listingthe available controls in the DfuSe Demonstration interface.1234561178910121314151617Doc ID 13379 Rev 413/2214/22 Doc ID 13379 Rev 4If the microcontroller in use in an STM32F105xx or an STM32F107xx, the DfuSe demo shows a new feature that consists in reading the option byte data over the exported “Option byte” memory part. A double click on the related item in the memory map (Item 6 inTable 1/Figure 9) opens a new dialog box that displays the read option bytes. Y ou can use this box to edit and apply your own configuration (see Figure 10).The tool is able to detect the capabilities of the selected memory part (read, write and erase). In case of an unreadable memory (readout protection activated), it indicates the memory read status and prompts to ask whether to deactivate the read protection or not.Table 1.DfuSe demo dialog box descriptionControlDescription1Lists the available DFU and compatible HID devices, the selected one is the one currently used.Compatible HID device is a HID class device providing the HID detach feature (USAGE_P AGE 0xFF00 and USAGE_DETACH 0x0055) in its report descriptor.Example:0xa1, 0x00, // Collection(Physical)0x06, 0x00, 0xFF, // Vendor defined usage page - 0xFF000x85, 0x80, // REPORT_ID (128)0x09, 0x55, // USAGE (HID Detach)0x15, 0x00, // LOGICAL_MINIMUM (0)0x26, 0xFF, 0x00, // LOGICAL_MAXIMUM (255)0x75, 0x08, // REPORT_SIZE (8 bits)0x95, 0x01, // REPORT_COUNT (1)0xB1, 0x82, // FEATURE (Data,Var,Abs,Vol)0xC0, // END_COLLECTION (Vendor defined)2Device identifiers for DFU mode; PID, VID and Version.3Device identifiers for Application mode; PID, VID and Version.4Send Enter DFU mode command. Target will switch from Application to DFU mode or send a HID Detach if the device is a compatible HID device.5Send Leave DFU mode command. Target will switch from DFU to Application mode.6Memory mapping, Double click each item to view more details about the memory part.7Choose destination DFU file, the uploaded data will be copied into this file.8Start Upload operation.9Size of the transferred data during the current operation (Upload/Upgrade).10Duration time of the current operation (Upload/Upgrade).11Available targets in the loaded DFU file.12Choose source DFU file, the downloaded data will be loaded from this file.13Start upgrade operation (Erase then download).14Verify if data was successfully uploaded.15Show the progress of the operation.16Abort current operation.17Exit application.Doc ID 13379 Rev 415/22Figure 10.Edit option byte dialog box3.2DFU file manager3.2.1“Want to do” dialog boxWhen DFU file manager application is executed, the “Want to do” dialog box appears, the user has to choose the file operation he wants to do. Select the first Radio button togenerate a DFU file from an S19, Hex or Bin file, or the second to extract an S19, Hex or Bin file from a DFU file (see Figure 11).Figure 11.“Want to do” dialog boxSelect “I want to GENERATE a DFU file from S19, HEX or BIN files” radio button if you want to generate a DFU file from S19, Hex or Binary files.16/22 Doc ID 13379 Rev 4Select “I want to EXTRACT S19, HEX or BIN files from a DFU one” radio button if you want to extract an S19, Hex or Binary file from a DFU file.3.2.2 File generation dialog boxIf the first choice was selected, click the OK button to display the “File Generation dialog box”. This interface allows the user to generate a DFU file from an S19, Hex or Bin file.Because S19, Hex and Bin files do not contain the target specification, the user must enter the Device properties (VID, PID and version), the T arget ID and the target name before generating the DFU file.Table 2.File generation dialog box descriptionControl Description1Vendor identifier 2Product identifier 3Firmware version4Available images to be inserted in the DFU file 5T arget identifier number 6Open S19 or Hex file 7Open Binary files 8T arget name9Delete selected image from the images list 10Generate DFU file 11Cancel and exit applicationDoc ID 13379 Rev 417/223.2.3 File extraction dialog boxIf the second choice in the “Want to do” dialog box was selected, Click the OK button to display the “File extraction” dialog box. This interface allows you to generate an S19, Hex or Bin file from a DFU file.Table 3.Multi bin injection dialog box descriptionControl Description1Path of the last opened binary file2Open binary files. A binary file could be a file of any format (Wave, video, T ext, etc.)3Start address of the loaded file 4Add file to the file list 5Delete file from file list 6File list7Confirm file selection 8Cancel and exit operationTable 4.File extraction dialog box descriptionControl Description 1Device vendor identifier2Device product identifier3Firmware version4Open DFU file5Image list in the loaded DFU file6T ype of the file to be generated7 Extract image to S19, Hex or Bin file8Cancel and exit application18/22 Doc ID 13379 Rev 4UM0412Step-by-step proceduresDoc ID 13379 Rev 419/224 Step-by-step procedures4.1 DfuSe demonstration procedures4.1.1How to upload a DFU file1.Run the “DfuSe demonstration” application (Start -> All Programs ->STMicroelectronics -> DfuSe -> DfuSe Demonstration).2. Click “Choose” button (Item 7 in Table 1/Figure 9) to select a DFU file.3. Select the memory target(s) in the memory mapping list (Item 6 in Table 1/Figure 9).4.Click “Upload” button (Item 8 in Table 1/Figure 9) to start uploading memory content to the selected DFU file.4.1.2 How to download a DFU file1.Run the “DfuSe demonstration” application (Start -> All Programs -> STMicroelectronics -> DfuSe -> DfuSe Demonstration).2. Click the “Choose” button (Item 12 in Table 1/Figure 9) to select a DFU file. thedisplayed Information such as VID, PID, Version and target number is read from the DFU file.3. Check the “Optimize upgrade duration” checkbox to ignore FF blocks during the upload.4. Check the “Verify after download” checkbox if you want to launch the verification process after downloading data.5.Click the “Upgrade” button (Item 13 in Table 1/Figure 9) to start upgrading file content to the memory.6. Click the “Verify” button (Item 14 in Table 1/Figure 9) to verify if the data wassuccessfully downloaded.Step-by-step procedures UM0412 4.2 DFU file manager procedures4.2.1 How to generate DFU files from S19/Hex/Bin files1.Run the “DFU File Manager” application (Start -> All Programs -> STMicroelectronics -> DfuSe-> DFU File Manager).2. Select “I want to GENERATE a DFU file from S19, HEX or BIN files” item in the “Wantto do” dialog box(Table11) then click “OK”.3. Create a DFU image from an S19/Hex or binary file.a) Set a non used Target ID number (Item 5 in Table2/Figure12).b) Fill the VID, PID, Version and the target namec) To create the image from an S19 or Hex file, click the “S19 or Hex” button (Item 6in Table2/Figure4) and select your file, a DFU image will be created for eachadded file.d) To create the image from one or more binary files, click the “Multi Bin” button (Item7 in Table2/Figure12) to show the “Multi Bin Injection” dialog box (Figure 13.).Click the Browse button (Item 2 in Table3/Figure13) to select a binary file(*.bin) orother format of file (Wave, Video, T ext,...).Set the start address in the address field (Item 3 in T able3/Figure13).Click the “Add to list” button (Item 4 in T able3/Figure13) to add the selectedbinary file with the given address.To delete an existing file, select it, then click the “Delete” button (Item 5 inTable3/Figure13).Redo the same sequence to add other binary files,Click “OK” to validate.4. Repeat step (3.) to create other DFU images.5. To create the DFU file, click “Generate”.4.2.2 How to extract S19/Hex/Bin files from DFU files1.Run “DFU File Manager” application (Start -> All Programs -> STMicroelectronics ->DfuSe -> DFU File Manage).2. Select “I want to EXTRACT S19, HEX or BIN files from a DFU one” radio button in the“Want to do” dialog box (Figure11) then click “OK”.3. Extract an S19/Hex or binary file from a DFU file.a) Click the Browse button (Item 4 in Table4/Figure14) to select a DFU file. Thecontained images will be listed in the images list (Item 4 in Table4/Figure14).b) Select an image from the images list.c) Select Hex, S19 or Multiple Bin radio button (Item 6 in Table4/Figure14).d) Click the “Extract” button (Item 7 in Table4/Figure14) to extract the selectedimage.4. Repeat step (3.) to extract other DFU images.20/22 Doc ID 13379 Rev 4UM0412Revision history Doc ID 13379 Rev 421/225 Revision historyTable 5.Document revision history DateRevision Changes 06-Jun-20071Initial release.02-Jan-20082Added Section 4.24-Sep-20083Updated Figure 9 to Figure 14.02-Jul-20094DfuSe demo upgraded to version V3.0.Section 3.1: DfuSe demonstration updated:–Figure 9: DfuSe demo dialog box updated–New feature added for STM32F105/107xx devices–Figure 10: Edit option byte dialog box addedUpdated in Section 3.2: DFU file manager :–Figure 11: “Want to do” dialog box–Figure 12: “Generation” dialog box–Figure 13: “Multi bin injection” dialog box–Figure 14: “Extract” dialog boxUM0412Please Read Carefully:Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice.All ST products are sold pursuant to ST’s terms and conditions of sale.Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.UNL ESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SAL E ST DISCL AIMS ANY EXPRESS OR IMPL IED WARRANTY WITH RESPECT TO THE USE AND/OR SAL E OF ST PRODUCTS INCL UDING WITHOUT L IMITATION IMPL IED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNL ESS EXPRESSL Y APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST.ST and the ST logo are trademarks or registered trademarks of ST in various countries.Information in this document supersedes and replaces all information previously supplied.The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.© 2009 STMicroelectronics - All rights reservedSTMicroelectronics group of companiesAustralia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America22/22 Doc ID 13379 Rev 4。

树莓派SD卡镜像备份

树莓派SD卡镜像备份一、准备工作1、已经配置启动的树莓派SD卡2、Linux系统的pc3、读卡器二、修改SD卡文件刚开始我先再win7下把SD卡接到pc上，发现无法读取。

用DISKGENIUS查看pc的磁盘状态，发现SD卡被格式化为两个分区，一个56M的Fat32分区，一个7.5G的Ext3分区。

如下图：Ext3分区在win下无法读出，所以改换linux系统打开SD卡。

在linux命令行上输入df -h可以看到有两个分区sbd1和sdb2已经挂载到pc上了。

接下来对SD中的文件进行修改。

ls进入两个分区，发现56M的分区是boot分区，7.4G的分区是树莓派的系统文件分区。

进入7.4G分区：在/home中有pi和我自己新建的djy用户的文件夹。

进入pi，新建一个tast文件输入this is the test file to edit the files in RPI's SD card成功后ls发现多了test文件 cat后文件内容正确。

三、备份SD卡既然已经读到SD卡，就可以用dd命令直接备份。

之前已经df过SD卡的路径是sdb1和sdb2 所以要备份整个卡就用路径/dev/sdb。

输入命令：（镜像写回SD卡命令：Sudo dd if=/home/djy/Rpi_save_3_6.img of=/dev/sdb)源是/evt/sdb既SD卡，目标是/home/djy/文件夹下的Rpi_save_3_6.img镜像备份到一半发现磁盘不足，只好换个路径。

备份好的img大小为8.1G。

可是Sd卡只用了2.2G的空间，备份却要8.1G，太浪费了。

查了dd的文档后，我用了以下命令：他在复制镜像的时候同时进行压缩。

节省了空间，最后得到的Rpi_save_3_6.gz 只有700M。

四、备份恢复到SD卡先用fdisk对SD卡格式化。

1、查看原有分区：2、删除分区，保存：SD卡已经空了：在用命令恢复备份：解压再写SD卡。

mini2440中SD卡测试源码阅读笔记

rGPECON = 0xaaaaaaaa; //SDCMD, SDDAT[3:0]
Uart_Printf("\nSDI Card Write and Read Test\n"); if(!SD_card_init()) //等待 SD 卡初始化完成
return; TR_Buf_new();//发送数据缓冲区初始化
}
}
if(!error) { Uart_Printf("\nThe Tx_buffer is same to Rx_buffer!\n"); Uart_Printf("SD CARD Write and Read test is OK!\n"); } } void View_Tx_buf(void) { } int SD_card_init(void) //SD 卡初始化
volatile unsigned int TR_end=0; int Wide=0; // 0:1bit, 1:4bit
int MMC=0; // 0:SD , 1:MMC
int Maker_ID; char Product_Name[7]; int Serial_Num; volatile int RCA; void Test_SDI(void) { U32 save_rGPEUP, save_rGPECON;
//送 CMD3, MMC（设置 RCA,产生 RSP1）,SD（设置 RCA,产生 RSP6）
//检查 CMD3 是否成功发送并收到响应
if(!Chk_CMDend(3, 1))
goto RECMD3; //出错，重新发送
rSDICSTA=0xa00; // 清除命令和应答结束标志位
//--Publish RCA

飞思卡尔半导体用户指南说明书

Freescale Semiconductor User’s Guide1OverviewThe Freescale Freedom development platform is a set of software and hardware tools for evaluation and development. It’s ideal for the rapid prototyping ofmicrocontroller-based applications. The Freescale Freedom KL26Z hardware (FRDM-KL26Z) is a capable and cost-effective design featuring a Kinetis L seriesmicrocontroller, the industry’s first microcontroller built on the ARM® Cortex™-M0+ core.FRDM-KL26Z can be used to evaluate the KL16 and KL26 Kinetis L series devices. It features a KL26Z128VLH4, a device boasting a maximum operating frequency of 48MHz, 128KB of flash, a full-speed USB controller, and numerous analog and digital peripherals. The FRDM-KL26Z hardware is form-factor compatible with the Arduino™ R3 pin layout, providing a broad range of expansion board options. The on-board interfaces include an RGB LED, a 6-axis digital sensor (combining a 3D accelerometer and 3Dmagnetometer), ambient light sensor, and a capacitive touch slider.The FRDM-KL26Z features the Freescale open standard embedded serial and debug adapter known as OpenSDA.Doc Number:FRDMKL26ZUGRev. 0, 10/2013Contents1.Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . 23.Getting started . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24.FRDM-KL26Z hardware overview . . . . . . . . . . . . . . 25.FRDM-KL26Z hardware description . . . . . . . . . . . . . 5FRDM-KL26Z User’s GuidebyFreescale Semiconductor, Inc.Reference documentsThis circuit offers several options for serial communications, flash programming and run-control debugging.2Reference documentsThe table below provides a list of reference documents for the FRDM-KL26Z hardware. All of these documents are available online at /FRDM-KL26Z.Table1. FRDM-KL26Z reference documentsFilename DescriptionFRDM-KL26Z Quick Start Package Quick Start Guide and supporting files for getting started with the FRDM-KL26Z FRDM-KL26Z User’s Guide This document—overview and detailed information for the FRDM-KL26ZhardwareFRDM-KL26Z Pinouts Spreadsheet of pin connections for all MCU pins. Includes pinout for the I/Oheaders, Arduino R3 compatibility chart, and OpenSDA MCU pinout.FRDM-KL26Z Schematics PDF schematics for the FRDM-KL26Z hardwareFRDM-KL26Z Design Package Zip file containing all design source files for the FRDM-KL26Z hardware OpenSDA User’s Guide Overview and instructions for use of the OpenSDA embedded debug circuit3Getting startedSee the FRDM-KL26Z Quick Start Package for step-by-step instructions to get started with the FRDM-KL26Z. See the Jump Start Your Design section on /FRDM-KL26Z for the Quick Start Package and software lab guides.4FRDM-KL26Z hardware overviewThe features of the FRDM-KL26Z include:•MKL26Z128VLH4 in a 64 LQFP package•Capacitive touch slider•FXOS8700CQ accelerometer and magnetometer•Tri-color (RGB) LED•Ambient light sensor•User push button•Flexible power supply options – USB, coin cell battery, external source•Battery-ready, power-measurement access points•Easy access to MCU I/O via Arduino™ R3 compatible I/O connectors•Programmable OpenSDA debug interface with multiple applications available including:—Mass storage device flash programming interface—P&E Debug interface provides run-control debugging and compatibility with IDE toolsFRDM-KL26Z hardware overview—CMSIS-DAP interface: new ARM standard for embedded debug interface—Data logging applicationFigure1 shows a block diagram of the FRDM-KL26Z design. The primary components and their placement on the hardware assembly are pointed out in Figure2.Figure1. FRDM-KL26Z block diagramFRDM-KL26Z hardware overview! (Figure2. FRDM-KL26Z feature call-outsFRDM-KL26Z hardware description5FRDM ‐KL26Z hardware description5.1Power supplyThere are multiple power supply options on the FRDM-KL26Z. It can be powered from either of the USB connectors, the VIN pin on the I/O header, an on-board coin cell battery, or an off-board 1.71-3.6V supply from the 3.3V pin on the I/O header. The USB and VIN supplies are regulated on-board using a 3.3V linear regulator to produce the main power supply. The other two sources are not regulated on-board. Table 2 provides the operational details and requirements for the power supplies.Table 2.Power supply requirementsNote that the OpenSDA circuit is only operational when a USB cable is connected and supplying power to J10. However, protection circuitry is in place to allow multiple sources to be powered at once.Figure 3 shows the schematic drawing for the power supply inputs and the on-board voltage regulator.Figure 3. Power supply schematicIn addition, regulated power can be supplied to J3 pin 10 from an external source through P5-9V_VIN by populating the board with an optional voltage regulator, e.g. a 7805 style regulator in a TO-220 package, thus providing a high current supply to external devices. To prevent voltage sag under a high load, C23,Supply Source Valid RangeOpenSDA Operational?Regulated on-board?OpenSDA USB (J7)5V Yes Yes KL26Z USB (J5)5V No Yes V in 4.3-9V No Yes 3.3V pin 1.71-3.6V No No Coin cell battery1.71-3.6VNoNoFRDM-KL26Z hardware descriptionC24, C25 & C28 should be populated with appropriately sized capacitors to match the regulator chosen. See Figure4.Figure4. Optional voltage regulator schematicTable3. FRDM-KL26Z power suppliesPowerDescriptionSupply NameP5-9V_VIN Power supplied from the V in pin of the I/O headers (J3 pin 16)P5V_SDA Power supplied from the OpenSDA USB connector (J10). A Schottky diode provides back drive protection.P5V_KL26Z Power supplied from the KL26Z USB connector (J6). A Schottky diode provides back drive protection P3V3_VREG Regulated 3.3V supply. Sources power to the P3V3 supply rail with an optional back drive protection Schottky diode.12P3V3_BATT Coin cell battery supply voltage. Sources power to the P3V3 supply rail with the option of adding a back drive protection Schottky diode.3P3V3Main supply rail for the FRDM-KL26Z assembly. May be sourced from P3V3_VREG, P3V3_BATT, or directly from the I/O headers (J3 pin 8).P3V3_KL26Z KL26Z MCU supply. Header J5 provides a convenient means for energy consumption measurements.4 P3V3_SDA OpenSDA circuit supply. Header J15 provides a convenient means for energy consumptionmeasurements.4P5V_USB Nominal 5V supplied to the I/O headers (J3 pin 10). Sourced from either the P5V_KL26Z or P5V_SDA supply through a back drive protection Schottky diode.FRDM-KL26Z hardware description5.2Serial and debug adapter (OpenSDA)OpenSDA is an open standard serial and debug adapter. It bridges serial and debug communications between a USB host and an embedded target processor as shown in Figure 5. The hardware circuit is based on a Freescale Kinetis K20 family microcontroller (MCU) with 128 KB of embedded flash and anintegrated USB controller. OpenSDA features a mass storage device (MSD) bootloader, which provides a quick and easy mechanism for loading different OpenSDA applications such as flash programmers, run-control debug interfaces, serial-to-USB converters, and more. See the OpenSDA User’s Guide for more details.Figure 5. OpenSDA high-level block diagramOpenSDA is managed by a Kinetis K20 MCU built on the ARM® Cortex™-M4 core. The OpenSDA circuit includes a status LED (D8) and a pushbutton (SW2). The pushbutton asserts a reset signal to the KL26Z target MCU. It can also be used to place the OpenSDA circuit into Bootloader mode. OpenSDA MCU RESET can be isolated from SW2 by cutting the trace between pins on J13. SPI and GPIO signals1By default the linear regulator, U1, is a 3.3V output regulator. However, this is a common footprint that would allow the user to modify the assembly to utilize an alternative device such as a 1.8V or 2.5V regulator. The KL26Z microcontroller has an operating range of 1.71V to 3.6V.2D2 is bypassed by J14. By default, the pins of J14 are shorted together, to reduce the voltage drop across D2. To use D2, cut the trace between the pins of J14.3If a coin cell battery is to be used, add a small amount of solder to the coin cell ground pad before adding the battery holder. Also, it is recommended to populate D1 as a protection diode when using a coin cell battery.4J5 and J15 are not populated by default. The two pins of these headers are in parallel with 0 Ω resistors. In addition, J5 is also in parallel with a 10 Ω resistor. To measure the energy consumption of the KL26Z, either a voltmeter or an ammeter may be used. To use a voltmeter, R3 (0 Ω) must be removed before connecting the voltmeter probes to the pins of J5. Both R3 and R2 (10 Ω) must be removed to measure current with an ammeter. For the OpenSDA MCU, energy consumption can be measured by removing R4 (0 Ω) and connecting ammeter probes to the pins of J15.FRDM-KL26Z hardware descriptionprovide an interface to the SWD debug port of the KL26Z. Additionally, signal connections are available to implement a UART serial channel. The OpenSDA circuit receives power when the USB connector J10 is plugged into a USB host.5.2.1Debug interfaceSignals with SPI and GPIO capability are used to connect directly to the SWD of the KL26Z. These signals are also brought out to a standard 10-pin (0.05”) Cortex Debug connector (J7). It is possible to isolate the KL26Z MCU from the OpenSDA circuit and use J7 to connect to an off-board MCU. To accomplish this, cut the trace on the bottom side of the PCB that connects J8 pin 1 to J8 pin 2. This will disconnect the SWD_CLK pin to the KL26Z so that it will not interfere with the communications to an off-board MCU connected to J7.Figure6. SWD debug connectorNote that J7 is not populated by default. A Samtec FTSH-105-02-F-D or compatible connector can be added to the J7 through-hole connector. A mating cable, such as a Samtec FFSD IDC cable, can then be used to connect from the OpenSDA of the FRDM-KL26Z to an off-board SWD connector.5.2.2Virtual serial portA serial port connection is available between the OpenSDA MCU and pins PTA1 and PTA2 of the KL26Z. Several of the default OpenSDA Applications provided by Freescale, including the MSD Flash Programmer and the P&E Debug Application, provide a USB communications device class (CDC) interface that bridges serial communications between the USB host and this serial interface on the KL26Z.5.3KL26Z microcontrollerThe target microcontroller of the FRDM-KL26Z is the KL26Z128VLH4, a Kinetis L series device in a 64 LQFP package. The KL26Z MCU features include:FRDM-KL26Z hardware description•32-bit ARM Cortex-M0+ core—Up to 48 MHz operation—Single-cycle fast I/O access port•Memories—128 KB flash—16 KB SRAM•System integration—Power management and mode controllers—Low-leakage wakeup unit—Bit manipulation engine for read-modify-write peripheral operations—Direct memory access (DMA) controller—Computer operating properly (COP) Watchdog timer•Clocks—Clock generation module with FLL and PLL for system and CPU clock generation—4 MHz and 32 kHz internal reference clock—System oscillator supporting external crystal or resonator—Low-power 1kHz RC oscillator for RTC and COP watchdog•Analog peripherals—16-bit SAR ADC w/ DMA support—12-bit DAC w/ DMA support—High speed comparator•Communication peripherals—Two 16-bit Serial Peripheral Interfaces (SPI)—USB dual-role controller with built-in FS/LS transceiver—USB voltage regulator—Two I2C modules—One low-power UART and two standard UART modules—One I2S module•Timers—One 6-channel Timer/PWM module—T wo 2-channel Timer/PWM modules—2-channel Periodic Interrupt Timer (PIT)—Real time clock (RTC)—Low-power Timer (LPTMR)—System tick timer•Human-Machine Interfaces (HMI)—General purpose input/output controllerFRDM-KL26Z hardware description—Capacitive touch sense input interface hardware module5.3.1Clock sourceThe Kinetis KL26 microcontrollers feature an on-chip oscillator compatible with three ranges of input crystal or resonator frequencies: 32-40 kHz (low freq. mode), 3-8 MHz (high frequency mode, low range) and 8-32 MHz (high frequency mode, high range). The KL26Z128 on the FRDM-KL26Z is clocked from an 8 MHz crystal.5.3.2USB interfaceThe Kinetis KL26 microcontrollers feature a dual-role USB controller with on-chip full-speed andlow-speed transceivers. The USB interface on the FRDM-KL26Z is configured as a full-speed USB device. J6 is the USB connector for this interface.Figure7. USB connector schematicIn order to enable USB host functionality on the FRDM-KL26Z, it is necessary to populate J9 and R8 as shown in Figure7. However, there is no electrical protection provided. Use the USB host functionality at your own risk.FRDM-KL26Z hardware description 5.3.3Serial portThe primary serial port interface signals are PTA1 and PTA2. These signals are connected to both the OpenSDA and to the J1 I/O connector. Note that the OpenSDA connection can be isolated from J1 by removing R13 & R14, if required.5.3.4ResetThe PTA20/RESET signal on the KL26Z128 is connected externally to a pushbutton, SW2, and also to the OpenSDA circuit. However, J13 has been provided to isolate the OpenSDA MCU from SW2. Isolating the RESET line allows a more accurate measurement of the target device’s power consumption in low-power modes. The reset button can be used to force an external reset event in the target MCU. The reset button can also be used to force the OpenSDA circuit into bootloader mode. See Section5.2, “Serial and debug adapter (OpenSDA), for more details.5.3.5DebugThe sole debug interface on all Kinetis L Series devices is a serial wire debug (SWD) port. The primary controller of this interface on the FRDM-KL26Z is the onboard OpenSDA circuit (see Section5.2, “Serial and debug adapter (OpenSDA)). However, an unpopulated 10-pin (0.05”) Cortex Debug connector, J7, provides access to the SWD signals. The Samtec FTSH-105-02-F-D or compatible connector can be added to the J7 through-hole debug connector to allow for an external debug cable to be connected.5.4Capacitive touch sliderTwo Touch Sense Input (TSI) signals, TSI0_CH9 and TSI0_CH10, are connected to capacitive electrodes configured as a touch slider. Freescale’s Touch Sense Software (TSS) provides a software library for implementing the capacitive touch slider.5.56-axis accelerometer and magnetometerA Freescale FXOS8700CQ low-power, six-axis accelerometer and magnetometer is interfaced through an I2C bus and two GPIO signals as shown in Table4. By default, the I2C address is 0x1D (SA0 pulled high).Table4. Accelerometer signal connectionsFX0S8700CQ KL26Z128SCL PTE24SDA PTE25INT1PTD0INT2PTD1FRDM-KL26Z hardware descriptionFigure 8. FXOS8700CQ schematic diagram5.6RGB LEDThree PWM-capable signals are connected to a red, green, blue LED, D7. The signal connections are shown in Table 5.Table 5. RGB LED signal connectionsFigure 9. RGB LED schematic diagramRGB LEDKL26Z128Red cathodePTE29Green cathodePTE31Blue cathodePTD511PTD5 is also connected to the I/O header on J2 pin 10 (also known as D13).FRDM-KL26Z hardware description5.7Ambient light sensorAn ambient light sensor is connected to ADC0_SE3 (PTE22). This sensor may be isolated from PTE22 by removing R36.5.8Input/Output connectorsThe KL26Z128VLK4 microcontroller is packaged in a 64-pin LQFP. Some pins are utilized in on-board circuitry, but many are directly connected to one of four I/O headers.The pins on the KL26Z microcontroller are named for their general purpose input/output port pin function. For example, the 1st pin on Port A is referred to as PTA1. The I/O connector pin names are given the same name as the KL26Z pin connected to it, where applicable.FRDM-KL26Z hardware descriptionNote that all pinout data is available in spreadsheet format in FRDM-KL26Z Pinouts. See Section2, “Reference documents” for details.5.9Analog reference voltageThe onboard ADC of the KL26Z128VLH4 MCU uses the Reference V oltage High (VREFH) and Reference V oltage Low (VREFL) pins to set high and low voltage references for the analog modules. On the FRDM-KL26Z, by default VREFH is attached to P3V3_KL26Z (3.3V Supply). VREFL is connected to GND. Figure10 illustrates this circuitry.Figure10. FRDM-KL26Z VREFH circuit schematicIf desired, VREFH can use a VDDA independent reference by adding R11 and a Zener diode (D6). R10 (0 Ω resistor) must be removed when implementing this option. Alternatively, VREFH can be attached to an external source through AREF by removing R10 and populating R9 with a 0 Ω resistor.5.10Arduino compatibilityThe I/O headers on the FRDM-KL26Z are arranged to allow compatibility with peripheral boards (known as shields) that connect to Arduino™ and Arduino-compatible microcontroller boards. The outer rows of pins (the even numbered pins) on the headers share the same mechanical spacing and placement as the I/O headers on the Arduino Revision 3 (R3) standard.FRDM-KL26Z hardware descriptionRefer to the FRDM-KL26Z Pinouts spreadsheet for a compatibility chart showing how all the functions of the KL26Z signals on the I/O connectors map to the pin functions available on the Arduino Uno R3.Document Number:FRDMKL26ZUG Rev. 010/2013Information in this document is provided solely to enable system and software implementers to use Freescale products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document.Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others. Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: /SalesTermsandConditions.How to Reach Us:Home Page:Web Support:/supportFreescale, the Freescale logo, and Kinetis are trademarks of FreescaleSemiconductor, Inc., Reg. U.S. Pat. & Tm. Off. ARM is the registered trademark ofARM Limited. ARM Cortex-M0+ is the trademark of ARM Limited. All other product orservice names are the property of their respective owners.© 2013 Freescale Semiconductor, Inc.。

SCminisd使用技巧问答。

A：V5和V6的区别不大，区别就是在一些联网，和支持烧录卡的种类上有些区别而已，修正了些无关紧要的小错误，而且目前来说没有说V6比V5要更适合用SC烧录卡的说法，总的来说。刷了V5的人就没必要刷V6了，除非有V7的出现（看看那时候会出现什么新功能）.
Q:更新1.60内核后我进不了GBA模式拉。我玩的是NDS，还有怎么进BIOS啊？
SC卡新人FAQ问题大合集（0913）
Q：升级内核时候屏幕显示“Data verify error please turn off GBA"数据效验错误，就是文件没拷贝完全.
A:有几种原因造成:1 读卡器有问题造成部分数据丢失;
2 下载内核不完全，需重新下载。
Q: 如何查看SC的内核办版本?
A: 在开机的时候按Ｌ＋Ｒ，进入测试画面，在测试画面中按Ａ可进入下一项，在最后一项就可看到内核版本．
Q: 如何保存游戏存档？
A: ＧＢＡ绝大部分游戏都是需要存档的，ＳＣ卡没有电池设计，存档需要保存到ＣＦ卡上，所以在游戏中存完档后，需要按L+R+A+SELECT进入存档菜单，这样存档才会被保存到ＣＦ卡上，永不掉档，下次玩游戏时，存档会自动调入．
Q: 什么是即时存档？
A: 即时存档也有叫实时存档，英文名叫：Real Time Save，她是游戏玩家玩不过游戏时，特别梦寐以求的功能，特别是玩动作游戏的时候，水平一般的玩家老打不过ＢＯＳＳ，或游戏太难的时候的最佳利器，目前电脑上的ＧＢＡ模拟器都有这个功能，不用再等到玩到游戏存盘点才能存档，直接在任何时候都可以保存下当时的游戏状态，死了后再重来，或以后接着玩，所以香港等地叫＂无限复活＂.最早推出这个功能要追述到上世纪90年代，香港邦谷公司推出了著名的超任博士，极大扩展了当时雄霸游戏市场的超级任天堂的功能，加入了金手指，慢动作，即时存档（无限复活），等强大功能，我还记得当年的电视广告就是，超级玛莉在进行游戏中，一遇到难的地方，马用用慢动作功能，一但死掉，马上用即时存档功能来无限复活，呵呵，就象时光可以倒流一样，打不过，从刚才存的地方马上又重来，呵呵，没有玩不过的游戏啦．当然，还有一个重要的功能，就是ＧＢＡ的游戏存档格式，或掉档再也不会困扰大家了，想什么时候存盘就什么时候存盘，不会出现这种情况：＂老妈说：快睡觉啦＂，这边还没有找到游戏中存档的地方，结果被老妈强行关机，白玩啦，呵呵

SDIO协议规范

SDIO协议规范篇一：SDIO协议简介SDIO卡SDIO卡是在SD内存卡接口的基础上发展起来的接口，SDIO接口兼容以前的SD内存卡，并且可以连接SDIO接口的设备，目前根据SDIO协议的SPEC，SDIO接口支持的设备总类有蓝牙，网卡，电视卡等。

SDIO协议是由SD卡的协议演化升级而来的，很多地方保留了SD卡的读写协议，同时SDIO协议又在SD卡协议之上添加了CMD52和CMD53命令。

由于这个，SDIO和SD卡规范间的一个重要区别是增加了低速标准，低速卡的目标应用是以最小的硬件开始来支持低速I/O能力。

低速卡支持类似调制解调器,条形码扫描仪和GPS接收器等应用。

高速卡支持网卡，电视卡还有“组合”卡等，组合卡指的是存储器+SDIO。

SDIO和SD卡的SPEC间的又一个重要区别是增加了低速标准。

SDIO卡只需要SPI和1位SD传输模式。

低速卡的目标应用是以最小的硬件开支来支持低速I/O能力，低速卡支持类似MODEM，条形扫描仪和GPS接收器等应用。

对组合卡来说，全速和4BIT操作对卡内存储器和SDIO部分都是强制要求的。

在非组合卡的SDIO设备里，其最高速度要只有达到25M，而组合卡的最高速度同SD卡的最高速度一样，要高于25M。

SDIO总线SDIO总线和USB总线类似，SDIO总线也有两端，其中一端是主机（HOST）端，另一端是设备端（DEVICE），采用HOST-DEVICE这样的设计是为了简化DEVICE的设计，所有的通信都是由HOST端发出命令开始的。

在DEVICE端只要能解溪HOST 的命令，就可以同HOST进行通信了。

SDIO的HOST可以连接多个DEVICE，如下图所示:这个是同SD的总线一样的,其中有如下的几种信号1. CLK信号:HOST给DEVICE的时钟信号.2. CMD信号：双向的信号，用于传送命令和反应。

3. DAT0-DAT3 信号:四条用于传送的数据线。

4. VDD信号:电源信号。

PCI_Express_Mini_CEM_12_26Oct07_cb

PCI Express®Mini Card ElectromechanicalSpecificationRevision 1.21March 28October 26, 20075Revision RevisionHistory Daterelease. 6/02/031.0 Initial1.1 Incorporated approved Errata and ECNs. 3/28/051.2 Incorporated approved ECNs. 10/26/2007PCI-SIG disclaims all warranties and liability for the use of this document and the information contained herein and assumes no responsibility for any errors that may appear in this document, nor does the PCI-SIG make a commitment to update the information contained herein.Contact the PCI-SIG office to obtain the latest revision of the specification.Membership ServicesE-mail: administration@Phone: 503-619-0569Fax: 503-644-6708Technical Supporttechsupp@DISCLAIMERThis PCI Express Mini Card Electromechanical Specification is provided "as is" with nowarranties whatsoever, including any warranty of merchantability, noninfringement, fitnessfor any particular purpose, or any warranty otherwise arising out of any proposal,specification, or sample. PCI-SIG disclaims all liability for infringement of proprietaryrights, relating to use of information in this specification. No license, express or implied, byestoppel or otherwise, to any intellectual property rights is granted herein.PCI, PCI Express, PCIe, and PCI-SIG are trademarks or registered trademarks of PCI-SIG.All other product names are trademarks, registered trademarks, or service marks of their respective owners.Copyright © 2003, 2005,-05 2007 PCI-SIG2Contents1. INTRODUCTION (7)1.1. O VERVIEW (7)1.2. S PECIFICATION R EFERENCES (9)1.3. T ARGETED A PPLICATIONS (9)1.4. F EATURES AND B ENEFITS (10)2. MECHANICAL SPECIFICATION (11)2.1. O VERVIEW (11)2.2. C ARD S PECIFICATIONS (11)2.2.1.Card Form Factor (12)2.2.2.Card and Socket Types (13)2.2.3.Card PCB Details (14)2.3. S YSTEM C ONNECTOR S PECIFICATIONS (23)2.3.1.System Connector (23)2.3.2.System Connector Parametric Specifications (27)C ONNECTOR A REA (28)2.4. I/O2.5. R ECOMMENDED S OCKET C ONFIGURATIONS (29)2.5.1.Single Use Full-Mini and Half-Mini Sockets (29)2.5.2.Dual-Use Sockets (32)2.5.3.Dual Head-to-Head Sockets (35)2.5.4.Side-by-Side Socket Spacing (37)2.6. T HERMAL G UIDELINES (38)2.6.1.Thermal Design Definitions (38)2.6.2.Thermal Guidelines for PCI Express Mini Card Add-in Card Designers (39)2.6.2.1. Implementation Considerations (40)2.6.3.Thermal Guidelines for Integrating Wireless Wide Area Network Mini Card Add-inCards (41)3. ELECTRICAL SPECIFICATIONS (45)3.1. O VERVIEW (45)3.2. S YSTEM I NTERFACE S IGNALS (45)3.2.1.Power Sources and Grounds (47)3.2.2.PCI Express Interface (47)B Interface (48)3.2.4.Auxiliary Signals (48)3.2.4.1. Reference Clock (48)3.2.4.2. CLKREQ# Signal (48)3.2.4.3. PERST# Signal (52)3.2.4.4. WAKE# Signal (52)3.2.4.5. SMBus (52)munications Specific Signals (53)3.2.5.1. Status Indicators (53)3.2.5.2. W_DISABLE# Signal (54)3er Identity Module (UIM) Interface (55)3.2.6.1. UIM_PWR (55)3.2.6.2. UIM_RESET (56)3.2.6.3. UIM_CLK (56)3.2.6.4. UIM_VPP (56)3.2.6.5. UIM_DATA (56)3.3. C ONNECTOR P IN-OUT D EFINITIONS (57)3.3.1.Grounds (58)3.3.2.Coexistence Pins (58)3.3.3.Reserved Pins (58)3.4. E LECTRICAL R EQUIREMENTS (58)3.4.1.Logic Signal Requirements (58)3.4.2.Digital Interfaces (59)3.4.3.Power (62)3.5. C ARD E NUMERATION (62)A. SUPPLEMENTAL GUIDELINES FOR PCI EXPRESS MINI CARD CONNECTORTESTING (63)A.1. T EST B OARDS A SSEMBLY (63)A.1.1.Base Board Assembly (64)A.1.2.Plug-in Cards Assembly (65)A.2. I NSERTION L OSS M EASUREMENT (66)A.3. R ETURN L OSS M EASUREMENT (66)A.4. N EAR E ND C ROSSTALK M EASUREMENT (66)B. I/O CONNECTOR GUIDELINES (69)B.1. W IRE-LINE M ODEMS (69)B.2. IEEE 802.3 W IRED E THERNET (69)W IRELESS E THERNET (69)B.3. IEEE802.114FiguresF IGURE 1-1: PCI E XPRESS M INI C ARD A DD-IN C ARD I NSTALLED IN A M OBILE P LATFORM (8)F IGURE 1-2: L OGICAL R EPRESENTATION OF THE PCI E XPRESS M INI C ARD S PECIFICATION (8)F IGURE 2-1: F ULL-M INI C ARD F ORM F ACTOR (M ODEM E XAMPLE A PPLICATION S HOWN) (12)F IGURE 2-2: H ALF-M INI C ARD F ORM F ACTOR (W IRELESS E XAMPLE A PPLICATION S HOWN) (13)F IGURE 2-3: F ULL-M INI C ARD T OP AND B OTTOM (15)F IGURE 2-4: H ALF-M INI C ARD T OP AND B OTTOM (16)F IGURE 2-5: C ARD T OP AND B OTTOM D ETAILS A AND B (17)F IGURE 2-6: C ARD E DGE (19)F IGURE 2-7: C ARD C OMPONENT K EEP O UT A REAS FOR F ULL-M INI C ARDS (21)F IGURE 2-8: C ARD C OMPONENT K EEP O UT A REAS FOR H ALF-M INI C ARDS (22)F IGURE 2-9: PCI E XPRESS M INI C ARD S YSTEM C ONNECTOR (23)F IGURE 2-13: I/O C ONNECTOR L OCATION A REAS (29)F IGURE 2-14: R ECOMMENDED S YSTEM B OARD L AYOUT FOR F ULL-M INI-O NLY S OCKET (30)F IGURE 2-15: R ECOMMENDED S YSTEM B OARD L AYOUT FOR H ALF-M INI-O NLY S OCKET (31)F IGURE 2-16: R ECOMMENDED S YSTEM B OARD L AYOUT (D ETAIL D) (32)F IGURE 2-17: D UAL-U SE S OCKET (33)F IGURE 2-18: R ECOMMENDED S YSTEM B OARD L AYOUT FOR D UAL-U SE S OCKET (34)F IGURE 2-19: D UAL H EAD-TO-H EAD S OCKET (36)F IGURE 2-20: R ECOMMENDED S YSTEM B OARD L AYOUT FOR D UAL H EAD-TO-H EAD S OCKETS (37)F IGURE 2-21: R ECOMMENDED S YSTEM B OARD L AYOUT (S IDE-BY-S IDE S PACING) (38)F IGURE 2-22: P OWER D ENSITY U NIFORM L OADING AT 80 P ERCENT C OVERAGE (40)F IGURE 3-1: P OWER-U P CLKREQ# T IMING (50)F IGURE 3-2: CLKREQ# C LOCK C ONTROL T IMINGS (51)TablesT ABLE 2-1: C ARD AND S OCKET T YPES C ROSS-C OMPATIBILITY (14)T ABLE 2-2: S YSTEM C ONNECTOR P HYSICAL R EQUIREMENTS (27)T ABLE 2-4: S YSTEM C ONNECTOR M ECHANICAL P ERFORMANCE R EQUIREMENTS (27)T ABLE 2-6: S YSTEM C ONNECTOR E LECTRICAL P ERFORMANCE R EQUIREMENTS (28)T ABLE 2-8: S YSTEM C ONNECTOR E NVIRONMENTAL P ERFORMANCE R EQUIREMENTS (28)T ABLE 2-10: M AXIMUM TDP (41)T ABLE 3-1: PCI E XPRESS M INI C ARD S YSTEM I NTERFACE S IGNALS (45)T ABLE 3-3: P OWER-U P CLKREQ# T IMINGS (50)T ABLE 3-5: CLKREQ# C LOCK C ONTROL T IMINGS (51)T ABLE 3-7: S IMPLE I NDICATOR P ROTOCOL FOR LED S TATES (53)T ABLE 3-10: R ADIO O PERATIONAL S TATES (55)T ABLE 3-11: S YSTEM C ONNECTOR P IN-OUT (57)T ABLE 3-13: DC S PECIFICATION FOR 3.3V L OGIC S IGNALING (59)T ABLE 3-14: S IGNAL I NTEGRITY R EQUIREMENTS AND T EST P ROCEDURES (60)T ABLE 3-16: P OWER R ATINGS (62)5611. Introduction1.1. OverviewThis specification defines an implementation for small form factor PCI Express cards. Thespecification uses a qualified sub-set of the same signal protocol, electrical definitions, andconfiguration definitions as the PCI Express Base Specification, Revision 1.0a1.1. Where this5specification does not explicitly define PCI Express characteristics, the PCI Express Base Specification governs.The primary differences between a PCI Express add-in card (as defined by the PCI Express Card Electromechanical Specification) and a PCI Express Mini Card add-in card is a unique card form factoroptimized for mobile computing platforms and a card-system interconnection optimized for10communication applications. Specifically, PCI Express Mini Card add-in cards are smaller and have smaller connectors than standard PCI Express add-in cards.Figure 1-1 shows a conceptual drawing of this form factor as it may be installed in a mobileplatform. Figure 1-1 does not reflect the actual dimensions and physical characteristics as thosedetails are specified elsewhere in this specification. However, it is representative of the general15concept of this specification to use a single system connector to support all necessary systeminterfaces by means of a common edge connector. Communications media interfaces may beprovided via separate I/O connectors and RF connectors each with independent cables as illustrated in Figure 1-1.78A-0381Figure 1-1: PCI Express Mini Card Add-in Card Installed in a Mobile Platform PCI Express Mini Card supports two primary system bus interfaces: PCI Express and USB as shown in Figure 1-2.S y s t e m B u s e s A-0339A PCI Express Mini CardModemEthernet WirelessSystem Interface Function I/O InterfaceFigure 1-2: Logical Representation of the PCI Express Mini Card Specification1.2. SpecificationReferencesThis specification requires references to other specifications or documents that will form the basis for some of the requirements stated herein.PCI Express Base Specification, Revision 1.0a1.1PCI Express Card Electromechanical Specification, Revision 1.0a1.15PCI Local Bus Specification, Revision 2.3Mini PCI Specification, Revision 1.0PCI Bus Power Management Interface Specification, Revision 1.11.2Advanced Configuration and Power Interface Specification, Revision 2.0bUniversal Serial Bus Specification, Revision 2.010SMBus Specification, Revision 2.0EIA-364-1000.01: Environmental Test Methodology for Assessing the Performance of Electrical Connectors and Sockets Used in Business Office ApplicationsEIA-364: Electrical Connector/Socket Test Procedures Including Environmental ClassificationsIS0/IEC 7816-2, 19992007-3-1, Information Technology - I I dentification Cards – -Integrated Circuit(s)15Cards – Part 2: Cards with Contacts – - Part 2: Dimensions and Location of the ContactsISO/IEC 7816-3, 1997-12-15, Second Addition, Information Technology - Identification Cards - IntegratedCircuit(s) Cards With Contacts - Part 3: Electronic Signals and Transmission Protocols IS0/IEC 7816-3, 2006, Identification Cards – Integrated Circuit Cards – Part 3: Cards with Contacts –Electrical Interface and Transmission Protocols ISO/IEC 7816-3, Amendment 1 2002-06-01, Amendment 1: 20Electrical Characteristics and Class Indication for Integrated Circuit(s) Cards Operating at 5 V, 3 V and 1,8VApplications1.3. TargetedAlthough the PCI Express Mini Card is originally intended for both wired and wirelesscommunication applications, it is not limited to such applications. Communications-specific25applications may include:Wired data communication:Local Area Network (LAN): 10/100/1000 Mbps EthernetWide Area Network (WAN): V.90/V.92 modemWireless data communication:30Wireless-LAN (W-LAN): 802.11b/g/a (2.4 GHz and 5.2 GHz bands)Wireless-WAN (W-WAN): Cellular data (e.g., GSM/GPRS, UMTS, and CDMA-2000)Wireless-Personal Area Network (W-PAN): Bluetooth9PCI Express Mini Card is targeted toward addressing system manufacturers’ needs for build-to-order and configure-to-order rather than providing a general end-user-replaceable module. Inspecific applications such as wireless, there are worldwide regulatory implications in providing end-user access to items such as antenna connections and frequency-determining components. It is up to the system manufacturer to limit access to appropriate trained service personnel and provide such 5notification to the user.Although not specifically considered, other applications that may also find their way to this form factor include advanced wired WAN technologies (xDSL and cable modem), location services using GPS, and audio functions.1.4. Features and Benefits10The performance characteristics of PCI Express make PCI Express Mini Card add-in cards desirable in a wide range of mobile systems. This mobile computer optimized form factor provides a number of benefits, including:Upgradeability – PCI Express Mini Card add-in cards are removable and upgradeable withavailable “new technology” cards. This allows upgrades to the newest technologies. System15manufacturers are responsible for providing sufficient notification in the accompanying manualwhen a qualified technician should perform the upgrade service.Flexibility – A single PCI Express Mini Card interface can accommodate various types of communications devices. Therefore, the OEM manufacturer can supply build-to-order systems(for example, a network interface card instead of a modem or Token Ring instead of Ethernet).20Reduced Cost – A standard form factor for small form factor add-in cards makes them more manufacturable, which may lead to reduced costs and provide an economy-of-scale advantageover custom manufactured form factors.Serviceability – PCI Express Mini Card add-in cards can be removed and easily serviced if theyfail.25Reliability – PCI Express Mini Card add-in cards will be mass-produced cards with higher quality than low-volume custom boards.Software Compatibility – PCI Express Mini Card add-in cards are intended to be fully compatible with software drivers and applications that will be developed for standard PCIExpress add-in cards.30Reduced Size – PCI Express Mini Card add-in cards are smaller than PC Cards, PCI Express add-in cards, Mini PCI add-in cards, and other add-in card form factors. This reduced sizepermits a higher level of integration of data communications devices into notebook PCs.Regulatory Agency Accepted Form Factor – Standardization of the PCI Express Mini Cardform factor will permit world wide regulatory agencies to approve PCI Express Mini Card35communications devices independent of the system. This significantly reduces cost and risk onthe part of systems manufacturers.Power Management – PCI Express Mini Card is designed to be truly mobile friendly for current and future mobile specific power management features.1022. MechanicalSpecification2.1. OverviewThis specification defines a two small form factor card s for systems in which a PCI Express add-in card cannot be used due to mechanical system design constraints. The specification defines asmaller card s based on a single 52-pin card-edge type connector for system interfaces. The5specification also defines the PCI Express Mini Card system board connector. In this document Mini Card refers to either form-factor. As the two form-factors primarily differ in length, they will be individually identified as the Full-Mini Card and the Half-Mini Card for the full length and half-length versions of the cards, respectively.2.2. CardSpecifications10There is one are two PCI Express Mini Card add-in card size s: Full-Mini Card and Half-Mini Card.For purposes of the drawings in this specification, the following notes apply:All dimensions are in millimeters, unless otherwise specified.All dimension tolerances are ± 0.15 mm, unless otherwise specified.Dimensions marked with an asterisk (*) are overall envelope dimensions and include space15allowances for insulation to comply with regulatory and safety requirements.Insulating material shall not interfere with or obstruct mounting holes or grounding pads.2.2.1. Card Form FactorThe card form factor s is are specified by Figure 2-1 and Figure 2-2. The se figure s illustrate s amodem example application s . The hatched area s shown in this these figure s represent s the available component volume for the card’s circuitry.A-03405.00 REFPIN 1Figure 2-1: Full-Mini Card Form Factor (Modem Example Application Shown)A-07295.00 REFFigure 2-2: Half-Mini Card Form Factor (Wireless Example Application Shown)2.2.2. Card and Socket TypesGiven the multiple card sizes defined for Mini Card, host platforms have options with regard to socket configurations implemented to support each of the card sizes and potentially the mixing of the two card sizes within a common socket arrangement.Single socket arrangements include those specific to Full-Mini Card (F1) and Half-Mini Card (H1) 5only usages. These sockets specifically have the card retention features for only one size card and are further defined in Section 2.5.1.Additionally, a single socket that optionally supports either a Full-Mini Card (F2) or a Half-Mini Card (H1 or H2) is possible to implement, this type being referred to as a dual-use socket and supports card retention for both size cards. See Section 2.5.2 for more details on this socket 10definition.A dual head-to-head socket is defined as an optional way to incorporate two socket connectors (identified as A and B) into a space that most closely replaces a single Full-Mini socket. Thisarrangement offers the choice of installing two Half-Mini Cards (one of which has to be a H2 type) or one Full-Mini Card (F2) enabling some additional flexibility for a selection of BTO options. See 15Section 2.5.3for more details on this socket definition.Table 2-1 defines cross-compatibility for a series of defined card and socket types. It is important to notice that the dual head-to-head socket arrangement has special limitations with regard to card compatibility.Table 2-1: Card and Socket Types Cross-CompatibilityFull-Mini-Only Socket* Half-Mini-OnlySocketDual-UseSocketDual Head-to-Head SocketCard TypesConnectorA ConnectorAConnectorAConnectorAConnectorBF1 Full-Mini1Yes No No No NoF2 Full-Mini withbottom-sidekeep outsYes No Yes Yes NoH1 Half-Mini No Yes Yes Yes NoH2 Half-Mini withbottom-sidekeep outsNo Yes Yes Yes Yes* Equivalent to the original Mini Card defined card and socket in Revision 1.1 of this specification.Mini Cards that were developed prior to this type definition are by default identified as Type F1.Given that the existing design meets the bottom-side keep out definition for Type F2, thensubsequently identifying the product as Type F2 is acceptable.2.2.2.2.2.3. Card PCB Details5Figure 2-3, Figure 2-4Figure 2-3, Figure 2-5Figure 2-4, and Figure 2-6Figure 2-5 provide the printed circuit board (PCB) details required to fabricate the card. The PCB for this application is expected to be 1.0 mm thick.A-0341A+0.2x R 0.80 M A XP i n n u m b e r i n g r e f e r e n c e :O d d p i n s – T o p S i d e E v e n p i n s – B o t t o m S i d eM A B C0.10x 2.15 R E F I NFigure 2-3: Full-Mini Card Top and BottomA-0728+0.2x R 0.80 M A XP i n n u m b e r i n g r e f e r e n c e :O d d p i n s – T o p S i d e E v e n p i n s – B o t t o m S i d eM A B C0.10x 2.15 R E F I NFigure 2-4: Half-Mini Card Top and BottomA-0342AD e t a i l B (B o t t o m S i d e )(T o p S i d e ).054.0Figure 2-5: Card Top and Bottom Details A and B1.35 MAXA-0343AA-0343BFigure 2-6: Card EdgeFigure 2-7and Figure 2-8 provide details regarding the component keep out areas on Full-Mini (Types F1 and F2) and Half-Mini Cards (Types H1 and H2), respectively.Component and routing (all layers)keep out area for hold down solutionsA-0344AA-0727B o t t o m S i d e (T y p e F 1)B o t t o m S i d e (T y p e F 2)2x 5.80C o m p o n e n t a n d r o u t i n g (a l l l a y e r s )k e e p o u t a r e a f o r h o l d d ow n s o l u t i o n s5T o p S i d e (T y p e s F 1 a n d F 2)4x 5.80Figure 2-7: Card Component Keep Out Areas for Full-Mini CardsA-0730B o t t o m S i d e (T y p e H 1)B o t t o m S i d e (T y p e H 2)2x 5.80C o m p o n e n t a n d r o u t i n g (a l l l a y e r s )T o p S i d e (T y p e s H 1 a n d H 2)Figure 2-8: Card Component Keep Out Areas for Half-Mini Cards2.3. System Connector SpecificationsThe PCI Express Mini Card system connector is similar to the SO-DIMM connector and is modeledafter the Mini PCI Type III connector without side retaining clips.Note: All dimensions are in millimeters, unless otherwise specified. All dimension tolerances are ± 0.15 mm, unless otherwise specified.5Connector2.3.1. SystemThe system connector is 52-pin card edge type connector. Detailed dimensions should be obtained from the connector manufacturer. Figure 2-9 shows the system connector. Figure 2-7, Figure 2-8, and Figure 2-9 show the recommended locations of the PCI Express Mini Card system connectoron the system board.10A-0345AFigure 2-9: PCI Express Mini Card System ConnectorA-0346AThe horizontal axis for the pattern is established by a line through the center of the Ø 1.60 and Ø 1.10holes. The vertical axis is 90˚ to the horizontal axis, through the center of datum E.Location of inserted card edge is aligned with of holes.Figure 2-7: Recommended System Board Layout (Single Socket)7 spacesA-0347 Figure 2-8: Recommended System Board Layout (Detail D)A-0348 Figure 2-9: Recommended System Board Layout (Dual Socket)2.3.2. SystemConnectorParametric SpecificationsTable 2-2, Table 2-4, Table 2-6, and Table 2-8 specify the requirements for physical, mechanical, electrical, and environmental performance for the system connector.Table 2-22-1: System Connector Physical RequirementsParameter SpecificationConnector Housing U.L. rated 94-V-1 (minimum) Must be compatible with lead-free soldering processContacts: Receptacle Copper alloyContact Finish: Receptacle Must be compatible with lead-free soldering processTable 2-42-2: System Connector Mechanical Performance RequirementsParameter SpecificationDurability EIA-364-9 50 cyclesTotal mating/unmating force* EIA-364-132.3 kgf maximumShock EIA-364-27, Test condition AAdd to EIA-364-1000 test group 3 with LLCR before vibration sequence.Note: Shock specifications assume that an effective card retention feature is used.* Card mating/unmating sequence:1. Insert the card at the angle specified by the manufacturer.2. Rotate the card into position.3. Reverse the installation sequence to unmate.Table 2-62-3: System Connector Electrical Performance RequirementsParameter SpecificationLow Level Contact Resistance EIA-364-2355 milliohms mΩmaximum (initial) per contact;20 mΩmilliohms maximum change allowedInsulation Resistance EIA-364-21> 5 x 108 @ 500 V DCDielectric Withstanding Voltage EIA-364-20> 300 V AC (RMS) @ sea levelCurrent Rating 0.50 amp A/power contact (continuous) The temperature rise above ambient shall not exceed 30 °C. The ambient condition is still air at 25 °C.EIA-364-70 method 2Voltage Rating 50 V AC per contactTable 2-82-4: System Connector Environmental Performance RequirementsParameter Specification Operating Temperature -40 °C to +80 °CEnvironmental Test Methodology EIA-364-1000.01Test Group, 1, 2, 3, and 4Useful Field Life 5 yearsTo ensure that the environmental tests measure the stability of the connector, the add-in cards used shall have edge finger tabs with a minimum plating thickness of 30 micro-inches of gold over50 micro-inches of nickel (for environmental test purposes only). Furthermore, it is highly desirablethat testing gives an indication of the stability of the connector when add-in cards at the lower and 5upper limit of the card thickness requirement are used. In any case, both the edge tab platingthickness and the card thickness shall be recorded in the environmental test report.2.3.3.2.4. I/O Connector AreaThe placement of I/O connectors on a PCI Express Mini Card add-in card is recommended to be atthe end opposite of the system connector as shown in Figure 2-13. The recommended area applies 10to both sides of the card, though typical placement will be on the top of the card due to theadditional height available. Depending on the application, one or more connectors may be required to provide for cabled access between the card and media interfaces such as LAN and modem line interfaces and/or RF antennas. This area is not restricted to I/O connectors only and can be usedfor circuitry if not needed for connectors.15A-0349A-0349AFigure 2-13: I/O Connector Location Areas2.5. Recommended Socket ConfigurationsThe following subsections address various recommended footprints for the system connector covering single-use sockets, dual-use sockets and multi-socket configurations.2.5.1. Single Use Full-Mini and Half-Mini SocketsFigure 2-14, Figure 2-15, and Figure 2-16 show the recommended system board layouts for single-5use sockets.A-0346AThe horizontal axis for the pattern is established by a line through the center of the Ø 1.60 and Ø 1.10holes. The vertical axis is 90˚ to the horizontal axis, through the center of datum E.Location of inserted card edge is aligned with of holes.Figure 2-14: Recommended System Board Layout for Full-Mini-Only SocketA-0731The horizontal axis for the pattern is established by a line through the center of the Ø 1.60 and Ø 1.10holes. The vertical axis is 90˚ to the horizontal axis, through the center of datum E.Location of inserted card edge is aligned with of holes.Figure 2-15: Recommended System Board Layout for Half-Mini-Only SocketA-03477 spacesFigure 2-16: Recommended System Board Layout (Detail D)2.5.2. Dual-Use SocketsFigure 2-17 illustrates the concept of a dual-use socket that can accept either a Full-Mini Card or a Half-Mini Card. This socket differs from the Full-Mini-only socket in that consideration is given to support hold down support for the installation of a Half-Mini Card into the same socket. All Mini Cards with the exception of the Type F1 Full-Mini Card are compatible with this socket. 5Figure 2-18 shows the recommended system board layout for the dual-use socket.A-0725H a l f -M i n i C a r d i n s t a l l e dD u a l -U s e S o c k e t w i t h n o M i n i C a r d s i n s t a l l e dF u l l -M i n i C a r d i n s t a l l e dC o n n e c t o r AC o n n e c t o r AFigure 2-17: Dual-Use SocketA-0726The horizontal axis for the pattern is established by a line through the center of the Ø 1.60 and Ø 1.10holes. The vertical axis is 90˚ to the horizontal axis, through the center of datum E.Location of inserted card edge is aligned with of holes.Figure 2-18: Recommended System Board Layout for Dual-Use Socket2.5.3. Dual Head-to-Head SocketsFigure 2-19 illustrates the concept of a dual head-to-head socket configuration. This optionalconfiguration defines a two connector (A and B) solution that is intended to allow installation foreither one Full-Mini Card or two Half-Mini Cards. Figure 2-20shows the recommended system board layout for this configuration based on overlaying the defined dual-use and Half-Mini-only5sockets (see Figure 2-15 and Figure 2-18 for additional dimensional details).It is important to note the limitations regarding card compatibility with this socket configuration.Connector A can accept all but the Type F1 Full-Mini Card. Connector B can only accept Type H2 Half-Mini Cards. When using two Half-Mini Cards in this configuration, care must be taken that atleast one of those cards be Type H2.10A-0724T w o H a l f -M i n i C a r d s i n s t a l l e dD u a l H e a d -t o -H e a d S o c k e t w i t h n o M i n i C a r d s i n s t a l l e dO n e F u l l -M i n i C a r d i n s t a l l e dC o n n e c t o r B (o n l y c o m p a t i b l e w i t h H 2 c a r d s )C o n n e c t o r AC o n n e c t o r AC o n n e c t o r B (o n l y c o m p a t i b l e w i t h H 2 c a r d s )C o n n e c t o r B (u n u s e d )Figure 2-19: Dual Head-to-Head Socket。

ISD-DEMO2360微控制器基础系统设计指南说明书

ISD-DEMO2360 User ManualThe information contained in this document is the exclusive intellectual property of Nuvoton Technology Corporation and shall not be reproduced without permission from Nuvoton.Nuvoton provides this document for reference purposes only in the design of ISD ChipCorder®microcontroller-based systems. Nuvoton assumes no responsibility for errors or omissions.All data and specifications are subject to change without notice.For additional information, please contact: Nuvoton Technology Corporation atPublication Release Date: Apr 13, 2016Contents1. Overview (3)2. Board Description (5)2.1. ISD-DEMO2360_QFN32 for QFN32 package (5)2.1.1. ISD-DEMO2360_QFN32 Jumper Description (5)2.2. ISD-DEMO2360_SOP16 for SOP16 package (6)2.2.1. ISD-DEMO2360_SOP16 Jumper Description (6)2.3. 2x5 connector pin assignment (7)3. Operation Description (7)3.1. Software Installation (7)3.2. Operation under VPE (8)4. ISD-DEMO2360 board schematic (10)4.1. ISD-DEMO2360_QFN32 schematic (10)4.2. ISD-DEMO2360_SOP16 schematic (11)5. Appendix: ISD-VPE Video Tutorial (12)6. Revision History (13)Publication Release Date: Apr 13, 20161.OverviewThe ISD2360 demo board is a small board dedicated for ISD2360 device evaluation andapplication development. The ISD2360 comes in two packages: QFN32 and SOP16, hence there are two types of demo boards for the ISD2360.-For QFN32 package: ISD-DEMO2360_QFN32 – shown in Picture 1-1 ISD-DEMO2360_QFN32-For SOP16 package: ISD-DEMO2360_SOP16 – shown in Picture 1-2Picture 1-1 ISD-DEMO2360_QFN32Picture 1-2 ISD-DEMO2360_SOPPublication Release Date: Apr 13, 2016The ISD2360 evaluation kit consists of three parts:-ISD-DEMO2360 (QFN or SOP)-ISD-ES_MINI_USB: a small interface board providing USB connection to PC-ISD-VPE2360: free downloadable GUI evaluation software for ISD2360.The ISD2360 demo board connecting to the ISD-ES_MINI_USB board, along with the ISD-VPE2360, makes up a small but complete evaluation system for ISD2360, as shown in Picture 1-3 A complete ISD2360 evaluation system.Picture 1-3 A complete ISD2360 evaluation systemPublication Release Date: Apr 13, 20162.Board Description2.1.ISD-DEMO2360_QFN32 for QFN32 package2.1.1.ISD-DEMO2360_QFN32 Jumper DescriptionJ1 – 2-pin power connector, to connect battery pack or external power supply J2 – 2-pin speaker connector directly connecting to ISD2360 PWM outputJ3 – Audio jack directly connecting to ISD2360 PWM outputJ4 – 2x5 10-pin connector connecting to ISD-ES_MINI_USB donglePublication Release Date: Apr 13, 2016J5 – Reserved, not to be used.2.2.ISD-DEMO2360_SOP16 for SOP16 package2.2.1.ISD-DEMO2360_SOP16 Jumper DescriptionJ2 – 2x5 10-pin connector connecting to ISD-ES_MINI_USB dongleJ3 – Audio jack directly connecting to ISD2360 PWM outputJ4 – 2-pin speaker connector directly connecting to ISD2360 PWM outputJ7 – Reserved, not to be used.J8 – 2-pin power connector, to connect battery pack or external power supplyPublication Release Date: Apr 13, 20162.3.2x5 connector pin assignmentThe ISD2360 demo board can be connected to ISD USB dongle via a 2x5 10-pinconnector. Table 2-1 shows the pin assignment.3.Operation Description3.1.Software InstallationSoftware DownloadThe ISD2360 user can use ISD-VPE2360 (VPE stands for Voice Prompt Editor) GUIsoftware to control the demo board, and fully evaluate the ISD2360 device.The ISD-VPE2360 software is freely downloaded from Nuvoton website, or from the link below:https:///FS/v.aspx?v=8a6e688761676eb6a4ad.During the software installation, user will be prompted for username and password. The user should email Nuvoton ChipCorder team at **********************, to requestPublication Release Date: Apr 13, 2016the username and password. In the email user should provide the detailed companyname and company address, city, including country name if outside of US. Thisinformation is required by Nuvoton to generate the username and password and tocontact the user for future software updates.System RequirementsThe ISD-VPE2360 is PC windows application software; it currently supports Windows XP, Windows 7- 32bit, and Windows 7- 64bit.3.2.Operation under VPEThe user can follow the sequence below to launch the ISD2360 VPE and start evaluating the ISD2360 chip functionality with the ISD-DEMO2360 board.-Connect a demo board to USB dongle-Plug in USB dongle into a PC USB port-Launch VPETo connect demo board with the USB dongle, both board need to face up for the connection.Please refer to Picture 3.2-1Demo board connects to USB dongle board with both boardsfacing up below.Publication Release Date: Apr 13, 2016Picture 3.2-1 Demo board connects to USB dongle board with both boards facing upPublication Release Date: Apr 13, 20164.ISD-DEMO2360 board schematic 4.1.ISD-DEMO2360_QFN32 schematicPublication Release Date: Apr 13, 20164.2.ISD-DEMO2360_SOP16 schematicPublication Release Date: Apr 13, 20165.Appendix: ISD-VPE Video TutorialThere are ISD-VPE video tutorials available online which can help users who are new to the ISD-VPE GUI software. Users can access these video tutorials using the web links below:o A Simple VPE project: https:///watch?v=BXTa7Kaux0oo A GPIO Trigger project: https:///watch?v=XVDcPGpHtkIo Record and playback project: https:///watch?v=o-L-6L3TXvcPublication Release Date: Apr 13, 20166.Revision HistoryPublication Release Date: Apr 13, 2016。

Atmel SMART SAMA5D4系列720p硬件视频解码器和高级安全密钥应用说明书

Key Applications• Control panels for security, home automation, thermostats, etc.• Surveillance cameras• Industrial human-machine interface (HMI)• Fitness equipment, such as treadmills and exercise machines • Industrial and residential gateways •Smart grid infrastructureThe new Atmel ® | SMART SAMA5D4 series, expands the SAMA5 microprocessors family and targets IoT, Industrial and Consumer applications. It is ARM ® Cortex ®-A5-based, and adds a 720p resolution hardware video decoder and advanced security features. The chip has significantly better system performance using the ARM NEON ™ 128-bit SIMD (single instruction, multiple data) architecture extension and a 128kByte L2 Cache. The IC has advanced security features to protect the application software from counterfeiting, to safeguard software assets, and to securely store and transfer data.Key Highlights720p 30fps Video PlaybackThe SAMA5D4 series enables you to bring up to 720p 30fps video playback to your user interface applications using theembedded hardware video decoder that supports H264, VP8, MPEG4, and JPEG. This is complemented by an integrated TFT LCD display controller and resistive touchscreen interface.High-performance ArchitectureBased on the ARM Cortex-A5 core with the ARM NEON SIMD engine, the SAMA5D4 series is ideal for applications requiring high-precision computing and fast signal processing. This series of microprocessors delivers 945DMIPS at 600MHz and a 128kB of L2 cache improves the overall system performance. The SAMA5D4 also features a 32-bit wide DDR controller running up to 200MHz that can deliver up to 1408MB/s of bandwidth. It is configurable in either a 16- or 32-bit bus interface allowing you an optimum trade-off between performance and memory cost.Advanced SecurityThe SAMA5D4 series security features prevent cloning of your application, protects and authenticates software, and securely stores and transfer data. It allows unique on-the-fly encryption and decryption of software code from the external DRAM, and includes secure boot, tamper detection pins, and safe erasure of security-critical data. The part features the ARM TrustZone ® system-wide approach to security as well as advanced hardware encryption engines supporting private and public key cryptography.Lifetime CommitmentAtmel offers customers a 12-years lifetime commitment from the time of this product’s introduction.Memory Connectivity User Interface User Interface System SecurityControl User Interface42-ch DMADDR2, LPDDR, LPDDR2Controller 3 HS/FS/LS USB ports 3 Host or 2 Host +1 Device2 EMAC 10/100w/ IEEE15882 HS SDIO/SD/MMC 8 UART, 8 SPI ,4 TWI, Soft modemTFT LCD Controller with Overlays720p Video Decoder Camera Interface,2 I2SResistive TouchscreenController2 RC OSC, 2 xtal OSC, 2 PLL, Voltage Regulator Watchdog, POR, RTC Backup unit with8 kb SRAMRSA, ECC co-processor 3DES, AES, SHA, TRNGOn the fly DDR Encryption/Decryption 8x Tamper Pins, Secure Boot5-ch 10-bit ADC 4 x 16-bit PWM 9 x 32-bit Timers152 IOsSLC/MLC NAND Controllerwith 24-bit ECC External Bus Interface128 kb SRAM BootROM 512 Fuse Bits64-bit AXI/AHBCortex ®-A5SAMA5D4600 MHz2x32 kb L1 Cache 128 kb L2 CacheAtmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T : (+1)(408) 441. 0311 F : (+1)(408) 436. 4200 | © 2015 Atmel Corporation. / Rev.: Atmel-45090B-SAMA5D4_E_US_092015Atmel,® Atmel logo and combinations thereof, Enabling Unlimited Possibilities,® and others are registered trademarks or trademarks of Atmel Corporation in U. S. and other countries. ARM,® ARM Connected ® logo and others are the registered trademarks or trademarks of ARM Ltd. Other terms and product names may be trademarks of others.Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RE-LATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shallnot be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.EcosystemAtmel has created and supports a free Linux ® distributions available at and https:///linux4sam . With our commitment to the Linux open-source community, we provide full coverage of SoC peripherals in the Linux kernel as well as bootloaders such as AT91Bootstrap and U-Boot.Atmel offers a free graphics software development kit (SDK) based on Qt available at . This SDK includes demos, widgets, backgound images, a set of icons, and useful graphical elements. Using these proven elements, you can develop your own customized user interface.Atmel is now offering a free Android ™ port for the SAMA5D devices, available at /android4sam . Originally developed for mobile handset devices, Android is ideal for use in embedded applications such as control panels, smart watches, DECT phones, and more. Android comes with multimedia and connectivity stacks, graphical user interfaces and a comprehensive SDK.For RTOS, bare metal C or C++ designers, Atmel delivers the softpack, a set of around 40 C drivers that run on the SAMA5D4 evaluation kits and exercises all peripherals. The softpack is also very useful for board bring up as well asquick prototyping and available for download from the product page on the Atmel web site.All devices are -40°C to +85°C temperature range.* Security: On the fly encryption/decryption of DRAM, secure boot, tamper detection pins, secure key storage, ARM Trust Zone, hardware cryptography engines RSA, ECC, AES, 3DES as well as SHA and TRNGTo evaluate and prototype your application, Atmel provides a low cost evaluation kit. To ease your design process and reduce your time-to-market, Atmel collaborates with a global and expanding network of partners that deliver hardware, PMIC, memories, SOM (system-on-module), and software solution for the SAMA5D4 series of MPUs. For more information on our partners and the Atmel evaluation kit, you can visit /microsite/SAMA5SAMA5D4 Series Selector GuideFor more information on the SAMA5D4 series, go to /SAMA5D4。

意法半导体DFUSe USB设备固件升级入门说明书

UM0412User manualDfuSe USB设备固件升级意法半导体扩展入门引言本文档介绍了演示用户界面，该界面专为介绍STMicroelectronics设备固件升级库的开发而设计。

该库的描述（包括其应用编程接口）包含在“DfuSe应用编程接口”文档中，并随DfuSe软件一起安装。

2019年3月Doc ID 13379 Rev 1 [English Rev 4]1/22目录UM0412目录1入门指南 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.1系统要求 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51.2演示程序的组成部分 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3DfuSe演示程序安装 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3.1软件安装 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61.3.2硬件安装 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62DFU文件 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123用户界面说明 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.1DfuSe演示 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133.2DFU文件管理器 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2.1“想要执行”对话框 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153.2.2“文件生成”对话框 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.2.3“文件提取”对话框 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174分步流程 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.1DfuSe演示步骤 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.1.1如何上传DFU文件 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.1.2如何下载DFU文件 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194.2DFU相关文件生成步骤 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2.1如何从S19/Hex/Bin文件生成DFU文件 . . . . . . . . . . . . . . . . . . . . . . . . . . 204.2.2如何从DFU文件提取S19/Hex/Bin文件 . . . . . . . . . . . . . . . . . . . . . . . . . . 20 5版本历史 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212/22Doc ID 13379 Rev 1 [English Rev 4]UM0412表格索引表格索引表1.“DfuSe演示”对话框说明 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14表2.“文件生成”对话框说明. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16表3.“Multi bin injection”对话框说明 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17表4.“文件提取”对话框说明. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18表5.文档版本历史 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21表6.中文文档版本历史. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21Doc ID 13379 Rev 1 [English Rev 4]3/22图片索引UM0412图片索引图1.系统属性对话框. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5图2.选择安装位置 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7图3.驱动选择选项 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8图4.驱动选择. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9图5.从磁盘安装 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10图6.进度消息. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10图7.警告消息. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11图8.安装完成. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11图9.“DfuSe演示”对话框. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13图10.“编辑选项字节”对话框. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15图11.“想要执行”对话框 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15图12.“生成”对话框. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16图13.“Multi bin injection”对话框. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17图14.“提取”对话框. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4/22Doc ID 13379 Rev 1 [English Rev 4]UM0412入门指南Doc ID 13379 Rev 1 [English Rev 4]5/221入门指南1.1 系统要求为了在Windows 操作系统上使用DfuSe 演示程序，PC 上的Windows 必须是较新的版本，例如Windows 98SE 、Millennium 、2000、XP 或VISTA 。

SDIO协议文档

SDIO协议文档SDIO1.00协议简介1目录1 目的 ..................................................................... ..................................................... - 1 - 2 备注 ..................................................................... ..................................................... - 1 - 3 SDIO SignalingDefinition ............................................................. ............................. - 1 -3.1 SDIO cardtypes .................................................................. ........................ - 1 -3.2 SDIO cardmodes .................................................................. ...................... - 1 -3.3 SDIO HostModes .................................................................. ..................... - 1 -3.4 信号引脚 ..................................................................... ............................... - 2 -3.5 Host requirements forSDIO ................................................................... ...... - 2 - 4 SDIO card初始化 ..................................................................... ................................ - 2 -4.1 IO CARD初始化的差异 ..................................................................... ........ - 2 -4.2 The IO_SEND_OP_COND Command(CMD5) ............................................ - 3 -4.3 The IO_SEND_OP_COND Response(R4) ................................................... - 4 - 5 Differences with SD Memory Specification(与SD内存标准的差异) ........................... - 4 -5.1 SDIO 命令清单 ..................................................................... .................... - 4 -5.2 Card DetectResistor ............................................................... ..................... - 5 -5.3 数据传输停止...................................................................... ....................... - 5 -5.4 Changes to SD Memory FixedRegisters ....................................................... - 5 -5.4.1 OCR寄存器 ..................................................................... ................... - 5 -5.4.2 CID寄存器 ..................................................................... .................... - 5 -5.4.3 RCA 寄存器 ..................................................................... .................. - 6 - 6 新IO读写命令 ..................................................................... .................................... - 6 -6.1 IO_RW_DIRECTcommand(CMD52) .......................................................... - 6 -6.2 IO_RW_DIRECTResponse(R5)............................................................ ....... - 6 -6.3 IO_RW_EXTENDEDcommand(CMD53) .................................................... - 7 -6.3.1 CMD53 数据传输格式 ..................................................................... .. - 7 - 7 SDIO内部操作 ..................................................................... .................................... - 8 -7.1 Register AccessTime ................................................................... ................ - 8 -7.2Interrupts ............................................................. ....................................... - 8 -7.3 SDIO Fixed InternelMap .................................................................... ......... - 8 -7.4 Common IOArea ................................................................... ..................... - 9 -7.5 CCCR(Card Common ControlRegister) ................................................... - 9 -7.6 FBR(Function BasicRegisters) ............................................................. .. - 12 -7.7 Card InformationStructure(CIS) ......................................................... ........ - 14 -7.8 Multiple Function SDIOCards ................................................................... - 14 -7.9 Setting Block Size withCMD53 ................................................................. - 14 - 8 Embedded I/O Code Storage Area(CSA) .................................................................. - 15 -21 目的本文描述的是基于SDIO标准协议1.0版本，主要描述协议中比较重要的细节信息。

ISD-ES_MINI_USB User Manual

ISD-ES_MINI_USB User Manual Version 1.0Publication Release Date: April 14, 2016ContentsOverview (3)Introduction (4)Installation (5)Push Button Operation (7)Board Schematic (9)Publication Release Date: April 14, 2016OverviewThis manual is for ISD-ES_MINI_USB Rev_A.Figure 1 – Top view of ISD-ES_MINI_USB boardFigure 2 – Bottom view of ISD-ES_MINI_USB boardFigure 3 – ISD-ES_MINI_USB board in plastic casePublication Release Date: April 14, 2016IntroductionISD-ES_MINI_USB, with its informal name as ISD USB dongle, is a USB bridge device which provides the communication link between PC and ISD digital ChipCorder demo board.Figure 4 shown below is a complete evaluation environment for ISD2100 series devices. The ISD USB dongle receives commands and data in USB packet from host PC, communicates with ISD2100 demo board through SPI and GPIO lines, and sends back ISD2100 device status and/or data to PC via USB packets. All the operations are initiated from VPE, a GUI application which runs on Windows PC.Figure 4 – A complete evaluation environment for ISD2100 devicePublication Release Date: April 14, 2016InstallationS oftware downloadISD-ES_MINI_USB must work under VPE–Voice Prompt Editor, the GUI application for evaluating Nuvoton Digital ChipCorder devices. Table below provides a lookup table for user to find what VPE is in need and where to download the corresponding VPE.User needs to fill out and submit the form on the website to request the username and password. Unfortunately, this registration process is not fully automatic yet when this manual is being written. Instead, Nuvoton staff will generate the username and password based on the information received, and send them to user in an email.System Requirements∙PC running Windows XP or Win7∙Support for Windows 10 will be available soon.Publication Release Date: April 14, 2016Normal Operations under VPE∙Connect a demo board to USB dongle∙Plug in USB dongle into a PC USB port∙Launch VPEFigure 5 – To connect demo board and USB dongle: top side face up for both boards.To connect demo board with the USB dongle, both board need to face up for the connection. Please refer to Figure 5 above.These operations do not have to follow a special order. USB dongle is hot pluggable, and so is the demo board. However, during digital programming, demo board needs to be connected otherwise the integrity of flash image cannot be guaranteed.Publication Release Date: April 14, 2016User can look for the VPE user manual in the VPE installation folder. Information regarding VPE and hardware evaluation functions can be found there.Figure 6below shows ISD-DEMO1500 and USB dongle together to provide an ISD15D00 evaluation environment.Figure 6 – USB dongle connected with ISD-DEMO15D00Push Button OperationFigure 7 shows the MM interface for the ISD USB dongle, they are:∙Power LED – Once board plugged in, this red LED should be lit indicating that 3.3 VCC is on.∙Status LED – The meaning of this LED is explained below.∙Push button – User press and hold the button for more than 2 seconds, then USB dongle will try to send Power-Up command and read back device status.o If USB dongle detects that these is no demo board connected, the status LED will flash infinitely; meantime, the USB dongle will continuously send power up and check statuscommand until it detects a demo board presented.o If USB detects ISD device powered up, then the USB dongle will send play_VM_#3 (SPI command sequence as 0xB0, 0x00, 0x03) command and meantime the Status LED willstay constantly on. If the ISD device has output path enabled and speaker connected,then user should be able to hear the sound effect in VM#3.Publication Release Date: April 14, 2016Figure 7 – Power LED, Status LED and Push buttonPublication Release Date: April 14, 2016Board SchematicPublication Release Date: April 14, 2016Publication Release Date: April 14, 2016。

基于SPI模式的Micro SD卡驱动设计与验证

基于SPI模式的Micro SD卡驱动设计与验证
张锋;潘冀宁;朱振荣
【期刊名称】《通讯世界》
【年(卷),期】2017(000)012
【摘要】为进一步降低SD主控的接口限制及设计成本,增强Micro SD卡产品的普适性,使没有SD Host模块的设备无需进行硬件扩展便可使用SD类设备,本文介绍了一种基于SPI模式的Micro SD卡驱动开发设计方法,并从硬件架构和软件流程上对上述驱动进行了详细分析论述.另外,本文基于STM32设计了配套的嵌入式主控,并与SPI模式的Micro SD卡设备联调,完成了设备的枚举测试和通信测试.经产品实测,该基于SPI模式的Micro SD卡使用正常,具有较高的实用价值.
【总页数】2页(P3-4)
【作者】张锋;潘冀宁;朱振荣
【作者单位】公安部第一研究所,北京100048;公安部第一研究所,北京100048;公安部第一研究所,北京100048
【正文语种】中文
【中图分类】TP333
【相关文献】
1.51单片机SD卡SPI模式操作 [J], 司新生
2.SPI模式下SD卡的读写 [J], 李书巳
3.SPI模式下SD卡驱动的设计与实现 [J], 田茂;鲜于李可;潘永才
4.SPI模式下SD卡的读写 [J], 李书巳
5.SPI模式下对SD卡的读写控制 [J], 尚怡君;葛明涛
因版权原因，仅展示原文概要，查看原文内容请购买。

9linux-2.6.35内核移植—SD卡驱动的添加

linux-2.6.35内核移植—SD卡驱动的添加分类：嵌入式2011-11-15 19:17 284人阅读评论(0) 收藏举报【实验目的】SD卡是嵌入式系统中最常用到的外部存储单元,现在的手机,相机等等消费电子及其它设备都在使用SD卡来弥补系统本身存储较小的缺点.这里我们在我们的系统中也添加SD卡的功能.【实验环境】1、Ubuntu 10.10发行版2、u-boot-2010.033、FS2410平台4、交叉编译器arm-none-linux-gnueabi-gcc-4.3.2【实验步骤】1、配置内核Device Drivers ---><*> MMC/SD/SDIO card support ---><*> MMC block device Drivers<*> Samsung S3C SD/MMC Card Interface support2、修改平台代码修改arch/arm/mach-s3c2410/mach-smdk2410.c 添加如下内容:static struct platform_device *smdk2410_devices[] __initdata = {&s3c_device_ohci,&s3c_device_lcd,&s3c_device_wdt,&s3c_device_i2c0,&s3c_device_iis,&s3c_device_sdi, //添加内容&s3c_device_adc,&s3c_device_ts,};3、添加SD卡热插拔功能按照上面两个步骤就能够是我们的SD卡正常工作了,只是不能实现热插拔的功能,必须在系统启动的时候就把卡插上,这样才能是SD卡正常的工作,否则就无法识别SD卡.查看FS2410原理图,发现SD卡的nCS_SD脚接在GPG10上,这个管脚用来监测SD卡插拔,于是我们添加如下代码修改arch/arm/mach-s3c2410/mach-smdk2410.c 添加如下内容：#include <mach/gpio.h>#include <linux/mmc/host.h>#include <plat/mci.h>/*SDI Support*/static struct s3c24xx_mci_pdata smdk2410_mmc_cfg __initdata = { .gpio_detect = S3C2410_GPG(10),.set_power = NULL,.ocr_avail = MMC_VDD_32_33,};在smdk2410_init中添加s3c24xx_mci_set_platdata(&smdk2410_mmc_cfg);4、重新编译内核$ make zImage5、拷贝内核到tftpboot目录下$ cp arch/arm/boot/zImage /tftpboot6、启动系统后插上SD卡s3c-sdi s3c2410-sdi: running at 0kHz (requested: 0kHz).s3c-sdi s3c2410-sdi: running at 396kHz (requested: 400kHz).s3c-sdi s3c2410-sdi: running at 396kHz (requested: 400kHz).s3c-sdi s3c2410-sdi: running at 396kHz (requested: 400kHz).s3c-sdi s3c2410-sdi: running at 396kHz (requested: 400kHz).s3c-sdi s3c2410-sdi: running at 396kHz (requested: 400kHz).s3c-sdi s3c2410-sdi: running at 396kHz (requested: 400kHz).s3c-sdi s3c2410-sdi: running at 396kHz (requested: 400kHz).s3c-sdi s3c2410-sdi: running at 12675kHz (requested: 25000kHz). s3c-sdi s3c2410-sdi: running at 12675kHz (requested: 25000kHz). mmc0: new SDHC card at address aaaammcblk0: mmc0:aaaa SD04G 3.69 GiBmmcblk0: p1这说明我们有一个4G的SD卡被发现了,它有一个分区7、创建设备节点# mknod mmcblk0p1 b 179 18、挂载SD卡# mount -t vfat /dev/mmcblkp1 /mnt9、查看SD卡内容# ls /mnt分享到：∙上一篇：linux-2.6.35内核移植—USB驱动的添加∙下一篇：linux-2.6.35内核移植—yaffs2文件系统的支持。

树莓派启动指南-无需屏幕键盘

目录第一步：格式化SD卡 (2)第二步：下载安装系统镜像 (2)第三步：通过SSH连接树莓派 (3)第四步：设置树莓派 (6)第五步：使用windows远程桌面访问树莓派桌面 (8)第六步：建立VNC获取树莓派桌面 (9)第七步：安装3.5寸触摸屏驱动 (11)第八步：配置摄像头 (15)第一步：格式化SD卡说明：未安装过Raspbian系统的SD卡可通过windows直接格式化，若要重新安装系统需要通过SDFormatter软件格式化。

因为windows无法识别SD文件类型，导致无法完全格式化，建议使用软件格式化SD卡。

1、下载SDFormatter软件下载地址：/rpi/SDFormatterv4.zip2、在电脑端解压安装然后插入你要格式化的Miscro SD卡，然后打开软件运行3、选择对应Miscro SD卡对应的磁盘符4、确认无误，点击格式化既可以完成格式化后，SD卡为FAT32格式第二步：下载安装系统镜像1、下载安装系统写入工具win32diskimager下载地址：https:///projects/win32diskimager/2、下载系统镜像下载地址：https:///downloads/raspbian/一般选择RASPBIAN STRETCH WITH DESKTOP镜像，下载种子文件通过迅雷下载更快。

3、下载好文件后：启动Win32DiskImager，映像文件处选择Raspbian系统映像文件，设备处选择盘符为你读卡器的盘符，点写入，然后点一下Yes确定操作，开始系统写入，写入完成，提示成功。

将Micro SD卡插入树莓派，接通电源启动4、备份系统新建一个后缀为.img的文件，在Win32DiskImager中打开，然后选择设备，点击读取，等待读取完成，SD卡中的映像便备份到此img文件中了。

之后可通过读取操作完成恢复。

第三步：通过SSH连接树莓派1、无显示器获取树莓派IP若路由器有多余网线接口可直接通过网线连接路由器和树莓派上网，否则可以使用如下方式使树莓派联网：将网线一端接到树莓派，另一端接到笔记本。