53272中文资料
信息论与纠错编码 (孙丽华 著) 电子工业出版社_khdaw
w .c
1−δ − ε (1 − ε ) / 2
− H 2 (ε )
om
]
− H 2 (ε )
(2) I(1;1) = log
I(1;0) = log
δ (1 − ε ) / 2
da
[
4.14 (1) C = ln 1 + 2e
kh
(2) C (ε = 0) = ln 1 + 2e
[
] = ln[1 + 2e ]
x5
11
21
20
hd
12 10
(4)Huffman 编码,D=4
消息 码字
.k
33 32
x1
2
x2
0
x3
x4
x5
31
3.21 (1)D=2
消息 码字
w
x1
x2
x3
x4
011
x5
001
aw .c
x6 x7 x8
110 1110 1111
答
x6
x7
x8
221
220
x6
x7
11
x8
10
30
x6
000
x7
1101
1
若侵犯了您的版权利益,敬请来信通知我们! ℡
kh
da
(2)H(X) =2.36 (Bit/符号)
w
2.11(1)H(X) = log6 = 2.58 (Bit/符号)
.c
1 = 225.6( Bit ) 52! 52! (2) I ( xi ) = − log q ( xi ) = log 13 4 13!39! 1 (3) H (U ) = - log = log 52 = log 4 × 3 = 2 log 13 = 7.4( Bit / 符号) 52 1 (4) H ( X ) − log = log 13 = 3.7( Bit / 符号) 13
rfc 5322标准
rfc 5322标准
RFC 5322 是一项Internet 标准,它规定了电子邮件的格式、结构和内容。
该标准于2008年发布,取代了之前的RFC 2822,并进一步扩展了电子邮件的语法和语义。
以下是RFC 5322 中的一些关键内容:
电子邮件地址格式:它定义了电子邮件地址的结构和语法,包括邮件头部(header)和邮件体(body)的各个部分。
邮件头部:包括发件人(From)、收件人(To)、抄送(CC)、密送(BCC)、主题(Subject)、日期(Date)等信息,以及其他可能的标头字段。
邮件体:邮件体包括邮件的正文内容,可以是纯文本、HTML 格式、附件等。
地址标准化:RFC 5322 规定了电子邮件地址的标准化格式,包括邮件用户名和邮件域名的结构和语法规则。
消息结构:它定义了电子邮件消息的结构,包括消息头部、消息体和附件的组织方式。
字符编码和传输:RFC 5322 规定了邮件内容的字符编码和传输方式,以确保邮件在网络上的可靠传输。
邮件格式标准化:RFC 5322 对邮件格式进行了标准化,以确保不同邮件客户端和邮件服务器之间的互操作性和兼容性。
总的来说,RFC 5322 标准化了电子邮件的格式、结构和内容,使得电子邮件系统能够在全球范围内进行通信和交换,为互联网邮件提供了统一的基础规范。
1。
汉字编码对照表
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66572资料
April 1996NEC Electronics Inc.A10616EU1V0DS00CMOS-8LHD3.3-Volt, 0.5-Micron CMOS Gate ArraysPreliminary DescriptionNEC's CMOS-8LHD gate-array family combines cell-based-level densities with the fast time-to-market and low development costs of gate arrays. With a unique heterogeneous cell architecture, CMOS-8LHD provides the very dense logic and RAM capabilities required to build devices for fast computer and communications systems.NEC delivers high-speed, 0.5-micron, drawn gate length (Leff=0.35-micron), three-level metal, CMOS technology with an extensive family of macros. I/O macros include GTL, HSTL, and pECL. TTL CMOS I/Os are provided with 5-V tolerance for applications requiring interface to 5-V logic. PCI signaling standards are also supported,including 3.3-V, 66 MHz PCI. The technology is enhanced by a set of advanced features, including phase-locked loops, clock tree synthesis, and high-speed memory. The CMOS-8LHD gate-array family of 3.3-V devices consists of 12 masters, offered in densities of 75K raw gates to 1.123 million raw gates. Usable gates range from 45K to 674K used gates.The gate-array family is supported by NEC's OpenCAD ®design system, a mixture of popular third-party EDA tools,and proprietary NEC tools. NEC proprietary tools include the GALET floorplanner, which helps to reduce design time and improve design speed, and a clock tree synthesis tool that automatically builds a balanced-buffer clock tree to minimize on-chip clock skew.Figure 1. CMOS-8LHD Package Options: BGA & QFPTable 1. CMOS-8LHD Family Features and BenefitsCMOS-8LHD ApplicationsThe CMOS-8LHD family is ideal for use in personal computer systems, engineering workstations, and telecommunications switching and transmission systems, where extensive integration and high speeds are primary design goals. With power dissipation of 0.21 µW/MHz/gate, CMOS-8LHD is also suited for lower-power applications where high performance is required.OpenCAD is a registered trademark of NEC Electronics Inc.CMOS-8LHD2Cell-Based Array ArchitectureThe CMOS-8LHD gate-array family is built with the Cell-Based Array (CBA) architecture licensed from the Silicon Architects Group of Synopsys. CBA architecture uses two types of cells: compute cells and drive cells.This heterogeneous cell architecture enables very high-density design. Compute cells are used to optimize intramacro logic. Drive cells are optimized for intermacro interconnect. The two cell types are also used to build macros with up to three different power/performance/area points.CBA has a rich macrocell library that is optimized for synthesis. RAM blocks are efficiently created from the CBA architecture, using compute cells as memory cores, and sense amplifiers and drive cells as word and address predecoder drivers.As shown in Figure 2, CBA is divided into I/O and array regions. The I/O region contains input and output buffers. The array region contains the gates used to build logic, RAM blocks, and other design features.Power Rail ArchitectureCMOS-8LHD provides additional flexibility for mixedvoltage system designs. As shown in Figure 2, the arrays contain two power rails: a 3.3-V rail, and V DD2.The V DD2 rail is used for interfaces such as 5-V PCI buffers where a clamping diode allows protection for up to an 11-V voltage spike, per the PCI revision 2.1specification.Figure 2. CBA Layout and Cell ConfigurationThe V DD2 rail is separated into sections to give flexibility for including two or more buses requiring special I/O voltage on one device. Each section can operate as an independent voltage zone, and sections can be linked together to form common voltage zones.Packaging and TestNEC utilizes BIST test structures for RAM testing. NEC also offers advanced packaging solutions including Plastic Ball Grid Arrays (PBGA), Plastic Quad Flat Packs (PQFP), and Pin Grid Arrays (PGA). Please call your local NEC ASIC design center representative for a listing of available master/package combinations.PublicationsThis data sheet contains preliminary specifications for the CMOS-8LHD gate-array family. Additional infor-mation will be available in NEC's CMOS-8LHD Block Library and CMOS-8LHD Design Manual . Call your local NEC ASIC design center representative or the NEC literature line for additional ASIC design information; see the back of this data sheet for locations and phone numbers.Table 2. CMOS-8LHD Base Array Line-upDevice Raw Gates Used Gates (1)Total Pads66562750404502416466563997925987518866565125216751292126656617963210777925266568202400121440268665692681281608763086657029792017875232466571359744215845356665725008643005184206657362054437232646866575802240481344532(1) Actual gate utilization varies depending on circuit implementation.Utilization is 60% for 3LM.3CMOS-8LHDInput/Output CapacitanceV DD =V I =0-V; f =1 MHzTerminal Symbol Typ Max Unit Input C IN 1020pF Output C OUT 1020pF I/OC I/O1020pF(1)Values include package pin capacitancePower ConsumptionDescription Limits Unit Internal gate (1)0.21µW/MHz Input buffer 2.546µW/MHz Output buffer10.60µW/MHzAbsolute Maximum RatingsPower supply voltage, V DD –0.5 to +4.6-VInput voltage, V I3.3-V input buffer (at V I < V DD + 0.5-V)–0.5 to +4.6-V 3.3-V fail-safe input buffer (at V I < V DD + 0.5-V)–0.5 to +4.6-V 5 V-tolerant (at V I < V DD + 3.0-V)–0.5 to +4.6-V Output Voltage, V O3.3-V output buffer (at V O < V DD + 0.5-V)–0.5 to +4.6-V 5-V-tolerant output buffer (at V O < V DD + 3.0-V)–0.5 to +4.6-V 5-V open-drain output buffer (at V O < V DD + 3.0-V)–0.5 to +4.6-VLatch-up current, I LATCH >1 A (typ)Operating temperature, T OPT –40 to +85°C Storage temperature, T STG–65 to +150°C (1) Assumes 30% internal gate switching at one timeCaution: Exposure to absolute maximum ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The device should not be operated outside the recommended operating conditions.Recommended Operating ConditionsV DD = 3.3-V ±0.165-V; T j = 0 to +100°C3.3-V Interface 5-V Interface5-V PCI 3.3-V PCIBlock BlockLevel LevelParameterSymbol Min Max Min Max Min Max Min Max Unit I/O power supply voltage V DD 3.0 3.6 3.0 3.6 3.0 5.5 3.0 3.6V Junction temperature T J 0+1000+1000+1000+100°C High-level input voltage V IH 2.0V DD 2.0 5.5 2.0V CC 0.5 V CCV CC V Low-level input voltage V IL 00.800.800.800.3 V CCV Positive trigger voltage V P 1.50 2.70 1.50 2.70————V Negative trigger voltage V N 0.60 1.60.60 1.6————V Hysteresis voltage V H 1.10 1.3 1.10 1.3————V Input rise/fall time t R , t F 0200020002000200ns Input rise/fall time, Schmittt R , t F1010————nsAC CharacteristicsV DD = 3.3-V ±0.3-V; T j = –40 to +125°C ParameterSymbol MinTypMax Unit Conditions Toggle frequency (F611)f TOG356MHzD-F/F; F/O = 2 mmDelay time2-input NAND (F322)t PD181ps F/O = 1; L = 0 mmt PD 186ps F/O = 2; L = typ (0.42 mm)Flip-flop (F611)t PD 573ps F/O = 1; L = 0 mm t PD 688ps F/O = 2; L = typ t SETUP 410ps —t HOLD 540ps —Input buffer (FI01)t PD 268ps F/O = 1; L = 0 mm t PD 312ps F/O = 2; L = typ Output buffer (9 mA) 3.3-V (FO01)t PD 1.316ns C L = 15 pF Output buffer (9 mA) 5-V-tolerant (FV01)t PD 1.228ns C L = 15 pF Output buffer (9 mA) 5-V-swing (FY01)t PD 1.517ns C L = 15 pF Output rise time (9 mA) (FO01)t R 1.347ns C L = 15 pF Output fall time (9 mA) (FO01)t F1.284nsC L = 15 pFCMOS-8LHD4(3)Rating is for only one output operating in this mode for less than 1 second.(4)Normal type buffer: I OH < I OL .(5)Balanced buffer: I OH = I OL .(6)Resistor is called 50ký to maintain consistency with previous families.Notes:(1)Static current consumption increases if an I/O block with on-chip pull-up/pull-down resistor or an oscillator is used. Call an NEC ASIC design center repre-sentative for assistance in calculation.(2)Leakage current is limited by tester capabilities. Specification listed representsthis measurement limitation. Actual values will be significantly lower.DC CharacteristicsV DD = 3.3-V ±0.165-V; T j = 0 to +100°C ParameterSymbol Min Typ Max Unit Conditions Quiescent current (1)µPD66578I DDS 2.0300µA V I = V DD or GND µPD66575, 66573, 66572I DDS 1.0300µA V I = V DD or GND Remaining mastersI DDS 0.5200µA V I = V DD or GND Off-state output leakage current3.3-V buffers, 3.3-V PCII OZ ±10µA V O = V DD or GND 5-V-tolerant buffers, 5-V PCI I OZ ±14µA V O = V DD or GND 5-V open-drainI OZ ±14µA V O = V DD or GND Output short circuit current (3)I OS –250mA V O = GND Input leakage current (2)5-V PCI I IH +70, –70µA V IN = 2.7-V, 0.5-V 3.3-V PCI I I ±10µA V IN = V DD or GND RegularI I ±10–5±10µA V I = V DD or GND 50 k Ω pull-up I I –180–40µA V I = GND 5 k Ω pull-up I I –1400–350mA V I = GND 50 k Ω pull-down I I 30160µA V I = V DDResistor values50 k Ω pull-up (6)R pu 2075k Ω5 k Ω pull-upR pu 2.68.6k Ω50 k Ω pull-down (6)R pu 22.5100k ΩInput clamp voltageV IC –1.2V I I = 18 mA Low-level output current (ALL buffer types)3 mA I OL 3mA V OL = 0.4-V 6 mA I OL 6mA V OL = 0.4-V 9 mA I OL 9mA V OL = 0.4-V 12 mA I OL 12mA V OL = 0.4-V 18 mA I OL 18mA V OL = 0.4-V 24 mAI OL 24mA V OL = 0.4-V High-level output current (5-V-tolerant block)3 mA I OH –3mA V OH = V DD –0.4-V 6 mA I OH –3mA V OH = V DD –0.4-V 9 mA I OH –3mA V OH = V DD –0.4-V 12 mA I OH –3mA V OH = V DD –0.4-V 18 mA I OH –4mA V OH = V DD –0.4-V 24 mAI OH –4mA V OH = V DD –0.4-V High-level output current (3.3-V interface block)3 mA I OH –3mA V OH = V DD –0.4-V 6 mA I OH –6mA V OH = V DD –0.4-V 9 mA I OH –9mA V OH = V DD –0.4-V 12 mA I OH –12mA V OH = V DD –0.4-V 18 mA I OH -18mA V OH = V DD –0.4-V 24 mAI OH -24mA V OH = V DD –0.4-V Output voltage (5-V PCI)High-level output voltage V OH 2.4mA I OH = 2 mALow-level output voltage V OL 0.55mA I OL = 3 mA, 6 mA Output voltage (3.3-V PCI)High-level output voltage V OH 0.9 V DDmA I OH = 500 µA Low-level output voltage V OL 0.1 V DDmA I OL = 1500 µA Low-level output voltageV OL 0.1V I OL = 0 mA High-level output voltage, 5-V TTL V OH V DD –0.2V I OL = 0 mA High-level output voltage, 3.3-VV OHV DD –0.1VI OH = 0 mACMOS-8LHD5CMOS-8LHD6Document No. A10616EU1V0DS00For literature, call toll-free 7 a.m. to 6 p.m. Pacific time: 1-800-366-9782or FAX your request to: 1-800-729-9288©1996 NEC Electronics Inc./Printed in U.S.A.NEC ASIC DESIGN CENTERSWEST•3033 Scott Boulevard Santa Clara, CA 95054TEL 408-588-5008FAX 408-588-5017•One Embassy Centre9020 S.W. Washington Square Road,Suite 400Tigard, OR 97223TEL 503-671-0177FAX 503-643-5911THIRD-PARTY DESIGN CENTERSSOUTH CENTRAL/SOUTHEAST•Koos Technical Services, Inc.385 Commerce Way, Suite 101Longwood, FL 32750TEL 407-260-8727FAX 407-260-6227•Integrated Silicon Systems Inc.2222 Chapel Hill Nelson Highway Durham, NC 27713TEL 919-361-5814FAX 919-361-2019•Applied Systems, Inc.1761 W. Hillsboro Blvd., Suite 328Deerfield Beach, FL 33442TEL 305-428-0534FAX 305-428-5906NEC Electronics Inc.CORPORATE HEADQUARTERS2880 Scott Boulevard P.O. Box 58062Santa Clara, CA 95052TEL 408-588-6000No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics Inc. (NECEL). The information in this document is subject to change without notice. ALL DEVICES SOLD BY NECEL ARE COVERED BY THE PROVISIONS APPEARING IN NECEL TERMS AND CONDITIONS OF SALES ONLY. INCLUDING THE LIMITATION OF LIABILITY,WARRANTY, AND PATENT PROVISIONS. NECEL makes no warranty, express, statutory, implied or by description, regarding informa-tion set forth herein or regarding the freedom of the described devices from patent infringement. NECEL assumes no responsibility for any errors that may appear in this document. NECEL makes no commitments to update or to keep current information contained in this document. The devices listed in this document are not suitable for use in applications such as, but not limited to, aircraft control systems,aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. “Standard” quality grade devices are recommended for computers, office equipment, communication equipment, test and measurement equipment, machine tools,industrial robots, audio and visual equipment, and other consumer products. For automotive and transportation equipment, traffic control systems, anti-disaster and anti-crime systems, it is recommended that the customer contact the responsible NECEL salesperson to determine the reliabilty requirements for any such application and any cost adder. NECEL does not recommend or approve use of any of its products in life support devices or systems or in any application where failure could result in injury or death.If customers wish to use NECEL devices in applications not intended by NECEL, customer must contact the responsible NECEL sales people to determine NECEL’s willingness to support a given application.SOUTH CENTRAL/SOUTHEAST•16475 Dallas Parkway, Suite 380Dallas, TX 75248TEL 972-735-7444FAX 972-931-8680•Research Triangle Park2000 Regency Parkway, Suite 455Cary, NC 27511TEL 919-460-1890FAX 919-469-5926•Two Chasewood Park 20405 SH 249, Suite 580Houston, TX 77070TEL 713-320-0524FAX 713-320-0574NORTH CENTRAL/NORTHEAST•The Meadows, 2nd Floor 161 Worcester Road Framingham, MA 01701TEL 508-935-2200FAX 508-935-2234•Greenspoint Tower2800 W. Higgins Road, Suite 765Hoffman Estates, IL 60195TEL708-519-3945FAX 708-882-7564。
53225资料
53225SOLID-STATE POWER CONTROLLER (SSPC)MiiHYBRID MICROELECTRONICS PRODUCTS DIVISIONFeatures:•I2t output trip•Output trip status•1000 VRMS Isolation•Power FET OutputLow On-state Resistance•Full Military compliance•Low control power consumption (3 mA @ 5 V typical)•125ºC screening available Applications:•Logic controlled circuit breakers • Dynamicloadswitching• Powerdistributionswitch • SupplysourceswitchingDESCRIPTIONThe 53225 is a military SPST solid-state relay. This light-weight device is mechanically resistant and electrically immune to contact-related problems inherent in mechanical relays.An I2t current let-through curve assures power supply, relay, and load protection from thermal stress yet provides large momentary currents to charge capacitive loads or start inductive loads. Any current versus time above the I2t curve initiates a trip condition and a status output is generated.Effective isolation of 1000 VRMS is provided from all inputs, case and outputs through magnetic coupling. Magnetic coupling contributes to very low control power, repeatable turn-on/turn-off times, and no output stage currents to provide status signals.Micropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.ELECTRICAL CHARACTERISTICS(-55°C ≤ TA ≤ 85°C, V BIAS = 5 V, V OUT + = 28 V, I OUT = 1.5 A unless otherwise noted)CHARACTERISTIC CONDITION MIN MAX UNITS 2 Terminal Configuration (see Fig. 2)Input Current5MADC Turn off voltage (V IN) 1.5VDC Turn on voltage (V IN) 3.8VDC Bias supply voltage range46VDC 3 Terminal Configuration (see Fig. 1)Control input Current V CONT = 5 VDC250µADC Control voltage range06VDC Bias supply voltage range0.56VDC Bias supply current5mADC Turn off voltage (V CONTROL) 3.9VDC Turn on voltage (V CONTROL)0.3VDC Noise Margin V OFF – V ON0.5VDCContinuous off leakage current (not tripped)V OUT+ = 60 VDCV OUT- = Ground150µADCOutput on voltage drop I L = 1.5 A0.45VDC Continuous operating load voltage60VDC Transient blocking voltage@ 1.0 mA80VDC On resistance RDS (ON)I LOAD = 100 mADC0.30OHMS Turn on time 3.0MS Turn off time 1.0MS Operating frequency20HZ DV/DT100V/µM Electrical system spike±600Peak Output Capacitance25 VDC, 100 kHz1000PF Input to output capacitance15PF Dielectric strength@ 1.0 mA maximum leakage1000VAC Insulation resistance@ 500 VDC, TA – 25°C103OHMSSurge Current (see Fig. 4)Guaranteed no trip@ 10 A surge70 Typ.MSTrip Reset Time Remove short / overload& Cycle input50MsStatus Output SpecificationStatus Supply Voltage (open Collector)5.032VDC Status off leakage current VS = 15 VDC4µADC Status on voltage I STATUS = 5 MA0.4VDC High-To-Low Transition Time I STATUS = 5 MA 1.0MS Notes:1. Input transition should be ≤ MSEC duration and input drive should be “bounceless contact” type.Micropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.Package DimensionsPIN FUNCTION1Control3Ground9V OUT -12V OUT +16Status22V BIASMicropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.Micropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.53225 SOLID-STATE POWER CONTROLLER (SSPC)TRIP STATUSSA - Three - Terminal ConnectionFigure 1V CONTROLV BIASV STATUSV BIAS V Figure 2B - Two - Terminal Connection(OFF)(ON)(OFF)OUTPUT (ON)STATUSTiming Diagram (3 Terminal Connection)Figure 353225 SOLID-STATE POWER CONTROLLER (SSPC)Micropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.。
莫尔斯代码
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逞6642 骋7488秤4439 吃0676 痴4035 持2170 匙0555 池3069 迟6688 弛1716驰7459 耻5103 齿7876 侈0172 尺1439 赤6375 翅5041 斥2444炽3589 充0339 冲0394 虫5722 崇1504 宠1404 抽2132 酬6804畴3985 踌6486 稠4464 愁1935 筹4693 仇0092 绸4846 瞅4197丑0010 臭5263 初0443 出0427 橱8599 厨1676 躇6484 锄6915雏7176 滁3315 除7110 楚2806 础4342 储0328 矗4238 搐2294触6051 处5710 揣2260 川1557 穿4502 椽2796 传0278 船5307喘0820 串0025 疮4056 窗4514 幢1617 床1643 闯7068 创0482吹0706 炊3507 捶2211 锤6925 垂0987 春2504 椿2797 醇6815唇0782 淳8708 淳3196 纯4783 蠢5868 戳2067 绰4862 疵4009茨5412 磁4318 雌7166 辞6588 慈1964 瓷8851 瓷3911 词6101此2974 刺0459 赐6337 次2945 聪5115 葱5523 囱0935 匆8116从1783 丛0654 凑0410 粗4723 醋6818 簇4662 促0191 蹿4533篡4647 摧2301 崔1508 催0275 脆5186 瘁4041 粹4733 淬3231翠5050 村2625 存1317 寸1407 磋4322 撮2331 搓2238 搓2278措2181 错2290 错6934 搭6671 达4594 答4079 瘩2092 打1129大0714 呆2983 傣2071 傣7831 戴1601 带2990 代6313 代0108贷5915 待1769 待6649 怠5104 怠1836 耽2137 丹0830 丹0030单6779 郸8473 掸9116 胆2481 氮8644 但0141 惮1998 淡3225诞6130 弹1734 蛋5751 当3981 挡2346 党7825 党8093 荡5616档2909 刀0430 捣2281 蹈6457 倒0227 岛1497 祷4411 导1418到0451 稻4470 悼1902 道6670 盗4142 德1795 得1779 的4104蹬6478 灯3597 登4098 等4583 瞪4223 凳0419 邓6772 堤1029豁6255 活3172 伙0129 火3499 获3752 或2057 惑1910 霍7202货6303 祸4393 击2345 圾0969 基1015 机2623 畸3982 稽4472积4480 箕4614 肌5133 饥7382 迹6619 激3423 讥6217 鸡7741姬1213 绩4921 缉4874 吉0679 极2817 棘2765 辑6549 籍4694集7162 及0644 急1838 疾4014 汲0378 汲3078 即0613 嫉1271级4878 级4787 挤2357 几0415 脊5182 己1569 蓟5636 技2111冀0370 季1323 伎0125 祭4385 剂0495 悸1900 济3444 寄1376寂1374 计6060 记6068 既2478 忌1803 际7139 妓1178 继4949纪4764 嘉0857 枷2666 夹1140 佳0163 家1367 加0502 荚5453颊7335 贾6328 甲3946 钾6905 假0250 稼4471 价0116架2665驾7468 嫁1268 歼3005 监4148 坚1017 尖1423 笺4608 间7035煎3553 兼0369 肩5144 艰5329 奸1169 缄4873 茧4942 检2914柬2687 碱4354 碱7769 碱8969 拣2245 简4675 俭0313 剪0477减8096 荐5433 槛2920 鉴7003 践6432 贱6345 见6015 键6943箭4628 件0115 健0256 舰5324 剑0494 饯7415 渐3362 溅3457涧3386 建1696 僵0304 姜1302 姜1203 将1412 浆3364 江3068疆3984 蒋5592 桨2862 奖1162 讲6199 匠0561 酱6830 降7100蕉5604 椒2786 礁4339 焦3542 胶5231 交0074 郊6738 浇3398骄7524 娇1293 嚼0920 搅2383 铰6890 矫4255 侥0299 脚5183狡3701 角6037 饺7398 缴4945 绞4819 剿0485 剿8464 教2403酵6806 轿6569 较6525 叫0663 窖4512 揭2263 接2234皆4105秸4447 街5894 阶7132 截2066 劫0506 节4634 桔2720 杰0267杰2638 捷2212 睫4208 竭4550 洁3381 结4814 解6043 姐1195戒2054 藉5659 芥5354 界3954 借0234 介0094 疥4003 诫6135届1447 巾1577 筋4585 斤2443 金6855 今0093 津3160 襟5992襟5995 紧4868 锦6930 仅0284 谨6310 谨6210 进6651 靳7246晋2516 禁4391 近6602 烬3612 浸3190 尽4147 劲0513 荆5427兢0352 茎5449 睛4200 晶2533 鲸7650 京0079 惊7528 精4737粳4734 经4842 井0064 警6224 警6226 景2529 颈7338 静7234境1064 敬2417 镜6975 径1777 痉3997 靖7231 竟4552 竞4544净0403 炯3518 窘4515 揪2262 究4496 纠4763 玖3773 韭7295久0036 灸3502 九9909 九9709 九9809 九0046 酒6794厩1673救2405 旧5283 臼5273 舅5279 咎0736 就1432 疚3998 鞠7263拘2153 狙3700 疽4013 居1446 驹7467 菊5468 局1444 咀0731矩4251 举5282 沮3107 聚5112 拒2147 据2207 巨1565 具0367距6415 踞6436 锯6920 俱0215 句0658 惧2040 炬3515 剧0489捐2196 鹃7710 娟1227 倦0239 眷4187 卷0608 绢4831 撅2313攫2384 抉2115 掘2228 倔8056 爵3635 觉6030 决0414 决6076绝4815 均0971 菌5497 钧6874 军6511 君0689 峻1498 俊0193竣4546 浚3182 郡6746 骏7486 喀0807 咖0739 卡0595 咯0748开7030 揩2261 楷2818 凯0418 慨1980 刊0436 堪1030 勘0522坎0974 砍4266 看4170 康1660 慷1988 糠4749 扛2095 抗2123亢0073 炕3510 考5072 拷2166 烤3628 靠7237 坷0985苛5381柯2688 棵2644 磕4326 颗7341 科4430 壳8199 咳0750 可0668渴3265 克0344 刻0466 客1356 课6143 肯5146 啃8186 垦1083恳2017 坑0977 吭0699 空4500 恐1858 孔1313 控2235 抠2305口0656 扣2099 寇1379 枯2661 哭0770 窟4516 苦5388 酷6807库1655 裤5974 夸1139 垮1006 挎2175 跨6421 胯5169 块1040筷4599 侩0312 快1816 宽1401 款2949 匡0562 筐4590 狂3693框2713 矿4349 眶4186 旷2568 况0400 亏5719 盔4140 岿8354窥4529 葵5525 奎1145 魁7608 傀0264 馈7432 愧1951 溃3391坤0981 昆2492 捆2190 困0938 括2161 扩2368 廓1674 阔7059。
7427223;中文规格书,Datasheet资料
Bezeichnung :description :Eigenschaften / properties Wert / valueEinheit / unitTol.Impedanz @ 1 Wg./impedance @ 1 turn Impedanz @ 1 Wg./impedance @ 1 turnImpedanz @ 2 Wg./impedance @ 2 turn Impedanz @ 2 Wg./impedance @ 2 turn33%+ 20°C+ 140°C 23-pol.SMU Update 06-10-12LFRoHS update 04-10-11JH Version 100-12-06NameÄnderung / modificationDatum / dateKunde / customerFreigabe erteilt / general release:CB Elektrische Eigenschaften / electrical properties:E Testbedingungen / test conditions:Luftfeuchtigkeit / humidity:Umgebungstemperatur / temperature:Betriebstemp. / operating temperature: -25°C ~ + 125°CF Werkstoffe & Zulassungen / material & approvals:3 W 800für Flachbandkabel / for flat cable [max]:Lagertemperatur / storage temperature: -55°C ~ + 125°C ΩDatum / date...........................................................................Unterschrift / signature Kontrolliert / approvedTestbedingungen / test conditionsWürth Elektronik eiSos GmbH & Co. KGD-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Geprüft / checked ZΩBasismaterial / base material:Curietemperatur / curie temperature: G Eigenschaften / general specifications:FLAT FERRITE COREΩ± 25%23ΩHP 4191 B für/for Z und/and material 16092A - Klemme / clamp Z48Z D Prüfgeräte / test equipment:...............................................................................................................................................................................................................................................Würth Elektronik100 MHz25 MHz ± 25%Z AWG26 - ø 0,8mm - Länge/length:220 mmBezeichnung :description :B:SMU Update 06-10-12LFRoHS update 04-10-11JH Version 100-12-06NameÄnderung / modificationDatum / dateGeprüft / checked Kontrolliert / approvedWürth Elektronik eiSos GmbH & Co. KGD-74638 Waldenburg · Max-Eyth-Strasse 1 - 3 · Germany · Telefon (+49) (0) 7942 - 945 - 0 · Telefax (+49) (0) 7942 - 945 - 400Würth Elektronik..........................................................................................................................................................................................................................................................................................................................Datum / dateUnterschrift / signature H Impedanzverlauf / impedance curve:1 x durch Bohrung Ferrit / 1 x times trough ferriteFreigabe erteilt / general release:Kunde / customerFLAT FERRITE COREDATUM / DATE : 2006-10-12This electronic component has been designed and developed for usage in general electronic equipment. Before incorporating this component into any equipment where higher safety andreliability is especially required or if there is the possibility of direct damage or injury to human body, for example in the range of aerospace, aviation, nuclear control, submarine, transportation, (automotive control, train control, ship control), transportation signal, disaster prevention, medical, public information network etc, Würth Elektronik eiSos GmbH must be informed before the design-in stage. In addition, sufficient reliability evaluation checks for safety must be performed on every electronic component which is used in electrical circuits that require high safety and reliability functions or performance.分销商库存信息: WURTH-ELECTRONICS 7427223。
编码解码芯片
2009-03-18 08:27PT2262/2272是台湾普城公司生产的一种CMOS工艺制造的低功耗低价位通用编解码电路,PT2262/2272最多可有12位(A0-A11)三态地址端管脚(悬空,接高电平,接低电平),任意组合可提供531441地址码,PT2262最多可有6位(D0-D5)数据端管脚,设定的地址码和数据码从17脚串行输出,可用于无线遥控发射电路。
编码芯片PT2262发出的编码信号由:地址码、数据码、同步码组成一个完整的码字,解码芯片PT2272接收到信号后,其地址码经过两次比较核对后,VT脚才输出高电平,与此同时相应的数据脚也输出高电平,如果发送端一直按住按键,编码芯片也会连续发射。
当发射机没有按键按下时,PT2262不接通电源,其17脚为低电平,所以315MHz的高频发射电路不工作,当有按键按下时,PT2262得电工作,其第17脚输出经调制的串行数据信号,当17脚为高电平期间315MHz的高频发射电路起振并发射等幅高频信号,当17脚为低平期间315MHz的高频发射电路停止振荡,所以高频发射电路完全收控于PT2262的17脚输出的数字信号,从而对高频电路完成幅度键控(ASK 调制)相当于调制度为100%的调幅。
PT2262/2272特点:CMOS工艺制造,低功耗,外部元器件少,RC振荡电阻,工作电压范围宽:~15v ,数据最多可达6位,地址码最多可达531441种。
应用范围:车辆防盗系统、家庭防盗系统、遥控玩具、其他电器遥控。
外形及引脚功能在具体的应用中,外接振荡电阻可根据需要进行适当的调节,阻值越大振荡频率越慢,编码的宽度越大,发码一帧的时间越长。
网站上大部分产品都是用2262/=2272/200K组合的,少量产品用2262/=2272/820K。
极限参数和电气参数2262应用电路1地址码和数据码都用宽度不同的脉冲来表示,两个窄脉冲表示“0”;两个宽脉冲表示“1”;一个窄脉冲和一个宽脉冲表示“F”也就是地址码的“悬空”。
72224中文资料
Listinቤተ መጻሕፍቲ ባይዱs
Listings and approvals below apply to the Reflective Beam Smoke Detectors. In some cases, certain modules may not be listed by certain approval agencies, or listing may be in process. Consult factory for latest listing status. • UL Listed:
Page 2 of 2
Reflective Beam CS-2154 06/23/04
Dimensions
8.25" H x 4.5" W x 4.75" D (cm: 21.0 H x 11.43 W x 12.065 D).
Finish
Gray/black.
Weight
1.5 lbs. (0.68 kg).
Range
15 ft. to 330 ft. (m: 5 to 100).
The Gamewell Company 12 Clintonville Road Northford, CT 06472-1610 Phone: 203-484-7161 Fax: 203-484-7118 A Honeywell Company © 2004 Gamewell
Smoke Detector Spacing
On smooth ceilings, up to 60 ft. (18.288 m) between projected beams and not more than one-half that spacing between a projected beam and a sidewall. Other spacing may be used depending on ceiling height, airflow characteristics, and response requirements. See NFPA 72 for further information.
BTS723GW中文资料
元器件交易网
BTS 723 GW Maximum Ratings at Tj = 25°C unless otherwise specified
Parameter Supply voltage (overvoltage protection see page 6) Supply voltage for full short circuit protection Tj,start = -40 ...+150°C Output Voltage to Vbb Negative voltage slope at output Load current (Short-circuit current, see page 7) Load dump protection2) VLoadDump = VA + Vs, VA = 27 V RI3) = 8 Ω, td = 200 ms; IN = low or high, each channel loaded with RL = 20 Ω, Operating temperature range Storage temperature range Power dissipation (DC)5) Ta = 25°C: (all channels active) Ta = 85°C: Maximal switchable inductance, single pulse Vbb = 12V, Tj,start = 150°C5), IL = 2.5 A, EAS = 110 mJ, 0 Ω one channel: IL = 3.5 A, EAS = 278 mJ, 0 Ω two parallel channels:
Block Diagram
Status pull up voltage IN1 ST1 Vbb
1052720-1资料
1052720-1 Product DetailsHome | Customer Support | Suppliers | Site Map | Privacy Policy | Browser Support© 2008 Tyco Electronics Corporation All Rights Reserved SearchProducts Documentation Resources My Account Customer Support Home > Products > By Type > RF & Coax > Product Feature Selector > Product Details1052720-1Active SMA/QMA RF ConnectorsAlways EU RoHS/ELV Compliant (Statement of Compliance)Product Highlights:?Connector?Jack?Connector Type = SMA?Without Snap-Lock?Terminate To Printed Circuit BoardView all Features | Find SimilarProductsCheck Pricing &AvailabilitySearch for ToolingProduct FeatureSelectorContact Us AboutThis ProductQuick LinksDocumentation & Additional InformationProduct Drawings:?OSM 4 HOLE FLANGE MOUNT JACK RECEPTACLE-SLOT TERMINAL (PDF, English)Catalog Pages/Data Sheets:?None AvailableProduct Specifications:?None AvailableApplication Specifications:?None AvailableInstruction Sheets:?None AvailableCAD Files:?None AvailableList all Documents Additional Information:?Product Line InformationRelated Products:?ToolingProduct Features (Please use the Product Drawing for all design activity)Product Type Features:?Product Type = Connector?Gender = Jack?Connector Type = SMA?Body Style = Straight?Number of Panel Mount Holes = 4?PCB Mount Angle = Vertical?Body Material = Stainless Steel?Body Finish = Passivated?Center Contact = With?Retractable Collar = Without?Safety Wire Holes = Without?Dielectric Material = PTFE FluorocarbonMechanical Attachment:?Panel Attachment = With?Panel Attachment Method = Flange?Panel Attachment Style = Front MountElectrical Characteristics:?Impedance (?) = 50 Body Related Features:?Snap-Lock = Without?Length (mm [in]) = 9.53 [0.375]Contact Related Features:?Contact Type = Slot Terminal?Center Contact Material = Beryllium Copper?Center Contact Plating = GoldIndustry Standards:?Government/Industry Qualification = No?RoHS/ELV Compliance = RoHS compliant, ELVcompliant?Lead Free Solder Processes = Wave soldercapable to 240°C, Wave solder capable to 260°C, Wave solder capable to 265°C, Reflowsolder capable to 245°C, Reflow solder capableto 260°C, Pin-in-Paste capable to 245°C, Pin-in-Paste capable to 260°C?RoHS/ELV Compliance History = Always wasRoHS compliantConditions for Usage:?Terminate To = Printed Circuit BoardOther:?Brand = AMPProvide Website Feedback | Contact Customer Support。
X25323S8-2.7资料
64K 32K 16K X25643/45X25323/25X25163/658K x 8 Bit4K x 8 Bit2K x 8 BitProgrammable Watchdog Timer & V CC Supervisory Circuit w/Serial E2PROMFEATURES•Programmable Watchdog Timer•Low Vcc Detection and Reset Assertion—Reset Signal Valid to Vcc=1V•Save Critical Data With Block Lock TM Protection —Block Lock TM Protect 0, 1/4, 1/2 or all of Serial E2PROM Memory Array•In Circuit Programmable ROM Mode•Long Battery Life With Low Power Consumption —<50µA Max Standby Current, Watchdog On —<1µA Max Standby Current, Watchdog Off—<5mA Max Active Current during Write—<400µA Max Active Current during Read• 1.8V to 3.6V, 2.7V to 5.5V and 4.5V to 5.5V Power Supply Operation•2MHz Clock Rate•Minimize Programming Time—32 Byte Page Write Mode—Self-Timed Write Cycle—5ms Write Cycle Time (Typical)•SPI Modes (0,0 & 1,1)•Built-in Inadvertent Write Protection—Power-Up/Power-Down Protection Circuitry —Write Enable Latch—Write Protect Pin•High Reliability•Available Packages—14-Lead SOIC (X2564x)—14-Lead TSSOP (X2532x, X2516x)—8-Lead SOIC (X2532x, X2516x)DESCRIPTIONThese devices combine three popular functions, Watch-dog Timer, Supply Voltage Supervision, and Serial E2PROM Memory in one package. This combination low-ers system cost, reduces board space requirements, and increases reliability.The Watchdog Timer provides an independent protection mechanism for microcontrollers. During a system failure, the device will respond with a RESET/RESET signal after a selectable time-out interval. The user selects the interval from three preset values. Once selected, the interval does not change, even after cycling the power. The user’s system is protected from low voltage condi-tions by the device’s low Vcc detection circuitry. When Vcc falls below the minimum Vcc trip point, the system is reset. RESET/RESET is asserted until Vcc returns to proper operating levels and stabilizes.The memory portion of the device is a CMOS Serial E2PROM array with Xicor’s Block Lock TM Protection. The array is internally organized as x 8. The device features a Serial Peripheral Interface (SPI) and software protocol allowing operation on a simple four-wire bus.The device utilizes Xicor’s proprietary Direct Write TM cell, providing a minimum endurance of 100,000 cycles per sector and a minimum data retention of 100 years.BLOCK DIAGRAMRESET/RESET7036 FRM 01元器件交易网X25643/45 X25323/25 X25163/65PIN DESCRIPTIONSSerial Output (SO)SO is a push/pull serial data output pin. During a read cycle, data is shifted out on this pin. Data is clocked out by the falling edge of the serial clock.Serial Input (SI)SI is a serial data input pin. All opcodes, byte addresses, and data to be written to the memory are input on this pin. Data is latched by the rising edge of the serial clock. Serial Clock (SCK)The Serial Clock controls the serial bus timing for data input and output. Opcodes, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin change after the falling edge of the clock input.Chip Select (CS)When CS is HIGH, the device is deselected and the SO output pin is at high impedance and unless a nonvolatile write cycle is underway, the device will be in the standby power mode. CS LOW enables the device, placing it in the active power mode. It should be noted that after power-up, a HIGH to LOW transition on CS is required prior to the start of any operation.Write Protect (WP)When WP is low and the nonvolatile bit WPEN is “1”, nonvolatile writes to the device’s Status Register are disabled, but the part otherwise functions normally. When WP is held high, all functions, including nonvolatile writes to the Status Register operate normally. If an internal Status Register Write Cycle has already been initiated, WP going low while WPEN is a “1” will have no effect on this write. Subsequent write attempts to the Status Register under these conditions will be disabled.The WP pin function is blocked when the WPEN bit in the Status Register is “0”. This allows the user to install the device in a system with WP pin grounded and still be able to program the Status Register. The WP pin functions will be enabled when the WPEN bit is set to a “1”.Reset (RESET/RESET)RESET/RESET is an active LOW/HIGH, open drain out-put which goes active whenever Vcc falls below the mini-mum Vcc sense level. It will remain active until Vcc rises above the minimum Vcc sense level for 200ms. RESET/ RESET will also go active if the Watchdog Timer is enabled and CS remains either HIGH or LOW longer than the selectable Watchdog time-out period. A falling edge of CS will reset the Watchdog Timer.PIN CONFIGURATIONPIN NAMES7036 FRM T01 Symbol DescriptionCS Chip Select InputSO Serial OutputSI Serial InputSCK Serial Clock InputWP Program Protect InputV SS GroundV CC Supply VoltageRESET/RESET Reset Output元器件交易网X25643/45X25323/25 X25163/65PRINCIPLES OF OPERATIONThe device is designed to interface directly with the syn-chronous Serial Peripheral Interface (SPI) of many popu-lar microcontroller families.The device monitors the bus and asserts RESET/RESET output if there is no bus activity within user programmable time-out period or the supply voltage falls below a preset minimum V trip. The device contains an 8-bit instruction register. It is accessed via the SI input, with data being clocked in on the rising edge of SCK. CS must be LOW during the entire operation.All instructions (T able 1), addresses and data are trans-ferred MSB first. Data input on the SI line is latched on the first rising edge of SCK after CS goes LOW. Data is out-put on the SO line by the falling edge of SCK. SCK is static, allowing the user to stop the clock and then start it again to resume operations where left off.Write Enable LatchThe device contains a Write Enable Latch. This latch must be SET before a Write Operation is initiated. The WREN instruction will set the latch and the WRDI instruction will reset the latch (Figure 3). This latch is automatically reset upon a power-up condition and after the completion of a valid Write Cycle.Status RegisterThe RDSR instruction provides access to the Status Reg-ister. The Status Register may be read at any time, even during a Write Cycle. The Status Register is formatted as follows:The Write-In-Progress (WIP) bit is a volatile, read only bit and indicates whether the device is busy with an internal nonvolatile write operation. The WIP bit is read using the RDSR instruction. When set to a “1”, a nonvolatile write operation is in progress. When set to a “0”, no write is in progress.The Write Enable Latch (WEL) bit indicates the Status of the Write Enable Latch. When WEL=1, the latch is set HIGH and when WEL=0 the latch is reset LOW. The WEL bit is a volatile, read only bit. It can be set by the WREN instruction and can be reset by the WRDS instruction.The Block Lock bits, BL0 and BL1, set the level of Block Lock TM Protection. These nonvolatile bits are pro-grammed using the WRSR instruction and allow the user to protect one quarter, one half, all or none of the E 2 PROM array . Any portion of the array that is Block Lock Protected can be read but not written. It will remain pro-tected until the BL bits are altered to disable Block Lock Protection of that portion of memory.. 7036 FRM T037654321WPEN FLB WD1WD0BL1BL0WELWIP7036 FRM T02Status Register Bits Array Addresses Protected BL1BL0X2564xX2532xX2516x00NoneNoneNone01$1800–$1FFF $0C00–$0FFF $0600–$07FF 10$1000–$1FFF $0800–$0FFF $0400–$07FF 11$0000–$1FFF $0000–$0FFF $0000–$07FFTable 1. Instruction Set *Instructions are shown MSB in leftmost position. Instructions are transferred MSB first.7036 FRM T04Instruction NameInstruction Format*OperationWREN 0000 0110Set the Write Enable Latch (Enable Write Operations)SFLB 0000 0000Set Flag BitWRDI/RFLB 0000 0100Reset the Write Enable Latch/Reset Flag Bit RSDR 0000 0101Read Status RegisterWRSR 0000 0001Write Status Register(Watchdog,BlockLock,WPEN & Flag Bits)READ 0000 0011Read Data from Memory Array Beginning at Selected Address WRITE0000 0010Write Data to Memory Array Beginning at Selected Address元器件交易网X25643/45X25323/25 X25163/65The Watchdog Timer bits, WD0 and WD1, select the Watchdog Time-out Period. These nonvolatile bits are programmed with the WRSR instruction. 7036 FRM T05The read only FLAG bit shows the status of a volatile latch that can be set and reset by the system using the SFLB and RFLB instructions. The Flag bit is automatically reset upon power up.The nonvolatile WPEN bit is programmed using the WRSR instruction. This bit works in conjunction with the WP pin to provide Programmable Hardware Write Protec-tion (T able 2). When WP is LOW and the WPEN bit is pro-grammed HIGH, all Status Register Write Operations are disabled.In Circuit Programmable ROM ModeThis mechanism protects the Block Lock and Watchdog bits from inadvertant corruption. It may be used to per-form an In Circuit Programmable ROM function by hard-wiring the WP pin to ground, writing and Block Locking the desired portion of the array to be ROM, and then pro-gramming the WPEN bit HIGH.Read SequenceWhen reading from the E 2 PROM memory array, CS is first pulled low to select the device. The 8-bit READ instruction is transmitted to the device, followed by the 16-bit address. After the READ opcode and address aresent, the data stored in the memory at the selected address is shifted out on the SO line. The data stored in memory at the next address can be read sequentially by continuing to provide clock pulses. The address is auto-matically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached, the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely .The read operation is terminated by taking CS high. Refer to the Read E 2 PROM Array Sequence (Figure 1).T o read the Status Register, the CS line is first pulled low to select the device followed by the 8-bit RDSR instruc-tion. After the RDSR opcode is sent, the contents of the Status Register are shifted out on the SO line. Refer to the Read Status Register Sequence (Figure 2).Write SequencePrior to any attempt to write data into the device, the “Write Enable” Latch (WEL) must first be set by issuing the WREN instruction (Figure 3). CS is first taken LOW,then the WREN instruction is clocked into the device.After all eight bits of the instruction are transmitted, CS must then be taken HIGH. If the user continues the Write Operation without taking CS HIGH after issuing the WREN instruction, the Write Operation will be ignored.T o write data to the E 2 PROM memory array, the user then issues the WRITE instruction followed by the 16 bit address and then the data to be written. Any unused address bits are specified to be “0’s”. The WRITE opera-tion minimally takes 32 clocks. CS must go low and remain low for the duration of the operation. If the address counter reaches the end of a page and the clock contin-ues, the counter will roll back to the first address of the page and overwrite any data that may have been previ-ously written.Status Register Bits Watchdog Time-out(Typical)WD1WD000 1.4 Seconds 01600 Milliseconds 10200 Milliseconds11DisabledTable 2. Block Protect Matrix 7036 FRM T06STATUS REGISTER STATUS REGISTER DEVICE PIN BLOCK BLOCK STATUS REGISTER WELWPENWP#PROTECTED BLOCKUNPROTECTEDBLOCKWPEN, BL0, BL1WD0, WD1, BITS0X X Protected Protected Protected 110Protected Writable Protected 10X Protected Writable Writable 1X1ProtectedWritableWritable元器件交易网X25643/45 X25323/25 X25163/65For the Page Write Operation (byte or page write) to be completed, CS can only be brought HIGH after bit 0 of the last data byte to be written is clocked in. If it is brought HIGH at any other time, the write operation will not be completed (Figure 4).T o write to the Status Register, the WRSR instruction is followed by the data to be written (Figure 5). Data bits 0and 1 must be “0” .While the write is in progress following a Status Register or E 2 PROM Sequence, the Status Register may be read to check the WIP bit. During this time the WIP bit will be high.RESET/RESET OperationThe RESET (X25xx3) output is designed to go LOW whenever V CC has dropped below the minimum trip point and/or the Watchdog timer has reached its programmable time-out limit.The RESET (X25xx5) output is designed to go HIGH whenever V CC has dropped below the minimum trip point and/or the watchdog timer has reached its programmable time-out limit.The RESET/RESET output is an open drain output and requires a pull up resistor.Operational NotesThe device powers-up in the following state:•The device is in the low power standby state.• A HIGH to LOW transition on CS is required to enter an active state and receive an instruction.•SO pin is high impedance.•The Write Enable Latch is reset.•The Flag Bit is reset.•Reset Signal is active for t PURST .Data ProtectionThe following circuitry has been included to prevent inad-vertent writes:• A WREN instruction must be issued to set the Write Enable Latch.•CS must come HIGH at the proper clock count in order to start a nonvolatile write cycle.Figure 1. Read E 2PROM Array Sequence元器件交易网元器件交易网X25643/45X25323/25X25163/65Figure 2. Read Status Register SequenceFigure 3. Write Enable Latch SequenceCS01234567SCKSIHIGH IMPEDANCESO7036 FRM05X25643/45 X25323/25 X25163/65Figure 4. Write SequenceFigure 5. Status Register Write SequenceSymbol Table元器件交易网X25643/45 X25323/25 X25163/65D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)7036 FRM T09POWER-UP TIMING 7036 FRM T10CAPACITANCE T A = +25 ° C, f = 1MHz, V CC = 5V. Notes:(1) V IL min. and V IH max. are for reference only and are not tested. 7036 FRM T11(2) This parameter is periodically sampled and not 100% tested.Symbol ParameterLimitsUnits Test ConditionsMin.Typ.Max. I CC1 V CC Write Current (Active)5mA SCK = V CC x 0.1/V CC x 0.9 @ 2MHz, SO = OpenI CC2 V CC Read Current (Active)0.4mA SCK = V CC x 0.1/V CC x 0.9 @ 2MHz, SO = OpenI SB1 V CC Standby Current WDT=OFF 1 µ A CS = V CC , V IN = V SS or V CC , VCC = 5.5V I SB2V CC Standby Current WDT=ON 50µA CS = V CC , V IN = V SS or V CC , V CC = 5.5V I SB3V CC Standby Current WDT=ON 20µA CS = V CC , V IN = V SS or V CC , V CC =3.6V I LI Input Leakage Current 0.110µA V IN = V SS to V CC I LO Output Leakage Current 0.110µA V OUT = V SS to V CCV IL (1)Input LOW Voltage –0.5V CC x0.3V V IH (1)Input HIGH Voltage V CC x0.7V CC +0.5V V OL1Output LOW Voltage 0.4V V CC > 3.3V, I OL = 2.1mA V OL2Output LOW Voltage 0.4V 2V < V CC ≤ 3.3V, I OL = 1mA V OL3Output LOW Voltage 0.4V V CC ≤ 2V, I OL = 0.5mA V OH1Output HIGH Voltage V CC –0.8 V V CC > 3.3V, I OH = –1.0mA V OH2Output HIGH Voltage V CC –0.4V 2V < V CC ≤ 3.3V, I OH = –0.4mA V OH3Output HIGH Voltage V CC –0.2V V CC ≤ 2V, I OH = –0.25mA V OLRSReset Output LOW Voltage0.4VI OL = 1mASymbolParameterMin.Max.Unitst PUR (2)Power-up to Read Operation 1ms t PUW (2)Power-up to Write Operation5msSymbolTestMax.UnitsConditionsC OUT (2)Output Capacitance (SO, RESET, RESET)8pF V OUT = 0V C IN (2)Input Capacitance (SCK, SI, CS, WP)6pFV IN = 0VABSOLUTE MAXIMUM RATINGS*T emperature under Bias ........................–65°C to +135°C Storage T emperature .............................–65°C to +150°C Voltage on any Pin with Respect to V SS .......–1.0V to +7V D.C. Output Current....................................................5mA Lead T emperature (Soldering, 10 seconds)............300°C RECOMMENDED OPERATING CONDITIONS7036 FRM T07*COMMENTStresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.This is a stress rating only and the functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.7036 FRM T08TempMin.Max.Commercial 0°C 70°C Industrial–40°C+85°CSupply Voltage LimitsX25xxx –1.8 1.8V-3.6V X25xxx –2.7 2.7V to 5.5V X25xxx4.5V-5.5V元器件交易网X25643/45 X25323/25 X25163/65A.C. CHARACTERISTICS (Over recommended operating conditions, unless otherwise specified)Data Input Timing7036 FRM T13Symbol Parameter Voltage RangeMin.Max.Unitsf SCK Clock Frequency 2.7V–5.5V 1.8V–3.6V 021MHz t CYC Cycle Time 2.7V–5.5V 1.8V–3.6V 5001000ns t LEAD CS Lead Time 2.7V–5.5V 1.8V–3.6V 250500ns t LAG CS Lag Time 2.7V–5.5V 1.8V–3.6V 250500ns tWH Clock HIGH Time 2.7V–5.5V 1.8V–3.6V 200400ns t WL Clock LOW Time 2.7V–5.5V 1.8V–3.6V 200400ns t SU Data Setup Time 2.7V–5.5V 1.8V–3.6V 50ns t H Data Hold Time 2.7V–5.5V 1.8V–3.6V 50nst RI (3)Input Rise Time 2.7V–5.5V 1.8V–3.6V 100ns t FI (3)Input Fall Time 2.7V–5.5V 1.8V–3.6V 100ns t CS CS Deselect Time 2.7V–5.5V 1.8V–3.6V 500ns t WC (4)Write Cycle Time2.7V–5.5V 1.8V–3.6V10msEQUIVALENT A.C. LOAD CIRCUIT AT 5V V CCA.C. TEST CONDITIONS 7036 FRM T12Input Pulse Levels V CC x 0.1 to V CC x 0.9Input Rise and Fall Times 10ns Input and Output Timing LevelV CC x0.5元器件交易网X25643/45 X25323/25 X25163/65Data Output Timing7036 FRM T14Notes:(3) This parameter is periodically sampled and not 100% tested.(4) t WC is the time from the rising edge of CS after a valid write sequence has been sent to the end of the self-timed internal nonvolatile write cycle.Symbol ParameterVoltage RangeMin.Max.Unitsf SCK Clock Frequency 2.7V–5.5V 1.8V–3.6V 021MHz t DIS Output Disable Time 2.7V–5.5V 1.8V–3.6V 250ns t V Output Valid from Clock Low 2.7V–5.5V 1.8V–3.6V 200400ns t HO Output Hold Time 2.7V–5.5V 1.8V–3.6V 0nst RO (3)Output Rise Time 2.7V–5.5V 1.8V–3.6V 100ns t FO (3)Output Fall Time2.7V–5.5V 1.8V–3.6V100ns元器件交易网Serial Output TimingSerial Input TimingPower-Up and Power-Down TimingRESET Output Timing 7036 FRM T15Notes:(5) This parameter is periodically sampled and not 100% tested.CS vs. RESET/RESET TimingRESET/RESET Output Timing 7036 FRM T16Symbol ParameterMin.Typ.Max.UnitsV TRIP Reset Trip Point Voltage, 5V Device Reset Trip Point Voltage, 2.7V Device Reset Trip Point Voltage, 1.8V Device 4.252.551.7 4.52.71.8V V V t PURST Power-up Reset Timeout 100200280ms t RPD (5)V CC Detect to Reset/Output 500ns t F (5)V CC Fall Time 0.1ns t R (5)V CC Rise Time 0.1ns V RVALIDReset Valid V CC1VSymbol ParameterMin.Typ.Max.Unitst WDO Watchdog Timeout Period, WD1 = 1, WD0 = 0 WD1 = 0, WD0 = 1 WD1 = 0, WD0 = 010045012006001.43008002ms ms sec t CST CS Pulse Width to Reset the Watchdog 400nst RSTReset Timeout100200300msPACKAGING INFORMATION0.014 (0.35)0.020 (0.51)(4X) 714-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE SNOTE: ALL DIMENSIONS IN INCHES (IN PARENTHESES IN MILLIMETERS)0.0075 (0.19)0.010 (0.25)X25643/45 X25323/25 X25163/650.014 (0.35)0.019 (0.49)(4X) 70.0075 (0.19)0.010 (0.25)8-LEAD PLASTIC SMALL OUTLINE GULL WING P ACKAGE TYPE SNOTE:ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS)元器件交易网NOTE:ALL DIMENSIONS IN INCHES (IN P ARENTHESES IN MILLIMETERS)14-LEAD PLASTIC, TSSOP, P ACKAGE TYPE V0° – 8Gage PlaneSeating PlaneDetail A (20X)LIMITED WARRANTYDevices sold by Xicor, Inc. are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. Xicor, Inc.makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. Xicor, Inc. makes no warranty of merchantability or fitness for any purpose. Xicor, Inc. reserves the right to discontinue production and change specifications and prices at any time and without notice.Xicor, Inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a Xicor, Inc. product. No other circuits, patents,licenses are implied.U.S. PATENTSXicor products are covered by one or more of the following U.S. Patents: 4,263,664; 4,274,012; 4,300,212; 4,314,265; 4,326,134; 4,393,481;4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829, 482; 4,874, 967;4,883, 976. Foreign patents and additional patents pending.LIFE RELATED POLICYIn situations where semiconductor component failure may endanger life, system designers using this product should design the system with appropriate error detection and correction, redundancy and back-up features to prevent such an occurence.Xicor’s products are not authorized for use in critical components in life support devices or systems.1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.ORDERING INFORMATIONPart Mark Convention DeviceV CC LimitsBlank = 5V ±10%2.7 = 2.7V to 5.5V 1.8 = 1.8V to 3.6VTemperature RangeBlank = Commercial = 0°C to +70°C I = Industrial = –40°C to +85°C PackageS14 = 14-Lead SOIC S8 = 8-Lead SOIC V14 = 14-Lead TSSOPBlank = 14-Lead SOICBlank = 5V ±10%, 0°C to +70°C I = 5V ±10%, –40°C to +85°C F = 2.7V to 5.5V , 0°C to +70°C G = 2.7V to 5.5V , –40°C to +85°C AG = 1.8V to 3.6V , 0°C to +70°C X25643/45P T -VX25643/45X XX25323/25X25163/65Blank = 8-Lead SOIC V = 14 Lead TSSOPBlank = 5V ±10%, 0°C to +70°C I = 5V ±10%, –40°C to +85°C F = 2.7V to 5.5V , 0°C to +70°C G = 2.7V to 5.5V , –40°C to +85°C AG = 1.8V to 3.6V , 0°C to +70°C X25323/25X XX25163/65。
改性塑料属性表
一、改性PP系列:改性PP系列材料系根据相关行业制品对材料的具体要求而制定的,在材料的强度、韧性与加工性能方面有着优异平衡性的系列材料,可以用注射、模压、挤出等方法成型,广泛应用于汽车、电器等行业。
注:上表中数据为产品实测性能,真实可靠,采用注射成型样片得到,仅供参考,不能作为材料标准值。
可以根据客户的要求制作各类产品或在相应的范围内调整。
二、超韧PP系列:超韧PP系列材料具有优异的韧性与强度的平衡性,特别是优异的低温特性,可以用注射、模压、挤出等方法成型,广泛应用于汽车、电器等行业。
注:上表中数据为产品实测性能,真实可靠,采用注射成型样片得到,仅供参考,不能作为材料标准值。
可以根据客户的要求制作各类产品或在相应的范围内调整。
三、填充PP系列:填充PP系列材料系矿粉填充改性PP系列材料,具有高硬度、高刚性、较高的耐热性能以及良好的冲击韧性,可以用注射、模压、挤出等方法成型,广泛应用于汽车、电器等行业。
注:上表中数据为产品实测性能,真实可靠,采用注射成型样片得到,仅供参考,不能作为材料标准值。
可以根据客户的要求制作各类产品或在相应的范围内调整。
推荐注射成型工艺参数ABS系列ABS系列材料在机械性能、加工性能、表面光泽度、配色性能等方面都有优秀表现,可以用注射、模压、一、电镀ABS/阻燃ABS/消光ABS:注:上表中数据为产品实测性能,真实可靠,采用注射成型样片得到,仅供参考,不能作为材料标准值。
可以根据客户的要求制作各类产品或在相应的范围内调整。
二、超韧PP系列:超韧PP系列材料具有优异的韧性与强度的平衡性,特别是优异的低温特性,可以用注射、模压、挤出等方法成型,广泛应用于汽车、电器等行业。
产品特性注:上表中数据为产品实测性能,真实可靠,采用注射成型样片得到,仅供参考,不能作为材料标准值。
可以根据客户的要求制作各类产品或在相应的范围内调整。
一、PC/ABS系列:改性PC/ABS系列材料系PC与ABS共混改性合金系列材料,具有优异的强度、韧性以及耐热性能,产品的尺寸稳定性好,可以用注射、模压、挤出等方法成型,广泛应用于汽车、电子、电器等行业。
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Micropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.Micropac reserves the right to make changes at any time in order to improve design and to supply the best product possible.53272 POWER MOSFET OPTOCOUPLER± 90V – 2.0AMiiMICROPAC INDUSTRIES MICROCIRCUITS PRODUCTSDIVISIONFeatures: • Performance over –55°C to +125°C• Compact Solid State Bi-directional Switch • AC/DC Power Switching •Maximum Average Current AC/DC: 1.0 A (1) DC only: 2.0 A (1) • Optically Coupled• Input/Output Isolation Tested to 1000 VDC • High Level of Transient Immunity • 3 A Output Surge Current• Shock and Vibration Resistant • MIL-PRF-38534• Electrically Similar to the 53124Applications:• Satellite/Space systems • Military/High Reliability Systems• Standard 28 VDC and 48 VDC Load Driver • Standard 24 VAC Load Driver • Aircraft Controls• AC/DC Electromechanical and Solid StateRelay Replacement • I/O Modules • Switching HeatersDESCRIPTIONThe 53272 is a single channel power MOSFET optocoupler expanding upon the electrical performance of Mii P/N 53124 with reduced R DS(ON) and increased current capability.Performance is specified over the full military temperature range. Functionally, the device operates as a single-pole, normally open (1 Form A) solid-state relay. The device is actuated by an input current, which can be supplied from standard logic types such as open-collector TTL. The input current biases a light emitting diode that is optically coupled to an integrated photovoltaic diode array. The photovoltaic array powers control circuitry that operates the output MOSFETs. Optimum switching of either AC or DC loads is provided by a configurable output. For AC loads, Connection A in Figure 1 must be used. Connection A will also switch DC loads but Connection B, in Figure 1, provides DC-only operation with the advantages of substantial reduction in on-resistance and twice the output current capability as that obtained with Connection A.Micropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.Micropac reserves the right to make changes at any time in order to improve design and to supply the best product possible.53272 Power MOSFET Optocoupler ABSOLUTE MAXIMUM RATINGS:Storage Temperature Range ..……………………………………………………….........……............... -65°C to +150°C Operating Ambient Temperature - T A ...................…………………………………………..….…..….. -55°C to +125°C Junction Temperature - T J ..............................……………………………………………...…….......….........…. +150°C Operating Case Temperature - T c .....................………………………………………...……….……............ +145°C (2) Lead Solder Temperature for 10 seconds .......................………………………………………....…….............. +260°C (1.6 mm below seating plane) Average Input Current - I F ....................…...……………………………………………..……..........…............... 20 mA Peak Repetitive Input Current - I Fpk .............…………………………………...…………………........…............. 40 mA (Pulse width < 100 ms; duty cycle < 50%) Peak Surge Input Current - I Fpk surge .............……………………………………………………….................. 100 mA (Pulse width < 0.2 ms; duty cycle < 0.1%) Reverse Input Voltage - V R ................................…………………………..……………………………..................... 5 V Average Output CurrentConnection A - I O ........................…………………………..…………………..……….................................... 1.0 A (1) Connection B - I O ..............................................………..………………………..……………………............ 2.0 A (1) Average Output Current, derated per Figure 3Connection A - I O .......................................…………………………………………..……………..................... 0.8 A Connection B - I O ........................................……………………………………………………..….................... 1.6 A Single Shot Output Current - Figure 4Connection A - I Opk surge (Pulse width < 10 ms) ........………………………………………..…...…………...... 4 A Connection B - I Opk surge (Pulse width < 10 ms) .........………………………………………..………………..... 8 A Output VoltageConnection A - V O .........................……………………………………………………..……..…......... –90 V to +90 V Connection B - V O ............................…...……………………………………………………….............. 0 V to +90 V Average Output Power Dissipation - Figure 5 ........………………………………………….…………….... 800 mW (3)RECOMMENDED OPERATING CONDITIONS:Parameter Symbol Min. Max. Units Input Current (ON) I F (ON) 5 20 mA Input Voltage (OFF)V F (OFF) 0 0.6 VDC Operating TemperatureT A -55+125 °CMicropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.Micropac reserves the right to make changes at any time in order to improve design and to supply the best product possible.53272 Power MOSFET OptocouplerELECTRICAL SPECIFICATIONS T A = -55°C to +125°C, unless otherwise specified.* All typical values are at T A = 25°C, I F (ON) = 10 mA, V F (OFF) = 0.6 V unless otherwise specified.53272 Power MOSFET Optocoupler TYPICAL CHARACTERISTICSAll typical values are at T A = 25°C, I F (ON) = 10 mA, V F (OFF) = 0.6 V unless otherwise specified.Notes:1. Maximum average current rating where the case temperature (T C) is maintained below 120°C.2. Maximum junction to case thermal resistance for the device is 15°C/W, where case temperature (T C) ismeasured at the center of the package bottom.3. For rating, see Figure 5. The output power P D rating curve is obtained when the part is handling the maximumaverage output current I O as shown in Figure 3.4. During the pulsed R ON measurement (I O duration < 30 ms), ambient (T A) and case temperature (T C) are equal.5. Pins 2 through 3 shorted together and pins 5 through 8 shorted together.6. This is a momentary withstand test, not an operating condition.7. V OS is a function of I F and is defined between pins 5 and 8, with pin 5 as the reference. V OS must be measuredin a stable ambient (free of temperature gradients).8. Zero-bias capacitance measured between the LED anode and cathode.CAUTION:Care should be taken not to exceed the maximum output power dissipation, maximum case temperature, and maximum junction temperature when repetitively switching loads.Micropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.Micropac reserves the right to make changes at any time in order to improve design and to supply the best product possible.53272 Power MOSFET OptocouplerMicropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.Micropac reserves the right to make changes at any time in order to improve design and to supply the best product possible.Micropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.Micropac reserves the right to make changes at any time in order to improve design and to supply the best product possible.53272 Power MOSFET OptocouplerMicropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.Micropac reserves the right to make changes at any time in order to improve design and to supply the best product possible.53272 Power MOSFET Optocoupler53272 Power MOSFET OptocouplerMicropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.Micropac reserves the right to make changes at any time in order to improve design and to supply the best product possible.Micropac Industries cannot assume any responsibility for any circuits shown or represent that they are free from patent infringement.Micropac reserves the right to make changes at any time in order to improve design and to supply the best product possible.53272Power MOSFET OptocouplerPackage DimensionsOrdering Information53272E Engineering Unit Non-Rad Version 53272-102ETU Rad Version No Screening 53272-108Rad Version Screened to H+ PIND53272-XXX TBD。