EDA-常见实例源程序代码vhdl(可编辑修改word版)

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VHDL程序范例使用说明

VHDL 程序举例文件夹中包括下面程序--------------------------------------------------------------------------------NOTE：该程序参考FPGA中文网站重要说明：不同软件对VHDL语法的支持范围是不一样的，以下程序中的某些语句可能不能运行在所有的软件平台之上，因此程序可能要作一些修改，同时务必注意阅读程序中的注释。

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组合逻辑：最高优先级编码器8位相等比较器三人表决器（三种不同的描述方式）加法器描述8位总线收发器：74245 （注2）地址译码（for m68008）多路选择器（使用select语句）LED七段译码（注1）多路选择器（使用if－else语句）双2－4译码器：74139多路选择器（使用when－else语句）汉明纠错吗编码器双向总线（注2）汉明纠错吗译码器三态总线（注2）时序逻辑：四D触发器：74175 用状态机实现的计数器简单的锁存器各种功能的计数器简单的12位寄存器通用寄存器带load、clr等功能的寄存器带三态输出的8位D寄存器：74374（注2）移位寄存器：74164存储器举例：(注3)FIFO状态机举例：一个简单的状态机莫尔型状态机1使用列举类型的状态机莫尔型状态机2带同步复位的状态机米勒型状态机使用变量的状态机带莫尔/米勒输出的状态机测试向量（Test Bench）举例：加法器源程序相应加法器的测试向量（test bench)波形发生器（含test beach）(注1) 经典双进程状态机（含test beach）其他设计举例：伪随机数产生器一个简单的UART步进电机控制器一个游戏程序直流电机控制器布斯乘法器伪随机比特发生器注1：含有不可综合语句，请自行修改注2：一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL 程序中。

EDA 常见实例源程序代码vhdl

第4章用VHDL程序实现常用逻辑电路4.1 组合逻辑电路设计4.1.1 基本逻辑门library ieee;use iee.std_logic_1164.all;entity jbm isport(a,b: in bit;f1,f2,f3,f4,f5,f: out bit);end jbm;architecture a of jbm isbeginf1<=a and b; --构成与门f2<=a or b; --构成或门f<=not a; --构成非门f3<=a nand b; --构成与非门f4<=a nor b; --构成异或门f5<=not(a xor b); --构成异或非门即同门end;4.1.2 三态门library ieee;use ieee.std_logic_1164.all;entity tri_s isport(enable: in std_logic;datain: in std_logic_vector(7 downto 0);dataout: out std_logic_vector(7 downto0));end tri_s;architecture bhv of tri_s isbeginprocess(enable,datain)beginif enable='1' thendataout<=datain;elsedataout<="ZZZZZZZZ";end if;end process;end bhv;4.1.3 3-8译码器library ieee;use ieee.std_logic_1164.all;entity decoder3_8 isport(a,b,c,g1,g2a,g2b: in std_logic;y: out std_logic_vector(7 downto 0));end decoder3_8;architecture a of decoder3_8 issignal dz:std_logic_vector(2 downto 0);begindz<=c&b&a;process (dz,g1,g2a,g2b)beginif(g1='1'and g2a='0'and g2b='0')thencase dz iswhen "000"=> y<="11111110";when "001"=> y<="11111101";when "010"=> y<="11111011";when "011"=> y<="11110111";when "100"=> y<="11101111";when "101"=> y<="11011111";when "110"=> y<="10111111";when "111"=> y<="01111111";when others=>y<="XXXXXXXX";end case;elsey<="11111111";end if;end process;4.1.4 优先编码器library ieee;use ieee.std_logic_1164.allentity coder isport(din: in std_logic_vector(0 to 7);output: out std_logic_vector(0 to 2));end coder;architecture behave of coder issignal sint: std_logic_vevtor(4 downto 0);beginprocess(din)beginif (din(7)='0') thenoutput <= "000" ;elsif (din(6)='0') thenoutput <= "100" ;elsif (din(5)='0') thenoutput <= "010" ;elsif (din(4)='0') thenoutput <= "110" ;elsif (din(3)='0') thenoutput <= "001" ;elsif (din(2)='0') thenoutput <= "101" ;elsif (din(1)='0') thenoutput <= "011" ;elseoutput <= "111" ;end if;end process;end behav;4.1.5 7段码译码器library ieee;use ieee.std_logic_1164.allentity decl7s isport (a: in std_logic_vector (3 downto 0);led7s: out std_logic_vector(6 downto 0));end decl7s;architecture behave of decl7s isbeginprocess(a)begincase a iswhen "0000" => led7s <= "0111111" ;when "0001" => led7s <= "0000110" ;when "0010" => led7s <= "1011011" ;when "0011" => led7s <= "1001111" ;when "0100" => led7s <= "1100110" ;when "0101" => led7s <= "1101101" ;when "0110" => led7s <= "1111101" ;when "0111" => led7s <= "0000111" ;when "1000" => led7s <= "1111111" ;when "1001" => led7s <= "1101111" ;when "1010" => led7s <= "1110111" ;when "1011" => led7s <= "1111100" ;when "1100" => led7s <= "0111001" ;when "1101" => led7s <= "1011110" ;when "1110" => led7s <= "1111001" ;when "1111" => led7s <= "1110001" ;when others => null;end case;end process;end behave;4.1.6二-十进制BCD译码器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity bcdymq isport(din : in integer range 15 downto 0;a,b : out integer range 9 downto 0);end;architecture fpq1 of bcdymq isbeginp1: process(din)beginif din<10 thena< =din;b< =0;elsea< =din-10;end if;end process p1;end;4.1.7 多位加（减）法器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity jianfaqi isport(a,b : in std_logic_vector(0 to 3);c0: in std_logic;c1: out std_logic;d : out std_logic_vector(0 to 3));end;architecture a of jianfaqi isbeginprocessbeginif a>b+c0 thend<=a-(b+c0);c1<='0';elsec1<='1';d<=("10000")-(b+c0-a);end if;end process ;end ;4.2 时序逻辑电路设计4.2.1 触发器RS触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity rsff isport(r,s,clk:in std_logic;q,qb:buffer std_logic);end rsff;architecture rsff_art of rsff issignal q_s,qb_s:std_logic;beginprocess(clk,r,s)beginif (clk'event and clk='1') thenif (s='1' and r='0') thenq_s<='0' ;qb_s<='1' ;elsif (s='0' and r='1') thenq_s <= '1' ;qb_s <= '0' ;elsif (s='0' and r='0') thenq_s <= q_s;qb_s <= qb_s;end if;q_s <= q_s;qb_s <= qb_s;end process;end rsff_art;同步复位D触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity syndff isport(d,clk,reset:in std_logic;q,qb:out std_logic);end syndff;architecture dff_art of syndff isbeginprocess(clk)beginif (clk'event and clk='1') thenif (reset='0') thenq<='0';qb<='1';elseq<=d;qb<=not q;end if;end if;end process;end dff_art;JK触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity asynjkff isport(j,k,clk,set.reset:in std_logic;q,qb:out std_logic);end asynjkff;architecture jkff_art of asynjkff issingal q_s,qb_s:std_logic;beginprocess(clk,set,reset)beginif (set='0' and reset='1' ) thenq_s<='1';qb_s<='0';elsif (set='1' and reset='0' ) thenq_s<='0';qb_s<='1';elsif (clk'event and clk='1') thenif (j='0' and k='1' ) thenq_s<='0';qb_s<='1';elsif (j='1' and k='0' ) thenq_s<='1';qb_s<='0';elsif (j='1' and k='1' ) thenq_s<=not q_s;qb_s<=not qb_s;end if;end if;q<= q_s;qb<= qb_s;end process;end jkff_art;T触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity tff isport(t,clk: in std_logic;q: out std_logic);end;architecture tff_art of tff issignal q_temp: std_logic;beginp1:process(clk)beginif rising_edge(clk) thenif t='1' then --当T=1时T触发器具有2分频的功能q_temp<=not q_temp;elseq_temp<=q_temp;end if;end if;q<=q_temp;end process;q<=q_temp;end tff_art;4.2.2计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 ISport( clk: in std_logic;q: out std_logic_vector(3 downto 0));end cnt4;architecture behave of cnt4 issignal q1: std_logic_vector(3 downto 0);beginprocess(clk)beginif (clk'event and clk = '1') thenq1<=q1+1;end if;end process;q<=q1;一般计数器设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 isport( clk,rst,en,updown: in std_logic;cq: out std_logic_vector(3 downto 0));end cnt10;architecture behave of cnt10 isbeginprocess(clk,rst,en,updown)variable cqi:std_logic_vector(3 downto 0);beginif rst='1' thencqi:=(others=>'0'); --计数器异步复位elsif (clk'event and clk = '1') then --检测时钟上升沿if en='1'then --检测是否允许计数（同步使能）if updown='0'thenif cqi<9 thencqi:=cqi+1; --允许计数,检测是否小于9elsecqi:=(others=>'0'); --大于9，计数值清零end if;elseif cqi>0 thencqi:=cqi-1; --检测是否大于0elsecqi:=(others=>'1'); ---否则，计数值置1end if;end if;end if;end if;cq<=cqi; --将计数值向端口输出end process;end behave;4.2.3 分频器library ieee;use std_logic_1164.all;use std_logic_unsigned.all;entity freq1 isport(clk: in std_logic;d: in std_logic_vector(7 downto 0);fout: out std_logic);end;architecture one of dvf issignal full: std_logic;beginp_reg:process(clk)variable cnt8: std_logic_vector(7 downto 0);if clk'event and clk='1'then --检测时钟上升沿if cnt8=''11111111'' thencnt8:=d; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8full<='1';--同时使溢出标志信号FULL输出为高电平elsecnt8:=cnt8+1;--否则继续作加1计数full<='0'; --且输出溢出标志信号FULL为低电平end if;end if;end process p_reg;p_div:process(full)variable cnt2: std_logic;beginif full'event and full='1' thencnt2:=not cnt2; --如果溢出标志信号FULL为高电平，T触发器输出取反if cnt2='1'thenfout<='1';elsefout<='0';end if;end if;end process p_div;end;4.2.4 移位寄存器library ieee;use ieee.std_logic_1164.all;entity shift isport(clk,c0: in std_logic;--时钟和进位输入md: in std_logic_vector(2 downto 0);--移位模式控制字d: in std_logic_vector(7 downto 0);--待加载移位的数据qb: out std_logic_vector(7 downto 0);--移位数据输出cn: out std_logic);--进位输出end;architecture behave of shift issignal reg: std_logic_vector(7 downto 0);signal cy: std_logic;beginprocess(clk,md,c0)beginif clk'event and clk='1' thencase md iswhen "001" => reg (0) <= c0 ;reg (7 downto 1) <= reg (6 downto 0);cy <= reg (7); --带进位循环左移when "010" => reg (0) <= reg (7);reg (7 downto 1) <= reg (6 downto 0); --自循环左移when "011" => reg (7) <= reg (0);reg (6 downto 0) <= reg (7 downto 1); --自循环右移when "100" => reg (7) <= C0 ;reg (6 downto 0) <= reg (7 downto 1);cy <= reg (0); --带进位循环右移when "101" => reg (7 downto 0) <= d(7 downto 0); --加载待移数when others => reg<= reg ; cy<= cy ; --保持end case;end if;end process;qb(7 downto 0) <= reg (7 downto 0); cn <= cy; --移位后输出end behav;4.3 状态机逻辑电路设计4.3.1 一般状态机设计library ieee;use ieee.std_logic_1164.all;entity s_machine isport ( clk,reset : in std_logic;state_inputs : in std_logic_vector(0 to1);comb_outputs : out integer range 0 to 15 );end s_machine;architecture behv of s_machine istype fsm_st is (s0, s1, s2, s3); --数据类型定义，状态符号化signal current_state, next_state: fsm_st; --将现态和次态定义为新的数据类型beginreg: process(reset,clk) --主控时序进程beginif reset = '1' thencurrent_state <= s0; --检测异步复位信号elsif clk='1' and clk'event thencurrent_state <= next_state;end if;end process;com:process(current_state, state_inputs) --主控组合进程begincase current_state iswhen s0 => comb_outputs<= 5;if state_inputs = "00" thennext_state<=s0;elsenext_state<=s1;end if;when s1 => comb_outputs<= 8;if state_inputs = "00" thennext_state<=s1;elsenext_state<=s2;end if;when s2 => comb_outputs<= 12;if state_inputs = "11" thennext_state <= s0;elsenext_state <= s3;end if;when s3 => comb_outputs <= 14;if state_inputs = "11" thennext_state <= s3;elsenext_state <= s0;end if;end case;end process;end behv;4.3.2状态机的应用library ieee;use ieee.std_logic_1164.all;entity asm_led isport(clk,clr : in std_logic;led1,led2,led3:out std_logic);end;architecture a of asm_led istype states is (s0,s1,s2,s3,s4,s5); --对状态机的状态声明signal q: std_logic_vector( 0 to 2);signal state : states;beginp1: process(clk,clr)beginif(clr='0')thenstate<=s0;elsif (clk'event and clk='1') thencase state iswhen s0=> state <=s1;when s1=> state <=s2;when s2=> state <=s3;when s3=> state <=s4;when s4=> state <=s5;when s5=> state <=s0;when others => state<=s0;end case;end if;end process p1;p2: process (clr,state)beginif(clr='0') thenled1<='0';led2<='0';led3<='0';elsecase state iswhen s0=> led1<='1';led2<='0';led3<='0';when s1=> led1<='0';led2<='1';led3<='0';when s2=> led1<='0';led2<='1';led3<='0';when s3=> led1<='0';led2<='0';led3<='1';when s4=> led1<='0';led2<='0';led3<='1';when s5=> led1<='0';led2<='0';led3<='1';when others => null;end case;end if;end process p2;end ;第6章EDA仿真技术应用实例6.1带使能和片选端的16：4线优先编码器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity pencoder isport(d:in std_logic_vector(7 downto 0);ei:in std_logic; --ei:enable inputgs,eo:out bit; --gs:chip select output;eo:enable outputq2,q1,q0:out std_logic);end pencoder;architecture encoder of pencoder isbeginprocess(d)beginif(d(0)='0' and ei='0')thenq2<='1';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(1)='0' and ei='0')thenq2<='1';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(2)='0' and ei='0')thenq2<='1';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(3)='0' and ei='0')thenq2<='1';q1<='0';q0<='0';gs<='0';eo<='1';elsif(d(4)='0' and ei='0')thenq2<='0';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(5)='0' and ei='0')thenq2<='0';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(6)='0' and ei='0')thenq2<='0';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(7)='0' and ei='0')then --d7 prioty encoderq2<='0';q1<='0';q0<='0';gs<='0';eo<='1';elsif(ei='1')thenq2<='1';q1<='0';q0<='1';gs<='1';eo<='1';elsif(d="11111111" and ei='0')thenq2<='1';q1<='1';q0<='1';gs<='1';eo<='0';end if;end process;end encoder;6.27段显示译码器设计译码器设计源代码：library ieee;use ieee.std_logic_1164.all;entity decoder47 isport(lt,ibr,ib_ybr:in bit;a: in std_logic_vector(3 downto 0);y:out std_logic_vector(6 downto 0));end decoder47;architecture art of decoder47 isbeginprocess(lt,ibr,ib_ybr,a)variable s: std_logic_vector(3 downto 0);begins:=a(3)&a(2)&a(1)&a(0);if lt='0' and ib_ybr='1' theny<="1111111"; --检查七段显示管是否正常elsif ibr='0' and a="0000" theny<="0000000";elsecase s iswhen"0000"=>y<="1111110"; --7Ewhen"0001"=>y<="0110000"; --30when"0010"=>y<="1101101"; --6Dwhen"0011"=>y<="1111001"; --79when"0100"=>y<="0110011"; --33when"0101"=>y<="1011011"; --5Bwhen"0110"=>y<="0011111"; --5Fwhen"0111"=>y<="1110000"; --70when"1000"=>y<="1111111"; --7Ewhen"1001"=>y<="1110011"; --7Bwhen"1010"=>y<="0001101"; --0Dwhen"1011"=>y<="0011001"; --19when"1100"=>y<="0100011"; --23when"1101"=>y<="1001011"; --4Bwhen"1110"=>y<="0001111"; --0Fwhen"1111"=>y<="0000000";end case;end if;end process;end art;6.3带异步清零端的12位二进制全加器设计子模块源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end adder4b;architecture art of adder4b issignal sint:std_logic_vector(4 downto 0);signal aa,bb:std_logic_vector(4 downto 0);beginprocess(clr)beginif clr='1'thensint<="00000";elseaa<='0'&a;bb<='0'&b;sint<=aa+bb+cin;end if;s<=sint(3 downto 0);cout<=sint(4);end process;end art;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder12b isport(clr,cin: in std_logic;a,b: in std_logic_vector(11 downto 0);s: out std_logic_vector(11 downto 0);cout:out std_logic);end adder12b;architecture art of adder12b iscomponent adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end component;signal carry_out1:std_logic;signal carry_out2:std_logic;beginu1:adder4b port map(clr=>clr,cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),s=>s(3 downto 0),cout=>carry_out1);u2:adder4b port map(clr=>clr,cin=>carry_out1,a=>a(7 downto 4),b=>b(7 downto 4),s=>s(7 downto 4),cout=>carry_out2);u3:adder4b port map(clr=>clr,cin=>carry_out2,a=>a(11 downto 8),b=>b(11 downto 8),s=>s(11 downto 8),cout=>cout);end art;6.4 带异步清零/置位端的JK触发器设计带异步清零/置位端的JK触发器源程序如下：library ieee;use ieee.std_logic_1164.all;entity jkff_logic isport(j,k,clk,clr,set:in std_logic;q:out std_logic);end jkff_logic;architecture art of jkff_logic issignal q_s:std_logic;beginprocess(clk,clr,set,j,k)beginif set='0' thenq_s<='1'; --异步置位elsif clr='1' thenq<='0'; --异步复位elsif clk'event and clk='1' thenif (j='0') and (k='1') thenq_s<='0';elsif(j='1') and (k='0') thenq_s<='1';elsif(j='1') and (k='1') thenq_s<=not q_s;end if;end if;q<=q_s;end process;end art;6.5 4位锁存器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity latch1b isport(d: in std_logic;ena: in std_logic; --使能端q: out std_logic);end latch1b;architecture art of latch1b isbeginprocess(d,ena)beginif ena='1' thenq<=d;end if;end process;end art;元件声明程序包设计源代码：library ieee;use ieee.std_logic_1164.all;package my_package iscomponent latch1port(d:in std_logic;ena:in std_logic;q: out std_logic);end component;end;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use work.my_package.all; --使用用户自定义的程序包entity latch4d isport(d: in std_logic_vector(3 downto 0);oen: in bit;q:out std_logic_vector(3 downto 0));end latch4d;architecture one of latch4d issignal sig_save:std_logic_vector(3 downto 0);begingetlatch:for n in 0 to 3 generate --用for_generate语句循环例化4个1位锁存器latchx:latch1 port map(d(n),g,sig_save(n)); --关联end generate;q<=sig_save when oen='0'else"ZZZZ";end one;6.6 32进制多样型计数器设计（1）32进制同步加法计数器源程序32进制同步加法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_plus isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_plus issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr,)beginif clr='1'thend1<=(others=>'0');d0<="0000"; --同步清零elsif clk'event and clk='1' thenif(d1=3 and d0=1)thend1<="0000";d0<="0000"; --计数到32时清零elsif(d0=1) thend0<="0000";d1<=d1+1;elsed0<=d0+1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（2）32进制同步减法计数器源程序32进制同步减法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_sub isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_sub issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr)beginif clr='1' thend1<="0000";d0<="0000"; --异步清零elsif clk'event and clk='1' thenif(d1=0 and d0=0) thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（3）32进制同步可逆计数器源程序32进制同步可逆计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_reversible isport(clk,clr,s:in std_logic; --s=1加法计数，s=0减法计数dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_reversible issignal d0,d1:std_logic_vector(3 downto 0); --d0代表个位，d1代表十位beginprocess(clk,clr,s)beginif clr='1'thend1<="0000";d0<="0000"; --异步清零elsif (clk'event and clk='1' )thenif s='1' thenif(d1=3 and d0=1) thend1<="0000";d0<="0000"; --计数到31时清零elsif(d0=1) thend0<="0000";d1<=d1+1;else d0<=d0+1;end if;elsif s='0' thenif(d1=0 and d0=0)thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（4）32进制异步加法计数器源程序32进制异步加法计数器源程序如下：①子模块D触发器源程序设计。

vhdl语言100例程序

vhdl语言100例程序以下是100个关于VHDL语言的程序示例：1. 用VHDL编写一个计数器模块2. 用VHDL编写一个SR-Latch模块3. 用VHDL编写一个JK-Flip Flop模块4. 用VHDL编写一个D-Flip Flop模块5. 用VHDL编写一个T-Flip Flop模块6. 用VHDL编写一个复位计数器模块7. 用VHDL编写一个移位寄存器模块8. 用VHDL编写一个状态机模块9. 用VHDL编写一个MUX模块10. 用VHDL编写一个DeMUX模块11. 用VHDL编写一个加法器模块12. 用VHDL编写一个减法器模块13. 用VHDL编写一个乘法器模块14. 用VHDL编写一个除法器模块15. 用VHDL编写一个比较器模块16. 用VHDL编写一个位逻辑模块17. 用VHDL编写一个字逻辑模块18. 用VHDL编写一个数据选择器模块19. 用VHDL编写一个FIFO队列模块20. 用VHDL编写一个LIFO栈模块21. 用VHDL编写一个流水线模块22. 用VHDL编写一个中断控制器模块23. 用VHDL编写一个时钟分频器模块24. 用VHDL编写一个IO控制器模块25. 用VHDL编写一个SPI通信控制器模块26. 用VHDL编写一个I2C通信控制器模块27. 用VHDL编写一个UART通信控制器模块28. 用VHDL编写一个哈希函数模块29. 用VHDL编写一个随机数产生器模块30. 用VHDL编写一个CRC校验器模块31. 用VHDL编写一个AES加密算法模块32. 用VHDL编写一个DES加密算法模块33. 用VHDL编写一个SHA加密算法模块34. 用VHDL编写一个MD5加密算法模块35. 用VHDL编写一个RSA加密算法模块36. 用VHDL编写一个卷积滤波器模块37. 用VHDL编写一个峰值检测器模块38. 用VHDL编写一个平滑滤波器模块39. 用VHDL编写一个中值滤波器模块40. 用VHDL编写一个微处理器模块41. 用VHDL编写一个信号发生器模块42. 用VHDL编写一个信号采集器模块43. 用VHDL编写一个频率计算器模块44. 用VHDL编写一个相位计算器模块45. 用VHDL编写一个时序分析器模块46. 用VHDL编写一个正弦波产生器模块47. 用VHDL编写一个余弦波产生器模块48. 用VHDL编写一个数字滤波器模块49. 用VHDL编写一个数字信号处理器模块50. 用VHDL编写一个数字识别模块51. 用VHDL编写一个自动售货机模块52. 用VHDL编写一个二进制加法器模块53. 用VHDL编写一个二进制减法器模块54. 用VHDL编写一个二进制乘法器模块55. 用VHDL编写一个二进制除法器模块56. 用VHDL编写一个自然对数模块57. 用VHDL编写一个指数函数模块58. 用VHDL编写一个三角函数模块59. 用VHDL编写一个高斯滤波器模块60. 用VHDL编写一个激光传感器模块61. 用VHDL编写一个超声波传感器模块62. 用VHDL编写一个光电传感器模块63. 用VHDL编写一个温度传感器模块64. 用VHDL编写一个气压传感器模块65. 用VHDL编写一个陀螺仪模块67. 用VHDL编写一个电流传感器模块68. 用VHDL编写一个电容传感器模块69. 用VHDL编写一个磁场传感器模块70. 用VHDL编写一个通信电缆模块71. 用VHDL编写一个电源控制器模块72. 用VHDL编写一个电机控制器模块73. 用VHDL编写一个汽车控制器模块74. 用VHDL编写一个飞机控制器模块75. 用VHDL编写一个摄像头模块76. 用VHDL编写一个音频控制器模块77. 用VHDL编写一个扬声器控制器模块78. 用VHDL编写一个拨号器模块79. 用VHDL编写一个振动控制器模块80. 用VHDL编写一个压力控制器模块81. 用VHDL编写一个过滤器模块82. 用VHDL编写一个微波发射模块84. 用VHDL编写一个智能电表模块85. 用VHDL编写一个闹钟模块86. 用VHDL编写一个计时器模块87. 用VHDL编写一个时间戳模块88. 用VHDL编写一个脉冲宽度模块89. 用VHDL编写一个电路仿真模块90. 用VHDL编写一个电路控制模块91. 用VHDL编写一个电路测试模块92. 用VHDL编写一个电路优化模块93. 用VHDL编写一个电路布局模块94. 用VHDL编写一个电路验证模块95. 用VHDL编写一个数字信号发生器模块96. 用VHDL编写一个数字信号反演器模块97. 用VHDL编写一个数字信号滤波器模块98. 用VHDL编写一个数字信号加速器模块99. 用VHDL编写一个数字信号降噪器模块100. 用VHDL编写一个数字信号解调器模块VHDL语言是一种硬件描述语言，它用于描述数字电路和系统。

EDA 第5章常用VHDL设计实例

14
WHEN S1=> z<='0'; IF xi ='1' THEN next_state<=S2; ELSE next_state<=S0; END IF; WHEN S2=> z<='0'; IF xi='1' THEN next_state<=S3; ELSE next_state<=S0; END IF; WHEN S3=> z<='0'; IF xi='1' THEN next_state<=S3; ELSE next_state<=S4; END IF; WHEN S4=> z<='0'; IF xi='1' THEN next_state<=S1; ELSE next_state<=S5; END IF; WHEN S5=> z<='0'; IF xi='1' THEN next_state<=S6; ELSE next_state<=S0; END IF; WHEN S6=> z<='0'; IF xi='1' THEN next_state<=S2; ELSE next_state<=S7; END IF; WHEN S7=> z<='1'; IF xi='1' THEN next_state<=S1; 2012-7-24ELSE next_state<=S0; END IF;
第5章常用VHDL设计实例
内容提要：常用数字电路的VHDL描述

vhdl编程实例

vhdl编程实例VHDL编程实例- 设计与实现一个4位的全加器在本篇文章中，我们将一步一步地回答如何设计和实现一个4位的全加器。

VHDL编程语言将是我们用于描述和模拟这个电路的工具。

第一步：理解全加器的原理在编写代码之前，我们首先需要理解全加器的原理。

全加器是一种用于对两个二进制数字进行相加的电路。

它接收三个输入信号：两个位的输入（A 和B）以及一个进位输入（C_in）。

全加器的输出结果为一个位的和（S）和一个进位输出（C_out）。

我们可以使用如下的真值表来描述全加器的输出结果：输入信号输出结果A B C_in S C_out0 0 0 0 00 0 1 1 00 1 0 1 00 1 1 0 11 0 0 1 01 0 1 0 11 1 0 0 11 1 1 1 1了解了全加器的工作原理后，我们可以开始编写代码了。

第二步：编写全加器的VHDL代码我们将使用VHDL语言来描述和模拟全加器。

下面是一个简单的4位全加器的VHDL代码实现：vhdlEntity声明entity full_adder isport (A, B : in std_logic_vector(3 downto 0);C_in : in std_logic;S : out std_logic_vector(3 downto 0);C_out : out std_logic);end full_adder;Architecture声明architecture Behavioral of full_adder isbeginprocess(A, B, C_in)variable carry : std_logic;begincarry := C_in;for i in 0 to 3 loopS(i) <= A(i) xor B(i) xor carry;carry := (A(i) and B(i)) or (carry and (A(i) xor B(i)));end loop;C_out <= carry;end process;end Behavioral;在此代码中，我们首先声明了一个实体（entity）和一个架构（architecture）。

EDA VHDL程序

10线－4线优先编码器的VHDL描述LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;ENTITY coder ISPORT ( din : IN STD_LOGIC_VECTOR(9 DOWNTO 0);output : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END coder;ARCHITECTURE behav OF CODER ISSIGNAL SIN : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINPROCESS (DIN)BEGINIF (din(9)='0') THEN SIN <= "1001" ;ELSIF (din(8)=‟0‟) THEN SIN <= "1000" ;ELSIF (din(7)='0') THEN SIN <= "0111" ;ELSIF (din(6)='0') THEN SIN <= "0110" ;ELSIF (din(5)='0') THEN SIN <= "0101" ;ELSIF (din(4)='0') THEN SIN <= "0100" ;ELSIF (din(3)='0') THEN SIN <= "0011" ;ELSIF (din(2)='0') THEN SIN <= "0010" ;ELSIF (din(1)='0') THEN SIN <= "0001" ;ELSE SIN <= “0000” ;END IF；END PROCESS ；Output <= sin ；END behav;计数器1 LIBRARY IEEE;2 USE IEEE.STD_LOGIC_1164.ALL;3 use IEEE.std_logic_unsigned.all;4 ENTITY CNT4 IS5 PORT ( CLK : IN STD_LOGIC ;6 Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) ;7 END CNT4;8 ARCHITECTURE bhv OF CNT4 IS9 SIGNAL Q1 : STD_LOGIC_VECTOR(3 DOWNTO 0);10 BEGIN11 PROCESS (CLK) BEGIN12 IF RISING_EDGE(CLK) zhen13 IF Q1 < 15 THEN14 Q1 <= Q1 + 1 ;15 ELSE16 Q1 <= (OTHERS => '0');17 END IF;18 END IF;19 END PROCESS ;20 Q <= Q1;21 END bhv;228位分频器程序设计LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY PULSE ISPORT ( CLK : IN STD_LOGIC;D : IN STD_LOGIC_VECTOR (7 DOWNTO 0);FOUT : OUT STD_LOGIC );END;ARCHITECTURE one OF PULSE ISSIGNAL FULL : STD_LOGIC;BEGINP_REG: PROCESS(CLK)VARIABLE CNT8 : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF CLK‟EVENT AND CLK = …1‟ THENIF CNT8 = "11111111" THENCNT8 := D; --当CNT8计数计满时，输入数据D被同步预置给计数器CNT8FULL <= '1'; --同时使溢出标志信号FULL输出为高电平ELSE CNT8 := CNT8 + 1; --否则继续作加1计数FULL <= '0'; --且输出溢出标志信号FULL为低电平END IF;END IF;END PROCESS P_REG;P_DIV: PROCESS(FULL)VARIABLE CNT2 : STD_LOGIC;BEGINIF FULL'EVENT AND FULL = '1' THENCNT2 <= NOT CNT2; --如果溢出标志信号FULL为高电平，D触发器输出取反IF CNT2 = '1' THEN FOUT <= '1';ELSE FOUT <= '0';END IF;END IF;END PROCESS P_DIV;END;同步递增计数器USE IEEE.STD_LOGIC_1164.ALL;USE IEEE STD_LOGIC_UNSIGNED.ALL;ENTITY Exe_8 IS ；PORT ( CLK: IN STD_LOGIC;Q: BUFFER STD_LOGIC_VECTOR (7 DOWNTO 0));END Exe_8;ARCHITECTURE a OF Exe_8 ISBEGINPROCESS(CLK)VARIABLE QTEMP : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINIF CLK'EVENT AND CLK='1' THENQTEMP:=QTEMP+1;END IF;Q<=QTEMP;END PROCESS;END a;描述下列VHDL程序的逻辑功能:要求：指出输入、输出端子；实体功能说明；画出逻辑功能图。

EDA代码

ready_set <='1';
INCNT <="0000";
scan_code <=SHIFTIN(7 DOWNTO 0);
IF SHIFTIN(7 DOWNTO 0)=x"F0" THEN
release <='1';
பைடு நூலகம்
ELSE
release <='0';
END IF;
IF (SHIFTIN(7 DOWNTO 0)/=X"E0") AND (release='0') THEN
begin if preset='0' then
bcd10<="0000"; co_1<='0'; else if clk='1'and clk'event then
if bcd1="1000" and bcd10="0101" then co_1<='1';
elsif bcd1="1001" and bcd10="0101" then bcd10<="0000"; co_1<='0';
entity baoshi is port(clk_2KHz,clk_1KHz,clk1Hz:in std_logic; bcd10S,bcd1S,bcd10M,bcd1M:in std_logic_vector(3 downto 0); clkout:out std_logic);
end baoshi;

EDA的一些程序代码

8-3优先编码器设计（1）VHDL代码LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY LS183 ISPORT (A,B,C,D,E,F,G,H: IN STD_LOGIC;L :OUT STD_LOGIC_VECTOR(2 DOWNTO 0);VGA :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END ENTITY;ARCHITECTURE BHV OF LS183 ISSIGNAL ABC : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINABC <= A & B & C & D & E & F & G & H; -- 并置A，B，C三个端口到信号ABC，便于编程VGA <= "0001"; -- 实验箱功能选择位设置PROCESS (ABC)BEGINIF ABC(0) = '0' THEN L <= "000";ELSIF ABC(1 DOWNTO 0) = "01" THEN L<="001";ELSIF ABC(2 DOWNTO 0) = "011" THEN L<="010";ELSIF ABC(3 DOWNTO 0) = "0111" THEN L<="011";ELSIF ABC(4 DOWNTO 0) = "01111" THEN L<="100";ELSIF ABC(5 DOWNTO 0) = "011111" THEN L<="101";ELSIF ABC(6 DOWNTO 0) = "0111111" THEN L<="110";ELSIF ABC(7 DOWNTO 0) = "01111111" THEN L<="111";END IF;END PROCESS;END ARCHITECTURE;时序仿真Test Bench文件内容（不含注释）及仿真波形图仿真时制作的Test Bench文件添加：WAIT FOR 200 ns; A<='0'; B<='1'; C<='1';D<='1';E<='1';F<='1';G<='1';H<='0';W AIT FOR 200 ns; A<='1'; B<='0'; C<='1';D<='1';E<='1';F<='1';G<='0';H<='1';W AIT FOR 200 ns; A<='1'; B<='1'; C<='0';D<='0';E<='0';F<='0';G<='1';H<='1';W AIT FOR 200 ns; A<='1'; B<='1'; C<='1';D<='0';E<='0';F<='1';G<='1';H<='1';W AIT FOR 200 ns; A<='1'; B<='1'; C<='1';D<='0';E<='1';F<='1';G<='1';H<='1';W AIT FOR 200 ns; A<='1'; B<='1'; C<='0';D<='1';E<='1';F<='1';G<='1';H<='1';W AIT FOR 200 ns; A<='1'; B<='0'; C<='1';D<='1';E<='1';F<='1';G<='1';H<='1';W AIT FOR 200 ns; A<='0'; B<='1'; C<='1';D<='1';E<='1';F<='1';G<='1';H<='1';8421码奇偶校验位发生器设计（1）VHDL代码LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;ENTITY xor42 ISPORT (B8,B4,B2,B1: IN STD_LOGIC;P, NP:OUT STD_LOGIC;VGA :OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END ENTITY;ARCHITECTURE BHV OF XOR42 ISSIGNAL e,f,g : STD_LOGIC;BEGINVGA <= "0001";e <= B8 XOR B4;f <= B2 XOR B1;g <= e XOR f;p <= g;NP <=g XOR '1';END ARCHITECTURE;注意：在Entity中务必添加VGA功能选择端口：VGA :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)在Architecture中务必添加功能选择设置：VGA <= "0001";（2）时序仿真Test Bench文件内容（不含注释）及仿真波形图LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY xor42_vhd_tst ISEND xor42_vhd_tst;ARCHITECTURE xor42_arch OF xor42_vhd_tst IS-- constants-- signalsSIGNAL B1 : STD_LOGIC;SIGNAL B2 : STD_LOGIC;SIGNAL B4 : STD_LOGIC;SIGNAL B8 : STD_LOGIC;SIGNAL NP : STD_LOGIC;SIGNAL P : STD_LOGIC;SIGNAL VGA : STD_LOGIC_VECTOR(3 DOWNTO 0); COMPONENT xor42PORT (B1 : IN STD_LOGIC;B2 : IN STD_LOGIC;B4 : IN STD_LOGIC;B8 : IN STD_LOGIC;NP : OUT STD_LOGIC;P : OUT STD_LOGIC;VGA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) );END COMPONENT;BEGINi1 : xor42PORT MAP (-- list connections between master ports and signals B1 => B1,B2 => B2,B4 => B4,B8 => B8,NP => NP,P => P,VGA => VGA);init : PROCESS-- variable declarationsBEGIN-- code that executes only onceWAIT FOR 100 ns; B8<='0';B4<='0';B2<='0';B1<='0'; WAIT FOR 100 ns; B8<='0';B4<='0';B2<='0';B1<='1'; WAIT FOR 100 ns; B8<='0';B4<='0';B2<='1';B1<='0'; WAIT FOR 100 ns; B8<='0';B4<='0';B2<='1';B1<='1'; WAIT FOR 100 ns; B8<='0';B4<='1';B2<='0';B1<='0'; WAIT FOR 100 ns; B8<='0';B4<='1';B2<='0';B1<='1'; WAIT FOR 100 ns; B8<='0';B4<='1';B2<='1';B1<='0'; WAIT FOR 100 ns; B8<='0';B4<='1';B2<='1';B1<='1'; WAIT FOR 100 ns; B8<='1';B4<='0';B2<='0';B1<='0'; WAIT FOR 100 ns; B8<='1';B4<='0';B2<='0';B1<='1'; WAIT FOR 100 ns; B8<='1';B4<='0';B2<='1';B1<='0';WAIT FOR 100 ns; B8<='1';B4<='0';B2<='1';B1<='1'; WAIT FOR 100 ns; B8<='1';B4<='1';B2<='0';B1<='0'; WAIT FOR 100 ns; B8<='1';B4<='1';B2<='0';B1<='1'; WAIT FOR 100 ns; B8<='1';B4<='1';B2<='1';B1<='0'; WAIT FOR 100 ns; B8<='1';B4<='1';B2<='1';B1<='1'; WAIT;END PROCESS init;always : PROCESS-- optional sensitivity list-- ( )-- variable declarationsBEGIN-- code executes for every event on sensitivity list WAIT;END PROCESS always;END xor42_arch;\半加器设计（1）VHDL代码LIBRARY IEEE; --半加器USE IEEE.STD_LOGIC_1164.ALL;ENTITY h_adder ISPORT (a,b: IN STD_LOGIC;co,so:OUT STD_LOGIC);END ENTITY;ARCHITECTURE fh1 OF h_adder ISSIGNAL abc:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGINabc<=a & b;PROCESS(abc)BEGINCASE abc ISWHEN"00"=>so<='0';co<='0';WHEN"01"=>so<='1';co<='0';WHEN"10"=>so<='1';co<='0';WHEN"11"=>so<='0';co<='1';WHEN OTHERS=>NULL;END CASE;END PROCESS;END ARCHITECTURE fh1;注意：在Entity中务必添加VGA功能选择端口：VGA :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)在Architecture中务必添加功能选择设置：VGA <= "0001";（2）时序仿真Test Bench文件内容（不含注释）及仿真波形图LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY f_adder_vhd_tst ISEND f_adder_vhd_tst;ARCHITECTURE f_adder_arch OF f_adder_vhd_tst IS-- constants-- signalsSIGNAL ain : STD_LOGIC;SIGNAL bin : STD_LOGIC;SIGNAL cin : STD_LOGIC;SIGNAL cout : STD_LOGIC;SIGNAL sum : STD_LOGIC;SIGNAL VGA : STD_LOGIC_VECTOR(3 DOWNTO 0);COMPONENT f_adderPORT (ain : IN STD_LOGIC;bin : IN STD_LOGIC;cin : IN STD_LOGIC;cout : OUT STD_LOGIC;sum : OUT STD_LOGIC;VGA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END COMPONENT;BEGINi1 : f_adderPORT MAP (-- list connections between master ports and signalsain => ain,bin => bin,cin => cin,cout => cout,sum => sum,VGA => VGA);init : PROCESS-- variable declarationsBEGIN-- code that executes only onceWAIT FOR 100 ns; ain<='0';bin<='0';cin<='0';WAIT FOR 100 ns; ain<='0';bin<='0';cin<='1';WAIT FOR 100 ns; ain<='0';bin<='1';cin<='0';WAIT FOR 100 ns; ain<='0';bin<='1';cin<='1';WAIT FOR 100 ns; ain<='1';bin<='0';cin<='0';WAIT FOR 100 ns; ain<='1';bin<='0';cin<='1';WAIT FOR 100 ns; ain<='1';bin<='1';cin<='0';WAIT FOR 100 ns; ain<='1';bin<='1';cin<='1';WAIT;END PROCESS init;always : PROCESS-- optional sensitivity list-- ( )-- variable declarationsBEGIN-- code executes for every event on sensitivity listWAIT;END PROCESS always;END f_adder_arch;带使能输入及同步清零的增1计数器（1）VHDL代码注意：在Entity中务必添加VGA功能选择端口：VGA :OUT STD_LOGIC_VECTOR(3 DOWNTO 0)在Architecture中务必添加功能选择设置：VGA <= "0001";LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY CNT16 ISPORT (CLK,CLR,EN : IN STD_LOGIC;Q : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);VGA : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END CNT16;ARCHITECTURE behav OF CNT16 ISBEGINVGA <="0001";PROCESS (CLK,CLR,EN)V ARIABLE QI : STD_LOGIC_VECTOR(3 DOWNTO 0);BEGINIF CLR = '1' THEN QI := (OTHERS =>'0');ELSIF CLK'EVENT AND CLK='1' THENIF EN ='1' THEN QI:=QI+1;ELSE QI := (OTHERS =>'0');END IF;END IF;Q <= QI;END PROCESS;END behav;（2）时序仿真Test Bench文件内容（不含注释）及仿真波形图生成Test Bench模板文件，做以下修改：在Architecture的常数声明部分添加……-- constantsCONSTANT clk_period : TIME := 40 ns; -- 该常数用于设置时钟周期，40 ns两个进程修改如下：init : PROCESS-- variable declarationsBEGIN-- code that executes only onceWAIT FOR 100 ns; en <='1';WAIT FOR 1500 ns; clr<='1';WAIT FOR 200 ns; clr<='0';WAIT;END PROCESS init;always : PROCESSBEGIN-- code executes for every event on sensitivity listclk<='1'; WAIT FOR clk_period/2;-- 时钟信号的Test Bench的一般描述clk<='0'; WAIT FOR clk_period/2;END PROCESS always;……其中黑体部分，是时钟信号仿真Test Bench的描述方式之一。

EDA中的VHDL代码

Eda中常用的程序集合1.六十进制计数器：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jsq60 isport (clk : in std_logic;co : out std_logic;y : out integer range 0 to 59); end jsq60;architecture one of jsq60 issignal yy : integer range 0 to 59; beginprocess(clk)beginif clk'event and clk = '1' thenyy<=yy+1;end if;if yy=15 thenco<='1';elseco<='0';end if;end process;y<=yy;end one;2.一百进制计数器：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity jsq100 isport (clk : in std_logic;co : out std_logic;y : out integer range 0 to 99); end jsq100;architecture one of jsq100 issignal yy : integer range 0 to 99; beginprocess(clk)beginif clk'event and clk = '1' thenyy<=yy+1;end if;if yy=99 thenco<='1';elseco<='0';end if;end process;y<=yy;end one;3.三八译码器：library ieee;use ieee.std_logic_1164.all;entity ym3_8 isport(a:in std_logic_vector(2 downto 0);b:out std_logic_vector(0 to 7)); end ym3_8;architecture rtl of ym3_8 isbeginprocess(a)begincase a iswhen"000"=> b<="11111110";when"001"=> b<="11111101";when"010"=> b<="11111011";when"011"=> b<="11110111";when"100"=> b<="11101111";when"101"=> b<="11011111";when"110"=> b<="10111111";when"111"=> b<="01111111";when others=>b<="00000000";end case;end process;end rtl;4.三人表决器的四种方法：附程序代码library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bjq3 isport (a,b,c:in std_logic;y:out std_logic);end;architecture one of bjq3 isbeginy<=(a and b ) or (a and c) or (b and c ); end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bjq3 isport (a,b,c:in std_logic;y:out std_logic);end;architecture one of bjq3 issignal m:std_logic_vector(2 downto 0);beginm<=a & b & c;y<='0' when (m="000")or(m="001")or(m="010")or(m=" 100" )else'1';end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bjq3 isport (a,b,c:in std_logic;y:out std_logic);end;architecture one of bjq3 issignal m: std_logic_vector(2 downto 0); beginm<=a&b&c;with m selecty<='0'when "000"|"001"|"010"|"100", '1'when others;end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bjq3 isport (m:in std_logic_vector(2 downto 0);y:out std_logic);end;architecture one of bjq3 isbeginprocess (m)begincase m iswhen "000"|"001"|"010"|"100"=>y<='0';when others =>y<='1';end case;end process;end;library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity bjq3 isport (m:in std_logic_vector(2 downto 0);y:out std_logic);end;architecture one of bjq3 isbeginprocess (m)beginif m="000" then y<='0';elsif m="001"then y<='0';elsif m="010"then y<='0';elsif m="011"then y<='1';elsif m="100"then y<='0';elsif m="101"then y<='1';elsif m="110"then y<='1';elsif m="111"then y<='1';end if;end process;end;、5.八三编码器library ieee;use ieee.std_logic_1164.all;entity yxbm8_3 isport( a: in std_logic_vector(7 downto 0);b: out std_logic_vector(2 downto 0));end yxbm8_3;architecture one of yxbm8_3 isbeginprocess(a)beginif a(7)<='0' then b<="000";elsif a(6)<='0' then b<="001";elsif a(5)<='0' then b<="010";elsif a(4)<='0' then b<="011";elsif a(3)<='0' then b<="100";elsif a(2)<='0' then b<="101";elsif a(1)<='0' then b<="110";else b<="111";end if;end process;end one;6.六选一，四选一数码选择；；；LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;entity mux61 isport(d0,d1,d2,d3,d4,d5,a0,a1,a2:instd_logic;y:out std_logic);end mux61;architecture rtl of mux61 issignal a:std_logic_vector(2 downto 0); beginprocess(a0,a1,a2)begina<=a2&a1&a0;case a iswhen "000"=>y<=d0;when "001"=>y<=d1;when "010"=>y<=d2;when "011"=>y<=d3;when "100"=>y<=d4;when "101"=>y<=d5;when others=>null;end case;end process;end rtl;library ieee;use ieee.std_logic_1164.all;entity mux41a isport (d0,d1,d2,d3,a1,a0:in std_logic; Y:outstd_logic);end entity mux41a;architecture one of mux41a issignal m,n,o,p:std_logic;begin m<=(not a1) and (not a0)andd0;n<=(not a1) and a0 and d1;o<=a1 and (not a0) and d2; p<=a1 and a0 and d3 ;y<=m or n or o or p;end one;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY max4_1 ISPORT(a,b,c,d,s1,s2 : IN STD_LOGIC;y : OUT STD_LOGIC);END ENTITY max4_1;ARCHITECTURE hf1 OF max4_1 ISSIGNAL ss : STD_LOGIC_VECTOR (0 TO 1); BEGINss<=s2&s1;PROCESS(ss)BEGINCASE ss ISWHEN "00" => y<=a;WHEN "01" => y<=b;WHEN "10" => y<=c;WHEN "11" => y<=d; WHEN OTHERS => NULL; END CASE;END PROCESS;END ARCHITECTURE hf1;。

(完整word版)VHDL语言实例

VHDL语言实例例 1：设计一七段显示译码器，用它来驱动七段发光管 LED显示十六进制数字 0 到9 和字母 A 到 F。

LED显示数码管为共阳极。

LIBRARYieee;USE ieee.std_logic_1164.all;ENTITY HEX2LEDISPORT(HEX :IN std_logic_vector(3 DOWNTO0);LED : OUT std_logic_vector(6 TO0));图例 1 七段显示译码END 器实体 HEX2LED;ARCHITECTURE HEX2LED_arc OF HEX2LED ISBEGIN--HEX-TO-SEVEN-SEGMENT DECODER--SEGMENT ENCODING----------5 ||1------ <--6--4 ||2--------3WITH HEX SELECTLED<= "1111001" when "0001","0100100" when "0010","0110000" when "0011","0011001" when "0100","0010010" when "0101","0000010" when "0110","1111000" when "0111","0000000" when "1000","0010000" when "1001","0001000" when "1010","0000011" when "1011","1000110" when "1100","0100001" when "1101","0000110" when "1110","0001110" when "1111","1000000" when others;END HEX2LED_arc;例 2：设计一个八选一数据选择器1）s 是通道选择信号 ,d0,d1,d2,d3,d4,d5,d6,d7数据输入out1 是数据输出ENTITY sels ISPORT(d0,d1,d2,d3,d4,d5,d6,d7:INBIT;s :INTEGERRANGE0TO7;out1 :OUT BIT);END sels;图例 2（a)八选一数据选择器实体ARCHITECTURE sels_arc OF sels ISBEGINWITH s SELECTout1 <= d0 WHEN 0,d1 WHEN 1,d2 WHEN 2,d3 WHEN 3,d4 WHEN 4,d5 WHEN 5,d6 WHEN 6,d7 WHEN 7;END sels_arc;2)A,B,C 是通道选择信号 ,I0,I1,I2,I3,I4,I5,I6,I7数据输入Q 是数据输出LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY mux8 ISPORT(I0,I1,I2,I3,I4,I5,I6,I7,A,B,C:INstd_logic;Q :OUT std_logic);END mux8;图例2（b) 八选一数据选择器实体ARCHITECTURE mux8_arc OF mux8 ISSIGNAL sel :INTEGER；BEGINQ <= I0 AFTER 10 ns WHEN sel= 0 ELSEI1 AFTER 10 ns WHEN sel= 1 ELSEI2 AFTER 10 ns WHEN sel= 2 ELSEI3 AFTER 10 ns WHEN sel= 3 ELSEI4 AFTER 10 ns WHEN sel= 4 ELSEI5 AFTER 10 ns WHEN sel= 5 ELSEI6 AFTER 10 ns WHEN sel= 6 ELSEI7 AFTER 10 ns ;sel <= 0 WHEN A= ‘0’ AND B= ‘0’ AND C= ‘0’ ELSE1 WHEN A=‘1’ AND B= ‘0’ AND C= ‘0’ ELSE2 WHEN A=‘0’ AND B= ‘1’ AND C= ‘0’ ELSE3 WHEN A=‘1’ AND B= ‘1’ AND C= ‘0’ ELSE4 WHEN A=‘0’ AND B= ‘0’ AND C= ‘1’ ELSE5 WHEN A=‘1’ AND B= ‘0’ AND C= ‘1’ ELSE6 WHEN A=‘0’ AND B= ‘0’ AND C= ‘1’ ELSE7;END mux8_arc;例 3：设计一 D触发器d 是输入端， clk 是时钟信号控制端， q 是触发器的输出端。

VHDL一些常用程序(EDA必考)

常用程序：●1/4位加法器、1/4位减法器、2/4/8位数据选择器、D/8D锁存器、D触发器、4位移位寄存器、2-4/3-8译码器、用with-select或者when-else设计同或门、异或门和或非门等、根据逻辑表达式编程等等，如F= ABC+(D+E)+GH。

加减法器件的设计要考虑如何采用元件例化语句和生成语句设计。

六、十进制计数器的设计●布置的第3章课后作业看了几本作业，大概清楚了哪些程序有难度，下面仅列出部分程序供大家参考：【减法器】1位减法器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.all;entity subber1 isport(a,b,cin:in std_logic;s:out std_logic;cout: out std_logic);end subber1;architecture one of subber1 isbegins<= (a xor b) xor cin;cout<= ((not a)nand b)nand(not(a xor b) nand cin);end one;4位减法器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE WORK.my_pkg.all;entity subber4 isport(a,b:in std_logic_vector(3 downto 0);cin: in std_logic;s:out std_logic_vector(3 downto 0);cout: out std_logic);end subber4;architecture one of subber4 issignal cout0,cout1,cout2: std_logic;beginu1: subber1 port map(a(0),b(0),cin,s(0),cout0);u2: subber1 port map(a(1),b(1),cout0,s(1),cout1);u3: subber1 port map(a(2),b(2),cout1,s(2),cout2);u4: subber1 port map(a(3),b(3),cout2,s(3),cout);程序包：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;PACKAGE my_pkg ISComponent subber1port(a,b:in std_logic;cin: in std_logic;s:out std_logic;cout: out std_logic);END Component;Component subber4port(a,b:in std_logic_vector(3 downto 0);cin: in std_logic;s:out std_logic_vector(3 downto 0);cout: out std_logic);END Component;end my_pkg;16位减法器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE WORK.my_pkg.all;entity subber16 isport( a,b:in std_logic_vector(15 downto 0);cin: in std_logic;s:out std_logic_vector(15 downto 0);cout: out std_logic);end subber16;architecture one of subber16 issignal cout0,cout1,cout2: std_logic;beginu1: subber4 port map(a(3 downto 0),b(3 downto 0),cin,s(3 downto 0),cout0);u2: subber4 port map(a(7 downto 4),b(7 downto 4),cout0,s(7 downto 4),cout1);u3: subber4 port map(a(11 downto 8),b(11 downto 8),cout1,s(11 downto 8),cout2);u4: subber4 port map(a(15 downto 12),b(15 downto 12),cout2,s(15 downto 12),cout); end one;【D触发器】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY dchufaqi ISPORT(clk,d,clr:IN STD_LOGIC;q:OUT STD_LOGIC);END dchufaqi;ARCHITECTURE example2 OF dchufaqi ISprocess( clk,d,clr)beginif (clr='0') then q<='0';elsif (clk'event and clk='1') thenq<=d;end if;end process;END example2;【4位移位寄存器】LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY shifter ISPORT(din,clk: IN bit;dout : out bit);END shifter;ARCHITECTURE a OF shifter IScomponent dffport(d,clk: in bit;q: out bit);end component dff;signal d: bit_vector(0 to 4);BEGINd(0)<=din;u1:dff port map(d(0),clk,d(1));u2:dff port map(d(1),clk,d(2));u3:dff port map(d=>d(2),clk=>clk,q=>d(3));u4:dff port map(d=>d(3),clk=>clk,q=>d(4));dout<=d(4);END a;【8D锁存器】（1）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY latch1 IS --1位锁存器的设计PORT ( d :IN STD_LOGIC;ena :IN STD_LOGIC;q :OUT STD_LOGIC);END latch1;ARCHITECTURE example4 OF latch1 ISSIGNAL sig_save:STD_LOGIC:=‘0’;BEGINPROCESS (d,ena)BEGINIF ena='1' THENSig_save<=D;END IF;Q<=sig_save;END PROCESS;END example4;（2）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;PACKAGE my_pkg ISCOMPONENT latch1 --latch1入程序包PORT ( d :IN STD_LOGIC;ena :IN STD_LOGIC;q :OUT STD_LOGIC);END COMPONENT;END my_pkg;（3）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE WORK.my_pkg.ALL;ENTITY ct74373 IS --8D锁存器的设计PORT (d: IN STD_LOGIC_VECTOR(7 DOWNTO 0);oen, g: IN STD_LOGIC;q: OUT STD_LOGIC _VECTOR(7 DOWNTO 0));END ct74373;ARCHITECTURE one OF ct74373 ISSIGNAL sigsave: STD_LOGIC_VECTOR(7 DOWNTO 0);BEGINGelatch: for n in 0 to 7 GENERATELatchx: latch1 port map(d(n),g,sigsave(n));END GENERA TE;Q<=sigsave when oen=‘0’ else“ZZZZZZZZ”;END one;【根据逻辑表达式编程等等，如F= ABC+(D+E)+GH】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;entity cytest isport(a,b,c,d,e,g,h: in std_logic;f: out std_logic);end cytest;architecture one of cytest issignal t1, t2,t3: std_logic;begint1<= a and b and c;t2<= d or e;t3<= g and h;f<= t1 or t2 or t3;end one;【六进制计数器】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE. STD_LOGIC_UNSIGNED.ALL;ENTITY CNT6 ISPORT (CLK, CLRN, ENA, LDN: IN STD_LOGIC;D: IN STD_LOGIC_VECTOR(3 DOWNTO 0);Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);COUT: OUT STD_LOGIC);END CNT6;ARCHITECTURE ONE OF CNT6 ISSIGNAL CI: STD_LOGIC_VECTOR(3 DOWNTO 0):="0000";BEGINPROCESS(CLK, CLRN, ENA, LDN,CI)BEGINIF CLRN='0' THEN CI<="0000";ELSIF CLK'EVENT AND CLK='1' THENIF LDN='0' THEN CI<=D;ELSIF ENA='1' THENIF CI<5 THEN CI<=CI+1;ELSE CI<="0000";END IF;END IF;END IF;Q<=CI;END PROCESS;COUT<= CI(0) AND CI(2);END ONE;【第3章课后作业——3.16】，用VHDL设计4选1数据选择器，然后用生成语句设计双4选1数据选择器（1）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux4_1 ISPORT(a,b,c,d:IN STD_LOGIC;s:IN STD_LOGIC_vector(1 downto 0);z:OUT STD_LOGIC);END mux4_1;ARCHITECTURE example3 OF mux4_1 ISBEGINPROCESS(a,b,c,d,s)BEGINCASE s ISWHEN "00" => z <= a;WHEN "01" => z <= b;WHEN "10" => z <= c;WHEN "11" => z <= d;WHEN OTHERS => z <= 'X';END CASE;END PROCESS;END example3;（2）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;PACKAGE mypkg ISCOMPONENT mux4_1PORT(a,b,c,d:IN STD_LOGIC;s:IN STD_LOGIC_vector(1 downto 0);z:OUT STD_LOGIC);END COMPONENT;END mypkg;（3）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE WORK.mypkg.ALL;ENTITY doublemux41 ISPORT(aa,bb,cc,dd:IN STD_LOGIC_VECTOR(1 DOWNTO 0);sel:IN STD_LOGIC_VECTOR(1 DOWNTO 0);q:OUT STD_LOGIC_VECTOR(1 DOWNTO 0));END doublemux41;ARCHITECTURE one OF doublemux41 ISBEGINgemux41: for n in 0 to 1 generateux: mux4_1 port map(aa(n),bb(n),cc(n),dd(n),sel,q(n));end generate;end one;【4-16译码器】updowncnt8library ieee;use ieee.std_logic_1164.all;entity updowncnt8 isport(clr,clk,ena,load,updown:in std_logic;d: in integer range 0 to 255;cout:out std_logic;q:buffer integer range 0 to 255);end updowncnt8;architecture one of updowncnt8 isbeginprocess (clk,ena,clr,d,load,updown)beginif clr='0' thenq<= 0;elsif clk'event and clk='1' thenif load ='1' thenq<=d;elsif ena='1' thenif updown='0'then q<=q-1;if q = 0 then cout <='0'; end if;else q<= q+1;if q =255 then cout <='1';else cout <='0'; end if ;end if;end if;end if;end process;end one;还有一些题的参考程序大家都可以在书上或者是课件中找到，请大家务必认真仔细，做题时最重要一点，就是要看清题意！比如加减计数器的设计，看清楚什么时候加法计数，什么时候减法计数。

EDA(第4讲)第3章 VHDL入门3

13三人表决器的设计——CSE语句课堂练习题语句课堂练习题
输入变量输出 a b 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 c 0 1 0 1 0 1 0 1 y 0 0 0 1 0 1 1 1 要求：根据真值表，写出VHDL程序 bjq a b c y
14
LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; END PROCESS; ENTITY bjq IS END ARCHITECTURE aa ; PORT (a, b, c : IN STD_LOGIC; y : OUT STD_LOGIC); END ENTITY bjq; ARCHITECTURE aa OF bjq is SIGNAL abc : STD_LOGIC_VECTOR(1 DOWNTO 0) ; BEGIN 输入变量输出 abc <= a & b & c; PROCESS(abc) a b c y BEGIN 0 0 0 0 CASE abc IS
0 0 0
0 1 1 0 0 1 1
1 0 1 0 1 0 1
0 0 1 0 1 1 1
15
; ; ; ;
1 1 1 1
外部端口
内部端口
端口连线：端口连线：信号
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或门的VHDL描述：or2a.vhd 描述：或门的描述
LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2a IS PORT (a, b :IN STD_LOGIC; c : OUT STD_LOGIC ); END ENTITY or2a；； ARCHITECTURE one OF or2a IS BEGIN c <= a OR b ; END ARCHITECTURE one ;

VHDL代码

VHDL代码[例1.4.26] 2输入与门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY and2 ISPORT(a, b : IN STD_LOGIC;y: OUT STD_LOGIC);END and2; ARCHITECTURE one OF and2 IS BEGINy<= a and b;END one;[例2.5.1] 2输入与非门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY nand2 ISPORT(a, b : IN STD_LOGIC;y: OUT STD_LOGIC);END nand2; ARCHITECTURE one OF nand2 IS BEGINy<= a nand b;END one;[例2.5.2] 2输入或门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2 ISPORT(a, b : IN STD_LOGIC;y: OUT STD_LOGIC);END or2;ARCHITECTURE one OF or2 IS BEGINy<= a or b;END one;[例2.5.3]非门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY hnot ISPORT(a : IN STD_LOGIC;y: OUT STD_LOGIC);END hnot; ARCHITECTURE one OF hnot IS BEGINy<= not a;END one;[例2.5.4] 2输入异或门的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY xor2 ISPORT(a, b : IN STD_LOGIC;y: OUT STD_LOGIC);END xor2; ARCHITECTURE one OF xor2 IS BEGINy<= a xor b;END one;[例3.8.1] 3线-8线译码器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY decoder38 ISPORT(a : IN STD_LOGIC_VECTOR(2 DOWNTO 0); y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END decoder38;ARCHITECTURE one OF decoder38 ISBEGINPROCESS (a)BEGINCASE a ISWHEN "000" => y<= "00000001";WHEN "001" => y<= "00000010";WHEN "010" => y<= "00000100";WHEN "011" => y<= "00001000";WHEN "100" => y<= "00010000";WHEN "101" => y<= "00100000";WHEN "110" => y<= "01000000";WHEN "111" => y<= "10000000";WHEN OTHERS =>null ;END CASE;END PROCESS;END one;[例3.8.2] 8线-3线优先编码器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY encoder83 ISPORT( d : IN STD_LOGIC_VECTOR(7 DOWNTO 0); encode: OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); END encoder83;ARCHITECTURE one OF encoder83 ISBEGINencode <= "111" when d(7) = '1' else "110" when d(6) = '1' else"101" when d(5) = '1' else"100" when d(4) = '1' else"011" when d(3) = '1' else"010" when d(2) = '1' else"001" when d(1) = '1' else"000" when d(0) = '1' ;END one;[例3.8.3] 4选1数据选择器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY mux41 isPORT (a,b,c,d : IN STD_LOGIC;s : IN STD_LOGIC_VECTOR(1 DOWNTO 0);z : OUT STD_LOGIC);END mux41;ARCHITECTURE one OF mux41 ISBEGINPROCESS (s ,a,b,c,d)BEGINCASE s ISWHEN "00" => z<= a;WHEN "01" => z<= b;WHEN "10" => z<= c;WHEN "11" => z<= d;WHEN OTHERS =>z<= 'x';END CASE;END PROCESS;END one;[例4.8.1] 同步复位D触发器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY d_ff isPORT (d,clk,reset : IN STD_LOGIC;q : OUT STD_LOGIC);END d_ff;ARCHITECTURE one OF d_ff IS BEGINPROCESS (clk)BEGINIF clk'EVENT AND clk='1' THENIF reset='1' THENQ<='0';ELSE q<=d;END IF;END IF;END PROCESS;END one;[例4.8.2] 边沿JK 触发器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY jk_ff isPORT (j,k,clk : IN STD_LOGIC;q, qn : OUT STD_LOGIC);END jk_ff;ARCHITECTURE one OF jk_ff IS SIGNAL q_s : STD_LOGIC; BEGINPROCESS (j,k,clk)BEGINIF clk'EVENT AND clk='1' THENIF J='0' AND k='0' THENq_s<= q_s;ELSIF J='0' AND k='1' THENq_s<='0';ELSIF J='1' AND k='0' THENq_s<='1';ELSIF J='1' AND k='1' THENq_s<=NOT q_s;END IF;END IF;END PROCESS;q<=q_s;qn<=not q_s;END one;[例5.6.1] 十进制计数器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY count10 isPORT (cp : IN STD_LOGIC;q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END count10;ARCHITECTURE one OF count10 ISSIGNAL count :STD_LOGIC_VECTOR(3 DOWNTO 0) ; BEGINPROCESS (cp)BEGINIF cp'EVENT AND cp='1' THENIF count <="1001" THENcount <="0000";ELSE count <= count +1;END IF;END IF;END PROCESS;q<= count;END one;[例5.6.2] 4位基本寄存器的VHDL描述LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY registerb isPORT (cp,reset : IN STD_LOGIC;data : IN STD_LOGIC_VECTOR(3 DOWNTO 0);q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ); END registerb;ARCHITECTURE one OF registerb ISBEGINPROCESS (cp)BEGINIF cp'EVENT AND cp='1' THEN IF reset='1' THENq<="0000";ELSEq<= data;END IF;END IF;END PROCESS;END one;。

(完整word版)EDA-常见实例源程序代码vhdl

第 4 章用VHDL 程序实现常用逻辑电路4.1 组合逻辑电路设计4.1.1 基本逻辑门library ieee;use iee.std_logic_1164.all;entity jbm isport(a,b: in bit;f1,f2,f3,f4,f5,f: out bit);end jbm;architecture a of jbm isbeginf1<=a and b; -- 构成与门f2<=a or b; -- 构成或门f<=not a; -- 构成非门f3<=a nand b; -- 构成与非门f4<=a nor b; -- 构成异或门f5<=not(a xor b); --构成异或非门即同门end;4.1.2 三态门library ieee;use ieee.std_logic_1164.all;entity tri_s isport(enable: in std_logic;datain: in std_logic_vector(7 downto 0); dataout: out std_logic_vector(7 downto0)); end tri_s;architecture bhv of tri_s isbeginprocess(enable,datain)beginif enable='1' then dataout<=datain;elsedataout<="ZZZZZZZZ";end if;end process;end bhv;4.1.3 3-8 译码器library ieee;use ieee.std_logic_1164.all;entity decoder3_8 isport(a,b,c,g1,g2a,g2b: in std_logic;y: out std_logic_vector(7 downto 0));end decoder3_8;architecture a of decoder3_8 issignal dz:std_logic_vector(2 downto 0);begindz<=c&b&a;process (dz,g1,g2a,g2b)beginif(g1='1'and g2a='0'and g2b='0')then case dz iswhen "111"=> y<="01111111"; whenothers=>y<="XXXXXXXX"; end case;elseend if;end process;4.1.4 优先编码器library ieee;use ieee.std_logic_1164.allentity coder isport(din: in std_logic_vector(0 to 7);output: out std_logic_vector(0 to 2));end coder;architecture behave of coder issignal sint: std_logic_vevtor(4 downto 0);beginprocess(din)beginif (din(7)='0') then output <= "000" ;elsif (din(6)='0') then output <= "100" ;elsif (din(5)='0') then output <= "010" ;elsif (din(4)='0') then output <= "110" ;elsif (din(3)='0') then output <= "001" ;elsif (din(2)='0') then output <= "101" ;elsif (din(1)='0') thenoutput <= "011" ;elseoutput <= "111" ;end if;end process;end behav;4.1.5 7 段码译码器library ieee;use ieee.std_logic_1164.allentity decl7s isport (a: in std_logic_vector (3 downto 0); led7s: out std_logic_vector(6 downto 0));end decl7s;architecture behave of decl7s isbeginprocess(a)begincase a iswhen "0000" => led7s <= "0111111" ;when "0001" => led7s <= "0000110" ;when "0010" =>when "0011" =>when "0100" =>when "0101" =>when "0110" =>when "0111" =>when "1000" =>when "1001" =>when "1010" =>when "1011" =>when "1100" =>when "1101" =>when "1110" => when "1111" => when others => end case;end process; end behave;4.1.6 二 -十进制 BCD 译码器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity bcdymq isport(din : in integer range 15 downto 0;a,b : out integer range 9 downto 0); end;architecture fpq1 of bcdymq isbeginp1: process(din)begin if din<10 thena< =din; b< =0;elsea< =din-10;b< =1;end if;end process p1;end;4.1.7 多位加(减)法器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity jianfaqi isport(a,b : in std_logic_vector(0 to 3); c0: in std_logic;c1: out std_logic;d : out std_logic_vector(0 to 3));end;architecture a of jianfaqi isbeginprocessbeginif a>b+c0 then d<=a-(b+c0); c1<='0';elsec1<='1'; d<=("10000")-(b+c0-a); end if;end process ;end ;4.2 时序逻辑电路设计4.2.1 触发器RS 触发器library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entityled7s <= "1011011" led7s <= "1001111" led7s <= "1100110" led7s <= "1101101" led7s <= "1111101" led7s <= "0000111" led7s <= "1111111" led7s <= "1101111" led7s <= "1110111" led7s <= "1111100" led7s <= "0111001" led7s <= "1011110" led7s <= "1111001"led7s <= "1110001"null;rsff is port(r,s,clk:in std_logic;q,qb:buffer std_logic); end rsff;architecture rsff_art of rsff is signal q_s,qb_s:std_logic;begin process(clk,r,s) beginif (clk'event and clk='1') thenif (s='1' and r='0') thenq_s<='0' ;qb_s<='1' ;elsif (s='0' and r='1') then q_s <= '1' ; qb_s <= '0' ;elsif (s='0' and r='0') then q_s <= q_s; qb_s <= qb_s;end if;end if;q_s <= q_s; qb_s <= qb_s;end process;end rsff_art;同步复位D 触发器library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_signed.all; entity syndff is port(d,clk,reset:in std_logic;q,qb:out std_logic); end syndff; architecture dff_art of syndff is begin process(clk) beginif (clk'event and clk='1') then if (reset='0') then q<='0';qb<='1';elseq<=d;qb<=not q; end if; end if;end dff_art;JK 触发器library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_signed.all;entity asynjkff is port(j,k,clk,set.reset:in std_logic; q,qb:outstd_logic);end asynjkff;architecture jkff_art of asynjkff is singalq_s,qb_s:std_logic;begin process(clk,set,reset) beginif (set='0' and reset='1' ) then q_s<='1'; qb_s<='0';elsif (set='1' and reset='0' ) thenq_s<='0';qb_s<='1';elsif (clk'event and clk='1') then if (j='0' and k='1' )then q_s<='0'; qb_s<='1';elsif (j='1' and k='0' ) then q_s<='1'; qb_s<='0';elsif (j='1' and k='1' ) then q_s<=not q_s;qb_s<=not qb_s;end if;end if; q<= q_s; qb<= qb_s;end process;end jkff_art;T 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity tff isport(t,clk: in std_logic; q: out std_logic);end; architecture tff_art of tff is signal q_temp: std_logic;begin p1:process(clk) begin if rising_edge(clk) then ift='1' thenq_temp<=not q_temp; elseq_temp<=q_temp;end if;-- 当T=1 时T 触发器具有 2 分频的功能end if;end process; q<=q_temp;end tff_art;4.2.2 计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 ISport( clk: in std_logic;q: out std_logic_vector(3 downto 0));end cnt4;architecture behave of cnt4 issignal q1: std_logic_vector(3 downto 0); beginprocess(clk)beginif (clk'event and clk = '1') then q1<=q1+1;end if;end process;q<=q1;end behave;般计数器设计library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity cnt10 isend cnt10;architecture behave of cnt10 is beginprocess(clk,rst,en,updown) variable cqi:std_logic_vector(3downto 0);port( clk,rst,en,updown: in cq: out std_logic;std_logic_vector(3 downto 0));beginif rst='1' thencqi:=(others=>'0');elsif (clk'event and clk = '1') thenif en='1'thenif updown='0'thenif cqi<9 then cqi:=cqi+1;else cqi:=(others=>'0');end if;elseif cqi>0 then cqi:=cqi-1;else cqi:=(others=>'1');end if;end if;end if;end if;cq<=cqi;end process; --计数器异步复位 --检测时钟上升沿 --检测是否允许计数（同步使能）-- 允许计数 ,检测是否小于 9 --大于 9，计数值清零 -- 检测是否大于 0 --- 否则，计数值置 1 -- 将计数值向端口输出end behave;4.2.3 分频器 library ieee; use std_logic_1164.all; usestd_logic_unsigned.all;entity freq1 isport(clk: in std_logic;d: in std_logic_vector(7 downto 0); fout: out std_logic);end; architecture one of dvf issignal full: std_logic; begin p_reg:process(clk)variable cnt8: std_logic_vector(7 downto 0);beginif clk 'event and clk= '1'thenentity shift isport(clk,c0: in std_logic; -- 时钟和进位输入md: in std_logic_vector(2 downto 0); --移位模式控制字 d: instd_logic_vector(7 downto 0); --待加载移位的数据 qb: outstd_logic_vector(7 downto 0); -- 移位数据输出 cn: out std_logic); -- 进位输出end;architecture behave of shift issignal reg: std_logic_vector(7 downto 0); signal cy: std_logic;begin if cnt8= '''' thencnt8:=d; full<= '1';else cnt8:=cnt8+1; full<= '0';end if; end if; end process p_reg;p_div:process(full)variable cnt2: std_logic;beginif full'event and full='1' thencnt2:=not cnt2;if cnt2='1'thenfout<='1';else fout<='0';end if;end if;end process p_div; end;4.2.4 移位寄存器 library ieee; useieee.std_logic_1164.all;-- 当 CNT8 计数计满时，输入数据 D 被同步预置给计数器-- 同时使溢出标志信号 FULL 输出为高电平 --否则继续作加 1 计数 --且输出溢出标志信号 FULL 为低电平 --如果溢出标志信号 FULL 为高电平， T 触发器输出取反CNT8 --检测时钟上升沿process(clk,md,c0)beginif clk'event and clk='1' thencase md islibrary ieee;use ieee.std_logic_1164.all;entity s_machine isport ( clk,reset : in std_logic;state_inputs : in std_logic_vector(0 to1); comb_outputs : out integer range 0 to 15 ); end s_machine;when s0 => comb_outputs<= 5; if state_inputs = "00" thennext_state<=s0;elsenext_state<=s1;end if;when s1 => comb_outputs<= 8; if state_inputs = "00" thennext_state<=s1;elsenext_state<=s2;end if;when s2 => comb_outputs<= 12; if state_inputs = "11" thennext_state <= s0;elsenext_state <= s3;end if;when "001" => reg (0) <= c0 ; reg (7 downto 1) <=reg (6 downto 0); cy <= reg (7);when "010" => reg (0) <= reg (7); reg (7 downto 1)<= reg (6 downto 0);when "011" => reg (7) <= reg (0);reg (6 downto 0) <= reg (7 downto 1); when"100" =>reg (7) <= C0 ; reg (6 downto 0) <= reg (7 downto 1); cy <= reg (0);when "101" => reg (7 downto 0) <= d(7 downto 0);when others => reg<= reg ; cy<= cy ;end case;end if;end process;qb(7 downto 0) <= reg (7 downto 0); cn <= cy;end behav; 4.3 状态机逻辑电路设计4.3.1 一般状态机设计--带进位循环左移--自循环左移 --自循环右移 --带进位循环右移 --加载待移数 -- 保持 --移位后输出 architecture behv of s_machine is typefsm_st is (s0, s1, s2, s3); signalcurrent_state, next_state: fsm_st; beginreg: process(reset,clk)beginif reset = '1' thencurrent_state <= s0;elsif clk='1' and clk'event thencurrent_state <= next_state; endif;end process;com:process(current_state, state_inputs)begincase current_state is--数据类型定义，状态符号化 --将现态和次态定义为新的数据类型 --主控时序进程 --检测异步复位信号 --主控组合进程when s3 => comb_outputs <= 14; if state_inputs = "11" thennext_state <= s3;elsenext_state <= s0;end if;end case;end process;end behv;4.3.2 状态机的应用library ieee; use ieee.std_logic_1164.all; entity asm_led isport(clk,clr : in std_logic;led1,led2,led3:out std_logic);end;architecture a of asm_led istype states is (s0,s1,s2,s3,s4,s5); -- 对状态机的状态声明signal q: std_logic_vector( 0 to 2);signal state : states;beginp1: process(clk,clr)beginif(clr='0')thenstate<=s0;elsif (clk'event and clk='1') then case state is when s0=> state <=s1;when s1=> state <=s2; when s2=> state <=s3; when s3=> state<=s4; when s4=> state <=s5; when s5=> state <=s0; when others =>state<=s0;end case;end if;end process p1;p2: process (clr,state)beginif(clr='0') thenled1<='0';led2<='0'; led3<='0';elsecase state iswhen s0=> led1<='1';led2<='0';led3<='0';when s1=> led1<='0';led2<='1';led3<='0'; when s2=>led1<='0';led2<='1';led3<='0'; when s3=>led1<='0';led2<='0';led3<='1'; when s4=>led1<='0';led2<='0';led3<='1'; when s5=>led1<='0';led2<='0';led3<='1'; when others => null;end case;end if;end process p2;end ;第 6 章EDA 仿真技术应用实例 6.1带使能和片选端的16：4 线优先编码器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity pencoder isport(d:in std_logic_vector(7 downto 0); ei:in std_logic; --ei:enable input gs,eo:out bit; --gs:chip select output;eo:enable outputq2,q1,q0:out std_logic);end pencoder;architecture encoder of pencoder is beginprocess(d)begin if(d(0)='0' and ei='0')then q2<='1';q1<='1';q0<='1'; gs<='0';eo<='1';elsif(d(1)='0' and ei='0')then q2<='1';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(2)='0' and ei='0')then q2<='1';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(3)='0' and ei='0')then q2<='1';q1<='0';q0<='0';gs<='0';eo<='1';elsif(d(4)='0' and ei='0')then q2<='0';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(5)='0' and ei='0')then q2<='0';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(6)='0' and ei='0')then q2<='0';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(7)='0' and ei='0')then --d7 prioty encoderq2<='0';q1<='0';q0<='0';gs<='0';eo<='1'; elsif(ei='1')thenq2<='1';q1<='0';q0<='1'; gs<='1';eo<='1';'0')then q2<='1';q1<='1';q0<='1'; gs<='1';eo<='0'; end if;end process; end encoder;6.27 段显示译码器设计译码器设计源代码：library ieee; use ieee.std_logic_1164.all;entity decoder47 is port(lt,ibr,ib_ybr:in bit;a: in std_logic_vector(3 downto 0); y:out std_logic_vector(6 downto 0)); end decoder47;architecture art of decoder47 is beginprocess(lt,ibr,ib_ybr,a)variable s: std_logic_vector(3 downto 0);begins:=a(3)&a(2)&a(1)&a(0);if lt='0' and ib_ybr='1' then--检查七段显示管是否正常y<="1111111";elsif ibr='0' and a="0000" then y<="0000000";elsecase s iswhen"0000"=>y<="1111110"; --7Ewhen"0001"=>y<="0110000"; --30when"0010"=>y<="1101101"; --6Dwhen"0011"=>y<="1111001"; --79when"0100"=>y<="0110011"; --33when"0101"=>y<="1011011"; --5Bwhen"0110"=>y<="0011111"; --5Fwhen"0111"=>y<="1110000"; --70when"1000"=>y<="1111111"; --7Ewhen"1001"=>y<="1110011"; --7Bwhen"1010"=>y<="0001101"; --0Dwhen"1011"=>y<="0011001"; --19when"1100"=>y<="0100011"; --23when"1101"=>y<="1001011"; --4Bwhen"1110"=>y<="0001111"; --0Fwhen"1111"=>y<="0000000";end case;end if;end process;end art;6.3 带异步清零端的12 位二进制全加器设计子模块源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0); s: out std_logic_vector(3 downto 0);cout:out std_logic);end adder4b;architecture art of adder4b issignal sint:std_logic_vector(4 downto 0);signal aa,bb:std_logic_vector(4 downto0);beginprocess(clr)beginif clr='1'thensint<="00000";elseaa<='0'&a;bb<='0'&b; sint<=aa+bb+cin;end if; s<=sint(3 downto 0); cout<=sint(4);end process; end art;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder12b is port(clr,cin: instd_logic;a,b: in std_logic_vector(11 downto 0); s: out std_logic_vector(11 downto 0); cout:outstd_logic);end adder12b; architecture art of adder12b is component adder4b is port(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0); s: out std_logic_vector(3 downto 0); cout:outstd_logic);end component;signal carry_out1:std_logic;signal carry_out2:std_logic;beginu1:adder4b port map(clr=>clr,cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0), s=>s(3 downto0),cout=>carry_out1);u2:adder4b port map(clr=>clr,cin=>carry_out1,a=>a(7 downto 4),b=>b(7 downto 4),s=>s(7 downto 4),cout=>carry_out2);u3:adder4b port map(clr=>clr,cin=>carry_out2,a=>a(11 downto 8),b=>b(11 downto 8), s=>s(11downto 8),cout=>cout);end art;6.4 带异步清零/置位端的JK 触发器设计带异步清零/置位端的JK 触发器源程序如下：library ieee;use ieee.std_logic_1164.all; entity jkff_logic is port(j,k,clk,clr,set:in std_logic;q:out std_logic); end jkff_logic; architecture art of jkff_logic is signal q_s:std_logic;begin process(clk,clr,set,j,k) beginif set='0' then q_s<='1'; -- 异步置位elsif clr='1' then q<='0'; -- 异步复位elsif clk'event and clk='1' then if (j='0') and (k='1') then q_s<='0';elsif(j='1') and (k='0') thenq_s<='1';elsif(j='1') and (k='1') then q_s<=not q_s;end if;end if; q<=q_s;end process;end art;6.5 4 位锁存器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity latch1b is port(d: in std_logic;ena: in std_logic; -- 使能端q: out std_logic);end latch1b;architecture art of latch1b isbegin process(d,ena) begin if ena='1' then q<=d;end if;end process;end art;元件声明程序包设计源代码：library ieee;use ieee.std_logic_1164.all;package my_package is component latch1port(d:in std_logic;ena:in std_logic;q: out std_logic);end component; end;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use work.my_package.all; --使用用户自定义的程序包entity latch4d isport(d: in std_logic_vector(3 downto 0);oen: in bit;q:out std_logic_vector(3 downto 0));end latch4d;architecture one of latch4d issignal sig_save:std_logic_vector(3 downto 0);begin getlatch:for n in 0 to 3 generate --用for_generate 语句循环例化4 个1 位锁存器latchx:latch1 port map(d(n),g,sig_save(n)); --关联end generate;q<=sig_save when oen='0'else"ZZZZ";• • • • 1end one;6.6 32 进制多样型计数器设计(1)32 进制同步加法计数器源程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_plus is port(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0)); end;architecture art of counter_plus issignal d0,d1:std_logic_vector(3 downto 0); --d0 代表个位，d1 代表十位beginprocess(clk,clr,)beginif clr='1'then d1<=(others=>'0');d0<="0000"; -- 同步清零elsif clk'event and clk='1' then if(d1=3 and d0=1)then d1<="0000";d0<="0000"; -- 计数到32 时清零elsif(d0=1) thend0<="0000"; d1<=d1+1;else d0<=d0+1;end if;end if; dout1<=d1;dout0<=d0;end process;end art;(2)32 进制同步减法计数器源程序32 进制同步减法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_sub is port(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_sub issignal d0,d1:std_logic_vector(3 downto 0); beginprocess(clk,clr)beginif clr='1' then d1<="0000";d0<="0000";elsif clk'event and clk='1' then if(d1=0 andd0=0) then d1<="0011";d0<="0001";elsif(d0=0) thend0<="0001";d1<=d1-1;else d0<=d0-1;d1<=d1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;--d0 代表个位，d1 代表十位--异步清零-- 设定容量3132 进制同步可逆计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_reversible isport(clk,clr,s:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));--s=1 加法计数，s=0 减法计数end;architecture art of counter_reversible is signald0,d1:std_logic_vector(3 downto 0); beginprocess(clk,clr,s)beginif clr='1'then d1<="0000";d0<="0000";elsif (clk'event and clk='1' )thenif s='1' thenif(d1=3 and d0=1) thend1<="0000";d0<="0000";elsif(d0=1) then d0<="0000";d1<=d1+1;else d0<=d0+1; end if;elsif s='0' then if(d1=0 andd0=0)then d1<="0011"; d0<="0001";elsif(d0=0) then d0<="0001";d1<=d1-1;elsed0<=d0-1; d1<=d1;end if;end if;end if;dout1<=d1;dout0<=d0;end process;end art;(4)32 进制异步加法计数器源程序32 进制异步加法计数器源程序如下：①子模块D 触发器源程序设计。

(完整word版)EDA实验报告序列检测器的VHDL设计

实验七序列检测器的VHDL设计一、实验目的用状态机实现序列检测器的设计，了解一般状态机的设计与应用。

二、实验设计原理序列检测器可用于检测一组或多组由二进制码组成的脉冲序列信号，当序列检测器连续收到一组串行二进制码后，如果这组码与检测器中预先设置的码相同，则输出 1，否则输出 0。

由于这种检测的关键在于正确码的收到必须是连续的，这就要求检测器必须记住前一次的正确码及正确序列，直到在连续的检测中所收到的每一位码都与预置数的对应码相同。

在检测过程中，任何一位不相等都将回到初始状态重新开始检测。

书上P168例5-11 描述的电路完成对序列数“11100101”的检测，当这一串序列数高位在前(左移)串行进入检测器后，若此数与预置的密码数相同，则输出“A”,否则仍然输出“B”。

三、实验内容用VHDL状态机设计一个8位序列信号检测器。

要求：利用QuartusII进行文本编辑输入、仿真测试并给出仿真波形，了解控制信号的时序，最后进行引脚锁定并完成硬件测试实验。

程序设计及程序分析如下：LIBRARY IEEE ;USE IEEE.STD_LOGIC_1164.ALL;ENTITY SCHK ISPORT(DIN, CLK, CLR : IN STD_LOGIC;AB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));END SCHK;ARCHITECTURE behav OF SCHK ISSIGNAL Q : INTEGER RANGE 0 TO 8 ;SIGNAL D : STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIND <= “11100101” ;PROCESS( CLK, CLR )BEGINIF CLR = ‘1' THEN Q <= 0 ;ELSIF CLK'EVENT AND CLK='1' THENCASE Q ISWHEN 0=> IF DIN = D(7) THEN Q <= 1 ; ELSE Q <= 0 ; END IF ;WHEN 1=> IF DIN = D(6) THEN Q <= 2 ; ELSE Q <= 0 ; END IF ;WHEN 2=> IF DIN = D(5) THEN Q <= 3 ; ELSE Q <= 0 ; END IF ;WHEN 3=> IF DIN = D(4) THEN Q <= 4 ; ELSE Q <= 0 ; END IF ;WHEN 4=> IF DIN = D(3) THEN Q <= 5 ; ELSE Q <= 0 ; END IF ;WHEN 5=> IF DIN = D(2) THEN Q <= 6 ; ELSE Q <= 0 ; END IF ;WHEN 6=> IF DIN = D(1) THEN Q <= 7 ; ELSE Q <= 0 ; END IF ;WHEN 7=> IF DIN = D(0) THEN Q <= 8 ; ELSE Q <= 0 ; END IF ;WHEN OTHERS => Q <= 0 ;END CASE ;END IF ;END PROCESS ;PROCESS( Q )BEGINIF Q = 8 THEN AB <= “1010” ;ELSE AB <= “1011” ;END IF ;END PROCESS ;END behav ;四、仿真分析编译仿真后的波形如下所示：由仿真结果可以看到，由于预置的密码数是“11100101”，当输入的序列数与上述的数字相同，输出才由B变成A。

eda第3章VHDL编程基础4-5

向
* CASE 语句
控
* LOOP 语句
制语
* EXIT 语句
句
* NEXT 语句
* NULL 语句（空操作语句）
* RETURN 语句（返回语句） * WAIT 语句（等待语句） *子程序调用语句
沈阳农业大学信息与电气工程学院
第3章 VHDL编程基础
顺序语句只能出现在进程(Process)和子程序中。
G(2) := H(1) ；G(1) := H(2) ； E := H(3) ；F := H(4) ；
沈阳农业大学信息与电气工程学院
第3章 VHDL编程基础
3.4.2 转向控制语句转向控制语句共有五种： IF 语句 CASE 语句 LOOP语句 NEXT 语句 EXIT 语句
沈阳农业大学信息与电气工程学院
说明数据类型、子程序、变量等
END PROCESS [进程标号]；
It is important that the sensitivity list includes all signals that might cause an output to change.
沈阳农业大学信息与电气工程学院
第3章 VHDL编程基础
沈阳农业大学信息与电气工程学院
第3章 VHDL编程基础
ARCHITECTURE rt OF mux21_2 IS
BEGIN
PROCESS ( a,b,c,p1,p2 ) IS
BEGIN
IF ( p1='1‘ ) THEN z <= a;
p1=‘1’
ELSIF ( p2='0‘ ) THEN
z <= b; p2=‘0’ ELSE
END PROCESS；

EDA常用电路设计程序

用VHDL进行基本逻辑电路设计总结组合逻辑电路设计、时序逻辑电路设计、状态机设计、存储器设计（调用宏功能模块进行设计）1 组合逻辑电路设计常见组合逻辑电路设计主要有：基本门电路、3-8译码器、8-3线优先编码器、比较器、多路选择器、三态门电路、单向总线驱动器、双向总线缓冲器等。

1.1 基本门电路基本门电路用VHDL语言来描述十分方便。

为方便起见，在下面的两输入模块中，使用VHDL中定义的逻辑运算符，同时实现一个与门、或门、与非门、或非门、异或门及反相器的逻辑。

LIBRARY IEEE；USE IEEE.STD_LOGIC_1164.ALL；ENTITY GATE ISPORT (A，B：IN STD_LOGIC；YAND,YOR,YNAND,YNOR,YNOT,YXOR：OUT STD_LOGIC)；END GATE；ARCHITECTURE ART OF GATE ISBEGINYAND <=A AND B；--与门输出YOR <=A OR B；--或门输出YNAND <=A NAND B；--与非门输出YNOR <=A NOR B；--或非门输出YNOT <=A NOT B；--反相器输出YXOR <=A XOR B；--异或门输出END ART；1.2 3-8译码器下面我们分别以2种方法描述一个3-8译码器。

方法1：使用CASE_WHEN 语句LIBRARY IEEE；USE IEEE.STD_LOGIC_1164.ALL；ENTITY DECODER ISPORT(SEL：IN STD_LOGIC_VECTOR(2 DOWNTO 0)；EN: IN STD_LOGIC; ---加使能控制端Y：OUT STD_LOGIC _VECTOR (7 DOWNTO 0))；END;ARCHITECTURE ART1 OF DECODER ISBEGINPROCESS(SEL,EN)BEGINY<=”11111111”;IF(EN=’1’) THENCASE SEL ISWHEN "000"=> Y(0)<= ‘0’；--输出低有效WHEN "001"=> Y(1)<= ‘0’；WHEN "010"=> Y(2)<= ‘0’；WHEN "011"=> Y(3)<= ‘0’；WHEN "100"=> Y(4)<= ‘0’；WHEN "101"=> Y(5)<= ‘0’；WHEN "110"=> Y(6)<= ‘0’；WHEN "111"=> Y(7)<= ‘0’；WHEN OTHERS=>NULL；END CASE；ELSE Y<=”11111111”;END IF;END PROCESS;END ART1；方法2：使用条件选择WHEN ELSE语句ARCHITECTURE ART2 OF DECODER ISBEGINY (0)<=‘0’ WHEN (EN=’1’AND SEL="000") ELSE ’1’；Y (1)<=‘0’ WHEN (EN=’1’AND SEL="001") ELSE ’1’；Y (2)<=‘0’ WHEN (EN=’1’AND SEL="010") ELSE ’1’；Y (3)<=‘0’ WHEN (EN=’1’AND SEL="011") ELSE ’1’；Y (4)<=‘0’ WHEN (EN=’1’AND SEL="100") ELSE ’1’；Y (5)<=‘0’ WHEN (EN=’1’AND SEL="101") ELSE ’1’；Y (6)<=‘0’ WHEN (EN=’1’AND SEL="110") ELSE ’1’；Y (7)<=’0’ WHEN (EN=’1’AND SEL="111") ELSE ’1’；END ART2；注意：使用了8条 WHEN ELSE 语句1.3 8-3线优先编码器8-3线优先编码器输入信号为y0、y1、y2、y3、y4、y5、y6和y7，输出信号为OUT0、OUT1和OUT2。

vhdl 源代码

VHDL源代码：library ieee; --显示器彩条发生器use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity VGA isport(clk,mode :in std_logic; --扫描时钟/显示模式选择时钟d,hs,vs,r,g,b:out std_logic); --行，场同步/红，绿，蓝end VGA;architecture a of VGA issignal hs1,vs1,fclk,cclk,divide_clk,dly: std_logic;signal mmode :std_logic_vector(1 downto 0); --方式选择signal cnt :std_logic_vector(2 downto 0);signal fs :std_logic_vector(3 downto 0);signal cc :std_logic_vector(4 downto 0); --行同步/横彩条生成 signal ll :std_logic_vector(8 downto 0); --长同步/竖彩条生成 signal grbh :std_logic_vector(3 downto 1); --X 横彩条signal grby :std_logic_vector(3 downto 1); --Y 竖彩条signal grbx :std_logic_vector(3 downto 1); --文字signal grbt :std_logic_vector(3 downto 1); --图案signal grbp :std_logic_vector(3 downto 1);signal grb :std_logic_vector(3 downto 1);signal x :integer range 0 to 800;signal x1: integer range 0 to 800;signal y1: integer range 0 to 600;signal x2: integer range 0 to 800;signal x3: integer range 0 to 800;signal x4: integer range 0 to 800;signal x5: integer range 0 to 800;signal x7: integer range 0 to 800;signal x8: integer range 0 to 800;signal x9: integer range 0 to 800;signal x10: integer range 0 to 800;signal x11: integer range 0 to 800;signal y2: integer range 0 to 600;signal y3: integer range 0 to 600;signal y4: integer range 0 to 600;signal y5: integer range 0 to 600;signal y6: integer range 0 to 600;signal c: integer range 0 to 30;begingrb(3)<=(grbp(3) xor mode) and hs1 and vs1;grb(2)<=(grbp(2) xor mode) and hs1 and vs1;grb(1)<=(grbp(1) xor mode) and hs1 and vs1;process(mode)beginif mode'event and mode='1' thenif mmode="11" thenmmode<="00";elsemmode<=mmode+1;end if;end if;end process; --四种模式process (mmode)beginif mmode="00" then grbp<=grbx;elsif mmode="01" then grbp<=grbh; --选择横彩条 elsif mmode="10" then grbp<=grby; --选择竖彩条 elsif mmode="11" then grbp<=grbh xor grby; --选择棋盘格 else grbp<="000";end if;end process;process(clk) --3/4分频 beginif clk'event and clk='1' thencnt<=cnt+3;dly<=cnt(2);end if;--if cnt<3 then-- divide_clk<='0';--elsif cnt<5 then-- divide_clk<='1';--else-- cnt<="000";--end if;end process;divide_clk<=(cnt(2) xor dly) and clk;process(divide_clk) --13分频beginif divide_clk'event and divide_clk='1' then if fs=12 thenfs<="0000";elsefs<=fs+1;end if;end if;end process;process(fclk)beginif fclk'event and fclk='1' thenif cc=29 thencc<="00000";elsecc<=cc+1;end if;end if;end process;d<=fclk;process(cclk)beginif cclk'event and cclk='1' thenif ll=481 thenll<="000000000";elsell<=ll+1;end if;end if;end process;process(cc,ll)beginif cc>23 then --行同步hs1<='0';elsehs1<='1';end if;if ll>479 then --长同步vs1<='0';elsevs1<='1';end if;end process;process(clk)beginif clk'event and clk='1' thenif hs1='0' thenx<=0;elsex<=x+1;end if;end if;end process;process(x,ll,cc,hs1,vs1)variable s1: integer range 0 to 3;beginif cc<3 then grbh<="111"; --竖彩条 elsif cc<6 then grbh<="110";elsif cc<9 then grbh<="101";elsif cc<12 then grbh<="100";elsif cc<15 then grbh<="011";elsif cc<18 then grbh<="010";elsif cc<21 then grbh<="001";else grbh<="000";end if;if ll<60 then grby<="111"; --横彩条 elsif ll<120 then grby<="110";elsif ll<180 then grby<="101";elsif ll<240 then grby<="100";elsif ll<300 then grby<="011";elsif ll<360 then grby<="010";elsif ll<420 then grby<="001";else grby<="000";end if;if x=4 thengrbx<="100";elsif x=180 thengrbx<="001";elsegrbx<="000";end if;if ll>20 and ll<24 thenif x<110 thengrbx<="100";end if;end if;if ll>30 and ll<33 thenif x<80 thengrbx<="100";end if;end if;if ll>445 and ll<449 thenif x>90 thengrbx<="001";end if;end if;if ll>437 and ll<440 thenif x>100 thengrbx<="001";end if;end if;--"湖"if ll>89 and ll<94 thenif x=100 or x=103 or x=106 or x=107 or x=108 then grbx<="110";end if;end if;if ll>93 and ll<98 thenif x=102 or x=103 or x=104 or x=106 or x=108 then grbx<="110";end if;end if;if ll>97 and ll<102 thenif x=100 or x=103 or x=106 or x=107 or x=108 then grbx<="110";end if;end if;if ll>101 and ll<106 thenif x=102 or x=103 or x=104 or x=106 or x=108 then grbx<="110";end if;end if;if ll>105 and ll<110 thenif x=100 or x=102 or x=104 or x=106 or x=107 or x=108 then grbx<="110";end if;end if;if ll>109 and ll<114 thenif x=100 or x=102 or x=103 or x=104 or x=106 or x=108 then grbx<="110";end if;end if;if ll>113 and ll<118 thenif x=106 thengrbx<="110";end if;end if;--"南"if ll>121 and ll<126 thenif x=104 thengrbx<="110";end if;end if;if ll>125 and ll<130 thenif x>99 and x<109 thengrbx<="110";end if;end if;if ll>129 and ll<134 thenif x=104 thengrbx<="110";end if;end if;if ll>133 and ll<138 thenif x>99 and x<109 thengrbx<="110";end if;end if;if ll>137 and ll<142 thenif x=100 or x=108 thengrbx<="110";end if;end if;if ll>141 and ll<146 thenif x=100 or x=103 or x=105 or x=108 thengrbx<="110";end if;end if;if ll>145 and ll<150 thenif x=100 or x=102 or x=103 or x=104 or x=105 or x=106 or x=108 then grbx<="110";end if;end if;if ll>149 and ll<154 thenif x=100 or x=104 or x=108 thengrbx<="110";end if;end if;if ll>153 and ll<158 thenif x=100 or x=102 or x=103 or x=104 or x=105 or x=106 or x=108 then grbx<="110";end if;end if;if ll>157 and ll<162 thenif x=100 or x=104 or x=108 thengrbx<="110";end if;end if;--"大"if ll>165 and ll<170 thenif x=103 or x=104 thengrbx<="110";end if;end if;if ll>169 and ll<174 thenif x=103 or x=104 thengrbx<="110";end if;end if;if ll>173 and ll<178 thenif x=100 or x=101 or x=102 or x=103 or x=104 or x=105 or x=106 or x=107 or x=108 thengrbx<="110";end if;end if;if ll>177 and ll<182 thenif x=103 or x=104 thengrbx<="110";end if;end if;if ll>181 and ll<186 thenif x=103 or x=104 thengrbx<="110";end if;end if;if ll>185 and ll<190 thenif x=103 or x=105 thengrbx<="110";end if;end if;if ll>189 and ll<194 thenif x=102 or x=103 or x=106 thengrbx<="110";end if;end if;if ll>193 and ll<198 thenif x=101 or x=102 or x=107 thengrbx<="110";end if;end if;if ll>197 and ll<202 thenif x=100 or x=101 or x=107 or x=108 thengrbx<="110";end if;end if;--"学"if ll>205 and ll<210 thenif x=102 or x=104 or x=106 thengrbx<="110";end if;end if;if ll>209 and ll<214 thenif x=100 or x=101 or x=102 or x=103 or x=104 or x=105 or x=106 or x=107 or x=108 thengrbx<="110";end if;end if;if ll>213 and ll<218 thenif x=100 or x=108 thengrbx<="110";end if;end if;if ll>217 and ll<222 thenif x=102 or x=103 or x=104 or x=105 or x=106 thengrbx<="110";end if;end if;if ll>221 and ll<226 thenif x=105 thengrbx<="110";end if;end if;if ll>225 and ll<230 thenif x=104 thengrbx<="110";end if;end if;if ll>229 and ll<234 thenif x=100 or x=101 or x=102 or x=103 or x=104 or x=105 or x=106 or x=107 or x=108 thengrbx<="110";end if;end if;if ll>233 and ll<238 thenif x=104 thengrbx<="110";end if;end if;if ll>237 and ll<242 thenif x=104 thengrbx<="110";end if;end if;if ll>241 and ll<245 thenif x=103 or x=104 thengrbx<="110";end if;end if;if vs1'event and vs1='1' thenif c=20 thenc<=0;case s1 iswhen 0 =>if x1=120 thens1:=1;elsex1<=x1+1 ; end if;when 1 =>if y1=350 thens1:=2;elsey1<=y1+1; end if;when 2 =>if x1=35 thens1:=3;elsex1<=x1-1; end if;when 3 =>if y1=280 thens1:=0;elsey1<=y1-1; end if;end case;elsec<=c+1;end if;end if;--"HU NAN DA XUE"x2<=x1+1;x3<=x1+2;x4<=x1+3;x5<=x1+5;x7<=x1+7;x8<=x1+8;x9<=x1+9;x10<=x1+10;x11<=x1+11;--y1<=250;y2<=y1+4;y3<=y1+8;y4<=y1+12;y5<=y1+16;y6<=y1+20;if ll>=y1 and ll<y2 thenif x=x1 or x=x5 or x=x7 or x=x8 or x=x11 thengrbx<="101";end if;end if;if ll>=y2 and ll<y3 thenif x=x1 or x=x5 or x=x7 or x=x8 or x=x9 or x=x11 thengrbx<="101";end if;end if;if ll>=y3 and ll<y4 thenif x=x1 or x=x2 or x=x3 or x=x4 or x=x5 or x=x7 or x=x9 or x=x11 then grbx<="101";end if;end if;if ll>=y4 and ll<y5 thenif x=x1 or x=x5 or x=x7 or x=x10 or x=x11 thengrbx<="101";end if;end if;if ll>=y5 and ll<y6 thenif x=x1 or x=x5 or x=x7 or x=x10 or x=x11 thengrbx<="101";end if;end if;if ll>100 and 11<150 then --图案设计if ll>121 and ll<126 thenif x>43 and x<57 thengrbx<="100";end if;elsif x=50 thengrbx<="100";end if;end if;if ll>150 and 11<200 thenif ll>171 and ll<176 thenif x>60 and x<74 thengrbx<="010";end if;elsif x=67 thengrbx<="010";end if;end if;if ll>200 and 11<250 then if ll>221 and ll<226 then if x>74 and x<88 then grbx<="001";end if;elsif x=81 thengrbx<="001";end if;end if;end process;fclk<=fs(2);cclk<=cc(4);hs<= not hs1;vs<= not vs1;g<=grb(3);r<=grb(2);b<=grb(1);end a;。

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第4 章用VHDL 程序实现常用逻辑电路4.1组合逻辑电路设计4.1.1基本逻辑门library ieee;use iee.std_logic_1164.all;entity jbm isport(a,b: in bit;f1,f2,f3,f4,f5,f: out bit);end jbm;architecture a of jbm isbeginf1<=a and b; --构成与门f2<=a or b; --构成或门f<=not a; --构成非门f3<=a nand b; --构成与非门f4<=a nor b; --构成异或门f5<=not(axor b); --构成异或非门即同门end;4.1.2三态门library ieee;use ieee.std_logic_1164.all;entity tri_s isport(enable: in std_logic;datain: in std_logic_vector(7 downto 0);dataout: out std_logic_vector(7 downto0));end tri_s;architecture bhv of tri_s isbeginprocess(enable,datain)beginif enable='1' thendataout<=datain;elsedataout<="ZZZZZZZZ";end if;end process;end bhv;4.1.33-8 译码器library ieee;use ieee.std_logic_1164.all;entity decoder3_8 isport(a,b,c,g1,g2a,g2b: in std_logic;y: out std_logic_vector(7 downto 0));end decoder3_8;architecture a of decoder3_8 issignal dz:std_logic_vector(2 downto 0);begindz<=c&b&a;process (dz,g1,g2a,g2b)beginif(g1='1'and g2a='0'and g2b='0')thencase dz iswhen "111"=> y<="01111111";when others=>y<="XXXXXXXX";end case;elseend if;end process;4.1.4优先编码器library ieee;use ieee.std_logic_1164.allentity coder isport(din: in std_logic_vector(0 to 7);output: out std_logic_vector(0 to 2));end coder;architecture behave of coder issignal sint: std_logic_vevtor(4 downto 0);beginprocess(din)beginif (din(7)='0') thenoutput <= "000" ;elsif (din(6)='0') thenoutput <= "100" ;elsif (din(5)='0') thenoutput <= "010" ;elsif (din(4)='0') thenoutput <= "110" ;elsif (din(3)='0') thenoutput <= "001" ;elsif (din(2)='0') thenoutput <= "101" ;elsif (din(1)='0') thenoutput <= "011" ;elseoutput <= "111" ;end if;end process;end behav;4.1.57 段码译码器library ieee;use ieee.std_logic_1164.allentity decl7s isport (a: in std_logic_vector (3 downto 0);led7s: out std_logic_vector(6 downto 0));end decl7s;architecture behave of decl7s isbeginprocess(a)begincase a iswhen "0000" => led7s <= "0111111" ;when "0001" => led7s <= "0000110" ;when "0010" => led7s <= "1011011" ;when "0011" => led7s <= "1001111" ;when "0100" => led7s <= "1100110" ;when "0101" => led7s <= "1101101" ;when "0110" => led7s <= "1111101" ;when "0111" => led7s <= "0000111" ;when "1000" => led7s <= "1111111" ;when "1001" => led7s <= "1101111" ;when "1010" => led7s <= "1110111" ;when "1011" => led7s <= "1111100" ;when "1100" => led7s <= "0111001" ;when "1101" => led7s <= "1011110" ;when "1110" => led7s <= "1111001" ;when "1111" => led7s <= "1110001" ;when others => null;end case;end process;end behave;4.1.6二-十进制BCD 译码器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity bcdymq isport(din : in integer range 15 downto 0;a,b : out integer range 9 downto 0);end;architecture fpq1 of bcdymq isbeginp1: process(din)beginif din<10 thena< =din;b< =0;elsea< =din-10;b< =1;end if;end process p1;end;4.1.7多位加（减）法器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity jianfaqi isport(a,b : in std_logic_vector(0 to 3);c0: in std_logic;c1: out std_logic;d : out std_logic_vector(0 to 3));end;architecture a of jianfaqi isbeginprocessbeginif a>b+c0 thend<=a-(b+c0);c1<='0';elsec1<='1';d<=("10000")-(b+c0-a);end if;end process ;end ;4.2时序逻辑电路设计4.2.1触发器RS 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity rsff isport(r,s,clk:in std_logic;q,qb:buffer std_logic);end rsff;architecture rsff_art of rsff issignal q_s,qb_s:std_logic;beginprocess(clk,r,s)beginif (clk'event and clk='1') thenif (s='1' and r='0') thenq_s<='0' ;qb_s<='1' ;elsif (s='0' and r='1') thenq_s <= '1' ;qb_s <= '0' ;elsif (s='0' and r='0') thenq_s <= q_s;qb_s <= qb_s;end if;end if;q_s <= q_s;qb_s <= qb_s;end process;end rsff_art;同步复位D 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity syndff isport(d,clk,reset:in std_logic;q,qb:out std_logic);end syndff;architecture dff_art of syndff isbeginprocess(clk)beginif (clk'event and clk='1') thenif (reset='0') thenq<='0';qb<='1';elseq<=d;qb<=not q;end if;end if;end process;end dff_art;JK 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity asynjkff isport(j,k,clk,set.reset:in std_logic;q,qb:out std_logic);end asynjkff;architecture jkff_art of asynjkff issingal q_s,qb_s:std_logic;beginprocess(clk,set,reset)beginif (set='0' and reset='1' ) thenq_s<='1';qb_s<='0';elsif (set='1' and reset='0' ) thenq_s<='0';qb_s<='1';elsif (clk'event and clk='1') thenif (j='0' and k='1' ) thenq_s<='0';qb_s<='1';elsif (j='1' and k='0' ) thenq_s<='1';qb_s<='0';elsif (j='1' and k='1' ) thenq_s<=not q_s;qb_s<=not qb_s;end if;end if;q<= q_s;qb<= qb_s;end process;end jkff_art;T 触发器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;entity tff isport(t,clk: in std_logic;q: out std_logic);end;architecture tff_art of tff issignal q_temp: std_logic;beginp1:process(clk)beginif rising_edge(clk) thenif t='1' then --当T=1 时T 触发器具有2 分频的功能q_temp<=not q_temp;elseq_temp<=q_temp;end if;end if;q<=q_temp;end process;q<=q_temp;end tff_art;4.2.2计数器library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt4 ISport( clk: in std_logic;q: out std_logic_vector(3 downto 0));end cnt4;architecture behave of cnt4 issignal q1: std_logic_vector(3 downto 0);beginprocess(clk)beginif (clk'event and clk = '1') thenq1<=q1+1;end if;end process;q<=q1;end behave;一般计数器设计library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity cnt10 isport( clk,rst,en,updown: in std_logic;cq: out std_logic_vector(3 downto 0));end cnt10;architecture behave of cnt10 isbeginprocess(clk,rst,en,updown)variable cqi:std_logic_vector(3 downto 0);beginif rst='1' thencqi:=(others=>'0'); --计数器异步复位elsif (clk'event and clk = '1') then --检测时钟上升沿if en='1'then --检测是否允许计数（同步使能）if updown='0'thenif cqi<9 thencqi:=cqi+1; --允许计数,检测是否小于9elsecqi:=(others=>'0'); --大于9，计数值清零end if;elseif cqi>0 thencqi:=cqi-1; --检测是否大于0elsecqi:=(others=>'1'); ---否则，计数值置1end if;end if;end if;end if;cq<=cqi; --将计数值向端口输出end process;end behave;4.2.3分频器library ieee;use std_logic_1164.all;use std_logic_unsigned.all;entity freq1 isport(clk: in std_logic;d: in std_logic_vector(7 downto 0);fout: out std_logic);end;architecture one of dvf issignal full: std_logic;beginp_reg:process(clk)variable cnt8: std_logic_vector(7 downto 0);beginif clk'event and clk='1'then --检测时钟上升沿if cnt8='''' thencnt8:=d; --当CNT8 计数计满时，输入数据D 被同步预置给计数器CNT8full<='1'; --同时使溢出标志信号FULL 输出为高电平elsecnt8:=cnt8+1; --否则继续作加1 计数full<='0'; --且输出溢出标志信号FULL 为低电平end if;end if;end process p_reg;p_div:process(full)variable cnt2: std_logic;beginif full'event and full='1' thencnt2:=not cnt2; --如果溢出标志信号FULL 为高电平，T 触发器输出取反if cnt2='1'thenfout<='1';elsefout<='0';end if;end if;end process p_div;end;4.2.4移位寄存器library ieee;use ieee.std_logic_1164.all;entity shift isport(clk,c0: in std_logic; --时钟和进位输入md: in std_logic_vector(2 downto 0); --移位模式控制字d:in std_logic_vector(7 downto 0); --待加载移位的数据qb:out std_logic_vector(7 downto 0); --移位数据输出cn: outstd_logic); --进位输出end;architecture behave of shift issignal reg: std_logic_vector(7 downto 0);signal cy: std_logic;beginprocess(clk,md,c0)beginif clk'event and clk='1' thencase md iswhen "001" => reg (0) <= c0 ;reg (7 downto 1) <= reg (6 downto 0);cy <= reg (7); --带进位循环左移when "010" => reg (0) <= reg (7);reg (7 downto 1) <= reg (6 downto 0); --自循环左移when "011" => reg (7) <= reg (0);reg (6 downto 0) <= reg (7 downto 1); --自循环右移when "100" => reg (7) <= C0 ;reg (6 downto 0) <= reg (7 downto 1);cy <= reg (0); --带进位循环右移when "101" => reg (7 downto 0) <= d(7 downto 0); --加载待移数when others => reg<= reg ; cy<= cy ; --保持end case;end if;end process;qb(7 downto 0) <= reg (7 downto 0); cn <= cy; --移位后输出end behav;4.3状态机逻辑电路设计4.3.1一般状态机设计library ieee;use ieee.std_logic_1164.all;entity s_machine isport ( clk,reset : in std_logic;state_inputs : in std_logic_vector(0 to1);comb_outputs : out integer range 0 to 15 );end s_machine;architecture behv of s_machine istype fsm_st is (s0, s1, s2, s3); --数据类型定义，状态符号化signal current_state, next_state: fsm_st; --将现态和次态定义为新的数据类型beginreg: process(reset,clk) --主控时序进程beginif reset = '1' thencurrent_state <= s0; --检测异步复位信号elsif clk='1' and clk'event thencurrent_state <= next_state;end if;end process;com:process(current_state, state_inputs) --主控组合进程begincase current_state iswhen s0 => comb_outputs<= 5;if state_inputs = "00" thennext_state<=s0;elsenext_state<=s1;end if;when s1 => comb_outputs<= 8;if state_inputs = "00" thennext_state<=s1;elsenext_state<=s2;end if;when s2 => comb_outputs<= 12;if state_inputs = "11" thennext_state <= s0;elsenext_state <= s3;end if;when s3 => comb_outputs <= 14;if state_inputs = "11" thennext_state <= s3;elsenext_state <= s0;end if;end case;end process;end behv;4.3.2状态机的应用library ieee;use ieee.std_logic_1164.all;entity asm_led isport(clk,clr : in std_logic;led1,led2,led3:out std_logic);end;architecture a of asm_led istype states is (s0,s1,s2,s3,s4,s5); --对状态机的状态声明signal q: std_logic_vector( 0 to 2);signal state : states;beginp1: process(clk,clr)beginif(clr='0')thenstate<=s0;elsif (clk'event and clk='1') thencase state iswhen s0=> state <=s1;when s1=> state <=s2;when s2=> state <=s3;when s3=> state <=s4;when s4=> state <=s5;when s5=> state <=s0;when others => state<=s0;end case;end if;end process p1;p2: process (clr,state)beginif(clr='0') thenled1<='0';led2<='0';led3<='0';elsecase state iswhen s0=> led1<='1';led2<='0';led3<='0';when s1=> led1<='0';led2<='1';led3<='0';when s2=> led1<='0';led2<='1';led3<='0';when s3=> led1<='0';led2<='0';led3<='1';when s4=> led1<='0';led2<='0';led3<='1';when s5=> led1<='0';led2<='0';led3<='1';when others => null;end case;end if;end process p2;end ;第6 章EDA 仿真技术应用实例6.1 带使能和片选端的16：4 线优先编码器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity pencoder isport(d:in std_logic_vector(7 downto 0);ei:in std_logic; --ei:enable inputgs,eo:out bit; --gs:chip select output;eo:enable outputq2,q1,q0:out std_logic);end pencoder;architecture encoder of pencoder isbeginprocess(d)beginif(d(0)='0' and ei='0')thenq2<='1';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(1)='0' and ei='0')thenq2<='1';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(2)='0' and ei='0')thenq2<='1';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(3)='0' and ei='0')thenq2<='1';q1<='0';q0<='0';gs<='0';eo<='1';elsif(d(4)='0' and ei='0')thenq2<='0';q1<='1';q0<='1';gs<='0';eo<='1';elsif(d(5)='0' and ei='0')thenq2<='0';q1<='1';q0<='0';gs<='0';eo<='1';elsif(d(6)='0' and ei='0')thenq2<='0';q1<='0';q0<='1';gs<='0';eo<='1';elsif(d(7)='0' and ei='0')then --d7 prioty encoderq2<='0';q1<='0';q0<='0';gs<='0';eo<='1';elsif(ei='1')thenq2<='1';q1<='0';q0<='1';gs<='1';eo<='1';'0')thenq2<='1';q1<='1';q0<='1';gs<='1';eo<='0';end if;end process;end encoder;6.27 段显示译码器设计译码器设计源代码：library ieee;use ieee.std_logic_1164.all;entity decoder47 isport(lt,ibr,ib_ybr:in bit;a: in std_logic_vector(3 downto 0);y:out std_logic_vector(6 downto 0));end decoder47;architecture art of decoder47 isbeginprocess(lt,ibr,ib_ybr,a)variable s: std_logic_vector(3 downto 0);begins:=a(3)&a(2)&a(1)&a(0);if lt='0' and ib_ybr='1' theny<="1111111"; --检查七段显示管是否正常elsif ibr='0' and a="0000" theny<="0000000";elsecase s iswhen"0000"=>y<="1111110"; --7Ewhen"0001"=>y<="0110000"; --30when"0010"=>y<="1101101"; --6Dwhen"0011"=>y<="1111001"; --79when"0100"=>y<="0110011"; --33when"0101"=>y<="1011011"; --5Bwhen"0110"=>y<="0011111"; --5Fwhen"0111"=>y<="1110000"; --70when"1000"=>y<="1111111"; --7Ewhen"1001"=>y<="1110011"; --7Bwhen"1010"=>y<="0001101"; --0Dwhen"1011"=>y<="0011001"; --19when"1100"=>y<="0100011"; --23when"1101"=>y<="1001011"; --4Bwhen"1110"=>y<="0001111"; --0Fwhen"1111"=>y<="0000000";end case;end if;end process;end art;6.3带异步清零端的12 位二进制全加器设计子模块源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end adder4b;architecture art of adder4b issignal sint:std_logic_vector(4 downto 0);signal aa,bb:std_logic_vector(4 downto 0);beginprocess(clr)beginif clr='1'thensint<="00000";elseaa<='0'&a;bb<='0'&b;sint<=aa+bb+cin;end if;s<=sint(3 downto 0);cout<=sint(4);end process;end art;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder12b isport(clr,cin: in std_logic;a,b: in std_logic_vector(11 downto 0);s: out std_logic_vector(11 downto 0);cout:out std_logic);end adder12b;architecture art of adder12b iscomponent adder4b isport(clr,cin: in std_logic;a,b: in std_logic_vector(3 downto 0);s: out std_logic_vector(3 downto 0);cout:out std_logic);end component;signal carry_out1:std_logic;signal carry_out2:std_logic;beginu1:adder4b port map(clr=>clr,cin=>cin,a=>a(3 downto 0),b=>b(3 downto 0),s=>s(3 downto 0),cout=>carry_out1);u2:adder4b port map(clr=>clr,cin=>carry_out1,a=>a(7 downto 4),b=>b(7 downto 4),s=>s(7 downto 4),cout=>carry_out2);u3:adder4b port map(clr=>clr,cin=>carry_out2,a=>a(11 downto 8),b=>b(11 downto 8),s=>s(11 downto 8),cout=>cout);end art;6.4带异步清零/置位端的JK 触发器设计带异步清零/置位端的JK 触发器源程序如下：library ieee;use ieee.std_logic_1164.all;entity jkff_logic isport(j,k,clk,clr,set:in std_logic;q:out std_logic);end jkff_logic;architecture art of jkff_logic issignal q_s:std_logic;beginprocess(clk,clr,set,j,k)beginif set='0' thenq_s<='1'; --异步置位elsif clr='1' thenq<='0'; --异步复位elsif clk'event and clk='1' thenif (j='0') and (k='1') thenq_s<='0';elsif(j='1') and (k='0') thenq_s<='1';elsif(j='1') and (k='1') thenq_s<=not q_s;end if;end if;q<=q_s;end process;end art;6.5 4 位锁存器设计子模块设计源代码：library ieee;use ieee.std_logic_1164.all;entity latch1b isport(d: in std_logic;ena: in std_logic; --使能端q: out std_logic);end latch1b;architecture art of latch1b isbeginprocess(d,ena)beginif ena='1' thenq<=d;end if;end process;end art;元件声明程序包设计源代码：library ieee;use ieee.std_logic_1164.all;package my_package iscomponent latch1port(d:in std_logic;ena:in std_logic;q: out std_logic);end component;end;顶层模块设计源代码：library ieee;use ieee.std_logic_1164.all;use work.my_package.all; --使用用户自定义的程序包entity latch4d isport(d: in std_logic_vector(3 downto 0);oen: in bit;q:out std_logic_vector(3 downto 0));end latch4d;architecture one of latch4d issignal sig_save:std_logic_vector(3 downto 0);begingetlatch:for n in 0 to 3 generate --用for_generate 语句循环例化4 个1 位锁存器latchx:latch1 port map(d(n),g,sig_save(n)); --关联end generate;q<=sig_save when oen='0'else"ZZZZ";end one;6.632 进制多样型计数器设计（1）32 进制同步加法计数器源程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_plus isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_plus issignal d0,d1:std_logic_vector(3 downto 0); --d0 代表个位，d1 代表十位beginprocess(clk,clr,)beginif clr='1'thend1<=(others=>'0');d0<="0000"; --同步清零elsif clk'event and clk='1' thenif(d1=3 and d0=1)thend1<="0000";d0<="0000"; --计数到32 时清零elsif(d0=1) thend0<="0000";d1<=d1+1;elsed0<=d0+1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（2）32 进制同步减法计数器源程序32 进制同步减法计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_sub isport(clk,clr:in std_logic;dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_sub issignal d0,d1:std_logic_vector(3 downto 0); --d0 代表个位，d1 代表十位beginprocess(clk,clr)beginif clr='1' thend1<="0000";d0<="0000"; --异步清零elsif clk'event and clk='1' thenif(d1=0 and d0=0) thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;dout1<=d1;dout0<=d0;end process;end art;32 进制同步可逆计数器源程序如下：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity counter_reversible isport(clk,clr,s:in std_logic; --s=1 加法计数，s=0 减法计数dout0,dout1: out std_logic_vector(3 downto 0));end;architecture art of counter_reversible issignal d0,d1:std_logic_vector(3 downto 0); --d0 代表个位，d1 代表十位beginprocess(clk,clr,s)beginif clr='1'thend1<="0000";d0<="0000"; --异步清零elsif (clk'event and clk='1' )thenif s='1' thenif(d1=3 and d0=1) thend1<="0000";d0<="0000"; --计数到31 时清零elsif(d0=1) thend0<="0000";d1<=d1+1;else d0<=d0+1;end if;elsif s='0' thenif(d1=0 and d0=0)thend1<="0011";d0<="0001"; --设定容量31elsif(d0=0) thend0<="0001";d1<=d1-1;elsed0<=d0-1;d1<=d1;end if;end if;end if;dout1<=d1;dout0<=d0;end process;end art;（4）32 进制异步加法计数器源程序32 进制异步加法计数器源程序如下：①子模块D 触发器源程序设计。