MEMORY存储芯片NAND512W3A2SN6E中文规格书

ERASE BLOCK MULTI-PLANE (60h-D1h)
The ERASE BLOCK MULTI-PLANE (60h-D1h) command queues a block in the specified
plane to be erased in the NAND Flash array. This command can be issued one or more
times. Each time a new plane address is specified, that plane is also queued for a block
to be erased. To specify the final block to be erased and to begin the ERASE operation
for all previously queued planes, issue the ERASE BLOCK (60h-D0h) command. This
command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).
To queue a block to be erased, write 60h to the command register, then write three ad-
dress cycles containing the row address; the page address is ignored. Conclude by writ-
ing D1h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY =
0)for t DBSY.
To determine the progress of t DBSY, the host can monitor the target's R/B# signal, or
alternatively, the status operations (70h, 78h) can be used. When the LUN's status
shows that it is ready (RDY = 1, ARDY = 1), additional ERASE BLOCK MULTI-PLANE
(60h-D1h) commands can be issued to queue additional planes for erase. Alternatively,
the ERASE BLOCK (60h-D0h) command can be issued to erase all of the queued blocks.
For multi-plane addressing requirements for the ERASE BLOCK MULTI-PLANE (60h-
D1h) and ERASE BLOCK (60h-D0h) commands, see Multi-Plane Operations.
Figure 56: ERASE BLOCK MULTI-PLANE (60h–D1h) Operation
Cycle type DQ[7:0]
RDY
16Gb, 32Gb, 64Gb Asynchronous/Synchronous NAND
Erase Operations
Table 40: AC Characteristics: Synchronous Command, Address, and Data (Continued)
16Gb, 32Gb, 64Gb Asynchronous/Synchronous NAND Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous)
Figure 77: READ PAGE CACHE RANDOM
WE#
CE#
ALE
CLE
RE#
RDY
DQx
WE#CE#
ALE
CLE RE#RDY DQx
16Gb, 32Gb, 64Gb Asynchronous/Synchronous NAND Asynchronous Interface Timing Diagrams。