SYSTEM EQUIPPED WITH PROCESSOR AND CACHE MEMORY, A
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专利名称：SYSTEM EQUIPPED WITH PROCESSOR AND CACHE MEMORY, AND METHOD OF
CONTROLLING SAID CACHE MEMORY
发明人：TAKAHASHI, HIROMASA,IINO, HIDEYUKI
申请号：EP91916225
申请日：19910918
公开号：EP0502206A4
公开日：
19940309
专利内容由知识产权出版社提供
摘要：A system comprising a cache memory (2) connected to a processor (1) and a main storage (3), wherein the processor includes means 1A for outputting a discrimination signal S designating whether the access to be made to the cache memory is a data access of continuous addresses or a data access of discontinuous addresses, and the cache memory (2) includes means 2A for handling errors in its operation on the basis of the outputted discrimination signal. During access to data of discontinuous addresses, control is so made as to suppress unnecessary accesses to the main storage. In this way, penality at the time of a failure of a cache operation is reduced and eventually, efficiency of the system can be improved as a whole by accomplishing a high speed operation 申请人：FUJITSU LIMITED
地址：1015, KAMIKODANAKA NAKAHARA-KU; KAWASAKI-SHI KANAGAWA 211
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