P6KA39中文资料

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P6KA15中文资料

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P6KA6.8 THRU P6KA43A
AUTOMOTIVE TRANSIENT VOLTAGE SUPPRESSOR
Breakdown Voltage - 6.8 to 43 Volts
D *
Peak Pulse Power - 600 Watts
FEATURES
P A T E
N
T E
DO-204AC
0.034 (0.86) 1.0 (25.4) MIN. 0.028 (0.71) DIA.
0.300 (7.6) 0.230 (5.8)
0.140 (3.6) 0.104 (2.6) DIA. 1.0 (25.4) MIN.
♦ Designed for under the hood applications ♦ Plastic package has Underwriters Laboratory Flammability Classification 94V-0 ♦ Exclusive patented PAR™ oxide passivated chip construction ♦ 600W peak pulse power surge capability with a 10/1000µs waveform repetition rate (duty cycle): 0.01% ♦ Excellent clamping capability ♦ Low incremental surge resistance ♦ Fast response time: typically less than 1.0ps from 0 Volts to V(BR) ♦ For devices with V(BR)≥10V, ID are typically less than1.0µA ♦ High temperature soldering guaranteed: 300°C/10 seconds, 0.375" (9.5mm) lead length, 5lbs. (2.3 kg) tension

W39V080FAP中文资料

W39V080FA Data Sheet1M × 8 CMOS FLASH MEMORYWITH FWH INTERFACE Table of Contents-1.GENERAL DESCRIPTION (3)2.FEATURES (3)3.PIN CONFIGURATIONS (4)4.BLOCK DIAGRAM (4)5.PIN DESCRIPTION (4)6.FUNCTIONAL DESCRIPTION (5)6.1Interface Mode Selection and Description (5)6.2Read (Write) Mode (5)6.3Reset Operation (5)6.4Accelerated Program Operation (5)6.5Boot Block Operation and Hardware Protection at Initial- #TBL & #WP (5)6.6Sector Erase Command (6)6.7Program Operation (6)6.8Dual BIOS (6)6.9Hardware Data Protection (6)6.10Write Operation Status (7)6.10.1DQ7: #Data Polling (7)6.10.2RY/#BY: Ready/#Busy (7)6.10.3DQ6: Toggle Bit (7)6.10.4DQ5: Exceeded Timing Limits (8)6.11Identification Input pin ID[3:0] (8)6.12Register (8)6.12.1General Purpose Inputs Register (8)6.12.2Block Locking Registers (8)6.12.3Product Identification Registers (10)6.13Table of Operating Modes (11)6.13.1Operating Mode Selection - Programmer Mode (11)6.13.2Operating Mode Selection - FWH Mode (11)6.14Fwh Cycle Definition (12)6.15Embedded Programming Algorithm (13)6.16Embedded Erase Algorithm (14)6.17Embedded #Data Polling Algorithm (15)6.18Embedded Toggle Bit Algorithm (16)6.19Software Product Identification and Boot Block Lockout Detection Acquisition Flow..177.DC CHARACTERISTICS (18)7.1Absolute Maximum Ratings (18)7.2Programmer interface Mode DC Operating Characteristics (18)7.3FWH interface Mode DC Operating Characteristics (19)7.4Power-up Timing (19)7.5Capacitance (19)Publication Release Date: Dec. 13, 2005W39V080FA8.PROGRAMMER INTERFACE MODE AC CHARACTERISTICS (20)8.1AC Test Conditions (20)8.2AC Test Load and Waveform (20)8.3Read Cycle Timing Parameters (21)8.4Write Cycle Timing Parameters (21)8.5Data Polling and Toggle Bit Timing Parameters (21)9.TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE (22)9.1Read Cycle Timing Diagram (22)9.2Write Cycle Timing Diagram (22)9.3Program Cycle Timing Diagram (23)9.4#DATA Polling Timing Diagram (23)9.5Toggle Bit Timing Diagram (24)9.6Sector Erase Timing Diagram (24)10.FWH INTERFACE MODE AC CHARACTERISTICS (25)10.1AC Test Conditions (25)10.2Read/Write Cycle Timing Parameters (25)10.3Reset Timing Parameters (25)11.TIMING WAVEFORMS FOR FWH INTERFACE MODE (26)11.1Read Cycle Timing Diagram (26)11.2Write Cycle Timing Diagram (26)11.3Program Cycle Timing Diagram (27)11.4#DATA Polling Timing Diagram (28)11.5Toggle Bit Timing Diagram (29)11.6Sector Erase Timing Diagram (30)11.7FGPI Register/Product ID Readout Timing Diagram (31)11.8Reset Timing Diagram (31)12.ORDERING INFORMATION (32)13.HOW TO READ THE TOP MARKING (32)14.PACKAGE DIMENSIONS (33)14.132L PLCC (33)14.232L STSOP (8X14mm) (33)14.340L TSOP (10 mm x 20 mm) (34)15.VERSION HISTORY (35)W39V080FAPublication Release Date: Dec. 13, 20051. GENERAL DESCRIPTIONThe W39V080FA is an 8-megabit, 3.3-volt only CMOS flash memory organized as 1M × 8 bits. For flexible erase capability, the 8Mbits of data are divided into 16 uniform sectors of 64 Kbytes. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is required for accelerated program. The unique cell architecture of the W39V080FA results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and FWH bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the FWH interface mode, this device complies with the Intel FWH specification. The device can also be programmed and erased using standard EPROM programmers.2. FEATURES•Single 3.3-volt operations: − 3.3-volt Read − 3.3-volt Erase − 3.3-volt Program• Fast program operation: − VPP = 12V− Byte-by-Byte programming: 9 μS (typ.) • Fast erase operation:− Sector erase 0.9 Sec. (typ.) • Fast read access time: Tkq 11 nS • Endurance: 30K cycles (typ.) • Twenty-year data retention • 16 Even sectors with 64K bytes • Any individual sector can be erased • Dual BIOS function− Full-chip partition with 8M-bit or dual-block partition with 4M-bit •Hardware protection:− #TBL supports 64-Kbyte Boot Block hardware protection− #WP supports the whole chip except Boot Block hardware protection• Hardware Features•Ready/#Busy output (RY/#BY)− Detect program or erase cycle completion • Hardware reset pin (#RESET)− Reset the internal state machine to the readmode• VPP input pin− Acceleration (ACC) function acceleratesprogram timing• Low power consumption− Read Active current: 15 mA (typ. for FWH mode)• Automatic program and erase timing with internal V PP generation• End of program or erase detection − Toggle bit − Data polling• Latched address and data • TTL compatible I/O• Available packages: 32L PLCC, 32L STSOP,40L TSOP(10 x 20 mm), 32L PLCC Lead free, 32L STSOP Lead free and 40L TSOP (10 x 20 mm) Lead freeW39V080FA3. PIN CONFIGURATIONS4. BLOCK DIAGRAM5. PIN DESCRIPTIONINTERFACE SYM.PGM FWH PIN NAMEIC**Interface Mode Selection#RESET * * Reset#INIT * Initialize#TBL * Top Boot Block Lock #WP * Write Protect CLK * CLK InputFGPI[4:0]*General Purpose InputsID[3:0] *Identification Inputs Pull Down with Internal Resistors FWH[3:0] * Address/Data InputsFWH4 * FWH Cycle InitialD/#F *Dual Bios/Full ChipPull Down with Internal Resistors U/#L *Upper 4M/Lower 4MPull Down with Internal Resistors R/#C * Row/Column Select A[10:0] * Address Inputs DQ[7:0]* Data Inputs/Outputs#OE * Output Enable #WE * Write Enable RY/#BY* Ready/ BusyVDD * * Power Supply VSS * * Ground VPP * * Accelerate Program Power Supply RSV * * Reserved PinsNC**No ConnectionW39V080FA6. FUNCTIONAL DESCRIPTION6.1 Interface Mode Selection and DescriptionThis device can operate in two interface modes, one is Programmer interface mode, and the other is FWH interface mode. The IC pin of the device provides the control between these two interface modes. These interface modes need to be configured before power up or return from #RESET. When IC pin is set to high state, the device will be in the Programmer mode; while the IC pin is set to low state (or leaved no connection), it will be in the FWH mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed. The row address are mapped to the higher internal address A[19:11]. And the column address are mapped to the lower internal address A[10:0]. For FWH mode, It complies with the FWH Interface Specification. Through the FWH[3:0] and FWH4 to communicate with the system chipset .6.2 Read (Write) ModeIn Programmer interface mode, the read (write) operation of the W39V080FA is controlled by #OE (#WE). The #OE (#WE) is held low for the host to obtain (write) data from (to) the outputs (inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As for in the FWH interface mode, the read or write is determined by the "bit 0 & bit 1 of START CYCLE ". Refer to the FWH cycle definition and timing waveforms for further details.6.3 Reset OperationThe #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals.6.4 Accelerated Program OperationThe device provides accelerated program operations through the ACC function. This function is primarily intended to allow a faster manufacturing throughput in the factory.6.5 Boot Block Operation and Hardware Protection at Initial- #TBL & #WPThere is a hardware method to protect the top boot block and other sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not be programmed/erased.In order to detect whether the boot block feature is set on or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address FFFF2(hex). You can check the DQ2/DQ3 at the address FFFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is “0”, it means the #TBL pin is tied to high state. In such condition, whether boot block can be programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is “1”, it means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is “0”, it means the #WP pin is in high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if the DQ3 is “1”, then all the sectors except the boot block are programmed/erased inhibited.To return to normal operation, perform a three-byte command sequence (or an alternate single-byte command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.Publication Release Date: Dec. 13, 2005W39V080FA6.6 Sector Erase CommandSector erase is a six bus cycles operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the Sector erase command. The Sector address (any address location within the desired Sector) is latched on the rising edge of R/#C in programmer mode, while the command (30H) is latched on the rising edge of #WE.Sector erase does not require the user to program the device prior to erase. When erasing a Sector, the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations.The automatic Sector erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last Sector erase command pulse and terminates when the data on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the sectors being erased.Refer to the Erase Command flow Chart using typical command strings and bus operations.6.7 Program OperationThe W39V080FA is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming.The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byte-program command is entered. The internal program timer will automatically time-out (9μS typ.-T BP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle.6.8 Dual BIOSThe W39V080FA provides a solution for Dual-BIOS application. In FWH mode, when D/#F is low, the device functions as a full-chip partition of 8M-bit which address ranges from FFFFFh to 00000h with A[19:0]. If D/#F is driven high, the device functions as a dual-block partition that each block consists of 4M-bit. For dual-block partition, there is only one 4M-bit block, either upper or lower, can be accessed. The U/#L pin selects either upper or lower 4M-bit block and its address ranges from 7FFFFh to 00000h with A[19:0]. When U/#L is low, the lower 4M-bit block will be selected; while, U/#L is high, the upper 4M-bit block will be selected.6.9 Hardware Data ProtectionThe integrity of the data stored in the W39V080FA is also hardware protected in the following ways:(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.(2) V DD Power Up/Down Detection: The programming and read operation are inhibited when V DD isless than 2.0V typical.(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This preventsinadvertent writes during power-up or power-down periods.W39V080FA6.10 Write Operation StatusThe device provides several bits to determine the status of a program or erase operation: DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY in programmer mode, to determine whether an Embedded Program or Erase operation is in progress or has been completed.6.10.1 DQ7: #Data PollingThe #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress or completed. Data Polling is valid after the rising edge of the final #WE pulse in the command sequence.During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data programmed to DQ7. Once the Embedded Program algorithm has completed, the device outputs the data programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is active for about 1μS, and then the device returns to the read mode.During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded Erase algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the sectors selected for erasure must be provided to read valid status information on DQ7.After an erase command sequence is written, if all sectors selected for erasing are protected, #Data Polling on DQ7 is active for about 100μS, and then the device returns to the read mode. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid.Just before the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may change from providing status information to valid data on DQ7. Depending on when it samples the DQ7 output, the system may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ7-DQ0 will appear on successive read cycles.6.10.2 RY/#BY: Ready/#BusyThe RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in parallel with a pull-up resistor to V DD.When the output is low (Busy), the device is actively erasing or programming. When the output is high (Ready), the device is in the read mode or standby mode.6.10.3 DQ6: Toggle BitToggle Bit on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete. Toggle Bit I may be read at any address, and is valid after the rising edge of the final #WE pulse in the command sequence (before the program or erase operation), and during the sector erase time-out.During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either #OE to control the read cycles. Once the operation has completed, DQ6 stops toggling.Publication Release Date: Dec. 13, 2005W39V080FAAfter an erase command sequence is written, if all sectors selected for erasing are protected, DQ6toggles for about 100μS, and then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selectedsectors which are protected.The system can use DQ6 to determine whether a sector is actively erasing. If the device is activelyerasing (i.e., the Embedded Erase algorithm is in progress), DQ6 toggles. If a program address fallswithin a protected sector, DQ6 toggles for about 1 μs after the program command sequence is written,and then returns to reading array data.6.10.4 DQ5: Exceeded Timing LimitsDQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit.DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not successfully completed.The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, thedevice stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.”Under both these conditions, the system must hardware reset to return to the read mode.6.11 Identification Input pin ID[3:0]These pins are part of mechanism that allows multiple parts to be used on the same bus. The bootdevice should be 0000b. And all the subsequent parts should use the up-count strapping.6.12 RegisterThere are three kinds of registers on this device, the General Purpose Input Registers, the Block LockControl Registers and Product Identification Registers. Users can access these registers through respective address in the 4Gbytes memory map. There are detail descriptions in the sections below.6.12.1 General Purpose Inputs RegisterThis register reads the FGPI[4:0] pins on the W39V080FA.This is a pass-through register which canread via memory address FFBC0100(hex). Since it is pass-through register, there is no default value.GPI Register TableBIT FUNCTION7 − 5 Reserved4 Read FGPI4 pin status3 Read FGPI3 pin status2 Read FGPI2 pin status1 Read FGPI1 pin status0 Read FGPI0 pin status6.12.2 Block Locking RegistersThis part provides 16 even 64Kbytes blocks, and each block can be locked by register control. Thesecontrol registers can be set or clear through memory address. Below is the detail description.W39V080FAPublication Release Date: Dec. 13, 2005Block Locking Registers type and access memory map TableREGISTERSREGISTERSTYPECONTROL BLOCKDEVICE PHYSICALADDRESS4GBYTES SYSTEM MEMORY ADDRESSBLR15 R/W 15 0FFFFFh – 0F0000h FFBF0002h BLR14 R/W 14 0EFFFFh – 0E0000h FFBE0002h BLR13 R/W 13 0DFFFFh – 0D0000h FFBD0002h BLR12 R/W 12 0CFFFFh – 0C0000h FFBC0002h BLR11 R/W 11 0BFFFFh – 0B0000h FFBB0002h BLR10 R/W 10 0AFFFFh – 0A0000h FFBA0002h BLR9 R/W 9 09FFFFh – 090000h FFB90002h BLR8 R/W 8 08FFFFh – 080000h FFB80002h BLR7 R/W 7 07FFFFh – 070000h FFB70002h BLR6 R/W 6 06FFFFh – 060000h FFB60002h BLR5 R/W 5 05FFFFh – 050000h FFB50002h BLR4 R/W 4 04FFFFh – 040000h FFB40002h BLR3 R/W 3 03FFFFh – 030000h FFB30002h BLR2 R/W 2 02FFFFh – 020000h FFB20002h BLR1 R/W 1 01FFFFh – 010000h FFB10002h BLR0R/W00FFFFh – 000000hFFB00002hBlock Locking Register Bits Function TableBIT FUNCTION7 – 3 Reserved2 Read Lock1: Prohibit to read in the block where set0: Normal read operation in the block where clear. This is default state.1 Lock Down1: Prohibit further to set or clear the Read Lock or Write Lock bits. This Lock Down Bit can only be set not clear. Only the device is reset or re-powered, the Lock Down Bit is cleared.0: Normal operation for Read Lock or Write Lock. This is the default state. 0 Write Lock1: Prohibited to write in the block where set. This is default state. 0: Normal programming/erase operation in the block where clear.W39V080FARegister Based Block Locking Value Definitions TableBIT [7:3] BIT 2 BIT 1 BIT 0 RESULTAccess.Full00000 0 0 000000 0 0 1 Write Lock. Default State.00000 0 1 0 Locked Open (Full Access, Lock Down).00000 0 1 1 Write Locked, Locked Down.Locked.Read00000 1 0 000000 1 0 1 Read & Write Locked.00000 1 1 0 Read Locked, Locked Down.00000 1 1 1 Read & Write Locked, Locked Down.Read LockAny attempt to read the data of read locked block will result in “00H.” The default state of any block is unlocked upon power up. User can clear or set the write lock bit anytime as long as the lock down bit is not set.Write LockThis is the default state of blocks upon power up. Before any program or erase to the specified block, user should clear the write lock bit first. User can clear or set the write lock bit anytime as long as the lock down bit is not set. The write lock function is in conjunction with the hardware protect pins, #WP & TBL. When hardware protect pins are enabled, it will override the register block locking functions and write lock the blocks no matter how the status of the register bits. Reading the register bit will not reflect the status of the #WP or #TBL pins.Lock DownThe default state of lock down bit for any block is unlocked. This bit can be set only once; any further attempt to set or clear is ignored. Only the reset from #RESET or #INIT can clear the lock down bit. Once the lock down bit is set for a block, then the write lock bit & read lock bit of that block will not be set or cleared, and keep its current state.6.12.3 Product Identification RegistersThere is an alternative software method to read out the Product Identification in both the Programmer interface mode and the FWH interface mode. Thus, the programming equipment can automatically matches the device with its proper erase and programming algorithms.In the full-chip(8Mb) FWH interface mode, a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FFBC, 0001(hex) can output the device code, D3(hex).For Dual-BIOS(4Mbx2) FWH mode , a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FFBC,0001(hex) can output the device code 93(hex).In the software access mode, a JEDEC 3-byte command sequence can be used to access the product ID for programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs the device code, D3(hex).” The product ID operation can be terminated by a three-byte command sequence or an alternate one-byte command sequence (see Command Definition table for detail).W39V080FAPublication Release Date: Dec. 13, 20056.13 Table of Operating Modes6.13.1 Operating Mode Selection - Programmer ModeMODE PINS#OE#WE#RESETADDRESSDQ.Read V IL V IH V IH AIN Dout Write V IH V ILV IHAIN DinStandby X X V IL X High ZWrite Inhibit V IL X V IH X High Z/DOUT X V IH V IH X High Z/DOUTOutput DisableV IH X V IH X High Z6.13.2 Operating Mode Selection - FWH ModeOperation modes in FWH interface mode are determined by "START Cycle" when it is selected. When it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle Definition".Table of Command DefinitionCOMMAND NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE DESCRIPTION Cycles (1)Addr. Data Addr. DataAddr. DataAddr. DataAddr. DataAddr. DataRead 1 A IN D OUTSector Erase 6 5555 AA 2AAA 555555 805555 AA 2AAA 55SA (5)30Byte Program 4 5555 AA 2AAA 555555 A0A IN D INProduct ID Entry 3 5555 AA 2AAA 555555 90 Product ID Exit (4)35555 AA2AAA 555555 F0Product ID Exit (4) 1 XXXX F0 Notes: 1. The cycle means the write command cycle not the FWH clock cycle. 2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[19:11] 3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex) 4. Either one of the two Product ID Exit commands can be used. 5. SA: Sector AddressSA = FXXXXh for Unique Sector15 (Boot Sector) SA = 7XXXXh for Unique Sector7 SA = EXXXXh for Unique Sector14 SA = 6XXXXh for Unique Sector6 SA = DXXXXh for Unique Sector13 SA = 5XXXXh for Unique Sector5 SA = CXXXXh for Unique Sector12 SA = 4XXXXh for Unique Sector4 SA = BXXXXh for Unique Sector11 SA = 3XXXXh for Unique Sector3 SA = AXXXXh for Unique Sector10 SA = 2XXXXh for Unique Sector2 SA = 9XXXXh for Unique Sector9 SA = 1XXXXh for Unique Sector1 SA = 8XXXXh for Unique Sector8SA = 0XXXXh for Unique Sector0W39V080FA6.14 Fwh Cycle DefinitionFIELDNO. OF CLOCKSDESCRIPTIONSTART 1"1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWHMemory Write cycle. 0000b" appears on FWH bus to indicate the initial IDSEL 1 This one clock field indicates which FWH component is being selected. MSIZE 1 Memory Size. There is always show “0000b” for single byte access. TAR2Turned Around TimeADDR 7Address Phase for Memory Cycle. FWH supports the 28 bits address protocol. The addresses transfer most significant nibble first and leastsignificant nibble last. (i.e. Address[27:24] on FWH[3:0] first, and Address[3:0] on FWH[3:0] last.) SYNC N Synchronous to add wait state. "0000b" means Ready, "0101b" means ShortWait, "0110b" means Long Wait, "1001b" for DMA only, "1010b" meanserror, and other values are reserved. DATA 2 Data Phase for Memory Cycle. The data transfer least significant nibble firstand most significant nibble last. (i.e. DQ[3:0] on FWH[3:0] first, then DQ[7:4]on FWH[3:0] last.)W39V080FA 6.15 Embedded Programming AlgorithmPublication Release Date: Dec. 13, 2005W39V080FA 6.16 Embedded Erase AlgorithmW39V080FA 6.17 Embedded #Data Polling AlgorithmPublication Release Date: Dec. 13, 2005W39V080FA 6.18 Embedded Toggle Bit AlgorithmW39V080FAPublication Release Date: Dec. 13, 20056.19 Software Product Identification and Boot Block Lockout Detection AcquisitionFlowNotes for software product identification/boot block lockout detection:(1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex)(2) A1−A19 = V IL ; manufacture code is read for A0 = V IL ; device code is read for A0 = V IH .(3) The device does not remain in identification and boot block lockout detection mode if power down. (4) The DQ[3:2] to indicate the sectors protect status as below:DQ2 DQ30 64Kbytes Boot Block Unlocked by #TBL hardware trappingWhole Chip Unlocked by #WP hardware trapping Except Boot Block164Kbytes Boot Block Locked by #TBL hardware trappingWhole Chip Locked by #WP hardware trapping Except Boot Block(5) The device returns to standard operation mode.(6) Optional 1-write cycle (write F0 (hex.) at XXXX address) can be used to exit the product identification/boot block lockoutdetection.W39V080FA7. DC CHARACTERISTICS7.1 Absolute Maximum RatingsPARAMETER RATINGUNIT Power Supply Voltage to V SS Potential -0.5 to +4.0 VOperating Temperature 0 to +70 °CStorage Temperature -65 to +150 °CD.C. Voltage on Any Pin to Ground Potential -0.5 to V DD +0.5 VV PP Voltage -0.5 to +13 VTransient Voltage (<20 nS) on Any Pin to Ground Potential -1.0 to V DD +0.5 VNote: Exposure to conditions beyond those listed under Absolute Maximum Ratings May adversely affect the life and reliabilityof the device.7.2 Programmer interface Mode DC Operating Characteristics(V DD = 3.3V ± 0.3V, V SS= 0V, T A = 0 to 70° C)LIMITSPARAMETER SYM. TESTCONDITIONSMIN.TYP. MAX.UNITPower Supply Current (read)I CC1In Read or Write mode, all DQs openAddress inputs = 3.0V/0V, at f = 3 MHz- 15 20 mAPower Supply Current (erase/ write)I CC2In Read or Write mode, all DQs openAddress inputs = 3.0V/0V, at f = 3 MHz- 35 45mAInput Leakage Current I LI V IN = V SS to V DD --90μAOutput Leakage Current I LO V OUT = V SS to V DD --90μAInput Low Voltage V IL - -0.5-0.8V Input High Voltage V IH - 2.0-V DD +0.5VOutput Low Voltage V OL I OL = 2.1 mA - - 0.45 VOutput High Voltage V OH I OH = -0.1mA 2.4- - V。

W39V080APZ资料

W39V080A Data Sheet1M × 8 CMOS FLASH MEMORYWITH LPC INTERFACE Table of Contents-1.GENERAL DESCRIPTION (3)2.FEATURES (3)3.PIN CONFIGURATIONS (4)4.BLOCK DIAGRAM (4)5.PIN DESCRIPTION (4)6.FUNCTIONAL DESCRIPTION (5)6.1Interface Mode Selection and Description (5)6.2Read (Write) Mode (5)6.3Reset Operation (5)6.4Boot Block Operation and Hardware Protection at Initial- #TBL & #WP (5)6.5Sector Erase Command (6)6.6Program Operation (6)6.7Dual BIOS (6)6.8Hardware Data Protection (6)6.9Write Operation Status (7)7.TABLE OF OPERATING MODES (10)7.1Operating Mode Selection - Programmer Mode (10)7.2Operating Mode Selection - LPC Mode (10)7.3Standard LPC Memory Cycle Definition (10)8.TABLE OF COMMAND DEFINITION (11)8.1Embedded Programming Algorithm (12)8.2Embedded Erase Algorithm (13)8.3Embedded #Data Polling Algorithm (14)8.4Embedded Toggle Bit Algorithm (15)8.5Software Product Identification and Boot Block Lockout Detection Acquisition Flow..169.DC CHARACTERISTICS (17)9.1Absolute Maximum Ratings (17)9.2Programmer interface Mode DC Operating Characteristics (17)9.3LPC interface Mode DC Operating Characteristics (18)9.4Power-up Timing (18)10.CAPACITANCE (18)11.PROGRAMMER INTERFACE MODE AC CHARACTERISTICS (19)Publication Release Date: Dec. 28, 2005W39V080A11.1AC Test Conditions (19)11.2AC Test Load and Waveform (19)11.3Read Cycle Timing Parameters (20)11.4Write Cycle Timing Parameters (20)11.5Data Polling and Toggle Bit Timing Parameters (20)12.TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE (21)12.1Read Cycle Timing Diagram (21)12.2Write Cycle Timing Diagram (21)12.3Program Cycle Timing Diagram (22)12.4#DATA Polling Timing Diagram (22)12.5Toggle Bit Timing Diagram (23)12.6Sector Erase Timing Diagram (23)13.LPC INTERFACE MODE AC CHARACTERISTICS (24)13.1AC Test Conditions (24)13.2Read/Write Cycle Timing Parameters (24)13.3Reset Timing Parameters (24)14.TIMING WAVEFORMS FOR LPC INTERFACE MODE (25)14.1Read Cycle Timing Diagram (25)14.2Write Cycle Timing Diagram (25)14.3Program Cycle Timing Diagram (26)14.4#DATA Polling Timing Diagram (27)14.5Toggle Bit Timing Diagram (28)14.6Sector Erase Timing Diagram (29)14.7GPI Register/Product ID Readout Timing Diagram (30)14.8Reset Timing Diagram (30)15.ORDERING INFORMATION (31)16.HOW TO READ THE TOP MARKING (31)17.PACKAGE DIMENSIONS (32)17.132L PLCC (32)17.232L STSOP (8x14mm) (32)17.340L TSOP (10 mm x 20 mm) (33)18.VERSION HISTORY (34)W39V080APublication Release Date: Dec. 28, 20051. GENERAL DESCRIPTIONThe W39V080A is an 8-megabit, 3.3-volt only CMOS flash memory organized as 1M × 8 bits. For flexible erase capability, the 8Mbits of data are divided into 16 uniform sectors of 64 Kbytes. The device can be programmed and erased in-system with a standard 3.3V power supply. A 12-volt VPP is required for accelerated program. The unique cell architecture of the W39V080A results in fast program/erase operations with extremely low current consumption. This device can operate at two modes, Programmer bus interface mode and LPC bus interface mode. As in the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the LPC interface mode, this device complies with the Intel LPC specification. The device can also be programmed and erased using standard EPROM programmers.2. FEATURESy Single 3.3-volt operations: − 3.3-volt Read − 3.3-volt Erase − 3.3-volt Programy Fast Program operation:− VPP = 12V− Byte-by-Byte programming: 9 μS (typ.)y Fast Erase operation:− Sector erase 0.9 Sec. (tpy.) y Fast Read access time: Tkq 11 nS y Endurance: 30K cycles (typ.) y Twenty-year data retention y 16 Even sectors with 64K bytes y Any individual sector can be erased y Dual BIOS function− Full-chip Partition with 8M-bit or Dual-block Partition with 4M-bit y Hardware protection:− #TBL supports 64-Kbyte Boot Blockhardware protection− #WP supports the whole chip except Boot Block hardware protectiony Ready/#Busy output (RY/#BY)− Detect program or erase cycle completion y Hardware reset pin (#RESET)− Reset the internal state machine to the read mode y VPP input pin− Acceleration (ACC) function accelerates program timingy Low power consumption− Read Active current: 15 mA (typ. for LPC mode)y Automatic program and erase timing withinternal V PP generation y End of program or erase detection − Toggle bit − Data pollingy Latched address and data y TTL compatible I/Oy Available packages: 32L PLCC, 32L STSOP,40L TSOP(10 x 20 mm), 32L PLCC Lead free, 32L STSOP Lead free and 40L TSOP (10 x 20 mm) Lead freeW39V080A3. PIN CONFIGURATIONS4. BLOCK DIAGRAM5. PIN DESCRIPTIONINTERFACESYM.PGM LPCPIN NAMEMODE * *Interface Mode Selection #RESET * *Reset #INIT *Initialize#TBL *Top Boot Block Lock #WP *Write Protect CLK *CLK InputGPI[4:0] *General Purpose Inputs ID[3:0] *Identification InputsPull Down with Internal ResistorsLAD[3:0] *Address/Data Inputs #LFRAME *LPC Cycle InitialD/#F *Dual Bios/Full ChipPull Down with Internal Resistors U/#L *Upper 4M/Lower 4MPull Down with Internal ResistorsR/#C * Row/Column Select A[10:0]* Address Inputs DQ[7:0]* Data Inputs/Outputs #OE * Output Enable #WE * Write Enable RY/#BY * Ready/Busy VDD * *Power Supply VSS * *Ground RSV * *Reserve Pins NC * *No ConnectionW39V080A6. FUNCTIONAL DESCRIPTION6.1 Interface Mode Selection and DescriptionThis device can be operated in two interface modes, one is Programmer interface mode, and the other is LPC interface mode. The MODE pin of the device provides the control between these two interface modes. These interface modes need to be configured before power up or return from #RESET. When MODE pin is set to high position, the device is in the Programmer mode; while the MODE pin is set to low position, it is in the LPC mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed. The row address is mapped to the higher internal address A[19:11]. And the column address is mapped to the lower internal address A[10:0]. For LPC mode, It complies with the LPC Interface Specification Revision 1.1 Through the LAD[3:0] and #LFRAME to communicate with the system chipset .6.2 Read (Write) ModeIn Programmer interface mode, the read(write) operation of the W39V080A is controlled by #OE (#WE). The #OE (#WE) is held low for the host to obtain (write) data from(to) the outputs(inputs). #OE is the output control and is used to gate data from the output pins. The data bus is in high impedance state when #OE is high. As in the LPC interface the “bit 1 of CYCLE TYPE+DIR” determines mode, the read or write. Refer to the timing waveforms for further details.6.3 Reset OperationThe #RESET input pin can be used in some application. When #RESET pin is at high state, the device is in normal operation mode. When #RESET pin is at low state, it will halt the device and all outputs will be at high impedance state. As the high state re-asserted to the #RESET pin, the device will return to read or standby mode, it depends on the control signals.6.4 Boot Block Operation and Hardware Protection at Initial- #TBL & #WPThere is a hardware method to protect the top boot block and other sectors. Before power on programmer, tie the #TBL pin to low state and then the top boot block will not be programmed/erased. If #WP pin is tied to low state before power on, the other sectors will not be programmed/erased.In order to detect whether the boot block feature is set on or not, users can perform software command sequence: enter the product identification mode (see Command Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address FFFF2(hex). You can check the DQ2/DQ3 at the address FFFF2 to see whether the #TBL/#WP pin is in low or high state. If the DQ2 is “0”, it means the #TBL pin is tied to high state. In such condition, whether boot block can be programmed/erased or not will depend on software setting. On the other hand, if the DQ2 is “1”, it means the #TBL pin is tied to low state, then boot block is locked no matter how the software is set. Like the DQ2, the DQ3 inversely mirrors the #WP state. If the DQ3 is “0”, it means the #WP pin is in high state, then all the sectors except the boot block can be programmed/erased. On the other hand, if the DQ3 is “1”, then all the sectors except the boot block are programmed/erased inhibited.To return to normal operation, perform a three-byte command sequence (or an alternate single-byte command) to exit the identification mode. For the specific code, see Command Codes for Identification/Boot Block Lockout Detection.Publication Release Date: Dec. 28, 2005W39V080A6.5 Sector Erase CommandSector erase is a six-bus cycles operation. There are two "unlock" write cycles, followed by writing the "set-up" command. Two more "unlock" write cycles then follows by the Sector erase command. The Sector address (any address location within the desired Sector) is latched on the rising edge of R/#C in programmer mode, while the command (30H) is latched on the rising edge of #WE.Sector erase does not require the user to program the device prior to erase. When erasing a Sector, the remaining unselected sectors are not affected. The system is not required to provide any controls or timings during these operations.The automatic Sector erase begins after the erase command is completed, right from the rising edge of the #WE pulse for the last Sector erase command pulse and terminates when the data on DQ7, Data Polling, is "1" at which time the device returns to the read mode. Data Polling must be performed at an address within any of the sectors being erased.Refer to the Erase Command flow Chart using typical command strings and bus operations.6.6 Program OperationThe W39V080A is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is needed before programming.The program operation is initiated by a 4-byte command cycle (see Command Codes for Byte Programming). The device will internally enter the program operation immediately after the byte-program command is entered. The internal program timer will automatically time-out (9μS typ. - T BP) once it is completed and then return to normal read mode. Data polling and/or Toggle Bits can be used to detect end of program cycle.6.7 Dual BIOSThe W39V080A provides a solution for Dual-BIOS application. In LPC mode, when D/#F is low, the device functions as a full-chip partition of 8M-bit which address ranges from FFFFFh to 00000h with A[19:0]. If D/#F is driven high, the device functions as a dual-block partition that each block consists of 4M-bit. For dual-block partition, there is only one 4M-bit block, either upper or lower, can be accessed. The U/#L pin selects either upper or lower 4M-bit block and its address ranges from 7FFFFh to 00000h with A[19:0]. When U/#L is low, the lower 4M-bit block will be selected; while, U/#L is high, the upper 4M-bit block will be selected.6.8 Hardware Data ProtectionThe integrity of the data stored in the W39V080A is also hardware protected in the following ways:(1) Noise/Glitch Protection: A #WE pulse of less than 15 nS in duration will not initiate a write cycle.(2) V DD Power Up/Down Detection: The programming and read operation are inhibited when V DD isless than 2.0V typical.(3) Write Inhibit Mode: Forcing #OE low or #WE high will inhibit the write operation. This preventsinadvertent writes during power-up or power-down periods.W39V080APublication Release Date: Dec. 28, 20056.9 Write Operation StatusThe device provides several bits to determine the status of a program or erase operation: DQ5, DQ6, and DQ7. Each of DQ7 and DQ6 provides a method for determining whether a program or erase operation is complete or in progress. The device also offers a hardware-based output signal, RY/#BY in programmer mode, to determine whether an Embedded Program or Erase operation is in progress or has been completed.DQ7: #Data PollingThe #Data Polling bit, DQ7, indicates whether an Embedded Program or Erase algorithm is in progress or completed. Data Polling is valid after the rising edge of the final #WE pulse in the command sequence.During the Embedded Program algorithm, the device outputs on DQ7 and the complement of the data programmed to DQ7. Once the Embedded Program algorithm has completed, the device outputs the data programmed to DQ7. The system must provide the program address to read valid status information on DQ7. If a program address falls within a protected sector, #Data Polling on DQ7 is active for about 1 S, and then the device returns to the read mode.　During the Embedded Erase algorithm, #Data Polling produces “0” on DQ7. Once the Embedded Erase algorithm has completed, #Data Polling produces “1” on DQ7. An address within any of the sectors selected for erasure must be provided to read valid status information on DQ7.After an erase command sequence is written, if all sectors selected for erasing are protected, #Data Polling on DQ7 is active for about 100S, and then the device returns to the read mode. I f not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors that are protected. However, if the system reads DQ7 at an address within a protected sector, the status may not be valid.Just before the completion of an Embedded Program or Erase operation, DQ7 may change asynchronously with DQ0-DQ6 while Output Enable (#OE) is set to low. That is, the device may change from providing status information to valid data on DQ7. Depending on when it samples the DQ7 output, the system may read the status or valid data. Even if the device has completed the program or erase operation and DQ7 has valid data, the data outputs on DQ0-DQ6 may be still invalid. Valid data on DQ7-DQ0 will appear on successive read cycles.RY/#BY: Ready/#BusyThe RY/#BY is a dedicated, open-drain output pin which indicates whether an Embedded Algorithm is in progress or complete. The RY/#BY status is valid after the rising edge of the final #WE pulse in the command sequence. Since RY/#BY is an open-drain output, several RY/#BY pins can be tied together in parallel with a pull-up resistor to VDD.When the output is low (Busy), the device is actively erasing or programming. When the output is high (Ready), the device is in the read mode or standby mode.DQ6: Toggle Bit IToggle Bit I on DQ6 indicates whether an Embedded Program or Erase algorithm is in progress or complete. Toggle Bit I may be read at any address, and is valid after the rising edge of the final #WE pulse in the command sequence (before the program or erase operation), and during the sector erase time-out.During an Embedded Program or Erase algorithm operation, successive read cycles to any address cause DQ6 to toggle. The system may use either #OE to control the read cycles. Once the operation has completed, DQ6 stops toggling.W39V080A After an erase command sequence is written, if all sectors selected for erasing are protected, DQ6 toggles for about 100 S, and then returns to reading array data. If not all selected sectors are protected, the Embedded Erase algorithm erases the unprotected sectors, and ignores the selected sectors which are protected.The system can use DQ6 to determine whether a sector is actively erasing. If the device is actively erasing (i.e., the Embedded Erase algorithm is in progress), DQ6 toggles. If a program address falls within a protected sector, DQ6 toggles for about 1 μS after the program command sequence is written, and then returns to reading array data.Reading Toggle Bits DQ6Whenever the system initially starts to read toggle bit status, it must read DQ7-DQ0 at least twice in a row to determine whether a toggle bit is toggling or not. Typically, the system would note and store the value of the toggle bit after the first read. While after the second read, the system would compare the new value of the toggle bit with the first one. If the toggle bit is not toggling, the device has completed the program or erase operation. The system can read array data on DQ7-DQ0 on the following read cycle.However, if after the initial two read cycles, the system finds that the toggle bit is still toggling, the system also should note whether the value of DQ5 is high or not(see the section on DQ5). If DQ5 is high, the system should then determine again whether the toggle bit is toggling or not, since the toggle bit may have stopped toggling just as DQ5 went high. If the toggle bit is no longer toggling, the device has successfully completed the program or erase operation. If it is still toggling, the device did not completed the operation, and the system must write the reset command to return to reading array data.Then the system initially determines that the toggle bit is toggling and DQ5 has not gone high. The system may continue to monitor the toggle bit and DQ5 through successive read cycles, and determines the status as described in the previous paragraph. Alternatively, the system may choose to perform other system tasks. In this case, the system must start at the beginning of the algorithm while it returns to determine the status of the operation.DQ5: Exceeded Timing LimitsDQ5 indicates whether the program or erase time has exceeded a specified internal pulse count limit. DQ5 produces “1” under these conditions which indicates that the program or erase cycle was not successfully completed.The device may output “1” on DQ5 if the system tries to program “1” to a location that was previously programmed to “0.” Only the erase operation can change “0” back to “1.” Under this condition, the device stops the operation, and while the timing limit has been exceeded, DQ5 produces “1.”Under both these conditions, the system must hardware reset to return to the read mode. REGISTERThere are two kinds of registers on this device, the General Purpose Input Registers and Product Identification Registers. Users can access these registers through respective address in the 4Gbytes memory map. There are detail descriptions in the sections below.General Purpose Inputs RegisterThis register reads the GPI[4:0] pins on the W39V080A.This is a pass-through register which can read via memory address FFBC0100(hex), or FFBxE100(hex). Since it is pass-through register, there is no default value.W39V080APublication Release Date: Dec. 28, 2005GPI Register TableBIT FUNCTION7 − 5 Reserved4 Read GPI4 pin status 3 Read GPI3 pin status 2 Read GPI2 pin status 1 Read GPI1 pin status 0Read GPI0 pin statusProduct Identification RegistersThere is a software method to read out the Product Identification in both the Programmer interface mode and the LPC interface mode. Thus, the programming equipment can automatically matches the device with its proper erase and programming algorithms.In the full-chip(8Mb) LPC interface mode, a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FFBC, 0001(hex) can output the device code D0(hex).For dual-BIOS(4Mbx2) LPC mode , a read from FFBC, 0000(hex) can output the manufacturer code, DA(hex). A read from FFBC,0001(hex) can output the device code 90(hex).In the software access mode, a JEDEC 3-byte command sequence can be used to access the product ID for programmer interface mode. A read from address 0000(hex) outputs the manufacturer code, DA(hex). A read from address 0001(hex) outputs sequence or an alternate one-byte command sequence (see Command Definition table for detail).the device code, D0(hex).” The product ID operation can be terminated by a three-byte command.Identification Input Pins ID[3:0]These pins are part of mechanism that allows multiple parts to be used on the same bus. The boot device should be 0000b. And all the subsequent parts should use the up-count strapping. Memory Address MapThere are 8M bytes space reserved for BIOS Addressing. The 8M bytes are mapped into a single 4M system address by dividing the ROMs into two 4M byte pages. For accessing the 4M byte BIOS storage space, the ID[2:1] pins are inverted in the ROM and are compared to address lines [21:20]. ID[3] can be used as like active low chip-select pin. The 32Mbit address space is as below:BLOCK LOCK ADDRESS RANGE4M Byte BIOS ROM None FFFF, FFFFh: FFC0, 0000hThe ROM responds to top 1M byte pages based on the ID pins strapping according to the followingtable:ID[2:1] PINSROM BASED ADDRESS RANGE00x FFFF, FFFFh: FFF0, 0000h 01x FFEF, FFFFh: FEF0, 0000h 10x FFDF, FFFFh: FFD0, 0000h 11xFFCF, FFFFh: FFC0, 0000hW39V080A7. TABLE OF OPERATING MODES7.1 Operating Mode Selection - Programmer ModeMODE PINS#OE#WE#RESETADDRESSDQ.Read V IL V IH V IH AIN Dout Write V IH V ILV IHAIN DinStandby X X V IL XHigh ZWrite Inhibit V IL X V IH X High Z/DOUT X V IH V IH X High Z/DOUTOutput DisableV IH X V IH XHigh Z7.2 Operating Mode Selection - LPC ModeOperation modes in LPC interface mode are determined by "cycle type" when it is selected. When itis not selected, its outputs (LAD[3:0]) will be disable. Please reference to the "Standard LPC Memory Cycle Definition".7.3 Standard LPC Memory Cycle DefinitionFIELDNO. OF CLOCKSDESCRIPTIONStart 1 "0000b" appears on LPC bus to indicate the initialCycle Type & Dir 1 "010Xb" indicates memory read cycle; while "011xb" indicates memory write cycle. "X" mean don't have to care. TAR2Turned Around TimeAddr. 8Address Phase for Memory Cycle. LPC supports the 32 bits address protocol. The addresses transfer most significant nibble first and leastsignificant nibble last. (i.e. Address[31:28] on LAD[3:0] first , and Address[3:0] on LAD[3:0] last.) Sync. N Synchronous to add wait state. "0000b" means Ready, "0101b" meansShort Wait, "0110b" means Long Wait, "1001b" for DMA only, "1010b"means error, other values are reserved. Data 2 Data Phase for Memory Cycle. The data transfer least significant nibblefirst and most significant nibble last. (i.e. DQ[3:0] on LAD[3:0] first ,then DQ[7:4] on LAD[3:0] last.)W39V080APublication Release Date: Dec. 28, 20058. TABLE OF COMMAND DEFINITIONCOMMAND NO. OF 1ST CYCLE 2ND CYCLE 3RD CYCLE 4TH CYCLE 5TH CYCLE 6TH CYCLE DESCRIPTION Cycles (1) Addr. Data Addr. DataAddr. DataAddr. DataAddr. DataAddr. DataRead 1 A IN D OUT Sector Erase 6 5555 AA 2AAA 555555 80 5555 AA 2AAA 55SA (5) 30Byte Program 4 5555 AA 2AAA 555555 A0 A IN D INProduct ID Entry 3 5555 AA 2AAA 555555 90 Product ID Exit (4) 3 5555 AA 2AAA 555555 F0Product ID Exit (4)1XXXX F0Notes: 1. The cycle means the write command cycle not the LPC clock cycle. 2. The Column Address / Row Address are mapped to the Low / High order Internal Address. i.e. Column Address A[10:0] are mapped to the internal A[10:0], Row Address A[7:0] are mapped to the internal A[19:11] 3. Address Format: A14−A0 (Hex); Data Format: DQ7-DQ0 (Hex) 4. Either one of the two Product ID Exit commands can be used. 5. SA: Sector AddressSA = FXXXXh for Unique Sector15 (Boot Sector) SA = 7XXXXh for Unique Sector7 SA = EXXXXh for Unique Sector14 SA = 6XXXXh for Unique Sector6 SA = DXXXXh for Unique Sector13 SA = 5XXXXh for Unique Sector5 SA = CXXXXh for Unique Sector12 SA = 4XXXXh for Unique Sector4 SA = BXXXXh for Unique Sector11 SA = 3XXXXh for Unique Sector3 SA = AXXXXh for Unique Sector10 SA = 2XXXXh for Unique Sector2 SA = 9XXXXh for Unique Sector9 SA = 1XXXXh for Unique Sector1 SA = 8XXXXh for Unique Sector8SA = 0XXXXh for Unique Sector0W39V080A 8.1 Embedded Programming AlgorithmW39V080A 8.2 Embedded Erase AlgorithmPublication Release Date: Dec. 28, 2005W39V080A 8.3 Embedded #Data Polling AlgorithmW39V080A 8.4 Embedded Toggle Bit AlgorithmPublication Release Date: Dec. 28, 2005W39V080A 8.5 Software Product Identification and Boot Block Lockout DetectionAcquisition FlowNotes for software product identification/boot block lockout detection:(1) Data Format: DQ7−DQ0 (Hex); Address Format: A14−A0 (Hex)(2) A1−A19 = V IL; manufacture code is read for A0 = V IL; device code is read for A0 = V IH.(3) The device does not remain in identification and boot block lockout detection mode if power down.(4) The DQ[3:2] to indicate the sectors protect status as below:DQ2 DQ30 64Kbytes Boot Block Unlocked by #TBL hardwaretrapping Whole Chip Unlocked by #WP hardware trapping Except Boot Block1 64Kbytes Boot Block Locked by #TBL hardwaretrapping Whole Chip Locked by #WP hardware trapping Except Boot Block(5) The device returns to standard operation mode.(6) Optional 1-write cycle (write F0 (hex.) at XXXX address) can be used to exit the product identification/boot block lockoutdetection.W39V080APublication Release Date: Dec. 28, 20059. DC CHARACTERISTICS9.1 Absolute Maximum RatingsPARAMETER RATING UNITPower Supply Voltage to V SS Potential -0.5 to +4.0 V Operating Temperature 0 to +70 °C Storage Temperature-65 to +150 °C D.C. Voltage on Any Pin to Ground Potential -0.5 to V DD +0.5 V V PP Voltage-0.5 to +13 V Transient Voltage (<20 nS) on Any Pin to Ground Potential-1.0 to V DD +0.5VNote: Exposure to conditions beyond those listed under Absolute Maximum Ratings May adversely affect the life and reliabilityof the device.9.2 Programmer interface Mode DC Operating Characteristics(V DD = 3.3V ± 0.3V, V SS = 0V, T A = 0 to 70° C)LIMITSPARAMETER SYM. TEST CONDITIONSMIN.TYP. MAX.UNITPower Supply Current (read)ICC1 In Read or Write mode, all DQs openAddress inputs = 3.0V/0V, at f = 3MHz- 15 20 mAPower Supply Current (erase/ write)ICC2 In Read or Write mode, all DQs openAddress inputs = 3.0V/0V, at f = 3MHz - 35 45mA Input Leakage Current ILIVIN = VSS to VDD- - 90 μA Output Leakage CurrentILO VOUT = VSS to VDD - - 90 μA Input Low Voltage VIL - -0.5- 0.8 V Input High Voltage VIH-2.0 - VDD +0.5 V Output Low Voltage VOL IOL = 2.1 mA - - 0.45 V Output High VoltageVOH IOH = -0.1mA2.4--VW39V080A9.3 LPC interface Mode DC Operating Characteristics(V DD = 3.3V ± 0.3V, V SS= 0V, T A = 0 to 70° C)LIMITS PARAMETER SYM. TESTCONDITIONSMIN. TYP. MAX.UNITPower Supply Current (read) I CC1All I out = 0A, CLK = 33 MHz,in LPC mode operation.- 15 20mAPower Supply Current (erase/write) I CC2All I out = 0A, CLK = 33 MHz,in LPC mode operation.- 35 45 mAStandby Current 1 Isb1 #LFRAME = 0.9 V DD, CLK = 33MHz,all inputs = 0.9 V DD / 0.1 V DDno internal operation- 20 50uAStandby Current 2 Isb2 #LFRAME = 0.1 V DD, CLK = 33MHz,all inputs = 0.9 V DD /0.1 V DDno internal operation.- 3 10mAInput Low Voltage V IL - -0.5-0.3V DD VInput Low Voltage of #INIT V ILI - -0.5-0.2V DD VInput High Voltage V IH - 0.5V DD- V DD +0.5VInput High Voltage of #INIT Pin V IHI - 1.35V-V DD +0.5VOutput Low Voltage V OL I OL = 1.5 mA - - 0.1 V DD VOutput High Voltage V OH I OH = -0.5 mA 0.9 V DD- - V9.4 Power-up TimingPARAMETER SYMBOLTYPICALUNIT Power-up to Read Operation T PU. READ 100 μSPower-up to Write Operation T PU. WRITE 5 mS10. CAPACITANCE(V DD = 3.3V, T A = 25° C, f = 1 MHz)PARAMETER SYMBOLCONDITIONS MAX. UNITI/O Pin Capacitance C I/O V I/O = 0V 12 pfInput Capacitance C IN V IN = 0V 6 pf。

PS48600-3B-2900用户手册V1.3

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2.1 安全规定 ....................................................................................................................................................................... 7 2.2 安装准备 ....................................................................................................................................................................... 7 2.3 机械安装 ....................................................................................................................................................................... 8
注意
启动电池保护的优点为电池电压较低时可以保护电池；缺点为电池电压下降到一定水平即切断电池，使得所有负载，包括重要与非重要的负载断电。软件取消电池保护的优点为延长重要负载供电时间，缺点为无法保护电池。也不能避免误操作或设备故障导致的非预期的误下电。而硬件取消电池保护则可以避免设备故障与误操作造成的非预期误下电，以最大限度地保证重要负载供电的不中断。

KA393A中文资料

©2001 Fairchild Semiconductor CorporationRev. 1.0.2Features•Single Supply Operation: 2V to 36V •Dual Supply Operation: ± 1V to ±18V•Allow Comparison of V oltages Near Ground Potential •Low Current Drain 800µA Typ.•Compatible with all Forms of Logic •Low Input Bias Current 25nA Typ.•Low Input Offset Current ±5nA Typ.•Low Offset V oltage ±1mV Typ.DescritpionThe KA293 series consists of two independent voltagecomparators designed to operate from a single power supply over a wide voltage range.8-DIP8-SOP9-SIP111Internal Block DiagramKA293/KA293A, KA393/KA393A, KA2903Dual Differential ComparatorKA293/KA293A, KA393/KA393A, KA29032Schematic DiagramAbsolute Maximum RatingsThermal DataParameterSymbol Value Unit Power Supply Voltage V CC ±18 or 36V Differential Input Voltage VI(DIFF)36V Input VoltageV I - 0.3 to +36V Output Short Circuit to GND -Continuous -Power Dissipation, Ta = 25°C 8-DIP 8-SOPP D1040480mWOperating Temperature KA393/KA393A KA293/KA293A KA2903T OPR 0 ~ + 70- 25 ~ + 85- 40 ~ + 85°CStorage TemperatureT STG - 65 ~ + 150°CParameterSymbol Value Unit Thermal Resistance Junction-Ambient Max.8-DIP 8-SOPR θja120260°C/WKA293/KA293A, KA393/KA393A, KA29033Electrical Characteristics(V CC =5V, T A =25°C, unless otherwise specified)NOTE 1KA393 / KA393A : 0 ≤ T A ≤ +70°C KA293 / KA293A : -25 ≤ T A ≤ +85°C KA2903 : -40 ≤ T A ≤ +85°CParameterSymbol ConditionsKA293A/KA393A KA293/KA393Unit Min.Typ.Max.Min.Typ.Max.Input Offset Voltage V IO V O(P) =1.4V, R S =0Ω-±1±2-±1±5mV V CM = 0 to1.5V Note 1--±4.0--±9.0Input Offset Current I IO -±5±50-±5±50nA Note 1--±150--±150Input Bias CurrentI BIAS-65250-65250nANote 1--400--400Input Common Mode Voltage RangeV I(R)-V CC -1.50-V CC -1.5VNote 10-V CC -20-V CC -2Supply Current I CC R L = ∞ , V CC = 5V -0.61-0.61mA R L = ∞, V CC = 30V -0.8 2.5-0.8 2.5Voltage Gain G V V CC =15V, R L ≥15K Ω (for large V O(P-P)swing )50200-50200-V/mV Large Signal Response TimeT LRES V I =TTL Logic Swing V REF =1.4V, V RL =5V,R L =5.1K Ω-350--350-nS Response Time T RES V RL =5V, R L =5.1K Ω- 1.4-- 1.4-µS Output Sink Current I SINK V I(-)≥1V, V I(+) =0V, V O(P) ≤1.5V 618-618-mA Output Saturation Voltage V SAT V I(-) ≥ 1V, VI(+) =0V -160400-160400mV I SINK = 4mA Note 1--700--700Output Leakage CurrentI O(LKG)V I(-) = 0V,V I(+) = 1VV O(P) = 5V -0.1--0.1-nA V O(P) = 30V-- 1.0-- 1.0µAKA293/KA293A, KA393/KA393A, KA29034Electrical Characteristics (Continued)(V CC =5V, T A =25°C, unless otherwise specified)NOTE 1KA393 / KA393A : 0 ≤ T A ≤ +70°C KA293 / KA293A : -25 ≤ T A ≤ +85°C KA2903 : -40 ≤ T A ≤ +85°CParameterSymbol ConditionsKA2903Unit Min.Typ.Max.Input Offset Voltage V IO V O(P) =1.4V, R S =0Ω-±1±7mV V CM = 0 to 1.5VNote 1-±9±15Input Offset Current I IO -±5±50nA Note 1-±50±200Input Bias Current I BIAS -65250nA Note 1--500Input Common Mode Voltage Range V I(R)0-V CC -1.5V Note 10-V CC -2Supply Current I CC R L = ∞ , V CC = 5V -0.61mA R L = ∞, V CC = 30V-1 2.5Voltage GainG V V CC =15V, R L ≥15K Ω(for large V O(P-P)swing )25100- V/mV Large Signal Response Time T LRES V I =TTL Logic SwingV REF =1.4V, V RL =5V, R L =5.1K Ω-350-nS Response Time T RES V RL =5V, R L =5.1K Ω- 1.5-µS Output Sink Current I SINK V I(-)≥1V, V I(+) =0V, V O(P) ≤1.5V 616-mA Output Saturation Voltage V SAT V I(-)≥1V, VI(+) =0V -160400mV I SINK = 4mA NOTE 1--700Output Leakage CurrentI O(LKG)V I(-) = 0V,V O(P) = 5V -0.1-nA V I(+) = 1VV O(P) = 30V-- 1.0µAKA293/KA293A, KA393/KA393A, KA29035Typical Performance CharacteristicsFigure 1.Supply Current vs Supply Voltage Figure 2.Input Current vs Supply VoltageFigure 3.Output Saturation Voltage vs Sink CurrentFigure 4.Response Time for Various InputOverdrive-Negative TransitionFigure 5.Response Time for Various InputOverdrive-Positive TransitionKA293/KA293A, KA393/KA393A, KA2903Mechanical DimensionsPackageDimensions in millimeters8-DIP6KA293/KA293A, KA393/KA393A, KA2903 Mechanical Dimensions (Continued)PackageDimensions in millimeters8-SOP7KA293/KA293A, KA393/KA393A, KA2903Mechanical Dimensions (Continued)PackageDimensions in millimeters9-SIP8KA293/KA293A, KA393/KA393A, KA29039Ordering InformationProduct NumberPackage Operating TemperatureKA393 8-DIP 0 ~ + 70°CKA393A KA393D 8-SOP KA393AD KA393S 9-SIP KA293 8-DIP-25 ~ + 85°CKA293A KA293D 8-SOP KA293AD KA2903 8-DIP -40 ~ + 85°C KA2903D8-SOPKA293/KA293A, KA393/KA393A, KA290312/21/01 0.0m 001Stock#DSxxxxxxxx2001 Fairchild Semiconductor CorporationLIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:1.Life support devices or systems are devices or systemswhich, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can bereasonably expected to result in a significant injury of the user.2. A critical component in any component of a life supportdevice or system whose failure to perform can bereasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANYLIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.。

[VIP专享]己二腈MSDS

自燃温度 550
(℃)：
燃烧爆炸危险性
燃烧热(kj/mol： 507
微溶于水、醚，溶于醇。
溶解性：
饱和蒸汽压(kPa)：无资料
相对密度(空气=1)： 3．73
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LG-P690用户指南说明书

內容安全及有效使用準則安全及有效使用準則 .......... (5)重要通知重要通知 (11)了解您的手機了解您的手機 (21)安裝智能卡（SIM 卡）及電池 (23)為手機充電 (24)安裝記憶卡 (25)格式化記憶卡 (26)您的桌面您的桌面 (27)觸控螢幕提示 (27)鎖定您的手機 (27)解鎖螢幕 (28)靜音模式 (28)主頁 (28)在您的桌面上新增小工具 (29)返回最近使用的應用程式 (29)通告欄 (30)檢視狀態列 (30)螢幕鍵盤 (32)輸入重音字母 ...................33Google 帳戶設定Google 帳戶設定 (34)建立您的 Google 帳戶 (34)登入您的 Google 帳戶 (34)通話功能通話功能 (36)撥打電話 (36)從通訊錄中撥打電話 (36)接聽來電和拒接來電 (36)調整通話音量 (36)通話期間撥打第二個電話 (36)檢視通話記錄 (37)通話設定 (37)通訊錄通訊錄 (38)搜尋聯絡人 (38)新增聯絡人 (38)常用的聯絡人 (38)訊息/電子郵件訊息/電子郵件 (39)訊息 (39)發送訊息 (39)更改訊息設定 (40)設定您的電子郵件 (40)Microsoft Exchange 電子郵件帳戶 (40)2其他 (POP3, IMAP) 電郵帳戶 (41)編寫及發送電子郵件 (42)處理帳戶資料夾 (43)新增及編輯電子郵件帳戶 (43)相機相機 (44)了解取景器 (44)快速拍照 (45)拍攝相片後 (45)使用進階設定 (45)檢視已儲存的相片 (47)視像攝錄機視像攝錄機 .......................... (48)瞭解取景器 (48)拍攝快速影片 (49)拍攝影片後 (49)使用進階設定 (49)觀看已儲存的影片 (50)觀看影片時調整音量 (50)多媒體多媒體 (51)檢視模式 (51)時間軸檢視 (51)使用 SmartShare (51)音樂 (52)播放歌曲 (52)使用 USB 大容量儲存裝置傳送檔案 (53)如何在手機上儲存音樂/影片檔案 (53)將通訊錄從舊手機移動至新手機 (54)使用藍芽從手機傳送數據 (54)使用收音機 (55)搜尋電台 (55)重設頻道 (56)收聽電台 (56)實用程式實用程式 (57)設定鬧鐘 (57)使用計算機 (57)新增事件至日曆 (57)更改您的預設日曆檢視模式 (58)Polaris Viewer (58)錄音程式 (59)錄製聲音或語音 (59)發送錄音 (59)3網絡功能網絡功能 (60)瀏覽器 (60)使用網絡工具列 (60)使用選項 (60)設定設定 (62)無線及網絡 (62)通話設定 (63)聲音 (64)顯示 (65)位置及安全 (65)應用程式 (66)帳號及同步處理 (66)隱私設定 (67)SD 卡及手機儲存 (67)語言及鍵盤 (67)語音輸入及輸出 (67)協助工具 (69)日期及時間 (69)關於手機 (69)Wi-Fi (69)開啟 Wi-Fi (69)連接至 Wi-Fi (69)共享手機的流動數據連接。

P6KA高压瞬变二极管

10 10 10 10 10 10 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
5.50 5.80 6.05 6.40 6.63 7.02 7.37 7.78 8.10 8.55 8.92 9.40 9.72 10.2 10.5 11.1 12.1 12.8 12.9 13.6 14.5 15.3
0.034 (0.86) 1.0 (25.4) MIN. 0.028 (0.71) DIA.
0.300 (7.6) 0.230 (5.8)
0.140 (3.6) 0.104 (2.6) DIA. 1.0 (25.4) MIN.
♦ Designed for under the hood applications ♦ Plastic package has Underwriters Laboratory Flammability Classification 94V-0 ♦ Exclusive patented PAR™ oxide passivated chip construction ♦ 600W peak pulse power surge capability with a 10/1000µs waveform repetition rate (duty cycle): 0.01% ♦ Excellent clamping capability ♦ Low incremental surge resistance ♦ Fast response time: typically less than 1.0ps from 0 Volts to V(BR) ♦ For devices with V(BR)≥10V, ID are typically less than1.0µA ♦ High temperature soldering guaranteed: 300°C/10 seconds, 0.375" (9.5mm) lead length, 5lbs. (2.3 kg) tension

P6产品规格书

产品规格书目录目录 01. 适用范围 (1)2. 产品说明 (1)3. 产品参数 (2)4. 信号引脚定义 (3)5. 规格型号说明 (4)6. IC贴片图 (4)7. 安装孔位图 (5)8. 室内P6.0八扫全彩表贴三拼一单元板备件 (7)9. 产品使用注意事项 (7)1. 适用范围本技术手册仅适用于室内P6.0（32*16）八扫全彩表贴三拼一单元板。

2. 产品说明2.1. 室内P6.0八扫全彩表贴三拼一单元板主要是由红色LED、绿色LED和蓝色LED组成矩阵，然后再固定到塑胶套件上而成；2.2. 此单元板含有驱动芯片和输入缓冲芯片，连接到LED显示屏控制系统即可显示视频、图像和文字信息等；2.3. 通过PWM信号驱动红色LED、绿色LED和蓝色LED的驱动芯片，可形成16,777,216种颜色变换；2.4. 此单元板可以按水平和垂直方向任意拼接，从而拼成不同大小的显示屏；2.5. 单元板的特点：●用超高亮的LED和优质的塑胶件●高对比度可达到良好的显示效果●重量轻易于安装、拆卸●可进行单点、单灯维护，成本低●采用恒流方式驱动LED，发光均匀，功耗低●像素间距为6.0mm，共有32*16个像素点，每个像素点由1R1G1B组成2.6. 单元板图片正视图背视图3. 产品参数（温度条件：Ta=25℃）4. 信号引脚定义HUB755. 规格型号说明产品型号命名规范：6. IC 贴片图7 B2 蓝色数据信号 8 GND 电源地 9 A 行电源控制信号 10 B 行电源控制信号 11 C 行电源控制信号 12 GND 电源地 13 CLK 时钟信号14 LAT数据锁存信号15OE使能信号16GND 电源地元器件贴片位置元器件贴片位置 74HC245 U1-U274H138 U3 16126D UR1-UR4、UG1-UG4、UB1- UB4 4953 T1-T8 电阻391，390ΩRR1-RR4、RG1-RG4、RB1-RB4电容104C1-C15排阻560，56Ω RP1-RP8、RP13-RP20 (空白)备注：VRR 、VRG 、VRB 为白平衡调节电阻，其阻值根据使用不同灯管的实际情况而定。

P6SMB36CAT3G中文资料

Publication Order Number: P6SMB11CAT3/D
元器件交易网
P6SMB11CAT3 Series
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Symbol
Parameter
元器件交易网
P6SMB11CAT3 Series
600 Watt Peak Power Zener Transient Voltage Suppressors
Bidirectional*
The SMB series is designed to protect voltage sensitive components from high voltage, high energy transients. They have excellent clamping capability, high surge capability, low zener impedance and fast response time. The SMB series is supplied in ON Semiconductor’s exclusive, cost-effective, highly reliable Surmetict package and is ideally suited for use in communication systems, automotive, numerical controls, process controls, medical equipment, business machines, power supplies and many other industrial/consumer applications.

P6KE39A,TVS瞬变抑制二极管中文资料

P6KE39APOWER: 600Wa t VOLTAGE RANGE: 6.8 - 440VP6KE6.8A(CA)-P6KE440A(CA)Classification Rating 94V-OFeaturesGlass Passivated Die ConstructionUni- and Bi-Directional Versions Available Excellent Clamping Capability Fast Response TimePlastic Case Material has UL Flammability Mechanical DataCase: JEDEC DO-15 Low Profile Molded Plastic Terminals: Axial Leads, Solderable per MIL-STD-202, Method 208Polarity: Cathode Band or Cathode Notch Weight: 0.40 grams (approx.)Maximum Ratings and Electrical Characteristics@T A =25°C unless otherwise specifiedCharacteristicSymbol ValueUnit Peak Pulse Power Dissipation at T A = 25°C (Note 1, 2, 5) Figure 3P PPM 600 MinimumW Peak Forward Surge Current (Note 3)I FSM 100A Peak Pulse Current on 10/1000µS Waveform (Note 1) Figure 1I PPM See Table 1A Steady State Power Dissipation (Note 2, 4)P M(AV) 5.0W Operating and Storage Temperature RangeT j , T STG-65 to +175°CNote: 1. Non-repetitive current pulse, per Figure 1 and derated above T A = 25°C per Figure 4.2. Mounted on 40mm 2 copper pad.3. 8.3ms single half sine-wave duty cycle = 4 pulses per minutes maximum.4. Lead temperature at 75°C = T L .5. Peak pulse power waveform is 10/1000µS.AXIAL LEADED TRANSIENT VOLTAGE SUPPERSSOR DIODE!!!!!!!!P6KE440CA10.5 14.513.412.186.577.971.364.658.953.248.544.740.934.231.428.525.722.820.919.017.115.214.312.49.508.657.797.136.45(uA)R RMW RMW@V leakage Reverse CurrentPulse Peak (A)Vc(V)(mA)BR MAX CurrentMax.BR MIN @I Min.Volgtage Breakdown (V)(BI)(Uni)Voltage Stand-Off Reverse Maximum Clamping V T PP(V)V @I Volgtage Breakdown Test (V)V T Volgtage @I PP P6KE6.8A P6KE6.8CA 5.80 7.14 10.0 57.1 1000.0P6KE7.5A P6KE7.5CA 6.40 7.88 10.0 11.3 53.1 500.0 P6KE8.2A P6KE8.2CA 7.028.61 10.0 49.6 200.0 P6KE9.1A P6KE9.1CA 7.78 9.55 1.0 44.8 50.0 P6KE10A P6KE10CA 8.55 10.5 1.0 41.4 10.0P6KE11A P6KE11CA 9.40 10.5 11.6 1.0 15.6 38.5 5.0 P6KE12A P6KE12CA10.2 11.412.6 1.0 16.7 35.9 5.0P6KE13A P6KE13CA11.1 13.7 1.0 18.2 33.0 5.0 P6KE15A P6KE15CA 12.8 15.8 1.0 21.2 28.3 5.0 P6KE16A P6KE16CA 13.6 16.8 1.0 22.5 26.7 5.0P6KE18A P6KE18CA 15.3 18.9 1.0 25.2 23.8 5.0 P6KE20A P6KE20CA 17.1 21.0 1.0 27.7 21.7 5.0 P6KE22A P6KE22CA 18.8 23.1 1.0 30.6 19.6 5.0 P6KE24A P6KE24CA 20.5 25.2 1.0 33.2 18.1 5.0 P6KE27A P6KE27CA 23.1 28.4 1.0 37.5 16.0 5.0 P6KE30A P6KE30CA 25.6 31.5 1.0 41.4 14.5 5.0 P6KE33A P6KE33CA 28.2 34.7 1.0 45.7 13.1 5.0P6KE36A P6KE36CA 30.8 37.8 1.0 49.9 12.0 5.0P6KE39A P6KE39CA 33.3 37.1 41.0 1.0 53.9 11.1 5.0 P6KE43A P6KE43CA 36.8 45.2 1.0 59.3 10.1 5.0 P6KE47A P6KE47CA 40.2 49.4 1.0 64.8 9.3 5.0 P6KE51A P6KE51CA 43.6 53.6 1.0 70.1 8.6 5.0P6KE56A P6KE56CA 47.8 58.8 1.077.0 7.8 5.0P6KE62A P6KE62CA 53.0 65.1 1.0 85.07.1 5.0 P6KE68A P6KE68CA 58.1 71.4 1.0 92.06.5 5.0 P6KE75A P6KE75CA 64.1 78.81.0 103 5.8 5.0P6KE82A P6KE82CA70.1 86.1 1.0 1135.3 5.0P6KE91A P6KE91CA 77.8 95.5 1.0 1254.85.0 P6KE100A P6KE100CA 85.5 95.0 105 1.0 137 4.4 5.0 P6KE110AP6KE110CA 94.0 105 116 1.0 1523.9 5.0 P6KE120AP6KE120CA102 114 126 1.0 165 3.6 5.0 P6KE130A P6KE130CA 111 124 137 1.0 179 3.4 5.0 P6KE150A P6KE150CA 128 143 158 1.0 207 2.9 5.0 P6KE160A P6KE160CA 136 152168 1.0 219 2.7 5.0 P6KE170A P6KE170CA 145 162 179 1.0 234 2.6 5.0 P6KE180A P6KE180CA 154 171 189 1.0 246 2.4 5.0 P6KE200A P6KE200CA 171 190 210 1.0 274 2.2 5.0 P6KE220A P6KE220CA 185 209 231 1.0 328 1.8 5.0 P6KE250A P6KE250CA 214 237 263 1.0 344 1.7 5.0 P6KE300A P6KE300CA 256 285 315 1.0 414 1.4 5.0 350 310 380 P6KE350A P6KE350CA 1.0 482 1.2 5.0 P6KE400A P6KE400CA 342 380 420 1.0 548 1.1 5.0 P6KE440A 3764184621.06021.05.0TYPERating at = 25 °C ambient temperature unless otherwise specified255075100125150175200100755025T ,AMBIENT TEMPERATURE (°C)Fig.4Pulse Derating CurveA P K P U L S E D E R A T I N G (%P K P W R O R C U R R E N T )25507510012515017520002.55.0T ,LEAD TEMPERATURE (°C)Fig.5,Steady State Power DeratingLP ,S T E A D Y S T A T E P O W E R D I S S I P A T I O N (W )d 0.11.0T ,PULSE WIDTH (µs)Fig.3Pulse Rating Curvep 0.1101001.010100100010000P ,P E A K P U L S E P O W E R (k W )P0123I ,P E A K P U L S E C U R R E N T (%)P p pt,TIME (ms)Fig.1Pulse Waveform110100100010100100010,000V ,REVERSE STANDOFF VOLTAGE (V)Fig.2Typical Junction CapacitanceRWM C ,C A P A C I T A N C E (p F )j。

低功耗瞬态二极管P6SMB39CA型号

低功耗瞬态二极管P6SMB39CA型号硕凯电子（Sylvia）一、最大额定值Notes:1.Non-repetitive current pulse,per Fig.3and derated above TA=25°C per Fig.2.2.Mounted on5.0mm x5.0mm(0.03mm thick)Copper Pads to each terminal.3.8.3ms single half sine-wave,or equivalent square wave,Duty cycle=4pulses per minutes maximum.4.VF<3.5V for VBR<200V and VF<6.5V for VBR>201V.二、瞬态二极管产品特性1、为表面安装应用优化电路板空间2、低泄漏3、单向和双向单元4、玻璃钝化结5、低电感6、优良的钳位能力7、600W的峰值功率能力在10×1000μ波形重复率（占空比）：0.01%8、快速响应时间：从0伏特到最小击穿电压通常小于1.0ps9、典型的，在电压高于12V时，反向漏电流小于5μA10、高温焊接：终端260°C/40秒11、典型的最大温度系数△Vbr=0.1%x Vbr@25°C x△T12、塑料包装有保险商实验室可燃性94V-013、无铅镀雾锡14、无卤化，符合RoHS15、典型失效模式是在指定的电压或电流下出现16、晶须测试是基于JEDEC JESD201A每个表4a及4c进行的17、IEC-61000-4-2ESD15kV(空气)，8kV(接触)18、数据线的ESD保护符合IEC61000-4-2(IEC801-2)19、数据线的EFT保护符合IEC61000-4-4(IEC801-4)三、脉冲降额曲线四、UL认证编号五、脉冲浪涌五、产品应用说明TVS器件非常适合保护I/O接口，Vcc总线和其他应用于电信、计算机、工业和消费电子应用的易损电路。

CS5460A中文数据手册

CS5460A
单相双向功率/电能 IC
特性
l l l l l l l l l l l l l l l 电能数据线性度：在1000 ：1 动态范围内线性度为 ±0.1% 片内功能：可以测量电能（有功），I *V，IRMS 和 VRMS ，具有电能-脉冲转换功能可以从串行EEPROM 智能“自引导”，不需要微控制器 AC 或DC 系统校准具有机械计度器/步进电机驱动器符合IEC687/1036 ，JIS 工业标准功耗<12mW 优化的分流器接口 V对I的相位补偿单电源地参考信号片内2.5V 参考电压（最大温漂60ppm/℃）简单的三线数字串行接口看门狗定时器内带电源监视器电源配置 VA+ = +5 V; VA- = 0V; VD+ = +3.3V～+5 V
概述
CS5460A 是一个包含两个ΔΣ模 - 数转换器（ADC）、高速电能计算功能和一个串行接口的高度集成的ΔΣ 模-数转换器。它可以精确测量和计算有功电能、瞬时功率、 IRMS 和VRMS ，用于研制开发单相2 线或3 线电表。CS5460A 可以使用低成本的分流器或互感器测量电流，使用分压电阻或电压互感器测量电压。CS5460A 具有与微控制器通讯的双向串口，芯片的脉冲输出频率与有功能量成正比。CS5460A 具有方便的片上AC/DC 系统校准功能。 “自引导”的特点使 CS5460A 能独自工作，在系统上电后自动初始化。在自引导模式中， CS5460A 从一个外部EEPROM 中读取校准数据和启动指令。使用该模式时，CS5460A 工作时不需要外加微控制器，因此当电表用于大批量住宅电能测量时，可降低电表的成本。订货信息： CS5460A-BS -40℃～＋85℃ 24 引脚 SSOP

Furman PST-6 电源保护设备说明书

The PST-6IntroductionThank you for purchasing the Furman Power Station-6 Power Conditioner. For over 30 years, Furman has pioneered the development of AC power products for the most demanding audio, video, and broadcast professionals. Furman’s Ground Contamination Free Surge Protection, Advanced Filtering Technology, and Digital-HD Television Ready circuitry can signiﬁ cantly improve your sensitive components while protecting them from spikes, surges and contaminated AC power.Today’s power grid typically experiences numerous electrical surges and spikes on a daily basis. At best, these irregularities can degrade your equipment’s performance; at worst, they can severely damage individual components or your entire system. Not so with Furman.With our exclusive Ground Contamination Free Surge Protection, your valued equipment is protected without the long-term damaging effect of conventional surge strips.Safety InformationTo obtain best results from your Furman Power Station-6 Power Conditioner, please be sure to read this manual carefully before using.Warning:To reduce the risk of electrical shock, do not expose this equipment to rain or moisture. Dangerous high voltages are present inside the enclosure. Do not remove the covers. There are no user serviceable parts inside. Refer servicing to qualiﬁ ed personnel only.2Important Safety Instructions:1. Please read and observe all safety and operating instructions before installing your Power Station-6 (PST-6). Retain these instructions for future reference.2. Your PST-6 should not be used near water – for example, neara bathtub, washbowl, kitchen sink, laundry tub, in a wet basement, near a swimming pool, etc.3. Do not place your PST-6 near heat sources such as radiators, heat registers, stoves or other appliances that produce heat.4. The PST-6 should only be connected to a 120 VAC, 60Hz, 15 amp grounded electrical outlet. Do not defeat the ground or change polarization of the power plug.5. Route the power cord and other cables so that they are not likely to be walked on, tripped over, or stressed. Pay particular attention to the condition of the cords and cables at the plugs, and the point where they exit your PST-6. To prevent risk of ﬁ re or injury, damaged cords and cables should be replaced immediately.6. Clean your PST-6 with a damp cloth only. Do not use solvents or abrasive cleaners. Never pour liquid on or into the unit.7. Your PST-6 should be serviced by qualiﬁ ed service personnel when:3• The power supply cord or the plug has been frayed, kinked, or cut.• Objects have fallen or liquid has spilled into the unit.• The unit has been exposed to rain or other moisture.• The unit does not appear to operate normally, exhibits a marked change in performance, or the Protection OK indicator is not lit.• The unit has been dropped, or the enclosure damaged.8. Your PST-6 requires that a safety ground be present for properoperation. Any attempt to operate the unit without a safety ground is considered improper operation and could invalidate the warranty.OperationAC, Telephone, and Coaxial ConnectorsTelco – Satellite / Cable Transient Voltage Surge Suppressors: The PST-6 features transient voltage surge suppression for both standard telephone lines, as well as cable and satellite lines utilizing standard coaxial connectors. As these surge suppressors are in-line, they will require an additional cable (supplied with the PST-6) to connect from their output to the control device requiring protection.All in-line surge suppressors feature our exclusive ground contamination free technology. This aids in eliminating audio buzzing, and the video hum-bars that can result from typical in-line suppressors. Further, our cable and satellite suppressors are TIVO friendly as well as HD-Digital Television ready. Both DC carrier signals as well as high bandwidth signals can pass through our 4circuit. In fact the bandwidth is less than 0.1dB loss at 1GHz!To connect your cabling to these in-line protectors, simply follow thein and out indications marked next to the Telco, and Cable / Satellite connectors.Note:It is not possible to make an in-line cable / satellite protector “maintenance-free.” Under extreme conditions, it is possible that the surge suppression in one of these devices could sacriﬁ ce itself after a catastrophic event. If the telephone, cable or satellite signal will no longer pass through our protector, please send your Power Station to Furman for servicing. To test this, simply disconnect the incoming and out going cable from the PST-6. Connect the incoming connector to the component that formerly received the out going connector, thus by-passing the in-line protection. If the signalis present (but not when used with the PST-6) then the protection circuit is damaged (assuming it worked properly before the storm or catastrophic event).Circuit BreakerIf the PST-6 is connected to an AC outlet where sufﬁ cient voltageis present, the unit should operate properly with the protection OK indicator lit, after the main power switch is turned to the on position.If the unit still does not function under these conditions check the circuit breaker button! It is the round black button adjacent to the incoming AC cord. If the circuit breaker trips immediately, there may be too great of a current load placed upon it. Simply disconnect one5product at a time until this no longer happens. If the breaker trips with no components connected, there may be a wiring defect that requires Furman service.IndicatorsProtection OK Indicator:Although Furman’s Ground Contamination Free Surge Suppression rarely requires servicing, nature has a way of occasionally creating electrical forces that are beyond the capabilities of any transient voltage surge suppressor device to absorb without some degree of damage. In the instance that this occurs, the blue “Protection OK” LED indicator will turn off. If this happens, Furman’s surge suppression circuit is compromised. The unit must be returned to Furman Sound, or an authorized Furman Service Center for repair.MountingIf the Power Station needs to be mounted to the inside panel of a rack or hung from a wall, a convenient crossed oval cutout is provided on the unit’s bottom panel. A standard No. 6 pan head screw can be used in the same way a picture is hung from a wall. Simply measure the centers on the bottom of your Power Station. This will be the distance from the two mounting holes drilled into your wall, rack or cabinet surface. Once the screw is fastened ﬂ ush with the surface, back it out approximately ½”. The screw head should push through the crossed cutout on the bottom surface of the Power Station. Next, simply allow the Power Station to move down and seat into the end of its oval cut-out. Adjust the pan head screw if necessary.6WarrantyFurman Sound, Inc., having its principal place of business at 1997 South McDowell Blvd., Petaluma, CA 94954 (“Manufacturer”) warrants its PST-6 (the “Product”) as follows:Manufacturer warrants to the original Purchaser of the Product that the Product sold hereunder will be free from defects in material and workmanship for a period of one year from the date of purchase. The Purchaser of the product is allowed ﬁ fteen days from the date of purchase to complete warranty registration by mail or on-line at the Furman website. If the Product does not conform to this Limited Warranty during the warranty period (as herein above speciﬁ ed), Purchaser shall notify Manufacturer in writing of the claimed defects. If the defects are of such type and nature as to be covered by this warranty, Manufacturer shall authorize Purchaser to return the Product to the Furman factory or to an authorized Furman repair location. Warranty claims should be accompanied by a copy of the original purchase invoice showing the purchase date; this is not necessary if the Warranty Registration was completed either via the mailed in warranty card or on-line website registration. Shipping charges to the Furman factory or to an authorized repair location must be prepaid by the Purchaser of the product. Manufacturer shall, at its own expense, furnish a replacement Product or,at Manufacturer’s option, repair the defective Product. Return shipping charges back to Purchaser will be paid by Manufacturer.THE FOREGOING IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS7FOR A PARTICULAR PURPOSE. Manufacturer does not warrant against damages or defects arising out of improper or abnormal use of handling of the Product; against defects or damages arising from improper installation, against defects in products or components not manufactured by Manufacturer, or against damages resulting from such non-Manufacturer made products or components. This warranty shall be cancelable by Manufacturer at its sole discretion if the product is modiﬁ ed in any way without written authorization from Furman Sound.This warranty also does not apply to Products upon which repairs have been affected or attempted by persons other than pursuant to written authorization by Manufacturer.THIS WARRANTY IS EXCLUSIVE. The sole and exclusive obligation of Manufacturer shall be to repair or replace the defective Product in the manner and for the period provided above. Manufacturer shall not have any other obligation with respect to the Products or any part thereof, whether based on contract, tort, strict liability or otherwise.Under no circumstances, whether based on this Limited Warranty or otherwise, shall Manufacturer be liable for incidental, special, or consequential damages. Manufacturer’s employees or representatives’ ORAL OR OTHER WRITTEN STATEMENTS DO NOT CONSTITUTE WARRANTIES, shall not be relied upon by Purchaser, and are not a part of the contract for sale or this limited warranty. This Limited Warranty states the entire obligation of Manufacturer with respect to the Product.If any part of this Limited Warranty is determined to be void or illegal, the remainder shall remain in full force and effect.8ServiceAll equipment being returned for repair must have a Return Authorization (R/A) Number. To get an R/A number, please call the Furman Service Department at (707) 763-1010 ext 121, between the hours of 8:00 am and 5:00 pm US Paciﬁ c Time. When returning equipment for repair, please use the original packaging to ship the product. Also, please enclose a note giving your name, address, phone number, e-mail address, and a description of the problem. Please display your R/A Number prominently on the front of all packages.91011Furman Sound, Inc.1997 South McDowell Blvd.Petaluma, California 94954-6919 USAPhone: 707-763-1010Fax: 707-763-1310Web: E-mail:********************12011104-D。

SM39R16A3内嵌16KB具...

产品目录 (3)描述 (3)订货信息 (3)特征 (3)各封装引脚配置 (4)系统方框图 (6)管脚描述 (7)特殊功能寄存器(SFR) (8)功能描述 (12)1.总特征 (12)1.1嵌入式程序存储器 (12)1.2IO口 (12)1.3指令时钟周期选择 (12)1.4时钟输出选择 (13)1.5复位 (13)1.6时钟源 (15)2.指令设置 (16)3.存储器结构 (20)3.1程序存储器 (20)3.2数据存储器 (21)3.3数据内存-低128字节(00H TO 7F H) (21)3.4数据存储器-高128字节(80H TO FF H) (21)3.5存储器-扩展的256字节($00到$FF) (21)4.CPU结构 (22)4.1累加器 (22)4.2B寄存器 (22)4.3程序状态字 (23)4.4堆栈指针 (23)4.5数据指针 (23)4.6数据指针1 (24)4.7时钟控制寄存器 (24)4.8接口控制寄存器 (25)5.GPIO管脚型态 (26)6.定时器0 和定时器1 (28)6.1定时器/计数器模式控制寄存器(TMOD) (28)6.2定时/计数控制寄存器(TCON) (29)6.3定时器输入频率控制寄存器 (29)6.4模式0(13位定时/计数) (30)6.5模式1(16位定时/计数) (31)6.6模式2(8位自动重载定时/计数) (31)6.7模式3(两个独立8位定时/计数(仅定时器0)) (32)7.定时器2 以及捕捉/比较单元 (32)7.1定时器2功能 (35)7.2比较功能 (36)7.3捕获功能 (38)8.串行接口0 (39)8.1串行接口由以下4种模式可以设置 (40)8.2串行接口的多重机通讯 (42)8.3输入频率控制寄存器 (42)8.4波特率发生器 (42)9.看门狗定时器 (44)10.中断 (48)10.1优先权配置 (51)11.电源管理单元 (53)11.1待机模式(空闲模式) (53)11.2停止模式 (53)12.脉宽调制器(PWM) (54)13.IIC 功能 (57)14.SPI功能 (62)15.KBI –键盘接口 (67)16.LVI –低压侦测中断 (70)17.10位模拟数字转换器(ADC) (71)18.在系统编程(INTERNAL ISP) (75)18.1ISP服务程序 (75)18.2锁定位(N) (75)18.3对ISP服务程序编程 (76)18.4启动ISP服务程序 (76)18.5ISP寄存器–TAKEY,IFCON,ISPFAH,ISPFAL,ISPFD AND ISPFC (76)19.比较器(COMPARATOR) (80)工作环境 (83)DC电气特性 (83)ADC电气特性 (85)COMPARATOR 电气特性 (85)LVI& LVR电气特性 (86)产品目录SM39R16A3U20,SM39R16A3U16,SM39R16A3U14,描述原来的8052有12时钟结构,一个机器周期需要12个时钟，大多数指令是一个或两个机器周期.因此，除了乘和除指令, 8052的每个指令使用12或24个时钟,此外,8052中的每个周期用了两个记忆提取.在许多情况下，第二个是假的提取,和额外的时钟被浪费了该SM39R16A3是一个快速的单芯片8位微控制器内核.这是一个全功能的8位嵌入式控制器，执行所有ASM51指令,具有与MCS - 51相同的指令设置订货信息SM39R16A3ihhkL yymmvi: 工艺标志{ U = 1.8V ~ 5.5V}hh: 封装脚位k: 封装形式后缀{as table below }L: 无铅标志{无文字即含铅，”P” 即无铅}yy: 年mm: 月v: 版本标志{ A, B,…}Postfix PackageN PDIP (300 mil)S SOP (300 mil)O SOP (150 mil)G SSOP (150 mil) 特征●工作电压: 1.8V ~ 5.5V●高速1T 架构，最高可达25MHz●1~8T 模式可使用软件编程●指令设置兼容 MCS-51●内置22.1184MHz RC振荡器，及可程序化的分频器●16KB字节的片上闪存程序存储器●512B 字节的标准的8052 RAM●双16-bit 数据指针 (DPTR0&DPTR1)●一个全双工通信的串行接口.附加波特率产生器●三个16-bit 的定时器/计数器（计时器0，1，2）●12 ~18 GPIOs(14L~ 20L封装脚位)，GPIOs 可选择四种型态(准双向口、推挽、开漏、只输入)，默认准双向口(上拉)●具有四级优先权的外部中断0&外部中断1●可编程的看门狗定时器（WDT）●一个IIC 接口（主/从机模式）●一个SPI 接口（主/从机模式）●4路 10bit 脉宽调制(PWM)●4路16bit 比较(PWM)/捕获/重载功能●7路10bit 模拟数字转换（ADC）加上1路通道0链接内部Vref●片上内建比较器●片上闪存存储器支持ISP/IAP/ICP及EEPROM 功能●ISP服务程序存储空间设置为N*128 byte (N=0 to 8) ●片上在线仿真功能(ICE)及片上在线调试功能(OCD) ●键盘接口(KBI) 共4个的中断源●ALE 输出选择●低电压中断/低电压复位(LVI/LVR )●管脚ESD性能超过4KV●增强用户代码保护●电源管理单元空闲及掉电模式各封装引脚配置20 Pin PDIP/SOP/SSOPCmp1Out/SPICLK/KBI0/P0.0 PWM1/MOSI/CC2/P1.7PWM0/MISO/CC1/P1.6RST/P1.5VSSOSC_IN/XTAL1/P3.1CLKOUT/XTAL2/P3.0SS/INT1/P1.4 OCISDA/IICSDA/INT0/P1.3 OCISCL/IICSCL/T0/P1.2P0.1/KBI1/ADC1/Cmp1NInP0.2/KBI2/ADC2/Cmp1PInP0.3/KBI3/T2/ADC3/Cmp0NIn P0.4/ADC4/Cmp0PInP0.5/ADC5/CC0/PWM2 VDDP0.6/ADC6/Cmp0OutP0.7/T1/ADC7/CC3/PWM3P1.0/TXDP1.1/RXD/T2EX16 Pin SOPPWM0/MISO/CC1/P1.6RST/P1.5VSS OSC_IN/XTAL1/P3.1CLKOUT/XTAL2/P3.0SS/INT1/P1.4 OCISDA/IICSDA/INT0/P1.3 OCISCL/IICSCL/T0/P1.2P0.3/KBI3/T2/ADC3/Cmp0NIn P0.4/ADC4/Cmp0PInP0.5/ADC5/CC0/PWM2 VDDP0.6/ADC6/Cmp0OutP0.7/T1/ADC7/CC3/PWM3P1.0/TXDP1.1/RXD/T2EX14 Pin SOPSM39R16A3PWM0/MISO/CC1/P1.6RST/P1.5VSSOSC_IN/XTAL1/P3.1CLKOUT/XTAL2/P3.0OCISDA/IICSDA/INT0/P1.3P1.2/IICSCL/T0/OCISCLVDD P1.0/TXD P1.1/RXD/T2EX PWM1/MOSI/CC2/P1.7P0.0/KBI0/SPICLK/Cmp1Out P0.1/KBI1/ADC1/Cmp1NIn P0.2/KBI2/ADC2/Cmp1PIn附注：出厂默认值注意事项(1) 管脚RST/P1.5于出厂时设置为一般双向I/O(P1.5)脚，若使用者需切换为复位脚可于刻录时将此管脚定义为RESET 脚(2) 2. 为避免偶然的情况下误入ISP 刻录状态(参考第18.4单元)，在上电时请确保没有连续的脉冲信号在管脚RXD P1.1及管脚P1.6必须置高，可于刻录时(3) 3. OSI_SDA/P1.3及OCI_SCL/P1.2于复位期间为ICP 刻录功能管脚，复位完成后切换成双向I/O.系统方框图Port 0Port 1Port 3T0T1CC0~CC3T2T2EXI C _S C L P W M 0P W M 1R X DX Dm p 0N I n /C m 1N I n m p 0O u t /C m p 1O u tXTAL1XTAL2D C 1 D C 2 D C 3 I C _S D AP I _M I S O P I _M O S I P I _C L K P I _S SD C 4D C 5 D C 6 D C 7O C I _S C (s h a r e w i t h I I C O C I _S D (s h a r e w i t h I I C RESET m p 0P I n /C m p 1P I n P W M 2P W M 3管脚描述20L 16L 14L 代号I/O 描述1 - 14 P0.0/KBI0/SPICLK/ADC0/ CMP1OutI/O P0口的位0 & 键盘接口中断0 & SPI 接口时钟&模数转换通道0 &比较器1输出2 - 1 P1.7/CC2/MOSI/PWM1 I/O P1口的位7 &计时器2及捕获/比较单元通道2& SPI 接口串行数据线主输出或从输入口&宽脉调制通道13 1 2 P1.6/CC1/MISO/PWM0 I/O P1口的位6 &计时器2及捕获/比较单元通道1& SPI 接口串行数据线主输入或从输出口&宽脉调制通道04 2 3 P1.5/RST I/O P1口的位5 &复位 5 3 4 VSSI 供电电源地6 4 5 P3.1/XTAL1/OSC_IN I/O P3口的位1 &晶振输入&外部振荡器输入7 5 6 P3.0/XTAL2/CLKOUT I/O P3口的位0 &晶振输出&时钟输出8 6 - P1.4/INT1/SS I/O P1口的位4 &外部中断1& SPI 接口从机跳线9 7 7 P1.3/INT0/IICSDA/OCISDA I/O P1口的位3 &外部中断0 & IIC 串行数据线 & ICE 和 ICP 功能的指令及数据输入10 8 8 P1.2/T0/IICSCL/ OCISCL I/O P1口的位2 &计时器0外部输入& IIC 串行时钟线 & ICE 和 ICP 功能的时钟输入11 9 9 P1.1/RXD/T2EX I/O P1口的位1 & 串行接口通道接收/发送数据 & 计时器2捕捉触发及捕获触发器12 10 10 P1.0/TXDI/O P1口的位0 &串行接口通道数据传输或接收模式0时钟13 11 - P0.7/T1/ADC7/ CC3/PWM3I/O P0口的位7 &计时器1外部输入&模数转换通道7 &计时器2及捕获/比较单元通道3 &宽脉调制通314 12 - P0.6/ADC6/CMP0Out I/O P0口的位6 & 模数转换通道6 &比较器0输出 15 13 11 VDDI 数位电源电压16 14 - P0.5/ADC5/CC0/PWM2 I/O P0口的位5 & 模数转换通道5 &计时器2及捕获/比较单元通道0 &宽脉调制通道217 15 - P0.4/ADC4/ CMP0PIn I/O P0口的位4 & 模数转换通道4 & 比较器0非反向输入18 16 - P0.3/KBI3/T2/ ADC3/CMP0NIn I/O P0口的位3 & 键盘接口中断3 & 计时器2外部输入时钟 &模数转换通道3 & 比较器0反向输入19 - 12 P0.2/KBI2/ADC2/ CMP1PIn I/O P0口的位2 & 键盘接口中断2 & 模数转换通道2 & 比较器1非反向输入20-13P0.1/KBI1/ADC1/ CMP1NInI/OP0口的位0 & 键盘接口中断1 & 模数转换通道1 & 比较器1反向输入特殊功能寄存器(SFR)特殊功能寄存器分布图如下所示：注：SM39R16A3特殊功能寄存器的重置值在下表描述寄存器地址重置值描述SYSTEMSP 81h 07h Stack PointerACC E0h 00h AccumulatorPSW D0h 00h Program Status WordB F0h 00h B RegisterDPL 82h 00h Data Pointer 0 low byteDPH 83h 00h Data Pointer 0 high byteDPL1 84h 00h Data Pointer 1 low byteDPH1 85h 00h Data Pointer 1 high byteAUX 91h 00h Auxiliary registerPCON 87h 00h Power ControlCKCON 8Eh 10h Clock control registerINTERRUPT & PRIORITYIRCON C0h 00h Interrupt Request Control RegisterIRCON2 97h 00h Interrupt Request Control Register 2寄存器地址重置值描述IEN0 A8h 00h Interrupt Enable Register 0IEN1 B8h 00h Interrupt Enable Register 1IEN2 9Ah 00h Interrupt Enable Register 2IP0 A9h 00h Interrupt Priority Register 0IP1 B9h 00h Interrupt Priority Register 1KBIKBLS 93h 00h Keyboard level selector RegisterKBE 94h 00h Keyboard input enable RegisterKBF 95h 00h Keyboard interrupt flag RegisterKBD 96h 00h Keyboard interface De-bounce control register UARTPCON 87h 00h Power ControlAUX 91h 00h Auxiliary registerSCON 98h 00h Serial Port, Control RegisterSBUF 99h 00h Serial Port, Data BufferSRELL AAh 00h Serial Port, Reload Register, low byteSRELH BAh 00h Serial Port, Reload Register, high bytePFCON D9h 00h Peripheral Frequency control registerADCADCC1 ABh 00h ADC Control 1 RegisterADCC2 ACh 00h ADC Control 2 RegisterADCDH ADh 00h ADC data high byteADCDL AEh 00h ADC data low byteADCCS AFh 00h ADC clock selectWDTRSTS A1h 00h Reset status registerWDTC B6h 04h Watchdog timer control registerWDTK B7h 00h Watchdog timer refresh key.TAKEY F7h 00h Time Access Key registerPWMPWMC B5h 00h PWM control registerPWMD0H BCh 00h PWM channel 0 data high bytePWMD0L BDh 00h PWM channel 0 data low bytePWMD1H BEh 00h PWM channel 1 data high bytePWMD1L BFh 00h PWM channel 1 data low bytePWMD2H B1h 00h PWM channel 2 data high bytePWMD2L B2h 00h PWM channel 2 data low bytePWMD3H B3h 00h PWM channel 3 data high bytePWMD3L B4h 00h PWM channel 3 data low bytePWMMDH CEh 00h PWM Max Data Register, high byte. PWMMDL CFh FFh PWM Max Data Register, low byte.寄存器地址重置值描述TIMER0/TIMER1TCON 88h 00h Timer/Counter ControlTMOD 89h 00h Timer Mode ControlTL0 8Ah 00h Timer 0, low byteTL1 8Bh 00h Timer 1, low byteTH0 8Ch 00h Timer 0, high byteTH1 8Dh 00h Timer 1, high bytePFCON D9h 00h Peripheral Frequency control registerPCA(TIMER2)CCEN C1h 00h Compare/Capture Enable RegisterCCL1 C2h 00h Compare/Capture Register 1, low byteCCH1 C3h 00h Compare/Capture Register 1, high byteCCL2 C4h 00h Compare/Capture Register 2, low byteCCH2 C5h 00h Compare/Capture Register 2, high byteCCL3 C6h 00h Compare/Capture Register 3, low byteCCH3 C7h 00h Compare/Capture Register 3, high byteT2CON C8h 00h Timer 2 ControlCCCON C9h 00h Compare/Capture ControlCRCL CAh 00h Compare/Reload/Capture Register, low byte CRCH CBh 00h Compare/Reload/Capture Register, high byte TL2 CCh 00h Timer 2, low byteTH2 CDh 00h Timer 2, high byteCCEN2 D1h 00h Compare/Capture Enable 2 registerGPIOP0 80h FFh Port 0P1 90h FFh Port 1P3 B0h FFh Port 3P0M0 D2h 00h Port 0 output mode 0P0M1 D3h 00h Port 0 output mode 1P1M0 D4h 00h Port 1 output mode 0P1M1 D5h 00h Port 1 output mode 1P3M0 DAh 00h Port 3 output mode 0P3M1 DBh 00h Port 3 output mode 1ISP/IAP/EEPROMIFCON 8Fh 00h Interface control registerISPFAH E1h FFh ISP Flash Address-High registerISPFAL E2h FFh ISP Flash Address-Low registerISPFD E3h FFh ISP Flash Data registerISPFC E4h 00h ISP Flash control registerTAKEY F7h 00h Time Access Key registerLVI/LVR/SOFTRESET寄存器地址重置值描述RSTS A1h 00h Reset status registerLVC E6h 20h Low voltage control registerSWRES E7h 00h Software Reset registerTAKEY F7h 00h Time Access Key registerSPIAUX 91h 00h Auxiliary registerSPIC1 F1h 08h SPI control register 1SPIC2 F2h 00h SPI control register 2SPITXD F3h 00h SPI transmit data bufferSPIRXD F4h 00h SPI receive data bufferSPIS F5h 40h SPI status registerIICAUX 91h 00h Auxiliary registerIICS F8h 00h IIC status registerIICCTL F9h 04h IIC control registerIICA1 FAh A0h IIC channel 1 Address 1 registerIICA2 FBh 60h IIC channel 1 Address 2 registerIICRWD FCh 00h IIC channel 1 Read / Write Data buffer IICEBT FDh 00h IIC Enable Bus Transaction register OPAOPPIN F6h 00H Comparator Pin Select registerCMP0CON FEh 00h Comparator 0 Control registerCMP1CON FFh 00h Comparator 1 Control register功能描述1. 总特征SM39R16A3是一个8位的微处理器,它的所有功能以及特殊功能寄存器（SFR）的详细定义将在以下章节给出.1.1 嵌入式程序存储器可通过编程器或在线编程(ISP)将程序加载到16KB的嵌入式闪存体中,其高品质的闪存体具有100K次的重复可擦写编程并记忆数据，如EEPROM。

LG P693 手机用户手册说明书

目录安全注意事项 (4)开始了解您的手机..9安装USIM卡和电池 (11)手机充电 (12)安装存储卡 (13)格式化存储卡 (13)您的主屏 (15)备注 (15)锁定您的手机 (15)解锁屏幕 (15)在手机主屏上添加窗口小部件 (15)查看近期任务 (16)通知器 (16)查看状态栏 (16)输入文本 (17)全键盘输入法 (18)手机键盘输入法 (18)手写屏幕输入法 (19)通话 (20)拨打电话 (20)呼叫联系人 (20)接听和拒绝电话 (20)拨打第二个电话 (20)查看通话记录 (21)通话设置 ............21联系人.. (21)搜索联系人 (21)添加新联系人 (21)信息/电子邮件 (22)信息 (22)发送信息 (22)信息框 (22)设置电子邮件 (22)照相机 (24)开始了解取景器 (24)快速拍照 (25)拍照后 (25)使用高级设置 (25)摄像机 (27)了解取景器 (27)快速摄像 (28)拍摄视频后 (28)使用高级设置 (28)查看保存的视频 (29)观看视频时调节音量 ..29多媒体 (30)更改相册内容显示的方式 (30)使用USB大容量存储设备传输文件 (30)2如何将音乐/视频文件保存到手机 (30)将原手机的联系人导入到新手机 (31)如何通过蓝牙从手机发送数据 (31)音乐 (32)播放歌曲 (32)使用SmartShare (33)使用收音机 (34)搜索电台 (34)重置频道 (34)收听无线广播 (35)其他应用程序 (36)实用工具 (38)设置闹钟 (38)使用计算器 (38)将事件添加到日历中 ..38更改日历视图 (38)录音机 (38)使用录音 (39)发送录制的声音 (39)Polaris Viewer (39)网络 (40)浏览器 (40)使用选项 (40)添加并访问书签 (40)更改网络浏览器设置 ..40设置 (41)无线和网络 (41)通话设置 (41)声音 (41)显示屏 (41)位置和安全 (41)应用程序 (41)帐户与同步 (42)隐私权 (42)存储卡和手机内存 (42)语言和键盘 (42)辅助功能 (42)日期和时间 (42)关于手机 (42)技术参数 (43)配件 (44)关于安全有效使用手机的准则 (45)3在将手机送到服务中心或给客服代表拨打电话之前，请检查一下您的手机所遇到的问题是不是在此节中描述了。

P6SMB39CAT3G资料

P6SMB11CAT3 Series600 Watt Peak Power Zener Transient Voltage Suppressors Bidirectional*The SMB series is designed to protect voltage sensitive components from high voltage, high energy transients. They have excellent clamping capability, high surge capability, low zener impedance and fast response time. The SMB series is supplied in ON Semiconductor’s exclusive, cost-effective, highly reliable Surmetic t package and is ideally suited for use in communication systems, automotive, numerical controls, process controls, medical equipment, business machines, power supplies and many other industrial/consumer applications.Features•Working Peak Reverse V oltage Range − 9.4 to 77.8 V •Standard Zener Breakdown V oltage Range − 11 to 91 V •Peak Power − 600 W @ 1 ms•ESD Rating of Class 3 (>16 KV) per Human Body Model •Maximum Clamp V oltage @ Peak Pulse Current•Low Leakage < 5 m A Above 10 V•UL 497B for Isolated Loop Circuit Protection •Response Time is Typically < 1 ns•Pb−Free Packages are AvailableMechanical Characteristics:CASE:V oid-Free, Transfer-Molded, Thermosetting Plastic FINISH:All External Surfaces are Corrosion Resistant and Leads are Readily SolderableMAXIMUM CASE TEMPERATURE FOR SOLDERING PURPOSES: 260°C for 10 SecondsLEADS:Modified L−Bend Providing More Contact Area to Bond Pads POLARITY:Polarity Band Will Not be IndicatedMOUNTING POSITION:AnyMAXIMUM RATINGSRating Symbol Value Unit Peak Power Dissipation (Note 1) @ T L = 25°C,Pulse Width = 1 msP PK600WDC Power Dissipation @ T L = 75°C Measured Zero Lead Length (Note 2) Derate Above 75°CThermal Resistance, Junction−to−LeadP DR q JL3.04025WmW/°C°C/WDC Power Dissipation (Note 3) @ T A = 25°C Derate Above 25°CThermal Resistance, Junction−to−AmbientP DR q JA0.554.4226WmW/°C°C/WOperating and Storage Temperature Range T J, Tstg−65 to+150°CStresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.1.10 X 1000 m s, non−repetitive2.1″ square copper pad, FR−4 board3.FR−4 board, using ON Semiconductor minimum recommended footprint, asshown in 403A case outline dimensions spec.*Please see P6SMB6.8AT3 to P6SMB200AT3 for Unidirectional devices.Devices listed in bold, italic are ON Semiconductor Preferred devices. Preferred devices are recommended choices for future use and best overall value.Device Package Shipping†ORDERING INFORMATIONP6SMBxxCAT3SMB2500/T ape & ReelP6SMBxxCAT3G SMB(Pb−Free)2500/T ape & Reel†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our T ape and Reel Packaging Specifications Brochure, BRD8011/D.The “T3” suffix refers to a 13 inch reel.ELECTRICAL CHARACTERISTICS(T A = 25°C unless otherwise noted)Symbol ParameterI PP Maximum Reverse Peak Pulse CurrentV C Clamping Voltage @ I PPV RWM Working Peak Reverse VoltageI R Maximum Reverse Leakage Current @ V RWMV BR Breakdown Voltage @ I TI T Test CurrentQ V BR Maximum Temperature Coefficient of V BRELECTRICAL CHARACTERISTICS (Devices listed in bold, italic are ON Semiconductor Preferred devices.)Device*DeviceMarkingV RWM(Note 4)I R@V RWMBreakdown Voltage V C @ I PP(Note 6)Q V BRC typ(Note 7)V BR Volts (Note 5)@ I T V C I PPVolts m A Min Nom Max mA Volts Amps%/°C pFP6SMB11CAT3, G P6SMB12CAT3, G P6SMB13CAT3, G 11C12C13C9.410.211.155510.511.412.411.051213.0511.612.613.711115.616.718.23836330.0750.0780.081865800740P6SMB15CAT3, G P6SMB16CAT3, G P6SMB18CAT3, G P6SMB20CAT3, G 15C16C18C20C12.813.615.317.1555514.315.217.11915.0516182015.816.818.921111121.222.525.227.7282724220.0840.0860.0880.09645610545490P6SMB22CAT3, G P6SMB24CAT3, G P6SMB27CAT3, G P6SMB30CAT3, G 22C24C27C30C18.820.523.125.6555520.922.825.728.5222427.053023.125.228.431.5111130.633.237.541.420181614.40.090.0940.0960.097450415370335P6SMB33CAT3, G P6SMB36CAT3, G P6SMB39CAT3, G P6SMB43CAT3, G 33C36C39C43C28.230.833.336.8555531.434.237.140.933.053639.0543.0534.737.84145.2111145.749.953.959.313.21211.210.10.0980.0990.10.101305280260240P6SMB47CAT3, G P6SMB51CAT3, G P6SMB56CAT3, G P6SMB62CAT3, G 47C51C56C62C40.243.647.853555544.748.553.258.947.0551.05566249.453.658.865.1111164.870.177859.38.67.87.10.1010.1020.1030.104220205185170P6SMB68CAT3, G P6SMB75CAT3, G P6SMB82CAT3, G P6SMB91CAT3, G 68C75C82C91C58.164.170.177.8555564.671.377.986.56875.05829171.478.886.195.51111921031131256.55.85.34.80.1040.1050.1050.1061551401301204. A transient suppressor is normally selected according to the working peak reverse voltage (V RWM), which should be equal to or greater thanthe DC or continuous peak operating voltage level.5.V BR measured at pulse test current I T at an ambient temperature of 25°C.6.Surge current waveform per Figure 2 and derate per Figure 3 of the General Data − 600 Watt at the beginning of this group.7.Bias Voltage = 0 V, F = 1 MHz, T J = 25°C*The “G’’ suffix indicates Pb−Free package available. Please refer back to Ordering Information on front page.P , P E A K P O W E R (k W )P 1101000.1t, TIME (ms)Figure 2. Pulse WaveformTYPICAL PROTECTION CIRCUITFigure 3. Pulse Derating CurveP E A K P U L S E D E R A T I N G I N % O F P E A K P O W E R O R C U R R E N T @ T A = 25C°T A , AMBIENT TEMPERATURE (°C)Figure 4. Typical Junction Capacitance vs. BiasVoltageBIAS VOLTAGE (VOLTS)110100C , C A P A C I T A N C E (p F )APPLICATION NOTESRESPONSE TIMEIn most applications, the transient suppressor device is placed in parallel with the equipment or component to be protected. In this situation, there is a time delay associated with the capacitance of the device and an overshoot condition associated with the inductance of the device and the inductance of the connection method. The capacitive effect is of minor importance in the parallel protection scheme because it only produces a time delay in the transition from the operating voltage to the clamp voltage as shown in Figure 4.The inductive effects in the device are due to actual turn-on time (time required for the device to go from zero current to full current) and lead inductance. This inductive effect produces an overshoot in the voltage across the equipment or component being protected as shown in Figure 5. Minimizing this overshoot is very important in the application, since the main purpose for adding a transient suppressor is to clamp voltage spikes. The SMB series have a very good response time, typically < 1 ns and negligible inductance. However, external inductive effects could produce unacceptable overshoot. Proper circuit layout, minimum lead lengths and placing the suppressor device as close as possible to the equipment or components to be protected will minimize this overshoot. Some input impedance represented by Z in is essential to prevent overstress of the protection device. This impedance should be as high as possible, without restricting the circuit operation.DUTY CYCLE DERATINGThe data of Figure 1 applies for non-repetitive conditions and at a lead temperature of 25°C. If the duty cycle increases, the peak power must be reduced as indicated by the curves of Figure 6. A verage power must be derated as the lead or ambient temperature rises above 25°C. The average power derating curve normally given on data sheets may be normalized and used for this purpose.At first glance the derating curves of Figure 6 appear to be in error as the 10 ms pulse has a higher derating factor than the 10 m s pulse. However, when the derating factor for a given pulse of Figure 6 is multiplied by the peak power value of Figure 1 for the same pulse, the results follow the expected trend.VFigure 5. Figure 6.Figure 7. Typical Derating Factor for Duty CycleD E R A T I N GF A C T O R10.70.50.30.050.10.010.020.030.07D, DUTY CYCLE (%)UL RECOGNITIONThe entire series has Underwriters Laboratory Recognition for the classification of protectors (QVGV2)under the UL standard for safety 497B and File #116110.Many competitors only have one or two devices recognized or have recognition in a non-protective category. Some competitors have no recognition at all. With the UL497B recognition, our parts successfully passed several testsincluding Strike V oltage Breakdown test, Endurance Conditioning, Temperature test, Dielectric V oltage-Withstand test, Discharge test and several more.Whereas, some competitors have only passed a flammability test for the package material, we have been recognized for much more to be included in their Protector category.PACKAGE DIMENSIONSSMBDO−214AACASE 403A−03ISSUE F*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.SURMETIC is a trademark of Semiconductor Components Industries, LLC.ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。

39K100资料

Device 39K30 39K50 39K100 39K165 39K200
Notes: 3. Speed bins shown here are for commercial operating range. Please refer to Delta39K ordering information on industrial-range speed bins on page 38. 4. Self-boot solution integrates the boot PROM (flash memory) with Delta39K die inside the same package. This flash memory can endure at least 10,000 programming/erase cycles and can retain data for at least 100 years.
PIM
LB 5 LB 4
Cluster RAM
Channel RAM
LB 2 LB 3
Cluster RAM
PIM
LB 5 LB 4
Cluster RAM
Channel RAM
LB 2 LB 3
Cluster RAM
PIM
LB 5 LB 4
Cluster RAM
Channel RAM
GCLK[3:0] 4 4 4 4
元器件交易网
Delta39K™ ISR™
CPLD Family CPLDs at FPGA Densities™
Features
• High density — 30K to 200K usable gates — 512 to 3072 macrocells — 136 to 428 maximum I/O pins — Twelve dedicated inputs including four clock pins, four global I/O control signal pins and four JTAG interface pins for boundary scan and reconfigurability Embedded memory — 80K to 480K bits embedded SRAM • 16K to 96K bits of (dual-port) channel memory High speed – 233-MHz in-system operation AnyVolt™ interface — 3.3V, 2.5V,1.8V, and 1.5V I/O capability Low-power operation — 0.18-mm six-layer metal SRAM-based logic process — Full-CMOS implementation of product term array — Standby current as low as 5mA • Simple timing model — No penalty for using full 16 product terms/macrocell — No delay for single product term steering or sharing • Flexible clocking — Spread Aware™ PLL drives all four clock networks • Allows 0.6% spread spectrum input clocks • Several multiply, divide and phase shift options — Four synchronous clock networks per device — Locally generated product term clock — Clock polarity control at each register • Carry-chain logic for fast and efficient arithmetic operations • Multiple I/O standards supported — LVCMOS (3.3/3.0/2.5/1.8V), LVTTL, 3.3V PCI, SSTL2 (I-II), SSTL3 (I-II), HSTL (I-IV), and GTL+ • Compatible with NOBL™, ZBT™, and QDR™ SRAMs • Programmable slew rate control on each I/O pin • User-programmable Bus Hold capability on each I/O pin • Fully 3.3V PCI-compliant (to 66-MHz 64-bit PCI spec, rev. 2.2) • CompactPCI hot swap ready • Multiple package/pinout offering across all densities — 208 to 676 pins in PQFP, BGA, and FBGA packages — Simplifies design migration across density — Self-Boot™ solution in BGA and FBGA packages • In-System Reprogrammable™ (ISR™) — JTAG-compliant on-board programming — Design changes do not cause pinout changes • IEEE1149.1 JTAG boundary scan