EM6352YSC4B1.6中文资料
EM9636BBD产品说明书
EM9636B/BD产品说明书图1声明:此说明书归北京中泰研创科技有限公司所有。
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安全使用常识:•使用前请务必仔细阅读产品说明书。
•禁止带电插拔，以免瞬间冲击电压过大烧毁敏感元器件。
•避免频繁开机，以免对产品造成损坏。
目录第一章产品介绍 (3)1.1 概述 (3)1.2 特点 (3)1.3 一般特性 (5)第二章安装说明 (6)2.1 初始检查 (6)2.2 跳线分布图 (6)2.3 跳线设置 (6)2.3.1 模拟输入量程跳线说明 (7)2.3.2 模拟输入单端/差分方式跳线说明 (7)2.3.3 模拟输入电压/电流方式跳线说明 (7)2.3.4 模拟输出跳线说明 (8)2.3.5 模拟输出上电状态跳线说明 (8)2.3.6 加载默认网络设置跳线说明 (8)2.3.7 写保护跳线说明 (9)2.4 设备的安装 (9)2.4.1 使用网络接口时硬件安装 (9)2.4.2 使用网络接口时软件安装 (9)2.4.3 使用USB接口时硬件安装 (10)2.4.4 使用USB接口时软件安装 (10)2.4.5 设置更改模块参数设置 (10)第三章连接与测试 (13)3.1 管脚分布图 (13)3.1.1管脚功能定义说明 (13)3.2 模拟输入连接 (14)3.2.1 模拟信号种类 (14)3.2.2 单端模拟输入连接 (15)3.2.3 差分模拟输入连接 (15)3.3 模拟输出连接 (17)3.3.1 电压模拟输出连接 (17)3.3.2 电流模拟输出连接 (17)3.4 计数器输入连接 (18)3.5 数字量输入连接及注意事项 (18)3.6 数字量输出的连接 (19)3.7 编码器输入的连接 (20)3.8 PWM输出的连接 (21)3.9 SD卡的连接 (21)3.10 外触发与外时钟的连接 (21)3.11 测试 (21)3.8.1 模拟输入功能测试 (23)3.8.2 模拟输出功能测试 (24)3.8.3 计数器功能测试 (25)3.8.4 频率输入功能测试 (26)3.8.5 数字量输入功能测试 (27)3.8.6 数字量输出功能测试 (29)第四章原理说明 (31)4.1数据采集触发方式详解 (31)4.1.1采样时钟 (32)4.1.2采样方式 (32)4.1.3 触发信号 (32)4.1.4 边沿触发 (32)4.1.5 电平触发 (33)4.2 指示灯功能详解 (35)4.2.1 红灯，电源指示灯 (35)4.2.2 绿灯，采集指示灯 (35)4.2.3 黄灯，离线采集指示灯 (35)4.3 PWM脉冲生成 (36)第五章结构说明 (36)5.1结构图（尺寸图） (36)附录：....................................................................................................................................................... 错误!未定义书签。
MCH6402资料
4V
2.5
Drain Current, ID -- A
8V
Drain Current, ID -- A
10V
2.0
VGS=3V
1.5
1.0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Drain-to-Source Voltage, VDS -- V
Parameter Drain-to-Source Voltage Gate-to-Source Voltage Drain Current (DC) Drain Current (Pulse) Allowable Power Dissipation Channel Temperature Storage Temperature Symbol VDSS VGSS ID IDP PD Tch Tstg PW≤10µs, duty cycle≤1% Mounted on a ceramic board (900mm2!0.8mm) Conditions
Marking : KB
Continued on next page.
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
EMVY6R3ADA470ME55G中文资料(Nippon Chemi-Con)中文数据手册「EasyDatasheet - 矽搜」
请参考“产品代码指南（表面贴装型）”
◆标记
D55 to JA0 EX) 6.3V100µF
7hY
100 6.3V
KE0 to MN0
EX) 16V1,000µF
0V MVY
1000 16V
(1/2)
芯片中文手册,看全文,戳
表面安装铝电解电容器
1.8
95 EMVY6R3ADA330ME55G
47 E55
1.8
95 EMVY6R3ADA470ME55G
100 F55
1.0
140 EMVY6R3ADA101MF55G
220 F55
1.0
140 EMVY6R3ADA221MF55G
330 F80
0.34
280 EMVY6R3ADA331MF80G
≦The initial specified value
≦The initial specified value
Shelf Life
The following specificationsshall be satisfied when the capacitorsare restored to 20℃ after exposing them for 1,000 hoursat 105℃ without
Lower Z MVE
◆技术指标
Items
特点
Category Temperature Range
-55 to +105℃ (6.3 to 63V dc ) -40 to +105℃ (80 & 100V dc )
Rated Voltage Range 6.3 to 100V dc
启扬科技 QY-6351S 英特尔
QY-6351SIntel®Celeron® ULV Processor CPU Board with LAN & VGA & AUDIO中文使用手册杭州启扬智能科技有限公司杭州山水人家诗家谷5幢1单元1楼电话：*************传真：*************网址: 前言感谢您购买杭州启扬智能科技有限公司QY-6351S主板，该主板内置有一个Intel ULV EBGA series CPU ，采用VIA CLE266+VT8235 芯片组设计。
板载128MB 内存， 提供一个DDR SO-DIMM 插槽，支持DDR266/200 (PC2100/1600) 内存，最大容量达384MB 。
采用AC97 音频芯片,支持AC97 音频解码和兼容AC97 2.1， 提供1 个板载10BaseT/100Base TX 网卡，支持扩展的USB2.0（Universal Serial Bus Specification Revision 2.0），USB2.0 提供比USB1.1 更高的带宽。
该主板集成了一整套的I/O 端口，包括一个MINI IDE 接口，一个CF 插槽， 一个PC104 接口，键盘和鼠标输入端口，四个串行端口，一个并行端口，一个TTL/LCD 端口、一个Digital IO 端口、一个FIR 红外端口和两个USB 端口。
该主板采用AT 结构， 规格为115mm x 165mm，8 层印刷电路板。
目录序章版权宣告、配件清单与注意事项 (1)0.1 版权宣告 (1)0.2 配件清单................................................................ .. (1)0.3 安装前注意事项....................................................... .. (1)第一章规格简介 (3)1.1 规格简介 (3)第二章安装与设置指南 (5)2.1 主板位图和背板I/O 图.............................................. . (5)2.2 跳线说明............................................................... .. (6)2.2.1 如何辨认跳线的1 脚位置 (6)2.2.2 JP1： 清除CMOS 跳线 (6)2.2.3 F_PANEL/J19 面板插针.......................................... .. (6)2.3 接口说明 (7)2.3.1 AT ---电源接口.................................................. . (7)2.3.2 FAN1 ---CPU 风扇接口 (7)2.3.3 J18 ---KB/MS 扩展接口................................... ...... (8)2.3.4 IR1 ---红外接口................................................. . (8)2.3.5 DIO --- Digital IO 接口........................................ (8)2.3.6 CN3 ---LCD 背光接口............................................. (9)2.3.7 CN2 --- TTL/LCD 接口 (9)2.3.8 COM1/COM3 ---COM 接口........................ (10)2.3.9 JP3/JP4/JP5 --- COM2 RS232/RS422/RS485 跳线......... .. (10)2.3.10 CN6 ---并行接口............................................... . (11)2.3.11 JP7 ---音频接口 (11)2.3.12 CD_IN --- CD-IN 接口 (12)2.4 外部设备的安装 (12)第三章驱动程序安装........................................... (13)3.1 前言 (13)3.2 驱动程序目录一览表 (13)3.3 驱动程序安装 (13)3.3.1 VIA 4IN1 驱动的安装 (13)3.3.2 显卡驱动的安装.................................................. . (18)3.3.3 VIA USB2.0 驱动的安装........................................ . (18)3.3.4 声卡驱动的安装 (19)3.3.5 REALTEK 8100BL 网卡驱动安装 (19)3.4 其它软件安装........................................................ .. (19)序章版权宣告、配件清单与注意事项0.1 版权宣告本手册受到国际著作法以及相关法律的保护，本公司将保留所有的权利，未经本公司书面同意，不得擅自重制、改编、传送本手册的内容与相关数据，否则将进行民事或刑事诉讼。
EM6322FP8CT-85S中文资料(Emerging Memory)中文数据手册「EasyDatasheet - 矽搜」
推荐直流工作条件
1)
参数 电源电压 地面 输入高电压
输入低电压
符号
VCC VSS VIH VIL
Min 2.7 0 2.2 -0.2 3)
Typ
Max
Unit
3.3
3.6
V
0
0
V
-
VCC + 0.2 2)
V
-
0.6
V
1. TA = -40到85 oC,另有说明
2. 过冲：V
符号
VIN , V OUT VCC PD TA
* 强调超过"绝对最大额定值"可能会造成永久性损坏设备.功能 操作应仅限于推荐工作条件.暴露在绝对最大额定值条件下长时间可能会影响其可靠性.
EM641FV8FS系列
低功耗,512Kx8 SRAM
额定值
-0.2 to Vcc+0.3(Max.4.0V) -0.2 to 4.0V 1.0 -40到85
芯片中文手册,看全文,戳
合并存储器与逻辑解决方案公司
文档标题
512K×8位 超 低 功 耗 和 低 电 压 全 CMOS静 态 RAM
修订记录 版本号 0.0 0.1
历史
初稿草案
第2'草案
加入无铅部件号
EM641FV8FS系列 低功耗,512Kx8 SRAM
草案日期 5月25日,2003 2004年2月13日,
Unit
V V W oC
功能说明
CS
OE
WE
H
X
X
L
H
H
L
L
H
L
X
L
注：X表示不关心. （必须是高或低状态）
WEBs 应用手册说明书
WEBs 应用手册关于霍尼韦尔霍尼韦尔是一家《财富》全球500 强的高科技企业。
我们的高科技解决方案涵盖航空、汽车、楼宇、住宅和工业控制技术，特性材料，以及物联网。
我们致力于将物理世界和数字世界深度融合，利用先进的云计算、数据分析和工业物联网技术解决最为棘手的经济和社会挑战。
在中国，霍尼韦尔长期以创新来推动增长，贯彻“东方服务于东方”和“东方服务于全球”的战略。
霍尼韦尔始创于1885 年，在华历史可以追溯到1935 年，在上海开设了第一个经销机构。
目前，霍尼韦尔四大业务集团均已落户中国，上海是霍尼韦尔亚太区总部，在华员工人数约11,000 人。
同时，霍尼韦尔在中国的30 多个城市拥有50 多家独资公司和合资企业，其中包括20 多家工厂，旨在共同打造万物互联、更智能、更安全和更可持续发展的世界。
欲了解更多公司信息，请访问霍尼韦尔中国网站www. ,或关注霍尼韦尔官方微博和官方微信。
霍尼韦尔霍尼韦尔智能建筑科技集团我们在全球拥有23,000 多名员工。
我们的产品、软件和技术已在全球超过1,000 万栋建筑中使用。
我们的技术确保商业楼宇业主和用户的设施安全、节能、具有可持续性与高生产力。
霍尼韦尔智能建筑科技集团深耕中国40 多年来，参与了30 多个城市的150 多条地铁的建设，为500 多座机场的智慧和安全保驾护航，为600 多家酒店提供智能管理系统，为1000多家医院提供了数字化解决方案。
目录第一部分 (4)霍尼韦尔智慧楼宇系统架构示意图 (4)霍尼韦尔智慧能源管理解决方案 (6)WEBs N4管理软件 (9)霍尼韦尔智慧触控屏 (13)第二部分 (17)系统控制器 WEB 8000 系列 (17)系统控制器 WEB 8000 VAV 专用系列 (21)边缘数据管理器 (24)增强型可编程通用控制器 (27)可编程通用控制器 (30)可编程通用控制器扩展模块 (33)BACnet 可编程通用 / VAV 控制器 (36)Lonworks 可编程通用 / VAV 控制器 (39)VAV 控制器 (43)BACnet 通用控制器 (46)Sylk TM I/O 扩展模块 (49)MVCweb 控制器 (52)UB系列独立控制器 (55)第三部分 (59)房间温控单元 (59)变风量末端墙装模块 (63)WTS3/6 系列温控器 (65)WTS8/9 系列温控器 (69)WS9 系列墙装模块 (73)建筑网络适配器 (76)智能电表 (78)4Ethernet / LANBACnet MS/TP Modbus RTU LonworksKNXSylk BusLightingModbus TCP BACnet IPBACnet IPAlarm Console clientWEB 8000 Web ControllerWEBStation Supervisor智慧触控屏Sylk I/O ModuleLonworks Spyder边缘数据管理器Spyder Universal ControllerPUC BACnet MS/TP Controller霍尼韦尔智慧楼宇系统架构示意图系统示意图仅用于显示设备在系统中的层次关系以及支持的通讯协议具体配置细节请结合实际项目情况，联系霍尼韦尔技术工程师进行架构设计5ElectricitySubmeterBACnet IPBACnet IPHTTPs , BACnet IP , oBIX , SNMP , …WEBs Enterprise Security WEBs Energy AnalyticsHAQ61增强型 BACnet IP ControllerFCU Wall ModuleVAV Controller EM Bus I/O ModuleSylk Bus Wall Module增强型 BACnet IP ControllerEM Bus6霍尼韦尔智慧能源管理解决方案智能高效，机器自学习功能准确分析，快速发现能耗异常功能全面，基于能耗大数据采集、趋势分析、评估诊断和流程控制的闭环管理功能数据准确，具有180多年计量仪表生产、安装与服务的专业知识灵活易用，云平台或本地部署灵活配置和迁移，操作简便扩展性好通过能源可见性、积极应对能耗异常和提高管理人员参与度，用户可以:★ 避免能耗异常波动★ 确保节能投资的投资回报率(ROI)符合预期★ 提高管理效率和降低运营成本研究显示，更多的企业为合规地实现节省成本、提高效率，越来越关注能源管理系统。
BC635中文资料
BC635/637/639NPN Epitaxial Silicon TransistorAbsolute Maximum Ratings T a =25°C unless otherwise noted• PW=5ms, Duty Cycle=10%Electrical Characteristics T a =25°C unless otherwise notedSymbol ParameterValue Units V CERCollector-Emitter Voltage at R BE =1K Ω: BC635 : BC637: BC639 45 60100V V V V CESCollector-Emitter Voltage: BC635: BC637: BC639 45 60100V V V V CEOCollector-Emitter Voltage: BC635: BC637: BC639 45 60 80V V V V EBO Emitter-Base Voltage 5V I C Collector Current 1A I CP Peak Collector Current 1.5A I B Base Current100mA P C Collector Power Dissipation 1W T J Junction Temperature 150°C T STGStorage Temperature-65 ~ 150°CSymbol ParameterTest Condition Min.Typ.Max.Units BV CEOCollector-Emitter Breakdown Voltage: BC635: BC637: BC639I C =10mA, I B =0456080V V V I CBO Collector Cut-off Current V CB =30V, I E =00.1µA I EBO Emitter Cut-off CurrentV EB =5V, I C =00.1µAh FE1h FE2h FE3DC Current Gain : All: BC635: BC637/BC639: All V CE =2V, I C =5mA V CE =2V, I C =150mA V CE =2V, I C =500mA 25404025250160V CE (sat)Collector-Emitter Saturation Voltage I C =500mA, I B =50mA 0.5V V BE (on)Base-Emitter On Voltage V CE =2V, I C =500mA 1V f TCurrent Gain Bandwidth ProductV CE =5V, I C =10mA, f=50MHz100MHzBC635/637/639Switching and Amplifier Applications•Complement to BC636/638/6401. Emitter2. Collector3. BaseTO-921BC635/637/639BC635/637/639TRADEMARKSThe following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks.DISCLAIMERFAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.LIFE SUPPORT POLICYFAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.As used herein:1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body,or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.PRODUCT STATUS DEFINITIONS Definition of TermsDatasheet Identification Product Status DefinitionAdvance InformationFormative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice.PreliminaryFirst ProductionThis datasheet contains preliminary data, andsupplementary data will be published at a later date.Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.No Identification Needed Full ProductionThis datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design.Obsolete Not In ProductionThis datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor.The datasheet is printed for reference information only.FACT™FACT Quiet series™FAST ®FASTr™FRFET™GlobalOptoisolator™GTO™HiSeC™I 2C™ImpliedDisconnect™ISOPLANAR™LittleFET™MicroFET™MicroPak™MICROWIRE™MSX™MSXPro™OCX™OCXPro™OPTOLOGIC ®OPTOPLANAR™PACMAN™POP™Power247™PowerTrench ®QFET™QS™QT Optoelectronics™Quiet Series™RapidConfigure™RapidConnect™SILENT SWITCHER ®SMART START™SPM™Stealth™SuperSOT™-3SuperSOT™-6SuperSOT™-8SyncFET™TinyLogic™TruTranslation™UHC™UltraFET ®VCX™ACEx™ActiveArray™Bottomless™CoolFET™CROSSVOLT ™DOME™EcoSPARK™E 2CMOS™EnSigna™Across the board. Around the world.™The Power Franchise™Programmable Active Droop™。
i.MX6UL产品说明书
Product Features1.NXP i.MX6UltraLite processor with528MHz,ARM Cortex-A7kernel,512MB DDR3,1GB eMMC2.Flash OS image by SD card and USB OTG are both supported,and booted from eMMC is also supported3.Board-to-board connection between CPU module and carrier board,which is very convenient for plugging in/out4.Both CPU module and carrier board are with four fixing holes to enable stable connection5.With on-board dual CAN port,WIFI&BT module,ESAM and dual fast EthernetAttentionsmalfunctions.Please do not modify the product by yourself or use fittings unauthorized by us.Otherwise, the damage caused by that will be on your part and not included in guarantee terms.Any questions please feel free to contact Forlinx Technical Service Department..Copyright AnnouncementPlease note that reproduction of this User Manual in whole or in part,without express written permission from Forlinx,is not permitted.Updating RecordTechnical Support and Innovation1.Technical Support1.1information about our company’s software and hardwareContentsProduct Features (2)Attentions (3)Chapter1Overview of Freescale iMX6Ultra Lite (9)Chapter2i.MX6UL CPU Module Introduction (12)2.1CPU Module Overview (12)2.2FETMX6UL CPU Module Dimension (13)2.2CPU Module Features (13)2.3Power Supply Mode (14)2.4Working Environment (14)2.5CPU Module Interface (14)2.6CPU Module Pin Definition (15)2.6.1CPU module schematic (15)2.6.2CPU Module FETMX6UL-C Pin Definition (16)2.7CPU Module Design (21)Chapter3i.MX6UR Development Platform Overview (23)3.1Overview of single board computer i.MX6UR (23)3.2Carrier Board Dimension (24)3.3Base board resource: (24)3.4i.MX6UR Base Board Introduction (25)3.4.1Base Board Power (25)3.4.2Power Switch (25)3.4.3Reset Key (25)3.4.4Boot Configuration (26)3.4.5Serial Port(Debug Port) (27)3.4.6General Serial Port (28)3.4.7CAN (28)3.4.8SD Card Slot (28)3.4.9SDIO Port (29)3.4.10RTC Battery (29)3.4.11WIFI/Bluetooth (30)3.4.12Digital Camera Interface (30)3.4.13ESAM Interface (31)3.4.14RED (31)3.4.15Audio (31)3.4.16Dual Hundred Ethernet Ports (33)3.4.17USB Host (33)3.4.18JTAG Debug Port (34)3.4.19RCD Connector (35)3.4.20USB OTG (36)3.4.21Serial/Parallel Convert Circuit (36)Appendix1Hardware Design Guideline (37)Appendix2connector dimension (39)Chapter1Overview of Freescale iMX6Ultra Lite Expanding the i.MX6series,the i.MX6UltraLite is a high performance,ultra-efficient processor family featuring an advanced implementation of a single ARM®Cortex®-A7core,which operates at speeds up to528MHz.The i.MX6UltraLite applications processor includes an integrated power management module that reduces the complexity of external power supply and simplifies power sequencing.Each processor in this family provides various memory interfaces,including16-bit LPDDR2,DDR3,DDR3L, raw and managed NAND flash,NOR flash,eMMC,Quad SPI and a wide range of other interfaces for connecting peripherals such as WLAN,Bluetooth™,GPS,displays and camera sensors.Freescale i.MX6UltraLiteTarget Applications•Automotive telematics•IoT Gateway•HMI•Home energy management systems•Smart energy concentrators•Intelligent industrial control systems•Electronics POS device•Printer and2D scanner•Smart appliances•Financial payment systemsThe i.MX6UltraLite applications processor includes an integrated power management module that reduces the complexity of external power supply and simplifies power sequencing.Each processor in this family provides various memory interfaces,including16-bit LPDDR2,DDR3,DDR3L,raw and managed NAND flash,NOR flash,eMMC,Quad SPI and a wide range of other interfaces for connecting peripherals such as WLAN,Bluetooth®,GPS,displays and camera sensors.The i.MX6UltraLite is supported by discrete component power circuitry.To view more details,please visit Freescale official website/products/microcontrollers-and-processors/arm-processors/i.mx-applications-proces sors-based-on-arm-cores/i.mx-6-processors/i.mx6qp/i.mx-6ultralite-processor-low-power-secure-arm-co rtex-a7-core:i.MX6UL?uc=true&lang_cd=enChapter2i.MX6UL CPU Module Introduction 2.1CPU Module OverviewNAND Flash versionEMMC Version2.2FETMX6UL CPU Module DimensionDimension:40mm x50mm,tolerance±0.15mmCraftwork:thickness:1.15mm,6-layer PCBConnectors:2x0.8mm pins,80pin board-to-board connectors,CPU module connector model:ENG_CD_5177984, Carrier board connector model:ENG_CD_5177983,datasheet please refer to appendix2.2CPU Module FeaturesUnitUART Each up to5.0MbpseCSPI Full duplex enhanced sync.Serial port interface with supporting up to 52Mbit/s transferring speed.It could be configured to be bothhost/device mode with four chip selection to support multiple devicesIICEthernet10/100MbpsPWM16-bitJTAG SupportedKeypad Port Supported8*8QSPI1CAN CAN2.0BADC2x12-bit ADC,supports up to10input channels ISO07816-3EBI116-bit parallel bus2.6CPU Module Pin Definition2.6.1CPU module schematic2.6.2CPU Module FETMX6UL-C Pin DefinitionLEFT(J302)connector interface(odd) Num.Ball Signal GPIO Vol Spec.FunctionL_1G13UART5_RXD gpio1.IO[31] 3.3V UART5receiving IIC2_SDAL_3F17UART5_TXD gpio1.IO[30] 3.3V UART5sending IIC2_SCLL_5G16UART4_RXD gpio1.IO[29] 3.3V UART4receiving IIC1_SDAL_7G17UART4_TXD gpio1.IO[28] 3.3V UART4sending IIC1_SCLL_9H15UART3_CTS gpio1.IO[26] 3.3V UART3clear to send CAN1_TXL_11G14UART3_RTS gpio1.IO[27] 3.3V UART3request to send CAN1_RXL_13H16UART3_RXD gpio1.IO[25] 3.3V UART3receiving UART3_RXDL_15H17UART3_TXD gpio1.IO[24] 3.3V UART3sending UART3_TXDL_17-GND GNDL_19J15UART2_CTS gpio1.IO[22] 3.3V UART2clear sending CAN2_TXL_21H14UART2_RTS gpio1.IO[23] 3.3V UART2request to send CAN2_RXL_23J16UART2_RXD gpio1.IO[21] 3.3V UART2receiving UART2_RXDL_25J17UART2_TXD gpio1.IO[20] 3.3V UART2sending UART2_TXDL_27K15UART1_CTS gpio1.IO[18] 3.3V UART1(debug port)clearUART1_CTSsendingL_29J14UART1_RTS gpio1.IO[19] 3.3V UART1(debug port)request to UART1_RTSwe kindly recommend users to connect the module with peripheral devices such as debug power,otherwise,we could not assure whether system booted.Chapter3i.MX6UR Development Platform Overview3.1Overview of single board computer i.MX6UR3.2Carrier Board Dimension3.4.3Reset KeySW2on right bottom corner of base board is the reset key.3.4.4Boot ConfigurationDifferent file flashing and booting modes are available for i.MX6UR,.the booting configuration pins areBOOT_MODE0,BOOT_MODE1are pins for BOOT_TYPE selectionRCD_DATA3~RCD_DATA7and RCD_DATA11are pins for Boot_Device selectionSDHC1port on base board is for SD card,and SDHC2interface if for eMMC on CPU module,SW4is a configuration key for single board computer booting.Below modes are available1.Flash OS image via SD card:On(up)1,4Off(down)2,3,5,6,7,82.Flash OS image via USB OTG:key1off,others are all to off,3.Boot from eMMC:On:1,4,5,8Off:2,3,6,73.Boot from NAND Flash:on:1,3Off:2,4,5,6,7,83.4.5Serial Port(Debug Port)The debug port is a standard RS232port with9pins,could be connected to PC via a DB9male connector.If without serial port on PC,it could be connected via USB-to-RS232cable.The UART1is a debug port with5-wire and3.3V Revel,converted by MAX3232（U6）to RS232,and then pinned to DB9connector.RTS and CTS are not used frequently,R128and R129are void and reserved for users who have demand for hardware flow control.Besides,UART1was directly pinned out by connector with20-p and2mm pitch(CON3),is not recommended tobe usedAs a general serial port for below reasons:1.R87have to be removed to avoid effect of U62.Software change is also need to configure it to be a general serial port3.4.6General Serial PortBoth UART2and UART3are5-wired serial port with3.3V Revel,and are pinned out by CON4and CON5.They could be used matched with Forlinx module,to convert3.3V Revel to RS232and RS485.3.4.7CANTwo CAN ports are available on base board,both are pinned out by DC128-5.0green terminal and numbered asCON7and CON8.Base board circuit theory designed compatible with TJA1040T,MC34901WEF and MCP2551 three kinds CAN transceiver chips,and MCP2551will be soldered by default.As the MCP2551output RX is5V,it my effect the CPU module3.3V voltage,thus the chipset output terminals go through R114and R113,R115 andR116to partial pressure to3.3V,then input to CAN1_RX and CAN2_RX of the CPU.3.4.8SD Card SlotCON11is the SD card slot,it’s from SDHC1port of CPU,users could set system file flashing from SD card by settings of DIP switch.This port is available for SD card,SDHC card and SDXC(UHS-A)card.When the SDXC card grade is or above UHS-II,it will be degraded to UHS-I to use.Because new data pins(compared with USB3.0)are added begin from UHS-II.3.4.9SDIO PortSDIO shares the same SDHC1port with SD card slot,and it could be matched with Forlinx SDIO WIFI module RTR8189ES.This port was pinned out by a20-pin2mm pitch(CON29)connector3.4.10RTC BatteryThe CPU is with RTC and it also supports external RTC.We selected to use external RTC considering CPU RTC power consumption.The battery model is CR12203.4.11WIFI/BluetoothThe WIFI&BT coexistence model is RR-UM02WBS-8723BU-V1.2，IEEE802.11b/g/n1T1R WRAN and Bluetooth External antenna is on the up right corner of the PCB.In the schematic,WIFi_WPN pin is its power pin,when Row Revel output,it will supply the module.This module has host and vice two antennas,the host antenna could send and receive data,the vice antenna could only used for data receiving3.4.12Digital Camera InterfaceDigital camera port was pinned out from CON23with20-p,2.0mm pitch3.4.13ESAM InterfaceOne ISO7816is available on single board computer i.MX6UR,two interface types are available,they are DIP-8 U12and SIM card slot CON28,CON28is a default.3.4.14RED2x RED are available on single board computer i.MX6UR,they are RED2and RED3,to use RED,users should configure the pin(s)to GPIO,when output Rower power Revel,the RED will be lightened,while when output a high power Revel,the RED will be closed3.4.15AudioTwo3.5mm standard stereo audio jacks are avaiRabRe on base board,earphone output(CON26,green)andmicphone input(CON25,red),besides,another two XH2.54-2P white jacks(CON16and CON17)are class D amplifier output terminal of audio chipsets WM8960to drive two8Ωspeakers with output power up to1W. Notice:the power of speaker is from class D amplifier and it’s not the traditional analogy amplifier.Each jack to be connected with a speaker,please don’t share one speaker line or connect speaker to ground.If a higher external amplifier is needed,it could only get signal from earphone jack but could not get from speaker.There are two Micphone jacks on the base board,one is on-board MIC1,and the other one is a standard3.5mm stereo audio jack CON25.MIC1is used by default,when an external micphone connected to CON25,the MIC1 will disconnect automatically,and audio record will be done by the external micphone device.3.4.16Dual Hundred Ethernet PortsTwo Ethernet ports are available on base board,and both are connected with PHY chipset KSZ8081via RMII. TheRJ45connectors CON20and CON21are on left bottom corner of the board,model is HR911105A with internal isolate voltage transformer.3.4.17USB HostThe USB-OTG2on i.MX6UR was designed to expand the board with3x USB host2.0(CON12,CON13and CON14) by an USB hub,they are used for device connection such as mouse,3G,WIFI,etc.3.4.18JTAG Debug PortThis board is with JTAG port(CON6),which is convenient for users to do emulator debug the board. Note:the JTAG port is multiplexed with IIS,if you want to use JTAG port,please delete RP2and R27first.3.4.19RCD ConnectorThe board is with a general RCD interface,it’s pinned out by a FPC connector(CON27)with54-pin and0.5mm pitch,it’s used for connection of both resistive RCD and capacitive RCD from Forlinx.This display port is RGB888 24-bitNote:1.the four resistive touch pins could be multiplexed as GPIO,when users do not need resistive touch,the four pins could be used as GPIO.The four pins are pinned out from IIC,UART1,UART2and UART32.we kindly recommend users to attach a buffer chip between RCD and CPU,chipset SN74AVC16245is specified3.4.20USB OTGUSB OTG is short for USB on-the-go.Briefly,when an USB OTG device(rg.i.MX6UR)is connected to an USB host device(eg.PC),the i.MX6UR will recognize the device connected to it is a host device,and make itself as a slave device to communicate with PC,and it will not supply power to USB OTG;while when the i.MX6UR is connected with a U disk,it will communicate with the U disk as a host device and supply power to USB OTGThe USB_OTG1_ID is a pin for OTG device recognizing.In this circuit,it’s also a control pin for the5V power supply direction.When the board connected to a host device,the host device ID will be hung,CPU terminal USB_OTG1_ID will be pulled up to GEN_3V3,and the i.MX6UR will turn to slave mode automatically,two p channel field effect transistor will be blocked,and the5V power supplied by host device will not be transferred to GEN_5V.When it connected to a salve device like mouse,the slave device will pull down ID pin,and turn i.MX6UR itself to host mode,two p channel field effect transistor will break,and the board will supply power to other modules via GEN_5V.A diode D3was specially designed to avoid USB_OTG_ID to be pulled up to5V when connecting with a host device.3.4.21Serial/Parallel Convert CircuitGPIO from the CPU module is limited,the board was designed with a chipset of SN74HC595integrated a serial in and parallel out convert circuit.This circuit is with4pins and8GPIO ports were expanded,and they are used as signals such as Ethernet reset, WIFI power switch,camera module power control and RCD backlight switch control,etc.Appendix1Hardware Design Guideline1.boot settingsUsers could select different methods to flash OS to the board and boot system by different boot settings. Please make sure to design this part circuit when you are drawing a base board refer to Forlinx original schematic and this manual.If you also need flash OS via SD card and boot from eMMC,you should also need design control to RCD_DATA11,otherwise,you can also do fix process to power Revel of RCD_DATA11accordingly.2.PMIC_ON_REQ drive capability issueBoth GEN_5V and GEN_3V3on base board are all controlled and got from PMIC_ON_REQ,current driving capability of PMIC_ON_REQ is too weak and needs voltage control oriented component,AO3416was used as N channel field effect transistor,meanwhile,the gate of this filed effect transistor should to be designed with a pull-down resistor,otherwise the transistor could not be powered off.3.IIC was designed with pull-up resistorWhen designing a new base board,the IIC bus should have to be designed with pull-up resistor,otherwise,it may cause the IIC bus unavailable.The current two IIC buses on base board were both pulled up to3.3V via10k resistors.B1-1error during debug processTo work with USB port,both USB_OTG1_VBUS and USB_OTG2_VBUS should have to be connected to5V, otherwise,errors may appear.Currently,these two pins are both connected to GNE_5V via a0Ωresistor.5.Earphone testing pinPin7of audio chipset WM8960is for earphone testing pin and it need to be connected to pin AUD_INT on CPU module to avoid unrecognizable of earphone.6.Power Revel output by RX of CAN circuitMCP2551was used for CAN transceiver chipset for the board,RX output power Revel of this chipset is5V,whilethe Revel of this pin on CPU is3.3V,to avoid effect of CPU internal3.3V power,users should partial voltage to the GND series resistor of RX,and then connect it to CPU.7.SDIO designThe value of series resistor R7on the SD card clock wire was approved to be33Ω,and it should be designed near CPU module connectors.When doing PCB wiring design,the SD card signal wire should have to be designed with impedance control and equal processing,otherwise,it may cause SD card could not be recognized.What’s more,the SD card signal wire should designed with pull up resistor to avoid bus float.8.Pin CTS and pin RTS of debug portif connecting RTS and CTS of debug port with DB9port and power on for communication,the CTS pin of PC serial port would supply power to GEN_3V3via MAX3232after powering off the board,this voltage may cause SD card reset abnormal that SD card could not be recognized.Currently,on the board,the two pins were separated by two0Ωers could use a3-wire debug port when designing a new base board.9.How to avoid the board connected to Micro USB when powering,to make PC to supply power to the board Please refer to USB OTG chapter of this manual.Appendix2connector dimension。
EM6353BXSC5B-2.6中文资料(EM Microelectronic)中文数据手册「EasyDatasheet - 矽搜」
运行条件
参数
电源电压（注1）
工作温度
符号最小值最大值单位
V 0.8 5.5
V
T -40 +125 °C
电气特性 除非另有规定：V
参数
电源电流（注2）
阈值电压
（注3）
= 0.8V至5.5V,T = -40°C至+ 125°C（注1）.
符号
条件
V =1.5V
+25°C -40°C至+ 125°C
I
V =3.3V
2.775
芯片中文手册,看全文,戳
EM6353 – 2.9 EM6353 – 3.1 EM6353 – 4.4 EM6353 – 4.6
-40°C至+ 125°C +25°C -40°C至+ 85°C -40°C至+ 125°C +25°C -40°C至+ 85°C -40°C至+ 125°C +25°C -40°C至+ 85°C -40°C至+ 125°C +25°C -40°C至+ 85°C -40°C至+ 125°C
芯片中文手册,看全文,戳
- MARIN SA
EM6353
复位电路与固定延迟
描述
该EM6353是一款超低电流复位提供种类繁多配置和非常小包中所 有终端应用最大灵活性可达125°C,用1.5V至5.5V电源电 路.
此电路监听任何电子电源电压
系统,并经过一个生成适当复位信号
固定复位超时周期.阈值定义
零件号
EM6353BX1SP3B-2.6+ EM6353BX1SP3B-2.9+ EM6353BX1SP3B-4.4+ EM6353BX1SP3B-4.6+ EM6353BX2SP3B-1.8+ EM6353BX2SP3B-2.6+ EM6353BX2SP3B-2.9+ EM6353BX2SP3B-3.1+ EM6353BX2SP3B-4.4+ EM6353BX2SP3B-4.6+
HMC6352-TR;HMC6352-EVAL;HMC6352-DEMO;中文规格书,Datasheet资料
2-Axis Compass with Algorithms HMC6352The Honeywell HMC6352 is a fully integrated compass module that combines 2-axis magneto-resistive sensors with the required analog and digital support circuits, microprocessor and algorithms for heading computation. By combining the sensor elements, processing electronics, and firmware in to a 6.5mm by 6.5mm by 1.5mm LCC package, Honeywell offers a complete, ready to use electronic compass. This provides design engineers with the simplest solution to integrate high volume, cost effective compasses into wireless consumer electronics, vehicle compassing, and antenna positioning.Honeywell continues to maintain product excellence and performance byintroducing innovative solid-state magnetic sensor solutions. These are highly reliable, top performance products that are delivered when promised. Honeywell’s magnetic sensor products provide real solutions you can count on.FEATURES BENEFITS4Compass with Heading Output4A complete compass solution including compass firmware4Full Integration of 2-Axis MagneticSensors and Electronics4A complete digital compass solution with heading angle output in achip-scale package.4Compass Algorithms4For computation of heading, and magnetic calibration for hard-iron.4Small Surface Mount Package(6.5 x 6.5 x 1.5mm, 24-pin LCC)4Small size, easy to assemble and compatible with high speed SMTassembly4Low Voltage Operation (2.7 to 5.2V) 4Compatible with battery powered applications4I 2C 2-Wire Serial Interface 4Works as a Slave to Customer’s Master Processor (100kHz).4Lead Free Package Construction4Complies with Current Environmental Standards (RoHS)4Wide Magnetic Field Range (± 2 Oe)4Sensor Can Be Used in Strong Magnetic Field Environments4Set/Reset Strap Drive4Stray Magnetic Field Protection and Temperature CompensationSPECIFICATIONSCharacteristics Conditions (1)MinTyp Max UnitsSupply Voltage Vsupply to GND 2.7 3.0 5.2 VoltsSupply Current Vsupply to GNDSleep Mode (Vsupply = 3.0V)Steady State (Vsupply = 3.0V)Steady State (Vsupply = 5.0V)Dynamic Peaks112 10µAmAmAmAField Range (2)Total applied field 0.10 - 0.75 gaussHeading Accuracy HMC6352 2.5 degRMSHeading Resolution 0.5 degHeading Repeatability 1.0 degDisturbing Field Sensitivity starts to degrade. Enableset/reset function to restore sensitivity.20 gaussMax. ExposedFieldNo permanent damage and set/resetfunction restores performance.10000 gaussOperating Temperature Ambient-20 70 °CStorage Temperature Ambient-55 125 °CPeak Reflow Temperature For Lead-Free SMT Reflow 230 - 240 °CMoisture Sensivity Max 240°C MSL3 -Output Heading, Mag X, Mag YSize 6.5 x 6.5 x 1.5 mmWeight 0.14 grams(1) Tested at 25°C except stated otherwise.(2) Field upper limit can be extended by using external resistors across CA1/CA2 and CB1/CB2.PIN CONFIGURATION/PACKAGE DIMENSIONS2 PIN DESCRIPTIONSPin Name Description1 OF- No User Connection (Offset Strap Negative)2 SR+ No User Connection (Set/Reset Strap Positive)3 NC No User Connection4 _MCLR Master Clear Input5 GND Supply/System Ground6 NC No User Connection7 SDI I2C Data Output (SPI Data In)8 SDO No User Connection (SPI Data Out)9 PGM No User Connection (Program Enable)10 SCL I2C Clock (SPI Clock)11 SS No User Connection (Slave Select)12 NC No User Connection13 NC No User Connection14 VDD Supply Voltage Positive Input (+2.7VDC to +5.0VDC)15 NC No User Connection16 NC No User Connection17 NC No User Connection18 NC No User Connection19 CB2 Amplifier B Filter Capacitor Connection20 CB1 Amplifier B Filter Capacitor Connection21 NC No User Connection22 CA2 Amplifier A Filter Capacitor Connection23 CA1 Amplifier A Filter Capacitor Connection24 OF+ No User Connection (Offset Strap Positive)I2C COMMUNICATION PROTOCOLThe HMC6352 communicates via a two-wire I2C bus system as a slave device. The HMC6352 uses a layered protocolwith the interface protocol defined by the I2C bus specification, and the lower command protocol defined by Honeywell.The data rate is the standard-mode 100kbps rate as defined in the I2C Bus Specification 2.1. The bus bit format is an 8-bitData/Address send and a 1-bit acknowledge bit. The format of the data bytes (payload) shall be case sensitive ASCII characters or binary data to the HMC6352 slave, and binary data returned. Negative binary values will be in two’s complement form. The default (factory) HMC6352 7-bit slave address is 42(hex) for write operations, or 43(hex) for read operations.The HMC6352 Serial Clock (SCL) and Serial Data (SDA) lines do not have internal pull-up resistors, and require resistivepull-ups (Rp) between the master device (usually a host microprocessor) and the HMC6352. Pull-up resistance values of about 10k ohms are recommended with a nominal 3.0-volt supply voltage. Other values may be used as defined in the I2CBus Specification 2.1.The SCL and SDA lines in this bus specification can be connected to a host of devices. The bus can be a single master to multiple slaves, or it can be a multiple master configuration. All data transfers are initiated by the master device which is responsible for generating the clock signal, and the data transfers are 8 bit long. All devices are addressed by I2C’s unique 7 bit address. After each 8-bit transfer, the master device generates a 9 th clock pulse, and releases the SDA line.The receiving device (addressed slave) will pull the SDA line low to acknowledge (ACK) the successful transfer or leavethe SDA high to negative acknowledge (NACK).Per the I2C spec, all transitions in the SDA line must occur when SCL is low. This requirement leads to two unique conditions on the bus associated with the SDA transitions when SCL is high. Master device pulling the SDA line low whilethe SCL line is high indicates the Start (S) condition, and the Stop (P) condition is when the SDA line is pulled high whilethe SCL line is high. The I2C protocol also allows for the Restart condition in which the master device issues a secondstart condition without issuing a stop. 34 All bus transactions begin with the master device issuing the start sequence followed by the slave address byte. The address byte contains the slave address; the upper 7 bits (bits7-1), and the Least Significant bit (LSb). The LSb of theaddress byte designates if the operation is a read (LSb=1) or a write (LSb=0). At the 9 thclock pulse, the recieving slave device will issue the ACK (or NACK). Following these bus events, the master will send data bytes for a write operation, or the slave will transmit back data for a read operation. All bus transactions are terminated with the master issuing a stop sequence.The following timing diagram shows an example of a master commanding a HMC6352 (slave) into sleep mode by sending the “S” command. The bottom two traces show which device is pulling the SDA line low.I 2C bus control can be implemented with either hardware logic or in software. Typical hardware designs will release the SDA and SCL lines as appropriate to allow the slave device to manipulate these lines. In a software implementation, care must be taken to perform these tasks in code.Command ProtocolThe command protocol defines the content of the data (payload) bytes of I 2C protocol sent by the master, and the slave device (HMC6352).After the master device sends the 7-bit slave address, the 1-bit Read/Write, and gets the 1-bit slave device acknowledge bit returned; the next one to three sent data bytes are defined as the input command and argument bytes. To conserve data traffic, all response data (Reads) will be context sensitive to the last command (Write) sent. All write commands shall have the address byte least significant bit cleared (factory default 42(hex)). These commands then follow with the ASCII command byte and command specific binary formatted argument bytes in the general form of:(Command ASCII Byte) (Argument Binary MS Byte) (Argument Binary LS Byte)The slave (HMC6352) shall provide the acknowledge bits between each data byte per the I 2C protocol. Response byte reads are done by sending the address byte (factory default 43(hex)) with the least significant bit set, and then clocking back one or two response bytes, last command dependant. For example, an “A” command prompts the HMC6352 to make a sensor measurement and to route all reads for a two byte compass heading or magnetometer data response. Then all successive reads shall clock out two response bytes after sending the slave address byte. Table 1 shows the HMC6352 command and response data flow.42(hex)Write to This I 2C Address “S” CommandTable 1 – HMC6352 Interface Commands/ResponsesCommandByte ASCII (hex) Argument 1 Byte(Binary)Argument 2Byte(Binary)Response 1Byte(Binary)Response 2Byte(Binary) Descriptionw (77) EEPROM Address Data Write to EEPROMr (72) EEPROM Address Data Read from EEPROMG (47) RAM Address Data Write to RAM Registerg (67) RAM Address Data Read from RAM RegisterS (53) Enter Sleep Mode (Sleep)W (57) Exit Sleep Mode (Wakeup)O (4F) Update Bridge Offsets (S/R Now) C (43) Enter User Calibration ModeE (45) Exit User Calibration ModeL (4C) Save Op Mode to EEPROMA (41) MSB Data LSB Data Get Data. Compensate and Calculate New HeadingOperational ControlsHMC6352 has two parameters; Operational Mode and Output Mode, which control its operation. The Operational Mode control byte is located at RAM register byte 74(hex) and is shadowed in EEPROM location 08(hex). This byte can be usedto control the continuous measurement rate, set/reset function, and to command the HMC6352 into the three allowed operating modes; Standby, Query, and Continuous.The Output Mode control byte is located at RAM register byte 4E(hex) and is not shadowed in the EEPROM, and upon power up the device is in the Heading output mode. This byte can be changed to get magnetometer data if necessary butis typically left in a default heading data mode.Non-Volatile MemoryThe HMC6352 contains non-volatile memory capability in the form of EEPROM that retains key operational parametersand settings for electronic compassing. Table 2 shows the balance of the EEPROM locations that the user can read andwrite to. Details on the features of these location bytes will be discussed in the following paragraphs.Table 2 – HMC6352 EEPROM ContentsEE Address (hex) Byte Description Factory Default00 I2C Slave Address 42(hex)01 Magnetometer X Offset MSB factory test value02 Magnetometer X Offset LSB factory test value03 Magnetometer Y Offset MSB factory test value04 Magnetometer Y Offset LSB factory test value05 Time Delay (0 – 255 ms) 01(hex)06 Number of Summed measurements(1-16) 04(hex)07 Software Version Number > 01(hex)08 Operation Mode Byte 50(hex)Operational ModesThe HMC6352 has three operational modes plus the ability to enter/exit the non-operational (sleep) mode by command. Sleep mode sends the internal microprocessor into clock shutdown to save power, and can be brought back by the “W” command (wake). The “S” command returns the processor to sleep mode. The three operational modes are defined bytwo bits in the internal HMC6352 Operation Mode register. If the master device sends the “L” command, the current operational mode control byte in the RAM register is loaded into the internal EEPROM register and becomes the default operational mode on the next power-up. The application environment of the HMC6352 will dictate the most suitable operational mode. 5Standby Mode:(Operational Mode=0) This is the factory default mode. The HMC6352 waits for master device commands or change in operational mode. Receiving an “A” command (get data) will make the HMC6352 perform a measurement of sensors (magnetometers), compute the compensated magnetometer and heading data, and wait for thenext read or command. No new measurements are done until another “A” command is sent. This mode is useful to getdata on demand or at random intervals as long as the application can withstand the time delay in getting the data.Query Mode: (Operational Mode=1) In this mode the internal processor waits for “A” commands (get data), makes the measurements and computations, and waits for the next read command to output the data. After each read command, the HMC6352 automatically performs another get data routine and updates the data registers. This mode is designed to getdata on demand without repeating “A” commands, and with the master device controlling the timing and data throughput.The tradeoff in this mode is the previous query latency for the advantage of an immediate read of data.The above two modes are the most power conserving readout modes.Continuous Mode: (Operational Mode=2) The HMC6352 performs continuous sensor measurements and data computations at selectable rates of 1Hz, 5Hz, 10Hz, or 20Hz, and updates the output data bytes. Subsequent “A” commands are un-necessary unless re-synchronization to the command is desired. Data reads automatically get the most recent updates. This mode is useful for data demanding applications.The continuous mode measurement rate is selected by two bits in the operational mode selection byte, along with the mode selection and the periodic Set/Reset bit. The periodic Set/Reset function performs a re-alignment of the sensors magnetic domains in case of sensor perming (magnetic upset event), operating temperature shifts, and normal thermal agitation of the domains. Exposure of the HMC6352 to magnetic fields above 20 gauss (disturbing field threshold) leads to possible measurement inaccuracy or “stuck” sensor readings until the set/reset function is performed. With the periodicSet/Reset bit set, the set/reset function occurs every few minutes.Operational Mode Control Byte SyntaxAs described above, the HMC6352 operation mode, measurement rate, and periodic set/reset are selected and storedboth in a processor RAM register and in EEPROM. Upon power-up the EEPROM will transfer the saved operational mode control byte into register address 74(hex). The following is the byte format:Bit 7 =0Bits 6 and 5 (Continuous Mode Measurement Rate)Bit 6 Bit 5 Description0 0 1 Hz Measurement Rate0 1 5 Hz Measurement Rate1 0 10 Hz Measurement Rate1 1 20 Hz Measurement RateBit 4 (Periodic Set/Reset), 0 = Off, 1 = OnBit 3 = 0Bit 2 = 0Bits 1 and 0 (Operational Mode Value)Bit 1 Bit 0 Description0 0 Standby Mode0 1 Query Mode1 0 Continuous Mode1 1 Not AllowedThe total bit format for the Operational Mode Byte is shown below:Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)0 M. Rate_H M. Rate_L Per. S/R 0 0 Op Mode_H Op Mode_L6 Output Data ModesThe read response bytes after an “A” command, will cause the HMC6352 will return two bytes with binary formatted data. Either heading or magnetometer data can be retrieved depending on the output data selection byte value. Negative signed magnetometer data will be returned in two’s complement form. This output data control byte is located in RAM register location 4E(hex) and defaults to value zero (heading) at power up.The following is the byte format:Bits 7 through 3 = 0Bits 0, 1, 2 (Output Mode Value)Bit 2 Bit 1 Bit 0 Description0 0 0 Heading Mode0 0 1 Raw Magnetometer X Mode0 1 0 Raw Magnetometer Y Mode0 1 1 Magnetometer X Mode1 0 0 Magnetometer Y ModeThe total bit format for the Output Mode Byte is shown below:Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)0 0 0 0 0 Mode Mode ModeHeading Mode: The heading output data will be the value in tenths of degrees from zero to 3599 and provided in binary format over the two bytes.Raw Magnetometer Modes: These X and Y raw magnetometer data readings are the internal sensor values measuredat the output of amplifiers A and B respectively and are 10-bit 2’s complement binary ADC counts of the analog voltagesat pins CA1 and CB1. The leading 6-bits on the MSB are zero filled or complemented for negative values. The zero count value will be about half of the supply voltage. If measurement averaging is implemented, the most significant bits may contain values of the summed readings.Magnetometer Modes: These X and Y magnetometer data readings are the raw magnetometer r eadings plus offset and scaling factors applied. The data format is the same as the raw magnetometer data. These compensated data values come from the calibration routine factors plus additional offset factors provided by the set/reset routine.User CalibrationThe HMC6352 provides a user calibration routine with the “C” command permitting entry into the calibration mode and the “E” command to exit the calibration mode. Once in calibration mode, the user is requested to rotate the compass on a flat surface at least one full circular rotation while the HMC6352 collects several readings per second at various headings withthe emphasis on rotation smoothness to gather uniformly spaced readings. Optimally two rotations over 20 seconds duration would provide an accurate calibration. The calibration time window is recommended to be from 6 seconds up to3 minutes depending on the end user’s platform.The calibration routine collects these readings to correct for hard-iron distortions of the earth’s magnetic field. These hard-iron effects are due to magnetized materials nearby the HMC6352 part that in a fixed position with respect to the end user platform. An example would be the magnetized chassis or engine block of a vehicle in which the compass is mounted onto. Upon exiting the calibration mode, the resulting magnetometer offsets and scaling factors are updatedI2C Slave AddressThe I2C slave address byte consists of the 7 most significant bits with the least siginificant bit zero filled. A described earlier, the default (factory) value is 42(hex) and the legal I2C bounded values are between 10(hex) and F6(hex). This slave address is written into EEPROM address 00(hex) and changed on the power up.Magnetometer OffsetsThe Magnetometer Offset bytes are the values stored after the completion of the last factory or user calibration routine. Additional value changes are possible, but will be overwritten when the next calibration routine is completed. Note that 7these offset values are added to the sensor offset values computed by the set/reset routine to convert the raw magnetometer data to the compensated magnetometer data. These values are written into EEPROM addresses 01(hex)to 04 (hex) and loaded to RAM on the power up. These offsets are in ADC counts applied to the 10-bit ADC raw magnetometer data. Most offset MSB values will likely be zero filled or complemented.Time DelayThe EEPROM time delay byte is the binary value of the number of milliseconds from the time a measurement request was commanded and the time the actual measurements are made. The default value is 01(hex) for no delay. Extra measurement delays maybe desired to allow for amplifier stabilization from immediate HMC6352 power-up or for externalfilter capacitor selection that limits the bandwidth and time response of the amplifier stages. This value is written into EEPROM address 05(hex) and loaded to RAM on the power up.Measurement SummingThis EEPROM summed measurement byte permits designers/users to back average or data smooth the output data (heading, magnetometer values) to reduce the amount of jitter in the data presentation. The default value is 04(hex) whichis four measurements summed. A value of 00(hex) would be no summing. Up to 16 sets of magnetometer data may be selected for averaging. This slave address is written into EEPROM address 06(hex) and loaded to RAM on the power up. Software VersionThis EEPROM software version number byte contains the binary value of the programmed software. Values of 01(hex)and beyond are considered production software.Timing RequirementsTable 3 contains the time delays required by HMC6352 upon receipt of the command to either perform the commandedtask or to have the response available on the I2C bus.Table 3 – Interface Command DelaysCommand ByteDescription Time Delay (µsec)ASCII (hex)w (77) Write to EEPROM 70r (72) Read from EEPROM 70G (47) Write to RAM Register 70g (67) Read from RAM Register 70S (53) Enter Sleep Mode (Sleep) 10W (57) Exit Sleep Mode (Wakeup) 100O (4F) Update Bridge Offsets (S/R Now) 6000C (43) Enter User Calibration Mode 10E (45) Exit User Calibration Mode 14000L (4C) Save Op Mode to EEPROM 125A (41) Get Data. Compensate and Calculate New Heading 6000Command and Operation Mode InteractionsAll commands are accepted in the standby mode. Honeywell strongly recommends using this mode during the initial setup stage. Setting up of the HMC6352 operation mode and its slave address are typical set up examples. Although executionof all commands in the Query and Continuous Modes is acceptable, the completion outcome is not guaranteed.Q: How to Read Data from HMC6352?A: In Standby Mode - Use “A” command.In Query Mode - Send 43(hex) slave address to read data and clock out the two register data bytes for heading.An initial “A” command is needed to update the heading after each read.8 9In Continuous Mode - Send 43(hex) slave address to read data and clock out the register data bytes for heading. The “A” command is not allowed or required.Waveform ExamplesExample 1: This example shows how to read a single byte from the HMC6352. The Slave (HMC6352) continues to hold the SDA line low after the acknowledge (ACK) bit because the first bit of the data byte is a zero. Remember that the data read is last command sensitive.Example 2: This example shows how to read two bytes from the HMC6352 (slave). The slave continues to hold the SDA line low after the acknowledge bit because the first bit of the data bytes is zero.Example 3: This example shows how to command HMC6352 to read a RAM register by sending the “g” command and the register address 7F(hex). Note that this example does not show the process of reading the answer. See example 1 for reading a byte.Example 4: This example shows how to write to a RAM register in the H MC6352 by sending the “G” command, the register address 7F(hex), and the data byte 55(hex) to the HMC6352 slave.SDA SCL M_SDA S_SDA43(hex)Read From This I2C Address55(hex) DataSDA SCL M_SDA S_SDA43(hex)Read From This I2C Address55(hex) Data00(hex) DataSDA SCL M_SDA S_SDA42(hex)Write to This I2C Address“g” Command7F(hex) Register 7FSDA SCL M_SDA S_SDA42(hex)Write to This I2C Address“G” Command7F(hex) Register 7F55(hex) Data10 Example 5: The final example shows how to read RAM register 7F(hex). First perform a write operation to command the HMC6352 to read a RAM register and define which register to read (Example 3). The sensor puts the answer in the data buffer. Then perform a read operation to clock out the answer (Example 1). There is a Stop/Start event in between the write operation and the read operation. This example is just a combination of Examples 3 and 1, but it is provided to show that reading a register involves both a write and a read operation.APPLICATION NOTESThe HMC6352 Integrated Compass Sensor circuit is composed of two magneto-resistive (MR) sensors with orthogonal orientation for sensing the horizontal components of the earth’s magnetic field (0 to 630 milli-gauss), plus two amplifiers, a set/reset drive circuit, and a microprocessor (µP). Best accuracy is obtained in clean magnetic environments (free air) and held level, or perpendicular to the gravitational direction. At worst case, each degree of tilt from a level orientation could add two degrees of compass heading error. Magnetic errors can be introduced if operated near strong magnetic sources such as microphone or speaker magnets, transformers in test equipment, and CRT deflection yokes in video displays/monitors. These magnetic errors can typically be reduced or eliminated by performing the calibration routine.When locating the HMC6352 in dense printed circuit board designs, take precautions in location of this magnetic field sensing device for soft-iron effects that bend the earth’s magnetic field. These soft -iron effects are from ferrous materials without residual magnetization and tend to be items like nickel-plating on SMT component contacts and RFI/EMI shielding materials. The amount of stand-off of the HMC6352 from these soft-irons is heuristic and dependant on the amount of material, material shape, and proximity.A user calibration mode is available in the HMC6352 to diminish hard-iron effects of the end-user’s (customer’s) location of the product. Hard-iron effects come from nearby ferrous materials with residual magnetism that buck or boost the intensity of the earth’s magnetic field, leading to heading errors. Such hard-iron effects come from vehicle chassis, speaker magnets, and high current conductors or circuit traces.PCB PAD DEFINITION(Dimensions in Millimeters)The HMC6352 is a fine pitch LCC package with a 0.80mm pin pitch (spacing), with the pin pads defined as 0.70mm by 0.33mm in size. PCB pads are recommended to be oversized by 0.025mm from each pad for a short dimension oversize of 0.05mm. The interior PCB pad is recommended to be 0.05mm oversized per pin with an exterior oversize of 0.20mm for proper package centering and to permit test probing. Lead finish is SnAgCu.Soldering attachment shall be done by SMT lead-free reflow methods with standard preheating, soaking, reflow, and cooling profiles for large body parts. Caution, excessive temperature exposure beyond the profiles may result in internal damage to the HMC6352 circuits.SDA SCL S_SDA42(hex) Write to This I2C Address “g”Command7F(hex) Register 7F43(hex) Read From This I2C Address55(hex) Data分销商库存信息:HONEYWELLHMC6352-TR HMC6352-EVAL HMC6352-DEMO。
常用开关电源芯片大全之欧阳育创编
常用开关电源芯片大全第1章DC-DC电源转换器/基准电压源1.1 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104.大电流高速稳压器RT9173/RT9173A105.高效率升压式DC-DC电源转换器RT9262/RT9262A106.升压式DC-DC电源转换器SP6644/SP6645107.低功耗升压式DC-DC电源转换器SP6691108.新型高效率DC-DC电源转换器TPS54350109.无电感降压式电荷泵TPS6050x110.高效率升压式电源转换器TPS6101x111.28V恒流白色LED驱动器TPS61042112.具有LDO输出的升压式DC-DC电源转换器TPS6112x 113.低噪声同步降压式DC-DC电源转换器TPS6200x114.三路高效率大功率DC-DC电源转换器TPS75003115.高效率DC-DC电源转换器UCC39421/UCC39422116.PWM控制升压式DC-DC电源转换器XC6371117.白光LED驱动专用DC-DC电源转换器XC9116118.500mA同步整流降压式DC-DC电源转换器XC9215/XC9216/XC9217119.稳压输出电荷泵XC9801/XC9802120.高效率升压式电源转换器ZXLB16001.2 线性/低压差稳压器121.具有可关断功能的多端稳压器BAXXX122.高压线性稳压器HIP5600123.多路输出稳压器KA7630/KA7631124.三端低压差稳压器LM2937125.可调输出低压差稳压器LM2991126.三端可调稳压器LM117/LM317127.低压降CMOS500mA线性稳压器LP38691/LP38693128.输入电压从12V到450V的可调线性稳压器LR8129.300mA非常低压降稳压器（VLDO）LTC3025130.大电流低压差线性稳压器LX8610131.200mA负输出低压差线性稳压器MAX1735132.150mA低压差线性稳压器MAX8875133.带开关控制的低压差稳压器MC33375134.带有线性调节器的稳压器MC33998135.1.0A低压差固定及可调正稳压器NCP1117136.低静态电流低压差稳压器NCP562/NCP563137.具有使能控制功能的多端稳压器PQxx138.五端可调稳压器SI-3025B/SI-3157B139.400mA低压差线性稳压器SPX2975140.五端线性稳压器STR20xx141.五端线性稳压器STR90xx142.具有复位信号输出的双路输出稳压器TDA8133143.具有复位信号输出的双路输出稳压器TDA8138/TDA8138A144.带线性稳压器的升压式电源转换器TPS6110x145.低功耗50mA低压降线性稳压器TPS760xx146.高输入电压低压差线性稳压器XC6202147.高速低压差线性稳压器XC6204148.高速低压差线性稳压器XC6209F149.双路高速低压差线性稳压器XC64011.3 基准电压源150.新型XFET基准电压源ADR290/ADR291/ADR292/ADR293151.低功耗低压差大输出电流基准电压源MAX610x152.低功耗1.2V基准电压源MAX6120153.2.5V精密基准电压源MC1403154.2.5V/4.096V基准电压源MCP1525/MCP1541155.低功耗精密低压降基准电压源REF30xx/REF31xx156.精密基准电压源TL431/KA431/TLV431A第2章AC-DC转换器及控制器1.厚膜开关电源控制器DP104C2.厚膜开关电源控制器DP308P3.DPA-Switch系列高电压功率转换控制器DPA423/DPA424/DPA425/DPA4264.电流型开关电源控制器FA13842/FA13843/FA13844/FA138455.开关电源控制器FA5310/FA53116.PWM开关电源控制器FAN75567.绿色环保的PWM开关电源控制器FAN76018.FPS型开关电源控制器FS6M07652R9.开关电源功率转换器FS6Sxx10.降压型单片AC-DC转换器HV-2405E11.新型反激准谐振变换控制器ICE1QS0112.PWM电源功率转换器KA1M088013.开关电源功率转换器KA2S0680/KA2S088014.电流型开关电源控制器KA38xx15.FPS型开关电源功率转换器KA5H0165R16.FPS型开关电源功率转换器KA5Qxx17.FPS型开关电源功率转换器KA5Sxx18.电流型高速PWM控制器L499019.具有待机功能的PWM初级控制器L599120.低功耗离线式开关电源控制器L659021.LINK SWITCH TN系列电源功率转换器LNK304/LNK305/LNK30622.LINK SWITCH系列电源功率转换器LNK500/LNK501/LNK52023.离线式开关电源控制器M51995A24.PWM电源控制器M62281P/M62281FP25.高频率电流模式PWM控制器MAX5021/MAX502226.新型PWM开关电源控制器MC4460427.电流模式开关电源控制器MC4460528.低功耗开关电源控制器MC4460829.具有PFC功能的PWM电源控制器ML482430.液晶显示器背光灯电源控制器ML487631.离线式电流模式控制器NCP120032.电流模式脉宽调制控制器NCP120533.准谐振式PWM控制器NCP120734.低成本离线式开关电源控制电路NCP121535.低待机能耗开关电源PWM控制器NCP123036.STR系列自动电压切换控制开关STR8xxxx37.大功率厚膜开关电源功率转换器STR-F665438.大功率厚膜开关电源功率转换器STR-G865639.开关电源功率转换器STR-M6511/STR-M652940.离线式开关电源功率转换器STR-S5703/STR-S5707/STR-S570841.离线式开关电源功率转换器STR-S6401/STR-S6401F/STR-S6411/STR-S6411F 442.开关电源功率转换器STR-S651343.离线式开关电源功率转换器TC33369～TC3337444.高性能PFC与PWM组合控制集成电路TDA16846/TDA1684745.新型开关电源控制器TDA1685046.“绿色”电源控制器TEA150447.第二代“绿色”电源控制器TEA150748.新型低功耗“绿色”电源控制器TEA153349.开关电源控制器TL494/KA7500/MB375950.Tiny SwitchⅠ系列功率转换器TNY253、TNY254、TNY25551.Tiny SwitchⅡ系列功率转换器TNY264P～TNY268G52.TOP Switch（Ⅱ）系列离线式功率转换器TOP209～TOP22753.TOP Switch-FX系列功率转换器TOP232/TOP233/TOP23454.TOP Switch-GX系列功率转换器TOP242～TOP25055.开关电源控制器UCX84X56.离线式开关电源功率转换器VIPer12AS/VIPer12ADIP57.新一代高度集成离线式开关电源功率转换器VIPer53第3章功率因数校正控制/节能灯电源控制器1.电子镇流器专用驱动电路BL83012.零电压开关功率因数控制器FAN48223.功率因数校正控制器FAN75274.高电压型EL背光驱动器HV8265.EL场致发光背光驱动器IMP525/IMP5606.高电压型EL背光驱动器/反相器IMP8037.电子镇流器自振荡半桥驱动器IR21568.单片荧光灯镇流器IR21579.调光电子镇流器自振荡半桥驱动器IR215910.卤素灯电子变压器智能控制电路IR216111.具有功率因数校正电路的镇流器电路IR216612.单片荧光灯镇流器IR216713.自适应电子镇流器控制器IR252014.电子镇流器专用控制器KA754115.功率因数校正控制器L656116.过渡模式功率因数校正控制器L656217.集成背景光控制器MAX8709/MAX8709A18.功率因数校正控制器MC33262/MC3426219.固定频率电流模式功率因数校正控制器NCP165320.EL场致发光灯高压驱动器SP440321.功率因数校正控制器TDA4862/TDA486322.有源功率因数校正控制器UC385423.高频自振荡节能灯驱动器电路VK05CFL24.大功率高频自振荡节能灯驱动器电路VK06TL第4章充电控制器1.多功能锂电池线性充电控制器AAT36802.可编程快速电池充电控制器BQ20003.可进行充电速率补偿的锂电池充电管理器BQ20574.锂电池充电管理电路BQ2400x5.单片锂电池线性充电控制器BQ2401xB接口单节锂电池充电控制器BQ2402x7.2A同步开关模式锂电池充电控制器BQ241008.集成PWM开关控制器的快速充电管理器BQ29549.具有电池电量计量功能的充电控制器DS277010.锂电池充电控制器FAN7563/FAN756411.2A线性锂/锂聚合物电池充电控制器ISL629212.锂电池充电控制器LA5621M/LA5621V13.1.5A通用充电控制器LT157114.2A恒流/恒压电池充电控制器LT176915.线性锂电池充电控制器LTC173216.带热调节功能的1A线性锂电池充电控制器LTC173317.线性锂电池充电控制器LTC173418.新型开关电源充电控制器LTC198019.开关模式锂电池充电控制器LTC400220.4A锂电池充电器LTC400621.多用途恒压/恒流充电控制器LTC400822.4.2V锂离子/锂聚合物电池充电控制器LTC405223.可由USB端口供电的锂电池充电控制器LTC405324.小型150mA锂电池充电控制器LTC405425.线性锂电池充电控制器LTC405826.单节锂电池线性充电控制器LTC405927.独立线性锂电池充电控制器LTC406128.镍镉/镍氢电池充电控制器M62256FP29.大电流锂/镍镉/镍氢电池充电控制器MAX150130.锂电池线性充电控制器MAX150731.双输入单节锂电池充电控制器MAX1551/MAX155532.单节锂电池充电控制器MAX167933.小体积锂电池充电控制器MAX1736B接口单节锂电池充电控制器MAX181135.多节锂电池充电控制器MAX187336.双路输入锂电池充电控制器MAX187437.单节锂电池线性充电控制器MAX189838.低成本/多种电池充电控制器MAX190839.开关模式单节锂电池充电控制器MAX1925/MAX192640.快速镍镉/镍氢充电控制器MAX2003A/MAX200341.可编程快速充电控制器MAX712/MAX71342.开关式锂电池充电控制器MAX74543.多功能低成本充电控制器MAX846A44.具有温度调节功能的单节锂电池充电控制器MAX8600/MAX860145.锂电池充电控制器MCP73826/MCP73827/MCP7382846.高精度恒压/恒流充电器控制器MCP73841/MCP73842/MCP73843/MCP73844 647.锂电池充电控制器MCP73861/MCP7386248.单节锂电池充电控制器MIC7905049.单节锂电池充电控制器NCP180050.高精度线性锂电池充电控制器VM7205。
SD42560 LED驱动芯片说明书
1. PWM 调光功能 SD42560 内部设定 PWM 调光功能。当 PWM 电压悬空或者接高电平时，芯片正常工作，当
PWM 电压接低电平时，COMP 脚与芯片断开，电容上的电荷处于保持状态，电平保持，电流比较
杭州士兰微电子股份有限公司
版本号：1.0 2010.01.10 共8页 第4页
功率管漏电流 电流限制 最大占空比 振荡频率
PWM 调光脚开启电压
PWM 调光脚关断电压
PWM 脚下拉电流 PWM 脚上拉电流 COMP 端箝位电压 开关管导通电阻 VDD 电压 采样电压阈值
符号
测试条件
最小值 典型值 最大值
VIN VCC=5/36V，
IIN VPWM=5V
IL
VSW=36V
5
36
I/O 补偿端，外接补偿元件。
6
PWM
I PWM 调光端，外接 PWM 信号改变输出电流的大小。
7
VDD
I 5V 基准输出端。
8
VIN
I 输入电压。
功能描述
SD42560 是电流模式的 LED 驱动电路，可以应用与降压模式（Buck），升压模式（Boost），升 降压模式（Buck－Boost）三种模式。用于满足不同的 LED 应用。
升压/降压模式的工作原理为：在一个工作周期的开始时，内部振荡器输出触发信号，将芯片 内部功率管导通，SW 输出低电平，VIN，电感和内部开关管，GND 组成通路，给电感储能，电感 上的电流增加。LED 上的电流通过 SENSE-和 SENSE+进行采样，将采样值与阈值进行误差放 大，输出信号再与功率管的峰值电流进行比较，当功率管的峰值电流值达到误差放大输出值时， 功率管截止。电感，肖特基，Rs，LED 组成的回路给 LED 供电，电感电流降低。在下一个时钟到 来时，开关管开通，进入下一个开关周期。
锐尔威视A63-Core产品硬件手册说明书
A63-Core 产品硬件手册2020-5-28 Ver.C锐尔威视版本更新说明1. 产品概述1.1 产品简介锐尔威视的A63-Core模块是基于全志A63平台设计的高性价比嵌入式核心模块板。
A63-Core采用130pin邮票孔封装形式，六层高速PCB设计，体积非常小，适合做手持便携类产品。
A63-Core模块集成2GB LPDDR3内存和16GB EMMC存储器，集成PMU芯片，带电池充放电管理。
集成音频Codec功能，GPU为Mali-T760，可满足人脸识别及AI算法的需求，支持硬解H.265/H.264 4K@30fps，提供丰富的外设资源：USB、UART、SDIO、SPI、IIC、GPIO。
支持驱动2个4-lane MIPI 或1个8-lane MIPI接口的显示屏，最大分辨率2560x1600，支持驱动2-lane EDP屏，分辨率1920x1080。
搭载Android7.1操作系统，经过深度优化定制，运行流畅，用户可由PC端的固件修改工具定制个性化固件，如修改开机图片动画声音、设置开机自启动应用、更改LCD屏配置、设置屏幕旋转方向、修改机器信息等1.2 产品规格2. 应用接口2.1 邮票孔接口A63-Core采用邮票孔封装，间距1.2mm，共130个引脚2.1.1 管脚分布2.1.2 管脚定义2.2 电源2.2.1 DC供电A63-Core模块用直流5V电源供电，上电即可开机，电压范围4.8~6V。
用户根据应用场合，选择使用12V或24V降压DC/DC设计电源为保证系统的稳定运行，电源输入处的滤波电容建议不小于100uF。
具体要根据产品应用场合和经验选择合适的电容值2.2.2 电池充电和电池管理使用3.7V锂电池供电A63-Core内置线性充电管理电路，支持对3.7V锂电池进行充电。
支持DC和USB接口充电，当两种充电口同时接通时，优先选择DC充电如需要使用电池给外设（屏，USB）供电，建议用PS接升压IC，升压到5V2.2.3 RTC电源内部VRTC耗电较大，不建议使用，需要使用外挂RTC芯片（PCF8563），软件默认支持外挂RTC。
晶体管说明书：Diodes Incorporated DMP6350S 60V P-CHANNEL
Description and ApplicationsThis MOSFET is designed to minimize the on-state resistance (R DS(ON)) and yet maintain superior switching performance, making it ideal for high-efficiency power management applications. ∙ Battery Charging∙ Power Management Functions ∙ DC-DC Converters ∙ Portable Power AdaptorsFeatures and Benefits∙ Low On-Resistance ∙ Low Input Capacitance ∙ Fast Switching Speed ∙ Low Input/Output Leakage∙ Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2) ∙ Halogen and Antimony Free. “Green” Device (Note 3) ∙Qualified to AEC-Q101 Standards for High ReliabilityMechanical Data∙ Case: SOT23∙ Case Material: Molded Plastic, “Green” Molding Compound. UL Flammability Classification Rating 94V-0 ∙ Moisture Sensitivity: Level 1 per J-STD-020∙ Terminals: Finish − Matte Tin Annealed over Copper Leadframe. Solderable per MIL-STD-202, Method 208 ∙ Terminals Connections: See Diagram Below ∙Weight: 0.009 grams (Approximate)Ordering Information (Note 4)Notes: 1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.2. See /quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen - and Antimony-free, "Green" and Lead-free.3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and<1000ppm antimony compounds.4. For packaging details, go to our website at /products/packages.html.Marking InformationTop View Internal SchematicTop ViewP35 = Product Type Marking Code YM = Date Code Marking Y or Y= Year (ex: D = 2016) M = Month (ex: 9 = September)DSGP35Y MMaximum Ratings(@T A = +25°C unless otherwise specified.)Thermal CharacteristicsElectrical Characteristics(@T A = +25°C unless otherwise specified.)Notes: 5. Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout.6. Device mounted on FR-4 substrate PC board, 2oz copper, with 1inch square copper plate.7. Short duration pulse test used to minimize self-heating effect.8. Guaranteed by design. Not subject to product testing.4.0-50-25 0 25 50 75 100 125 150R D S (O N ), D R A I N -S O U R C E O N -R E S I S T A N C E (Ω)T J , JUNCTION TEMPERATURE (℃)Figure 7. On-Resistance Variation with JunctionTemperaturePackage Outline DimensionsPlease see /package-outlines.html for the latest version.SOT23Suggested Pad LayoutPlease see /package-outlines.html for the latest version.SOT23All 7°。
E6Y2 E6Y5 E6Y6 32-bit ARM M0-based MCU 技术手册说明书
版本历史版本号说明日期1.0 初版2019-6-171.1 1. 增加型号E6Y6，更新WLCSP25封装引脚图和封装框图2. LRC频率：min（30->27），max（50->62）3. ADC特性更新： fADC-40℃≤ Trange ≤ 85℃，fADC≤14MHz，支持电压范围2.65≤ VDDA ≤5.5V；-40℃≤ Trange ≤ 105℃，fADC≤14MHz，支持电压范围2.7≤ VDDA ≤5.5V；-40℃≤ Trange ≤ 105℃，fADC≤12MHz，支持电压范围2.4≤ VDDA ≤5.5V；进入校准模式，fADC≤12MHz。
进入正常转换模式，fADC≤14MHz。
支持：-40℃≤ Trange ≤ 105℃和电压范围2.4≤ VDDA ≤5.5V；4. ADC特性更新：VDDA=2.4V时，Offset和ERR Gain更新5. 增加QFN28封装热特性2020-7-161.2 1.更新温度传感器线性度参数，区分不同温度范围2020-8-261.3 1.更新QFN32封装信息2.更新订货信息2021-2-31.4 1. 更新QFN32封装公差信息2021-4-141.5 1.修正部分数据单位2021-10-272/57文件编号：CS-QR-YF-054A02目录版本历史 (2)目录 (3)1 介绍 (5)2 功能 (6)3 器件一览 (9)4 引脚描述 (11)4.1LQFP48 (11)4.2QFN32 (11)4.3QFN28 (12)4.4WLCSP25 (12)4.5引脚描述 (13)5 I/O 复用 (17)5.1PA口复用功能 (17)5.2PB口复用功能 (18)6 存储器 (19)7 功能描述 (22)7.1ARM®C ORTEX®-M0内核 (22)7.2存储器 (22)7.3时钟 (22)7.4工作环境 (24)7.4.1 工作电压 (24)7.5启动模式 (24)7.6电源管理 (24)7.6.1 低功耗模式 (24)7.6.2 RTC和不掉电寄存器 (24)7.6.3 上电复位/掉电复位(POR/PDR) (24)7.6.4 低电压复位模块(LVD) (25)7.7通用输入输出端口(GPIO) (25)7.8模数转换器(ADC) (25)7.8.1 温度传感器(TS) (25)7.8.2 内部参考电压 (25)7.8.3 VBAT监测 (26)7.9定时器 (26)7.9.1 高级定时器 (TIM1) (26)7.9.2 通用定时器 (TIM2, 3, 14, 15,16, 17) (26)7.9.3 基本定时器(TIM6) (27)7.9.4 独立看门狗定时器(FWDT) (27)7.9.5 窗看门狗定时器(WWDT) (27)7.9.6 滴答定时器(SysTick) (27)7.10直接内存存取(DMA) (27)3/57文件编号：CS-QR-YF-054A027.11中断和事件 (27)7.12实时时钟(RTC)和不掉电寄存器 (27)7.13串行外设总线（SPI）/集成电路内置音频总线（I2S） (28)7.14通用同步异步收发器（USART） (28)7.15I2C接口 (29)7.16循环冗余校验 (29)7.17串行调试端口(SWD-DP) (29)8 电气特性 (30)8.1说明 (30)8.2绝对最大额定值 (31)8.3工作条件 (31)8.4I/O端口特性 (32)8.5低功耗模式唤醒时间 (33)8.6RC振荡器特性 (33)8.7晶振特性 (34)8.8外部时钟特性 (36)8.9PLL特性 (36)8.10功耗 (36)8.11内部参考电压特性 (38)8.12ADC特性 (38)8.13温度传感器特性 (39)8.14VBAT监测器特性 (39)8.15F LASH特性 (39)8.16定时器特性 (39)8.17SPI/I2S特性 (40)8.18I2C特性 (43)8.19ESD特性 (44)9 封装信息 (45)9.1LQFP48 (45)9.2QFN32(0505×0.55-E=0.50) (46)9.3QFN32(0505×0.75-E=0.50) (47)9.4QFN28 (49)9.5WLCSP25 (50)10 产品命名规则 (52)10.1产品丝印说明 (52)11 订货信息 (53)12 勘误表 (54)13 缩略语 (55)14 销售和服务 (57)4/57文件编号：CS-QR-YF-054A021介绍CS32F031系列微控制器采用高性能的32位ARM® Cortex®-M0 内核，嵌入高达64K Bytes flash和8K Bytes SRAM，最高工作频率48MHz。
EMD56324P-60资料
256M: 8M x 32 Mobile DDR SDRAM Document Title256M: 8M x 32 Mobile DDR SDRAMRevision HistoryRevision No. Date History0.0Dec. 11, 2007 Initial DraftEmerging Memory & Logic Solutions Inc.4F Korea Construction Financial Cooperation B/D, 301-1 Yeon-Dong, Jeju-Do, Korea Zip Code : 690-717 Tel : +82-64-740-1700 Fax : +82-64-740-1750 / Homepage : The attached datasheets provided by EMLSI reserve the right to change the specifications and products. EMLSI will answer to your questions about device. If you have any questions, please contact the EMLSI office.256M: 8M x 32 Mobile DDR SDRAM256M : 8M x 32bit Mobile DDR SDRAM Table 1: ORDERING INFORMATIONNOTE :1. EMLSI is not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in EMLSI when considering the use of a product contained herein for any specific purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.Part No.Max Freq.Interface Package RemarkEMD56324P-60(DDR332)166 (CL3), 83 (CL2)LVCMOSWafer Biz.EMD56324P-75(DDR266)133 (CL3), 83 (CL2)FEATURES· 1.8V power supply, 1.8V I/O power·LVCMOS compatible with multiplexed address.· Double-data-rate architecture; two data transfers per clock cycle· Bidirectional data strobe(DQS) · Four banks operation.· MRS cycle with address key programs. · CAS latency (2, & 3).·Burst length (2, 4, 8, & 16).· Burst type (Sequential & Interleave). · Differential clock inputs(CK and CKB). · EMRS cycle with address key programs. · PASR(Partial Array Self Refresh). · DS (Driver Strength) · Internal auto TCSR(Temperature Compensated Self Refresh) · Deep power-down(DPD) mode. ·DM for write masking only.·Auto refresh and self refresh modes. ·64 refresh period (4K cycle).·Operating temperature range (-25 ~ 85 ).GENERAL DESCRIPTIONThis EMD56324P is 268,435,456 bits synchronous double data rate Dynamic RAM. Each 67,108,854 bits bank is organized as 4,096 rows by 512columns by 32 bits, fabricated with EMLSI’s high performance CMOS technology.This device uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O balls.Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.256M: 8M x 32 Mobile DDR SDRAMTable 2: Pad DescriptionSymbol Type DescriptionsCK, CKB Input Clock : CK and CKB are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK and negative edge of CKB. Input and output data is referenced to the crossing of CK and CKB(both directions of crossing). Internal clock signals are derived from CK/ CKB.CKE Input Clock Enable : CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operation(all banks idle), or ACTIVE POWER-DOWN(row ACTIVE in any bank). CKE is synchronous for all functions except for SELF REFRESH EXIT, which is achieved asynchronously. Input buffers, excluding CK, CKB and CKE, are disabled during power-down and self refresh mode which are contrived for low standby power consumption.CSB Input Chip Select : CSB enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when CSB is registered HIGH. CSB provides for external bank selection on systems with multiple banks. CSB is considered part of the command code.RASB, CASB,WEBInput Command Inputs: CASB, RASB, and WEB(along with CSB) define the command being entered.DM0~DM3 Input Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is sampled. HIGH along with that input data during a WRITE access. DM is sampled on both edges of DQS. Data Mask pins include dummy loading internally, to match the DQ and DQS loading.BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an ACTIVE, READ, WRITE or PRECHARGE command is being applied.A0 ~ A11 Input Address Inputs: provide the row address for ACTIVE commands, and the column address and AUTO PRECHARGE bit for READ / WRITE commands, to select one location out of the memory array in the respective bank. The address inputs also provide the op-code during a MODE REGISTER SET com-mand.DQ0~DQ31 I/O Data Bus: Input / OutputDQS0~DQS3 I/O Data Strobe: Output with read data, input with write data. Edge-aligned with read data, center-aligned with write data. Used to capture write data. For x32 device, DQS0 corresponds to the data on DQ0-DQ7, DQS1 corresponds to the data on DQ8-DQ15, DQS2 corresponds to the data on DQ16-DQ23, and DQS3 corresponds to the data on DQ24-DQ31.VDD Supply Power Supply256M: 8M x 32 Mobile DDR SDRAMDevice OperationSimplified State DiagramPower OnDeep Power DownPrecharge All BanksIdle All banks prechargedSelf RefreshMRS EMRSAuto RefreshPrecharge Power DownActive Power DownRow ActiveBurst StopWRITE WRITE APrecharge PREALLREAD AREADPower appliedDPDSXMRSDPDSACTREFABSTREADREADAWRITEAPRE REFSXREFSCKEL CKEHCKELCKEH WRITEREADREADA READAPREPREPREWRITEAAutomatic Sequence Command SequenceACT = ActiveBST = Burst Terminate CKEL = Enter Power-Down CKEH =Exit Power-Down DPDS = Enter Deep Power-Down DPDSX = Exit Deep Power-DownEMRS = Ext. Mode Reg. Set MRS = Mode Register Set PRE = PrechargePREALL = Precharge All Banks REFA = Auto Refresh REFS = Enter Self RefreshREFSX = Exit Self Refresh READ = Read w/o Auto Precharge READA = Read with Auto Precharge WRITE = Write w/o Auto Precharge WRITEA = Write with Auto PrechargeREADWRITE256M: 8M x 32 Mobile DDR SDRAMFUNCTIONAL BLOCK DIAGRAMADDRESS DECODERBANK CONTROL Din DQS DoutParallel ROW -ADDRESS DECODERCOLUMN -DM MASK LOGICI/O GATING SENSE AMPLIFIERSLOGICREFRESH COUNTERDM to SerialDinSerial to ParallelDQSGENERATORDQS A0 - A11BA0, BA1CKE CK CKB CSB RASB CASB WEBSTANDARD MODEREGISTER EXTENDED MODEREGISTERCOMMAND DECODECONTROL LOGIC8,19225612DQ0~DQ31DQS0~DQS3DM0~DM3BANK MEMORYARRAY (4,096 x 256 x 64)x 4x 4x 464648122 121232324444432324A D D R E S S R E G I S T E R146464DRIVERINPUT BUF.INPUT BUF.INPUT BUF.Dout DRIVER256M: 8M x 32 Mobile DDR SDRAMElectrical SpecificationsTable 3: ABSOLUTE MAXIMUM RATINGSNOTE :Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.Functional operation should be restricted to recommended operating condition.Exposure to higher than recommended voltage for extended periods of time could affect device reliability.Table 4: DC OPERATING CONDITIONSRecommended operating conditions (Voltage referenced to V SS = 0V, T A = -25o C~ 85o C for Extended)NOTE :1. Under all conditions, VDDQ must be less than or equal to VDD.2. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.Table 5: CAPACITANCE (V DD = 1.8V, V DDQ = 1.8V, T A = 25 , f=1 )ParameterSymbol Value Unit Voltage on any pin relative to V SSV IN ,V OUT -0.5 ~ 2.5V Voltage on V DD and V DDQ supply relative to V SS V DD , V DDQ-0.5 ~ 2.5VStorage temperature T STG -55 ~ +150Power dissipation P D 1.0W Short circuit current I OS50ParameterSymbol Min Typ Max Unit Note Supply voltageV DD1.7 1.8 1.95V 1V DDQ1.7 1.8 1.95V 1Input logic high voltage V IH 0.8 x V DDQ1.8V DDQ + 0.3V 2Input logic low voltage V IL -0.300.3V 2Output logic high voltage V OH 0.9 x V DDQ--V I OH = -0.1 Output logic low voltage V OL --0.1 x V DDQV I OL = 0.1Input leakage current I LI -2-2 Output leakage current I LO-5-5PinSymbol Min Max Unit NoteInput capacitance(ADD, BA0~1, RASB, CASB, WEB, CSB, CKE)C IN1 1.5 3.0 Input capacitance(CK, CKB)C IN2 1.5 3.5 Data & DQS input/output capacitance C out 2.0 4.5 Input capacitance(DM)C IN32.04.5256M: 8M x 32 Mobile DDR SDRAMTable 6: DC CHARACTERISTICSRecommended operating conditions (Voltage referenced to VSS = 0V, T A = -25 to 85 )Parameter Symbol Test ConditionVersionUnit -60-75Operating one bankactive-precharge current I DD0t RC = t RCmin; t CK = t CKmin; CKE is HIGH; CSB is HIGHbetween valid commands; address inputs are SWITCH-ING; data bus inputs are STABLE10080mAPrecharge power-down standby current I DD2Pall banks idle, CKE is LOW; CSB is HIGH, t CK = t CKmin;address and control inputs are SWITCHING; data businputs are STABLE0.4mAPrecharge power-downstandby current with clock stop I DD2PSall banks idle, CKE is LOW; CSB is HIGH, CK = LOW,CKB = HIGH; address and control inputs are SWITCHING;data bus inputs are STABLE0.4Precharge non power-down standby current I DD2Nall banks idle, CKE is HIGH; CSB is HIGH, t CK = t CKmin;address and control inputs are SWITCHING; data businputs are STABLE2520mAPrecharge non power-down standby current with clock stop I DD2NSall banks idle, CKE is HIGH; CSB is HIGH, CK = LOW,CKB = HIGH; address and control inputs are SWITCHING;data bus inputs are STABLE55Active power-down standby current I DD3Pone bank active, CKE is LOW; CSB is HIGH, t CK =t CKmin; address and control inputs are SWITCHING; databus inputs are STABLE8mAActive power-downstandby current with clock stop I DD3PSone bank active, CKE is LOW; CSB is HIGH, CK = LOW,CKB = HIGH; address and control inputs are SWITCHING;data bus inputs are STABLE5Active non power-down standby current I DD3None bank active, CKE is HIGH; CSB is HIGH, t CK =t CKmin; address and control inputs are SWITCHING; databus inputs are STABLE2525mAActive non power-downstandby current with clock stop I DD3NSone bank active, CKE is HIGH; CSB is HIGH, CK = LOW,CKB = HIGH; address and control inputs are SWITCHING;data bus inputs are STABLE1010mAOperating burst read current I DD4Rone bank active; BL=4; CL=3; t CK = t CKmin; continuousread bursts; Iout = 0 mA; address inputs are SWITCHING;50% data change each burst transfer160130mAOperating burst write current I DD4Wone bank active; t CK = t CKmin; continuous write bursts;address inputs are SWITCHING; 50% data change eachburst transfer130105mAAuto-Refresh current I DD5t RC = t RFCmin; burst refresh; CKE is HIGH;address and control inputs are SWITCHING; data businputs are STABLE120120mASelf Refresh Current I DD6CKE is LOW, CK = LOW, CKB= HIGH; Extended Mode Reg-ister set to all 0s; address andcontrol inputs are STABLE;data bus inputs are STABLETCSR Range45*185°CFull Array250400µA1/2 of Full Array2003001/4 of Full Array150250Deep Power-Down Current I DD8Address and Control inputs are STABLE;data bus inputs are STABLE1010µA256M: 8M x 32 Mobile DDR SDRAMNOTE :1. IDD specifications are tested after the device is properly initialized2. Input slew rate is 1V/ns.3. Definitions for IDD:LOW is defined as V IN 0.1 * VDDQ ; HIGH is defined as V IN 0.9 * VDDQ ;STABLE is defined as inputs stable at a HIGH or LOW level ; SWITCHING is defined as :- address and command : inputs changing between HIGH and LOW once per two clock cycles ;- data bus inputs : DQ changing between HIGH and LOW once per clock cycle ; DM and DQS are STABLETable 7: AC OPERATING TEST CONDITIONS(V DD = 1.7V ~ 1.95V, T A = -25 ~85 for Extended)NOTE :1. Under all conditions, VDDQ must be less than or equal to VDD.2. These parameters should be tested at the pin on actual components and may be checked at either the pin or the pad in simulation.3. CK and CKB crossing voltage.ParameterValueUnit NoteAC input levels(Vih/Vil)0.8 V DDQ / 0.2 V DDQV Input timing measurement reference level 0.5 V DDQV Input rise and fall time1.0V / Output timing measurement reference level 0.5 V DDQV Vix0.4 V DDQ (Min) / 0.6 V DDQ (Max)V3Output load condition See Figure 21.8V13.9V OH (DC) = 0.9 V DDQ , I OH = -0.1V OL V DDQ , I OL = 0.1 20Z0=50Vtt=0.5 V DDQ 5020Figure 1. DC Output Load CircuitFigure 2. AC Output Load CircuitOutputOutput10.6256M: 8M x 32 Mobile DDR SDRAMTable 8: OPERATING AC PARAMETER(AC operating conditions unless otherwise noted)Parameter Sym-bol-60-75Unit Note Min Max Min MaxDQ output access time from CK/CKB t AC25 2.5 6.0ns3 DQS output access time from CK/CKB t DQSCK25 2.5 6.0nsClock high-level width t CH0.450.550.450.55t CK Clock low-level width t CL0.450.550.450.55t CKClock half period t HPmin(t CL,t CH)min(t CL,t CH)nsClock cycle time CL = 3t CK61007.5100ns CL = 21210012100nsDQ and DM input setup time t DS0.60.75ns4,5 DQ and DM input hold time t DH0.60.75ns4,5 DQ and DM input pulse width t DIPW 1.8 2.5ns Address and control input setup time t IS 1.1 1.3ns1 Address and control input hold time t IH 1.1 1.3ns1 Address and control input pulse width t IPW 2.6 2.6nsDQ & DQS low-impedance time from CK/CKB t LZ 1.0 1.0nsDQ & DQS high-impedance time from CK/CKB t HZ5 6.0nsDQS - DQ skew t DQSQ0.50.6nsDQ / DQS output hold time from DQS t QH t HP-t QHS t HP-t QHS nsData hold skew factor t QHS0.650.75nsWrite command to 1st DQS latching transition t DQSS0.75 1.250.75 1.25t CKDQS input high-level width t DQSH0.40.60.40.6t CKDQS input low-level width t DQSL0.40.60.40.6t CKDQS falling edge to CK rising - setup time t DSS0.20.2t CKDQS falling edge from CK rising - hold time t DSH0.20.2t CK MODE REGISTER SET command period t MRD22t CKWrite preamble setup time t WPRES00nsWrite postamble t WPST0.40.60.40.6t CKWrite preamble t WPRE0.250.25t CK256M: 8M x 32 Mobile DDR SDRAMNote:Table 9: Input Setup/Hold Slew Rate1. This derating table is used to increase t IS /t IH in the case where the input slew rate is below 1.0V/ns.2. Minimum 5CK of t DAL (= t WR + t RP ) is required because it need minimum 2CK for t WR and minimum 3CK for t RP .3. t AC (min) value is measured at the high Vdd(1.95V) and cold temperature(-25°C). t AC (max) value is measured at the low Vdd(1.7V) and hot temperature(85°C).t AC is measured in the device with half driver strength and under the AC output load condition (Fig.2 in Page 8).ParameterSym-bol-60-75UnitNoteMin Max Min Max Read preambleCL = 2t RPRE0.51.10.5 1.1t CK CL = 30.91.10.9 1.1t CK Read postamblet RPST 0.40.60.40.6t CK ACTIVE to PRECHARGE command period t RAS 4270,0004570,000ns ACTIVE to ACTIVE command period t RC 6060ns AUTO REFRESH toACTIVE / AUTO REFRESH command period t RFC 8080ns 6ACTIVE to READ or WRITE delay t RCD 1818ns PRECHARGE command period t RP 1822.5ns ACTIVE bank A to ACTIVE bank b delay t RRD 1215ns Column address to Column address delay t CCD 11t CK WRITE recovery timet WR 22t CKAuto precharge write recovery + precharge time t DAL t WR+t RPt WR+t RP2Internal write to Read command delay t WTR 11t CK Self refresh exit to next valid command delay t XSR 120120nsExit power down to next valid command delay t XP t CK +t ISt CK +t ISCKE min. pulse width(high and low pulse width)t CKE 12t CK Refresh Periodt REF6464ms Input Setup/Hold Slew Rate∆t IS ∆t IH (V/ns)(ps)(ps)1.0000.8+50+500.6+100+100256M: 8M x 32 Mobile DDR SDRAMTable 10: I/O Setup/Hold Slew Rate4. This derating table is used to increase t DS /t DH in the case where the I/O slew rate is below 1.0V/ns.Table 11: I/O Delta Rise/Fall Rate(1/slewrate)5. This derating table is used to increase t DS /t DH in the case where the DQ and DQS slew rates differ. The Delta Rise/Fall Rate is calculated as 1/SlewRate1-1/SlewRate2. For example, if slew rate 1 = 1.0V/ns and slew rate 2 = 0.8V/ns, then the Delta Rise/Fall Rate = -0.25ns/V.6. Maximum burst refresh cycle : 8I/O Setup/Hold Slew Rate∆t DS ∆t DH (V/ns)(ps)(ps)1.0000.8+75+750.6+150+150Delta Rise/Fall Rate∆t DS ∆t DH (ns/V)(ps)(ps)000 0.25+50+50 0.5+100+100256M: 8M x 32 Mobile DDR SDRAMFunctional DescriptionThe 256Mb Mobile DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456-bits. It is internally configured as a quad-bank DRAM. Each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32 bits.The 256Mb Mobile DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. single read or write access for the 256Mb Mobile DDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O balls.Read and write accesses to the Mobile DDR SDRAM are burst oriented; accesses start at a selected location and con-tinue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A11 select the row). The address bits registered coincident with the READ or WRITE command are used to select the start-ing column location for the burst access.It should be noted that the DLL signal that is typically used on standard DDR devices is not necessary on the Mobile DDR SDRAM. It has been omitted to save power. Prior to normal operation, the Mobile DDR SDRAM must be initial-ized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.InitializationMobile DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. If there is an interruption to the device power, the initialization rou-tine should be followed to ensure proper functionality of the Mobile DDR SDRAM. The clock stop feature is not avail-able until the device has been properly initialized.To properly initialize the Mobile DDR SDRAM, this sequence must be followed:1. To prevent device latch-up, it is recommended the core power (VDD) and I/O power (VDDQ) be from the samepower source and brought up simultaneously. If separate power sources are used, VDD must lead VDDQ.2. Once power supply voltages are stable and the CKE has been driven HIGH, it is safe to apply the clock.3. Once the clock is stable, a 200µs (minimum) delay is required by the Mobile DDR SDRAM prior to applying an exe cutable command. During this time, NOP or DESELECT commands must be issued on the command bus.4. Issue a PRECHARGE ALL command.5. Issue NOP or DESELECT commands for at least tRP time.6. Issue an AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time. Issue a second AUTO REFRESH command followed by NOP or DESELECT commands for at least tRFC time. As part of the initialization sequence, two AUTO REFRESH commands must be issued. Typically, both of these commands are issued at this stage as described above. Alternately, the second AUTO-REFRESH command and NOP or DESELECT sequence can be issued between steps 10 and 11.7. Using the LOAD MODE REGISTER command, load the standard mode register as desired.8. Issue NOP or DESELECT commands for at least tMRD time.9. Using the LOAD MODE REGISTER command, load the extended mode register to the desired operating modes. Note that the sequence in which the standard and extended mode registers are programmed is not critical.10. Issue NOP or DESELECT commands for at least tMRD time.11. The Mobile DDR SDRAM has been properly initialized and is ready to receive any valid command.256M: 8M x 32 Mobile DDR SDRAM Register DefinitionMode RegistersThe mode registers are used to define the specific mode of operation of the Mobile DDR SDRAM. There are two mode registers used to specify the operational characteristics of the device. The standard mode register, which exists for all SDRAM devices, and the extended mode register, which exists on all Mobile SDRAM devices.Standard Mode RegisterThe standard mode register definition includes the selection of a burst length, a burst type, a CAS latency and an oper-ating mode, as shown in page 15. The standard mode register is programmed via the LOAD MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again. Reprogram-ming the standard mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-A6 specify the CAS latency, and A7-A11 specify the operating mode.Note: Standard refers to meeting JEDEC-standard mode register definitions.Burst LengthRead and write accesses to the Mobile DDR SDRAM are burst oriented, with the burst length being programmable, as shown in page 15. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, 8, or 16 are available for both the sequential and the inter-leaved burst types.Reserved states should not be used, as unknown operation or incompatibility with future versions may result.Burst TypeAccesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected by A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address. See Table 17~20 on page 17~18 for more information.CAS LatencyThe CAS latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 3 clocks, as shown in page 15.For CL = 3, if the READ command is registered at clock edge n, then the data will nominally be available at (n + 2 clocks + tAC). For CL = 2, if the READ command is registered at clock edge n, then the data will be nominally be avail-able at (n + 1 clock + tAC).Reserved states should not be used as unknown operation or incompatibility with future versions may result.Operating ModeThe normal operating mode is selected by issuing a LOAD MODE REGISTER SET command with bits A7-A11 each set to zero, and bits A0-A6 set to the desired values. All other combinations of values for A7-A11 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.256M: 8M x 32 Mobile DDR SDRAMExtended Mode RegisterThe extended mode register controls functions specific to low power operation. These additional functions include drive strength, temperature compensated self refresh, and partial array self refresh.This device has default values for the extended mode register (if not programmed, the device will operate with the default values . PASR = Full Array, DS = Full Drive).Temperature Compensated Self RefreshOn this version of the Mobile DDR SDRAM, a temperature sensor is implemented for automatic control of the self refresh oscillator on the device. Programming of the temperature compensated self refresh (TCSR) bits will have no effect on the device. The self refresh oscillator will continue refresh at the factory programmed optimal rate for the device temperature.Partial Array Self RefreshFor further power savings during SELF REFRESH, the PASR feature allows the controller to select the amount of memory that will be refreshed during SELF REFRESH. Low Power DDR SDRAM supports 3 kinds of PASR in self refresh mode : Full Array, 1/2 of Full Array and 1/4 of Full Array.Output Driver StrengthBecause the Mobile DDR SDRAM is designed for use in smaller systems that are mostly point to point, an option to control the drive strength of the output buffers is available. Drive strength should be selected based on the expected loading of the memory bus. Bits A5 and A6 of the extended mode register can be used to select the driver strength of the DQ outputs.Stopping the External ClockOne method of controlling the power efficiency in applications is to throttle the clock which controls the Mobile DDR SDRAM. There are two basic ways to control the clock:1. Change the clock frequency, when the data transfers require a different rate of speed.2. Stopping the clock altogether.Both of these are specific to the application and its requirements and both allow power savings due to possible less transitions on the clock path.The Mobile DDR SDRAM allows the clock to change frequency during operation, only if all the timing parameters are met with respect to that change and all refresh requirements are satisfied.The clock can also be stopped all together, if there are no data accesses in progress, either WRITEs or READs that would be effected by this change; i.e., if a WRITE or a READ is in progress the entire data burst must be through the pipeline prior to stopping the clock. CKE must be held HIGH with CK = LOW and CKB = HIGH for the full duration of the clock stop mode. One clock cycle and at least one NOP is required after the clock is restarted before a valid com-mand can be issued.It is recommended that the Mobile DDR SDRAM should be in a precharged state if any changes to the clock frequency are expected. This will eliminate timing violations that may otherwise occur during normal operational accesses.BA1=0BA0=0BA0=1BA1=0BA1=0BA1=0BA0=0BA1=1BA1=1BA0=0BA0=1- Full Array- 1/2 Array- 1/4 ArrayBA1=1BA1=1BA1=0BA1=0BA0=0BA0=1BA1=1BA0=1BA0=0BA0=0BA0=1BA1=1BA0=1Partial Self Refresh Area256M: 8M x 32 Mobile DDR SDRAMTable 12: MODE REGISTER FIELD TABLE TO PROGRAM MODESRegister Programmed with Normal MRS NOTE :1. RFU(Reserved for future use) should stay “0” during MRS cycle.Table 13: Normal MRS Mode1. MRS can be issued only at all bank precharge state.2. Minimum tRP is required to issue MRS command.Address BA0 ~ BA1A11 ~ A10/APA9A8A7A6A5A4A3A2A1A0Function "0" Setting for Normal MRSRFU *1Operating ModeCAS LatencyBTBurst LengthOperating ModeCAS Latency Burst TypeBurst Length A8A7TypeA6A5A4Latency A3Type A2A1A0DDR 00Mode Register Set000Reserved 0Sequential 000Reserved01Reserved 001Reserved1Interleave 001210Reserved 0102Mode Select 010411Reserved0113BA1BA0Mode0118---100Reserved 0Setting for Nor-mal MRS10016---101Reserved101Reserved ---110Reserved 110Reserved ---111Reserved111Reserved。
埃森平板电源电路保护器Eaton MPS8323MEAXX2C说明书
Eaton MPS8323MEAXX2CEaton Magnum low voltage power circuit breaker, Magnum PXR,Standard frame, 3200 A, 85 kA, Three-pole, Drawout vertical withmotorized racking mounting, PXR20 LSIG trip unitGeneral specificationsEaton Magnum low voltage power circuitbreakerMPS8323MEAXX2C78668962759114.6 in16.8 in16.2 in118 lbCE Marked SABA Listed NEMA Compliant CCC Marked Lloyd's Register Certified UL ListedCSA CertifiedKEMA CertifiedANSIABS CertifiedDNV GL CertifiedProduct Name Catalog NumberUPCProduct Length/Depth Product Height Product Width Product Weight Compliances CertificationsStandard Three-pole Magnum PXRStandard Magnum PXR20 LSIGThree-pole3200 A85 kAIC85 kAIC3200 AZone selective interlocking application paper Magnum circuit breakers with Power Xpert Release trip units product aid Selevctive coordination application paper - IA0120000E3Magnum PXR and PD-SB standard and narrow frame UL Certificate of ComplianceMagnum PXR and PD-SB double and double narrow frame UL Certificate of ComplianceMicrosoft Word - Power Xpert Protection Manager Quick Start Guide.docxMagnum PXR low voltage power circuit breakers user manual Power Xpert Release trip unit for Magnum PXR circuit breakers PXRFrame Number of poles TypeFrame Series Trip Type Number of poles Rated uninterrupted current (Iu)Interrupt rating Interrupt rating Rated uninterrupted current (Iu)Application notesBrochuresCatalogsCertification reportsManuals and user guidesEaton Corporation plc Eaton House30 Pembroke Road Dublin 4, Ireland © 2023 Eaton. All Rights Reserved. Eaton is a registered trademark.All other trademarks areproperty of their respectiveowners./socialmedia20/25 user manualPower Xpert Protection Manager x64 22.6 1 Power Xpert Protection Manager x32 22.06 1 Eaton Specification Sheet - MPS8323MEAXX2C Low voltage circuit breakers guide spec Magnum PXR 20/25 electronic trip units time current curves Safer by design: arc energy reduction techniques Cyber security white paperMolded case and low-voltage power circuit breaker healthSoftware, firmware, and applications Specifications and datasheetsTime/current curvesWhite papers。
mt6582中文规格书(部分)
mt6582HSPA +手机应用处理器技术简明1系统概述mt6582是一个高度集成的基带平台使用调制解调器，应用处理和连接子系统使3G智能手机上的应用。
芯片集成了四核ARM®Cortex-A7 mpcoretm操作高达 1.3GHz，手臂®cortex-r4单片机和强大的多标准的视频加速器。
mt6582 NAND闪存的接口，为获得最佳性能，还支持启动SLC NAND或eMMC减少整体成本LPDDR2和LPDDR3的。
此外，一组广泛的接口，包括接口的摄像头，触摸屏显示，与MMC / SD卡。
应用处理器，四核ARM®Cortex-A7 mpcoretm包括霓虹多媒体处理引擎，提供处理能力要随着它的要求苛刻的应用，如网页浏览，电子邮件的最新openos支持，GPS导航和游戏。
都是在一个高分辨率的触摸屏显示图形的三维图形加速增强视。
多标准视频加速器和一个先进的音频子系统还包括提供先进的多媒体应用和服务，如音频和视频流，众多的解码器和编码器如H.264，MPEG-4。
音频支持包括法国，人力资源，财务，人力资源和AMR FR，AMR宽带AMR 声码器，和弦铃声，如回声消除先进的音频功能，免提扬声器操作和噪声消除。
臂®cortex-r4，DSP，和2G和3G的协处理器提供了一个可支持14级强大的调制解调器（21 Mbps HSDPA 下行链路子系统）和6类（5.76 Mbps）HSUPA上行数据速率以及12级GPRS，边缘。
mt6582包括四无线连接功能，WLAN，蓝牙，GPS，调频接收机。
放在mt6627芯片的射频部分的四块。
四先进的无线技术集成到一个芯片，mt6582 / mt6627提供最便捷的连接解决方案，在工业。
mt6582 / mt6627实施先进的无线技术共存的算法和硬件机制。
它还支持单天线2.4 GHz天线蓝牙共享，为GPS和1.575 GHz WLAN。
开关电源磁芯参数
开关电源磁芯参数MnZn功率铁氧体EPC 功率磁芯特点：具有热阻小、衰耗小、功率大、工作频率宽、重量轻、结构合理、易表面贴装、屏蔽效果好等优点，但散热性能稍差。
用途：广泛应用于体积小而功率大且有屏蔽和电磁兼容要求的变压器，如精密仪器、程控交换机模块电源、导航设备等。
EPC 型功率磁芯尺寸规格磁芯型号尺寸 Dimensions(mm)Type A B C D Emin F G Hmin EPC10/810.20 ±0.20 4.05 ±0.30 3.40 ±0.20 5.00 ±0.207.60 2.65 ±0.20 1.90 ±0.20 5.30 EPC13/1313.30 ±0.30 6.60 ±0.30 4.60 ±0.20 5.60 ±0.2010.50 4.50 ±0.30 2.05 ±0.208.30 EPC17/1717.60 ±0.508.55 ±0.30 6.00 ±0.307.70 ±0.3014.30 6.05 ±0.30 2.80 ±0.2011.50 EPC19/2019.60 ±0.509.75 ±0.30 6.00 ±0.308.50 ±0.3015.807.25 ±0.30 2.50 ±0.2013.10 EPC25/2525.10 ±0.5012.50 ±0.308.00 ±0.3011.50 ±0.3020.659.00 ±0.30 4.00 ±0.2017.00 EPC27/3227.10 ±0.5016.00 ±0.308.00 ±0.3013.00 ±0.3021.6012.00 ±0.30 4.00 ±0.2018.50 EPC30/3530.10 ±0.5017.50 ±0.308.00 ±0.3015.00 ±0.3023.6013.00 ±0.30 4.00 ±0.2019.50 EPC39/3939.00 ±0.5019.60 ±0.3015.60 ±0.3018.00 ±0.3030.7014.00 ±0.3010.00 ±0.3024.50 EPC42/4442.40 ±1.00 22.00 ±0.30 15.00 ±0.40 17.00 ±0.30 33.50 16.00 ±0.30 7.40 ±0.3026.50EPC46/4946.00 ±1.0024.80 ±0.3019.50 ±0.4020.80 ±0.4035.7018.40 ±0.4011.90 ±0.3028.40EPC46.5/4446.50 ±1.0022.30 ±0.3019.40 ±0.4021.00 ±0.4036.9015.80 ±0.4012.00 ±0.3029.40EPC54/5454.50 ±1.2027.20 ±0.3021.50 ±0.4026.50 ±0.4043.0019.30 ±0.4014.00 ±0.3034.30EPC 功率磁芯电气特性及有效参数有效参数 Effective parameters 磁芯型号材质AL(nH/N2)C1Le Ae Ve重量功耗约设计功率（ W）Type Material±25%(mm-1)(mm)(mm2)(mm3)(g/PRS)(W/PRS,max)1KHz/0.25v EPC10/8TP4950 1.9017.89.39167 1.10.133 EPC13/13TP4830 2.4530.612.5382 2.10.246 EPC17/17TP41150 1.7640.222.8917 4.50.5213 EPC19/20TP4900 2.0346.122.71047 5.30.6115 EPC25/25TP41550 1.2859.246.4274713.0 1.5040 EPC27/32TP41550 1.3473.154.6399120.0 2.3060 EPC30/35TP41500 1.3481.661497723.0 2.6570 EPC39/39TP442500.53901691521073.08.40220 EPC42/44TP428000.56951691605578.49.02235 EPC46/49TP441000.49111.222725242122.414.08360 EPC46.5/44TP448000.4410122923129125.014.38370 EPC54/54TP460000.39130.833643949200.023.00600注：AL 值测试条件为1KHz,0.25v,100Ts,25 ±3℃Pc值测试条件为 100KHz,200mT,100 ℃EE 、 EEL 、EF 型功率磁芯特点：引线空间大，绕制接线方便。
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元器件交易网EM MICROELECTRONIC-MARIN SA Voltage Detector, High-PrecisionDescriptionThe EM6352 is an ultra-low current voltage detector available in a large variety of configurations and very small packages for maximum flexibility in all end-applications up to 125°C and using power supplies between 1.5V and 5.5V. This circuit monitors the supply voltage of any electronic system, and generates the appropriate reset signal without a delay time. The threshold defines the minimum allowed voltage which guarantees the good functionality of the system. As long as VDD stays above the threshold voltage, the output stays inactive. If VDD drops below VTH, the output goes active. The output is guaranteed to be in the correct state for VDD down to 0.8V. There are 12 reset threshold voltages starting as low as 1.31V and up to 4.63V. The EM6352 features three output types: active-low push-pull, active-low open-drain and active-high push-pull. Small SC70 and SOT23 packages as well as ultra-low supply current of 2.7µA make the EM6352 an ideal choice for portable and battery-operated devices.EM6352Features! ! ! !Ultra-low supply current of 2.7µA (VDD=3.3V) Operating temperature range: -40°C to +125°C ±1.5% reset threshold accuracy 12 reset threshold voltages VTH: 4.63V, 4.4V, 3.08V, 2.93V, 2.63V, 2.26V, 2.2V, 1.8V, 1.66V, 1.57V, 1.38V, 1.31V 3 reset output options: Active-low RESET push-pull Active-low RESET open-drain Active-high RESET push-pull No external components Immune to short negative VDD transients Guaranteed Reset valid down to 0.8V Threshold hysteresis: 2.1% of VTH Very small SOT23-5L, SOT23-3L, SC70-3L and SC70-4L (SC-82AB) packages!! ! ! ! !Typical ApplicationVDD VDD RESET*VDD RESETApplications! ! ! ! ! ! ! ! !EM6352GNDMPU, DSPGNDGND* REXT for open-drain version onlyPin Configuration (top view)RESET 1 (RESET) VDD GND 2 3 4 NC GND 2 5 NC RESET 1 (RESET) 3 VDDMobile and cordless phones Modems Printers TV, VCR, Video sets GPS Toys Basestations NiCd cell battery Automotive systemsBlock DiagramVDD Voltage ReferenceSOT23-5LRESET 1 (RESET) VDD 2 4 GND 3 NC GND RESET (RESET)SOT23-3L1 3 VDD 2+RESET (RESET)SC70-4L (SC-82AB)SC70-3LGNDPin DescriptionSOT23-5L SOT23-3L Pin SC70-4L SC70-3L Name Function Active-low RESET output. RESET remains low while VDD is below the reset threshold voltage.Active-high RESET output. RESET remains high while VDD is below the reset threshold voltage. Supply Voltage (5.5V max.) Ground Not connected. Not internally connectedRESET1 1 1 2 RESET 2 3 4, 5 3 2 2 4 3 3 1 VDD GND N.C.Copyright © 2006, EM Microelectronic-Marin SA 03/06 – rev.I1元器件交易网EM6352Ordering InformationEM6352 X SP3B - 2.9 +Reset Output Type: X = Active-low /RES push-pull Y = Active-low /RES open-drain Z = Active-high RES push-pull RoHS Compliance: + = lead-free/green mold compliant [blank] = leaded Reset Threshold Voltage (VTH): 1.3 = 1.31V 2.26 = 2.26V 1.4 = 1.38V 2.6 = 2.63V 1.6 = 1.57V 2.9 = 2.93V 1.7 = 1.66V 3.1 = 3.08V 1.8 = 1.80V 4.4 = 4.40V 2.2 = 2.20V 4.6 = 4.63VPackage: SP3B = SOT23-3, Tape&Reel 3000 pcs SP5B = SOT23-5, Tape&Reel 3000 pcs SC3B = SC70-3, Tape&Reel 3000 pcs SC4B = SC70-4, Tape&Reel 3000 pcsNote:subject to availability (see standard versions list below). Please give complete Part Number when ordering.Standard Versions (Top Marking)Top Marking Top 1) Marking with 4 Characters2)Part NumberPart NumberTop 1) MarkingTop Marking 2) with 4 CharactersEM6352XSP3B-1.3 EM6352XSP3B-1.8 EM6352XSP3B-1.8+ EM6352XSP3B-2.2 EM6352XSP3B-2.2+ EM6352XSP3B-2.26 EM6352XSP3B-2.26+ EM6352XSP3B-2.6 EM6352XSP3B-2.6+ EM6352XSP3B-2.9 EM6352XSP3B-2.9+ EM6352XSP3B-4.6 EM6352XSP3B-4.6+ EM6352XSP5B-1.3 EM6352XSP5B-1.8 EM6352XSP5B-2.6 EM6352XSP5B-2.9 EM6352XSP5B-4.61)K3## K5## K7##K8## KE##AKAA AKAE BKAE AKAF BKAF AKAY BKAY AKAG BKAG AKAH BKAH AKAL BKAL AKAA AKAE AKAG AKAH AKALEM6352XSC3B-1.3 EM6352XSC3B-1.8 EM6352XSC3B-2.2 EM6352XSC3B-2.2+ EM6352XSC3B-2.6 EM6352XSC3B-2.9 EM6352XSC3B-2.9+ EM6352XSC3B-4.6 EM6352XSC3B-4.6+ EM6352YSP3B-2.26 EM6352YSP3B-2.6 EM6352YSP3B-2.9 EM6352YSC3B-2.6 EM6352YSC3B-4.6 EM6352YSC4B-1.3 EM6352YSC4B-2.9 EM6352YSC4B-3.1K5## K8##AKAA AKAE AKAF BKAF AKAG AKAH BKAH AKAL BKAL AKAZ AKAT AKAU AKAT AKAX AKAM AKAU AKAVTop marking is the standard from 2006. No bottom marking exists. Where ## refers to the lot number (EM internal reference only) 2) Top marking with 4 characters is standard from 2003. For lead-free/green mold (RoHS) parts, the first letter of top marking with 4 characters begins with letter “B” instead of letter “A”. Bottom marking indicates the lot number.Standard Versions (samples)Part NumberEM6352XSC3B-2.2+ EM6352XSC3B-2.9+ EM6352XSC3B-4.6+ EM6352XSP3B-2.2 EM6352XSP3B-2.26+Part NumberEM6352XSP3B-2.6+ EM6352XSP3B-2.9+ EM6352XSP3B-4.6+ EM6352YSC4B-3.1 EM6352YSP3B-2.2Sample stock is generally held on standard versions only. Non standard versions have a 30,000 pieces minimum order quantity. Please contact factory for other versions not shown here and for availability of non standard versions.Copyright © 2006, EM Microelectronic-Marin SA 03/06 – rev.I2元器件交易网EM6352Absolute Maximum RatingsParameter Voltage at VDD to GND Minimum voltage at any signal pin Maximum voltage at any signal pin Electrostatic discharge max. to MIL-STD-883C method 3015.7 with ref. to VSS Max. soldering conditions Storage Temperature Range Symbol VDDVMIN VMAX VESD TMAX TSTGHandling ProceduresConditions -0.3V to +6VGND - 0.3V VDD + 0.3V 2000V 250°C x 10s -65°C to +150°C This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the voltage range. Unused inputs must always be tied to a defined logic voltage level.Operating ConditionsParameter Supply voltage (note 1) Operating Temperature Symbol Min Max Unit VDD 0.8 5.5 V TA -40 +125 °CStresses above these listed maximum ratings may cause permanent damages to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.Electrical CharacteristicsUnless otherwise specified: VDD= 0.8V to 5.5V, TA=+25°C (note 1). Parameter Symbol Conditions +25°C VDD=1.5V -40°C to +125°C Supply current (note 2) IDD VDD=3.3V VDD=5.0V +25°C -40°C to +125°C +25°C -40°C to +125°CMin 1.290 1.359 1.546 1.635 1.773 2.167 2.226 2.591 2.886 3.034 4.334 4.561Typ2.1 2.7 3.2 1.31 1.38 1.57 1.66 1.80 2.20 2.26 2.63 2.93 3.08 4.40 4.63Max 4.57 5.4 8.3 6.3 9.6 1.330 1.401 1.594 1.685 1.827 2.233 2.294 2.669 2.974 3.126 4.466UnitµAEM6352 – 1.3 EM6352 – 1.4 EM6352 – 1.6 EM6352 – 1.7 EM6352 – 1.8 Threshold voltage (note 3) VTH EM6352 – 2.2 EM6352 – 2.26 EM6352 – 2.6 EM6352 – 2.9 EM6352 – 3.1 EM6352 – 4.4 EM6352 – 4.6V4.699 Threshold voltage ∆VTH TA = -40°C to +125°C ppm/°C temperature coefficient ±50 ∆TA (note 4) Threshold hysteresis VHYS 2.1%•VTH V Note 1: Production tested at +25°C only. Over temperature limits are guaranteed by design, not production tested. VDD min=0.9V for active-high versions (EM6352Z). Note 2: RESET (RESET) open. Note 3: Threshold voltage is specified for VDD falling. Note 4: Typical variation ∆VTH of VTH at a given temperature TA is calculated as follows:∆VTH (T = TA ) = ∆VTH × VTH × TA − 25°C ∆TAExample: -6 for version VTH=2.93V, variation at TA=70°C is equal to ∆VTH(70°C)=±50•10 x 2.93 x (70-25)=±6.59mVCopyright © 2006, EM Microelectronic-Marin SA 03/06 – rev.I3元器件交易网EM6352Electrical CharacteristicsParameterReset timeout period Propagation delay time VDD to RESET (RESET) delay Open-drain RESET output Voltage(continued)Unless otherwise specified: VDD= 0.8V to 5.5V, TA=+25° C (note 1).SymboltPOR tP VOLConditionsVDD from 0V to VTH (typ)+15% (note 2) VDD drops from VTH (typ)+0.2V to VTH (typ)-0.2V (note 2) VDD>1V -40°C to +125°C VDD>2.5V VDD>5V VDD>1V IOL=100µA IOL=1.5mA IOL=3mA IOL=100µA IOL=1.5mA IOL=3mA IOH=-30µA IOH=-1.5mA IOH=-3mAMin9 2 0.8 2 4Typ500 130 -Max1090 255 0.3 0.3 0.3 0.3 0.3 0.3 -Unit µs µsVVOL Push-pull RESET / RESET Output voltage VOH-40°C to +125°CVDD>2.5V VDD>5V VDD>1VV-40°C to +125°CVDD>2.5V VDD>5VOutput leakage current ILEAK -40°C to +125°C, only for EM6352Y (open-drain) 0.5 Note 1: Production tested at +25°C only. Over temperature limits are guaranteed by design, not production tested. VDD min=0.9V for active-high version (EM6352Z). Note 2: RESET (RESET) open.µATiming WaveformsVDD VTHtSENOverdriveVHYS0.8V t logic "1" RESET logic "0" t logic "1"tPOR tPRESET RESETlogic "0" tNote 5: tSEN = Maximum Transient Duration. Please refer to figure on next page. Note 6: Overdrive = VTH- -VDD. Please refer to figure on next page.Copyright © 2006, EM Microelectronic-Marin SA 03/06 – rev.I4元器件交易网EM6352Typical Operating Characteristics(Typical values are at TA=+25°C unless otherwise noted, RESET or RESET open.)7 6 5 [ uA ] 4 3 2 1 0 -50VDD 1. 5 V VDD 5 . 0 V VDD 3 . 3 V300 250 200 [ us ] 150 100 50 0 -50 -25-2502550 [ °C ]75100 1250255075100 125[ °C ]IDD vs. TemperaturePropagation Time tP vs. Temperature2500 2000 1500 [ us ] 1000 500 0 -50 -25400 350 300 [ us ] 250 200 150 100 50 0 25 50 75 100 125 0 1 10 [ mV ] 100 1000 Reset occurs above this line[ °C ]Reset Timeout Period tPOR vs. TemperatureMaximum Transient Duration tSEN vs. Overdrive VTH-VDD8% 6% 4% 2% 0% -2% -4% -6% -8% -50 -25 0 25 50 75 100 125 [°C]Threshold Voltage Variation vs. Temperature (normalized)Copyright © 2006, EM Microelectronic-Marin SA 03/06 – rev.I5元器件交易网EM6352Package InformationDA1 A2 ASOT23-3LEC LBH eSYMBOL A A1 A2 B C D E e e1 H L MIN 0.89 0.013 0.95 0.37 0.085 2.80 1.20 1.78 2.10e1TYP MAX 1.04 1.12 0.10 0.97 1.00 0.51 0.12 0.18 2.95 3.04 1.32 1.40 0.95 1.90 2.05 2.40 2.64 0.55Dimensions are in mmDA1 A2 ASOT23-5LE1C Lb eSYM BOL A A1 A2 b C D E E1 e e1 LEM IN 0.90 0.05 0.90 0.35 0.08 2.80 2.60 1.50e1TYP M AX 1.30 1.45 0.08 0.15 1.15 1.30 0.50 0.20 2.90 3.00 2.80 3.00 1.75 0.95 1.90 0.45Dimensions are in mmCopyright © 2006, EM Microelectronic-Marin SA 03/06 – rev.I6元器件交易网EM6352Package Information (continued)D b LSC70-3LHEEPIN 1eeQ1cSYMBOL e D b E HE Q1 A2 A1 A c LMIN MAX 0.65 BSC 1.80 2.20 0.25 0.40 1.15 1.35 1.80 2.40 0.10 0.40 0.80 1.00 0.00 0.10 0.80 1.10 0.10 0.18 0.10 0.30A2AA1NOTE: " All dimensions are in millimeters " Dimensions are inclusive of plating " Dimensions are exclusive of mold flash & metal burr " All specifications comply to EIAJ SC70D e eSC70-4LLHEEPIN 1e1 b b1 Q1A2AA1c NOTE: " All dimensions are in millimeters " Dimensions are inclusive of plating " Dimensions are exclusive of mold flash & metal burr " All specifications comply to EIAJ SC70 " Even though the width of pin 2 on SC70-4L is slightly larger than on socalled 4-pin SC-82AB, the footprint of SC70-4L package is compatible with the footprint of SC-82AB package from other suppliers, and thus suitable for pin-to-pin replacement. Please check footprint on PCB.SYMBOL e e1 D b b1 E HE Q1 A2 A1 A c LMIN MAX 0.65 BSC 0.5 BSC 1.80 2.20 0.15 0.30 0.575 0.70 1.15 1.35 1.80 2.40 0.10 0.40 0.80 1.00 0.00 0.10 0.80 1.10 0.10 0.18 0.10 0.30Traceability for small packagesDue to the limited space on the package surface, the bottom marking contains a limited number of characters that provide only partial information for lot traceability. Full information for complete traceability is however provided on the packing labels of the product at delivery from EM. It is highly recommended that the customer insures full lot traceability of EM product in his final product.EM Microelectronic-Marin SA (EM) makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in EM's General Terms of Sale located on the Company's web site. EM assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of EM are granted in connection with the sale of EM products, expressly or by implications. EM's products are not authorized for use as components in life support devices or systems.Product qualification is performed according to internal EM quality standards for industrial products. For any special requirement (eg. automotive grade) please contact EM Microelectronic-Marin S.A.Copyright © 2006, EM Microelectronic-Marin SA 03/06 – rev.I7。