IC datasheet pdf-UA9637A,pdf(Dual Differential Line Receiver)

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IC datasheet pdf-ADS7846,pdf(Touch-Screen Controller)

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NOTE: (1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI web site at .
US Patent No. 6246394 QSPI and SPI are registered trademarks of Motorola.
+VCC
X+ X–
Temperature Sensor
SAR
Y+ Y–
ADS7846
DOUT BUSY
Comparator 6-Channel MUX CDAC Serial Data Out CS
ADS7846
ADS 7846
AD S784 6
®
AD
S784
6
SBAS125H – SEPTEMBER 1999 – REVISED JANUARY 2005
TOUCH SCREEN CONTROLLER
FEATURES
q SAME PATION q INTERNAL 2.5V REFERENCE q q q q DIRECT BATTERY MEASUREMENT (0V to 6V) ON-CHIP TEMPERATURE MEASUREMENT TOUCH-PRESSURE MEASUREMENT QSPITM/SPITM 3-WIRE INTERFACE
PENIRQ

A3150光耦DataSheet

U E D P R O D U C T E F E R E N C E O N L Y .U250 f o r n e w d e s i g n Data Sheet 27621.40The A3150JLT and A3150JUA programmable switches provide tooth/valley recognition in large gear-tooth sensing applications. Each sensor consists of a single element, chopper-stabilized Hall-effect IC that can be programmed to the desired magnetic switch point, opti-mizing sensor airgap and timing accuracy performance after final packaging. The small package can be easily assembled and used in conjunction with a wide variety of gear/target shapes and sizes. The two devices differ only in package style.The sensing technology used for this sensor is Hall-effect based.The sensor incorporates a single-element Hall IC that switches inresponse to magnetic signals created by a ferrous target. The program-mability of the circuit eliminates magnet and system offsets such as those caused by tilt yet provides zero-speed detection capabilities without the associated running jitter inherent in classical digital solu-tions.A proprietary dynamic offset cancelation technique, with an internal high-frequency clock, reduces the residual offset voltage,which is normally caused by device overmolding, temperaturedependancies, and thermal stress. This technique produces devices that have an extremely stable quiescent output voltage, are immune to mechanical stress, and have precise recoverability after temperature cycling. Many problems normally associated with low-level analog signals are minimized by having the Hall element and amplifier in a single chip. Output precision is obtained by internal gain adjustments during the manufacturing process and operate-point programming in the user’s application.This sensor system is ideal for use in gathering speed, position, and timing information using gear-tooth-based configurations. TheA3150JLT/JUA are particularly suited to those applications that require accurate duty cycle control or accurate edge detection. The lower vibration sensitivity also makes these devices extremely useful for transmission speed sensing.3150Always order by complete part number: the prefix 'A' + the basic four-digit part number + a suffix to indicate operating temperature range +a suffix to indicate package style, e.g., A3150JLT .PROGRAMMABLE, CHOPPER-STABILIZED, HALL-EFFECT SWITCHContinued next page115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-********PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHCopyright © 2000, Allegro MicroSystems, Inc.Two package styles provide a magnetically opti-mized package for most applications. Suffix ‘–LT’ is a miniature SOT-89/TO-243AA transistor package for surface-mount applications; while suffix ‘–UA’ is a three-lead ultra-mini-SIP for through-hole mounting.FEATURES AND BENEFITSs Chopper Stabilized forExtremely Low Switch-Point Drift and Immunity to Mechanical Stresss Externally Programmed Switch Point s On-Chip Supply-Transient Protection s Output Short-Circuit Protections Single-Chip Sensing IC for High Reliability s Small Mechanical Size s <50µs Power-On Times Wide Operating Voltage Range s Defined Power-On State3150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHLimitsCharacteristic Symbol Test ConditionsMin.Typ.Max.Units Operate PointB OPProgrammable offset range 500670850G Initial (before programming)02040G Resolution8.01114G ∆B OPV CC = 14 V, after programming, B OP ≈ 500 G-358.0+35G HysteresisB hys5.02035GNOTE: Typical data is at V CC = 5 V and T A = +25°C and is for design information only.ELECTRICAL CHARACTERISTICS over operating voltage and temperature range (unless otherwise noted).LimitsCharacteristic Symbol Test Conditions Min.Typ.Max.Units Supply Voltage V CC Operating, T J < 165°C4.25–26V Power-On State POS After programming, V CC = 0 ¡ 5 V HIGH HIGH HIGH –Low Output Voltage V OUT(SAT)I OUT = 20 mA –175400mV Output Current Limit I OUTM V OUT = 12 V 658095mA Output Leakage Current I OFF V OUT = 24 V–0.210µA Supply CurrentI CCBefore programming, output OFF – 4.07.0mA Before programming, output ON– 5.08.0mA Reverse Supply Current I RCC V RCC = -30 V ––-5.0mA Power-On Delay t on V CC > 5 V–2050µs Output Rise Time t r R L = 820 Ω, C L = 20 pF –200–ns Output Fall Time t f R L = 820 Ω, C L = 20 pF–100–ns Clock Frequency f C –340–kHz Zener Voltage V Z I ZT = 100 µA, T A = 25°C 2732–V Zener Impedancez zI ZT = 10 mA, T A = 25°C –50100ΩNOTE: Typical data is at V CC = 5 V and T A = +25°C and is for design information only.MAGNETIC CHARACTERISTICS over operating supply voltage and temperature ranges.115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHTYPICAL ELECTRICAL CHARACTERISTICS255075100AMBIENT TEMPERATURE IN °C-50Dwg. GH-053-2125-25S U P P L Y C U R R E N T I N m A5.04.03.02.01.015010152025SUPPLY VOLTAGE IN VOLTSDwg. GH-041-25S U P P L Y C U R R E N T I N m A10300AMBIENT TEMPERATURE IN °C200Dwg. GH-040-4S A T U R A T I O N V O L T A G E I N m V3150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHFUNCTIONAL DESCRIPTIONChopper-Stabilized Technique. These devices use a proprietary dynamic offset cancellation technique, with an internal high-frequency clock to reduce the residual offset voltage of the Hall element that is normally caused by device overmolding, temperature dependencies, and thermal stress.This technique produces devices that have an extremely stable quiescent Hall output voltage, are immune to thermal stress, and have precise recoverability after temperature cycling. Thistechnique will also slightly degrade the device output repeatabil-ity.The Hall element can be considered as a resistor arraysimilar to a Wheatstone bridge. A large portion of the offset is a result of the mismatching of these resistors. The chopper-stabilizing technique cancels the mismatching of the resistors by changing the direction of the current flowing through the Hall plate and Hall voltage measurement taps, while maintaining the Hall-voltage signal that is induced by the external magnetic flux.The signal is, then, captured by a sample-and-hold circuit.Operation. The output of these devices switches low (turns ON) when a magnetic field (south pole) perpendicular to the Hall sensor exceeds the operate point threshold (B OP ). After turn-ON, the output is capable of sinking 25 mA and the output voltage is V OUT(SAT). When the magnetic field is reduced below the release point (B RP ), the device output goes high (turns OFF).The difference in the magnetic operate and release points is the hysteresis (B hys ) of the device. This built-in hysteresis allows clean switching of the output even in the presence of external mechanical vibration and electrical noise.Applications. It is strongly recommended that an external bypass capacitor be connected (in close proximity to the Hall sensor) between the supply and ground of the device to reduce both external noise and noise generated by the chopper-stabiliza-tion technique.The simplest form of magnet that will operate these devices is a bar magnet with the south-seeking pole towards the branded surface of the device. Many other methods of operation are possible. Extensive applications information on magnets and Hall-effect sensors is also available in the Allegro Electronic Data Book AMS-702 or Application Note 27701, orO U T P U T V O L T A G EFLUX DENSITYDwg. GH-007-2115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHPROGRAMMING PROTOCOLThe A3150JLT and A3150JUA operate points are pro-grammed by serially addressing the device through the supply terminal (pin1). After the correct operate point is determined, the device programming bits are selected and then a “lock” set to prevent any further (accidental)programming.Program Enable. To program the device, a sequence of pulses is used to activate/enable the addressing mode as shown in figure 1. This sequence of a V PP pulse, at least seven V PH pulses, and a V PP pulse with no supply interrup-tions, is designed to prevent the device from being pro-grammed accidentally (for example, as a result of noise on the supply line).VV V Dwg. WH-013Figure 1 — Program enablePROGRAMMING PROTOCOL over operating temperature range.LimitsCharacteristic Symbol DescriptionMin.Typ.Max.Units Programming VoltageV PL Minimum voltage during programming4.55.0 5.5V V PH 9.01011V V PP202325V Programming Current I PP Max. supply current during programming –250–mA Pulse Widtht d(0)OFF time between bits20––µs t d(1)Enable, address, program, or lock bit ON time 20––µs t dPProgram pulse ON time 100300–µs Pulse Rise Time t r V PL to V PH or V PP 11––µs Pulse Fall Timet fV PH or V PP to V PL 5.0––µsNOTE: Typical data is at T A = +25°C and is for design information only.3150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCH* In application, the terms “gear” and “target” are often interchanged. However, “gear” is preferred when motion is transferred.Address Determination. The operate point is adjust-able in 64 increments. With the appropriate target or gear*in position, the 64 switch points are sequentially selected (figure 2) until the required operate point is reached. Note that the difference between the operate point and the release point (hysteresis) is a constant for all addresses.Set-Point Programming. After the desired set-point address is determined (0 through 63), each bit of theequivalent binary address is programmed individually. For example, as illustrated in figure 3, to program address code 5 (binary 000101), bits 1 and 3 need to be programmed.Each bit is programmed during the wide V PP pulse and is not reversible.Lock Programming. After the desired set point is programmed, the program lock is then activated (figure 4)to prevent further programming of the device.V PV 0Dwg. WH-014A D D R E S S 0A D D R E S S 1A D D R E S S 2A D D R E S S N (UP T O 63)A D D R E S S N -1A D D R E S S N -2Figure 2 — Address determinationFigure 4 — Lock programmingV V VDwg. WH-016Figure 3 — Set-point programmingV V V Dwg. WH-015A115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHAll Allegro sensors are subjected to stringent qualification requirements prior to being released to production.To become qualified, except for the destructive ESD tests, no failures are permitted.CRITERIA FOR DEVICE QUALIFICATIONQualification Test Test Method and Test Conditions Test Length SamplesComments Biased Humidity (HAST)T A = 130°C, RH = 85%50 hrs 77V CC = V OUT = 5 V High-Temperature JESD22-A108,408 hrs77V CC = 24 V,Operating Life (HTOL)T A = 150°C, T J = 165°C V OUT = 20 V Accelerated HTOLJESD22-A108,504 hrs 77V CC = 24 V,T A = 175°C, T J = 190°C V OUT = 20 VAutoclave, Unbiased JESD22-A102, Condition C,96 hrs 77T A = 121°C, 15 psig High-Temperature MIL-STD-883, Method 1008,1000 hrs 77(Bake) Storage Life T A = 170°CTemperature CycleMIL-STD-883, Method 1010,500 cycles 77-65°C to +150°C Latch-Up—Pre/Post 6Reading Electro-Thermally—Pre/Post 6Induced Gate Leakage Reading ESD,CDF-AEC-Q100-002Pre/Post x per Test to failure,Human Body Model Reading test All leads > TBDElectrical DistributionsPer Specification—303150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHSENSOR LOCATIONS(±0.005” [0.13 mm] die placement)Package Designators “UA” and "UA-TL"Although sensor location is accurate to three sigma for a particular design, product improvements may result in small changes to sensor location.Dwg. MH-008-80.030"0.76 mm NOMDwg. MH-011-9APackage Designator “LT”115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCH0.440.35PACKAGE DESIGNATOR 'LT'(SOT-89/TO-243AA)Dimensions in Inches (for reference only)Dimensions in Millimeters (controlling dimensions)Dwg. MA-012-3 mmPads 1, 2, 3, and B — Low-Stress VersionPads 1, 2, and 3 only — Lowest Stress, But Not Self AligningNOTE: Exact body and lead configuration at vendor’s option within limits shown.Dwg. MA-012-3 inads 1, 2, 3, and B — Low-Stress Versionads 1, 2, and 3 only — Lowest Stress, But Not Self Aligning3150 PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCH Surface-Mount Lead Form (Suffix '-TL')Dimensions in Inches (controlling dimensions)Dimensions in Millimeters (for reference only)PACKAGE DESIGNATOR 'UA'Dwg. MH-014E mm1.27BSC°Dwg. MH-014E inBSC°NOTES: 1.Tolerances on package height and width represent allowable mold offsets. Dimensions given are measured at the widest point (parting line).2.Exact body and lead configuration at vendor’s option within limits shown.3.Height does not include mold gate flash.4.Recommended minimum PWB hole diameter to clear transition area is 0.035” (0.89 mm).5.Where no tolerance is specified, dimension is nominal.115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-50003150PROGRAMMABLE, CHOPPER-STABILIZED, PRECISION,HALL-EFFECT SWITCHThe products described herein are manufactured under one or more of the following U.S. patents: 5,045,920; 5,264,783; 5,442,283;5,389,889; 5,581,179; 5,517,112; 5,619,137; 5,621,319; 5,650,719;5,686,894; 5,694,038; 5,729,130; 5,917,320; and other patents pending.Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, ormanufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.Allegro products are not authorized for use as critical components in life-support appliances, devices, or systems without express written approval.The information included herein is believed to be accurate andreliable. However, Allegro MicroSystems, Inc. assumes no responsibil-ity for its use; nor for any infringements of patents or other rights of third parties that may result from its use.。

AAT 器件选型指南.pdf说明书

Part No.
Amplifiers Include
Vcc (V)
Icc
Ptot
(mA) (mW)
Toper Vio Iio (℃) (mV) (nA)
PKG
Replace Brand
LM358 LM393 LM324 LM339
2
16~32 50
500
0~70
2
2
SOP-8/DIP-8
2
2~36 0.4
128*8 256*8 512*8 1028*8 2056*8 5012*8 10024*8
Frequency Icc
Isb
(KHz)
(mA) (µA)
PKG
Replace Brand
Application
400
0.4~3 0.6~18 SOP-8/DIP-8 ATMEL/ISSI/ST/ROHM
400
400
0.4~3 0.6~18 SOP-8/DIP-8 ATMEL/ISSI/ST/ROHM
400
0.4~3 0.6~18 SOP-8/DIP-8 ATMEL/ISSI/ST/ROHM
400
0.4~3 0.6~18 SOP-8/DIP-8 ATMEL/ISSI/ST/ROHM
■ AAT General Line-up
I2-PAK
TO-220AB
TO-220IS
AAT PRODUCTS FOR CUSTOMERS
General Freque
Vcc
Device
ncy
Name
(KHz)
(V)
Vout (V)
Io (A)
7805
---
5~18

IC datasheet pdf-MAXQ1010,pdf (Security Token Microcontroller)

_______________________________________________________________ Maxim Integrated Products 1For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at .MAXQ1010Security Token Microcontroller with RTC and USBNote: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, go to: /errata .19-5259; Rev 0; 4/10Ordering Information continued on last page.+Denotes a lead(Pb)-free/RoHS-compliant package.*Contact factory for availability.**EP = Exposed pad.Selector Guide appears at end of data sheet.General Description The MAXQ1010 is a small, low-cost, low-power securemicrocontroller designed for security token applicationsand battery-powered applications where power andsecurity are both critically important.The microcontroller family contains a 32KB, 64KB, or128KB programmable flash memory that can be usedfor both application code and data storage. Each 512Bflash memory page supports 20,000 erase cycles and is programmable 16 bits at a time. This allows for uniqueschemes to extend the lifetime of the flash. For instance, dedicating four flash pages to store 32B of data that changes very often, the effective number of write cycles can approach 1.2 million (4 x 512 x 20,000/32). The device also contains 1KB or 2KB SRAM. An additional 128B secure key storage SRAM is instantly erased when a self-destruct input is triggered.The microcontroller also contains a hardware DES engi-ne and an AES accelerator, allowing applications to quickly respond to challenges and authenticate other devices using standards-based cryptography. A true-hardware random-number generator (RNG) is available for general application use, such as key generation, challenge generation, and random padding. Firmware and reference designs are available from Maxim for authentication applications.Multiple communication interfaces are implemented; an integrated USB transceiver and serial interface engine make USB applications extremely low cost. Other com-munication options include ISO 7816 UART, SPI K , I 2C, and a standard USART (universal synchronous/asynchro-nous receiver-transmitter). A real-time clock (RTC) is also included for security applications requiring a time base.For the ultimate in low-power battery-operated perfor-mance, an ultra-low-power stop mode (400nA typ) is included. In this mode, the minimum amount of circuitry is powered. Wake-up sources include external interrupts, the power-fail interrupt, a wake-up timer interrupt, and an RTC interrupt.Applications One-Time Password Generator USB Card Readers Features S High-Performance, Low-Power, 16-Bit RISC Core S DC to 12MHz Operation Across Entire Operating Range S 6MHz Internal Oscillator S 12MHz External Crystal (Required for USB Operation)S 1.7V to 3.6V Operating Voltage Range S 33 Total Instructions for Simplified Programming S Three Independent Data Pointers Accelerate Data Movement with Automatic Increment/Decrement S Dedicated Pointer for Direct Read from Code Space S 16-Bit Instruction Word, 16-Bit Data BusS 16 x 16-Bit General-Purpose Working Registers S 1-Wire ® Interface for Debugger and Flash Programming S Security FeaturesDES and AES Hardware AcceleratorsHardware True RNGSelf-Destruct Input Pin128B, Fast Wipe, Secure Secret Key SRAM RTC with Integrated OscillatorS Memory32/64/128KB Flash512-Byte Memory Page Sectors20,000 Erase/Write Cycles per SectorUp to 2KB Data SRAM6KB Utility ROM with User-Callable Routines S I/O and PeripheralsUSB 2.0 SIE and TransceiverSPI and USART I 2C Communication Ports ISO 7816 UART31 General-Purpose I/O PinsUp to 15 External Interrupts AvailableS Low Power ConsumptionSingle 1.7V to 3.6V Supply< 1µA Current in Lowest Power Stop ModeDivided System Clock Modes AvailableS Additional PeripheralsPower-Fail WarningPower-On Reset (POR)Programmable Watchdog TimerOrdering Information MAXQ and 1-Wire are registered trademarks of Maxim Integrated Products, Inc.SPI is a trademark of Motorola, Inc.PART TEMP RANGE PIN-PACKAGEMAXQ1010-A01+-40°C to +85°C 48 TQFN-EP**MAXQ1010X-0000+*-40°C to +85°C Bare dieMAXQ1010Security Token Microcontrollerwith RTC and USB 15 Block Diagram Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet, go to /MAXQ1010 and click on Request Full Data Sheet .。

IC datasheet pdf-LT1013AM,pdf(DUAL PRECISION OPERATIONAL AMPLIFIERS)

LT1013, DUAL PRECISION OPERATIONALLT1013, LT1013A, LT1013D DUAL PRECISION OPERATIONAL AMPLIFIERSLT1013, LT1013A, LT1013D DUAL PRECISION OPERATIONAL AMPLIFIERSLT1013, LT1013A, LT1013D DUAL PRECISION OPERATIONAL AMPLIFIERSLT1013, LT1013A, LT1013D DUAL PRECISION OPERATIONAL AMPLIFIERSLT1013, DUAL PRECISION OPERATIONALLT1013, DUAL PRECISION OPERATIONALPACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)5962-88760012A ACTIVE LCCC FK201TBD POST-PLATE N/A for Pkg Type 5962-8876001PA ACTIVE CDIP JG81TBD A42N/A for Pkg Type 5962-88760022A ACTIVE LCCC FK201TBD POST-PLATE N/A for Pkg Type 5962-8876002PA ACTIVE CDIP JG81TBD A42N/A for Pkg Type LT1013AMFKB ACTIVE LCCC FK201TBD POST-PLATE N/A for Pkg Type LT1013AMJG ACTIVE CDIP JG81TBD A42N/A for Pkg Type LT1013AMJGB ACTIVE CDIP JG81TBD A42N/A for Pkg Type LT1013AMP OBSOLETE PDIP P8TBD Call TI Call TILT1013CD ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013CDE4ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013CDG4ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013CDR ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013CDRE4ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013CDRG4ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013CP ACTIVE PDIP P850Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeLT1013CPE4ACTIVE PDIP P850Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeLT1013DD ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013DDE4ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013DDG4ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013DDR ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013DDRE4ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013DDRG4ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013DID ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013DIDE4ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013DIDG4ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013DIDR ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013DIDRE4ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013DIDRG4ACTIVE SOIC D82500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)LT1013DIP ACTIVE PDIP P850Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeLT1013DIPE4ACTIVE PDIP P850Pb-Free(RoHS)CU NIPDAU N/A for Pkg Type LT1013DMD ACTIVE SOIC D875TBD CU NIPDAU Level-1-220C-UNLIM LT1013DMDG4ACTIVE SOIC D875Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMLT1013DP ACTIVE PDIP P850Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeLT1013DPE4ACTIVE PDIP P850Pb-Free(RoHS)CU NIPDAU N/A for Pkg Type LT1013IP OBSOLETE PDIP P8TBD Call TI Call TILT1013MFKB ACTIVE LCCC FK201TBD POST-PLATE N/A for Pkg Type LT1013MJG ACTIVE CDIP JG81TBD A42N/A for Pkg Type LT1013MJGB ACTIVE CDIP JG81TBD A42N/A for Pkg TypeLT1013MP OBSOLETE PDIP P8TBD Call TI Call TILT1013Y OBSOLETE DIESALE Y0TBD Call TI Call TI(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.TAPE AND REEL INFORMATION*All dimensions are nominal Device Package Type Package DrawingPinsSPQ Reel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant LT1013CDR SOICD 82500330.012.4 6.4 5.2 2.18.012.0Q1LT1013DDR SOICD 82500330.012.4 6.4 5.2 2.18.012.0Q1LT1013DIDR SOIC D 82500330.012.4 6.4 5.2 2.18.012.0Q1*All dimensions are nominalDevice Package Type Package Drawing Pins SPQ Length(mm)Width(mm)Height(mm) LT1013CDR SOIC D8*******.5338.120.6 LT1013DDR SOIC D8*******.5338.120.6 LT1013DIDR SOIC D8*******.5338.120.6IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right, or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does 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UA9637

PACKAGING INFORMATION Orderable DeviceStatus (1)Package Type Package Drawing Pins Package Qty Eco Plan (2)Lead/Ball Finish MSL Peak Temp (3)UA9637ACDACTIVE SOIC D 875Pb-Free (RoHS)CU NIPDAU Level-2-250C-1YEAR UA9637ACDRACTIVE SOIC D 82500Pb-Free (RoHS)CU NIPDAU Level-2-250C-1YEAR UA9637ACJGOBSOLETE CDIP JG 8None Call TI Call TI UA9637ACPACTIVE PDIP P 850Pb-Free (RoHS)CU NIPDAU Level-NC-NC-NC UA9637ACPSRACTIVE SO PS 82000Pb-Free (RoHS)CU NIPDAU Level-2-260C-1YEAR/Level-1-235C-UNLIM (1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan -May not be currently available -please check /productcontent for the latest availability information and additional product content details.None:Not yet available Lead (Pb-Free).Pb-Free (RoHS):TI's terms "Lead-Free"or "Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all 6substances,including the requirement that lead not exceed 0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green (RoHS &no Sb/Br):TI defines "Green"to mean "Pb-Free"and in addition,uses package materials that do not contain halogens,including bromine (Br)or antimony (Sb)above 0.1%of total product weight.(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of thedate that it is provided.TI bases its knowledge and belief oninformation provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.PACKAGE OPTION ADDENDUM 18-Feb-2005Addendum-Page 1IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. T o minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDSP Broadband /broadbandInterface Digital Control /digitalcontrolLogic Military /militaryPower Mgmt Optical Networking /opticalnetwork Microcontrollers Security /securityTelephony /telephonyVideo & Imaging /videoWireless /wirelessMailing Address:Texas InstrumentsPost Office Box 655303 Dallas, Texas 75265Copyright 2005, Texas Instruments Incorporated。

AD9637BCPZ-40;AD9637BCPZ-80;AD9637BCPZRL7-40;AD9637BCPZRL7-80;AD9637-80EBZ;中文规格书,Datasheet资料

Octal, 12-Bit, 40/80 MSPS, Serial LVDS,1.8 V Analog-to-Digital Converter Data Sheet AD9637Rev. 0Information furnished by Analog Devices is believed to be accurate and reliable. However, noresponsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. T rademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, M A 02062-9106, U.S.A. Tel: 781.329.4700 Fax: 781.461.3113 ©2011 Analog Devices, Inc. All rights reserved.FEATURESLow power: 60 mW per channel at 80 MSPS with scalable power optionsSNR = 71.5 dBFS (to Nyquist)SFDR = 92 dBc (to Nyquist)DNL = ±0.4 LSB (typical), INL = ±0.5 LSB (typical)Serial LVDS (ANSI-644, default)Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs650 MHz full power analog bandwidth2 V p-p differential input voltage range1.8 V supply operationSerial port controlFull chip and individual channel power-down modes Flexible bit orientationBuilt-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolutionStandby modeAPPLICATIONSMedical imaging and nondestructive ultrasoundPortable ultrasound and digital beam-forming systems Quadrature radio receiversDiversity radio receiversOptical networkingTest equipmentGENERAL DESCRIPTIONThe AD9637 is an octal, 12-bit, 40/80 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 80 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications.The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled.The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmableFUNCTIONAL BLOCK DIAGRAMDFS DTP10215-1Figure 1.clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). The AD9637 is available in a RoHS-compliant, 64-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. This product is protected by a U.S. patent.PRODUCT HIGHLIGHTS1.Small Footprint. Eight ADCs are contained in a small,space-saving package.2.Low Power of 60 mW/Channel at 80 MSPS with ScalablePower Options.3.Ease of Use. A data clock output (DCO) is provided thatoperates at frequencies of up to 480 MHz and supportsdouble data rate (DDR) operation.er Flexibility. The SPI control offers a wide range offlexible features to meet specific system requirements.5.Pin Compatible with the AD9257 (14-Bit Octal ADC).AD9637Data SheetRev. 0 | Page 2 of 40TABLE OF CONTENTSFeatures..............................................................................................1 Applications.......................................................................................1 General Description.........................................................................1 Functional Block Diagram..............................................................1 Product Highlights...........................................................................1 Table of Contents..............................................................................2 Revision History...............................................................................2 Specifications.....................................................................................3 DC Specifications.........................................................................3 AC Specifications..........................................................................4 Digital Specifications...................................................................5 Switching Specifications..............................................................6 Timing Specifications..................................................................6 Absolute Maximum Ratings............................................................8 Thermal Characteristics..............................................................8 ESD Caution..................................................................................8 Pin Configuration and Function Descriptions.............................9 Typical Performance Characteristics...........................................11 AD9637-80..................................................................................11 AD9637-40..................................................................................14 Equivalent Circuits.........................................................................17 Theory of Operation......................................................................18 Analog Input Considerations....................................................18 Voltage Reference.......................................................................19 Clock Input Considerations......................................................20 Power Dissipation and Power-Down Mode...........................22 Digital Outputs and Timing.....................................................23 Built-In Output Test Modes..........................................................27 Output Test Modes.....................................................................27 Serial Port Interface (SPI)..............................................................28 Configuration Using the SPI.....................................................28 Hardware Interface.....................................................................29 Configuration Without the SPI................................................29 SPI Accessible Features..............................................................29 Memory Map..................................................................................30 Reading the Memory Map Register Table...............................30 Memory Map Register Table.....................................................31 Memory Map Register Descriptions........................................34 Applications Information..............................................................36 Design Guidelines......................................................................36 Power and Ground Recommendations...................................36 Exposed Pad Thermal Heat Slug Recommendations............36 VCM.............................................................................................36 Reference Decoupling................................................................36 SPI Port........................................................................................36 Outline Dimensions.......................................................................37 Ordering Guide.. (37)REVISION HISTORY10/11—Revision 0: Initial VersionData SheetAD9637Rev. 0 | Page 3 of 40SPECIFICATIONSDC SPECIFICATIONSAVDD = 1.8 V , DRVDD = 1.8 V , 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 1.AD9637-40 AD9637-80Parameter 1Temp M in Typ M ax M in Typ M ax Unit RESOLUTION 14 14 Bits ACCURACY No Missing Codes Full Guaranteed Guaranteed Offset Error Full −0.6 −0.3 +0.1 −0.7 −0.3 +0.1 % FSR Offset Matching Full 0.0 0.2 0.6 0.0 0.2 0.6 % FSR Gain Error Full −8.0 −2.1 +2.0 −7.0 −3.2 +1.0 % FSR Gain Matching Full −1.0 +1.7 +5.0 −1.0 +2.3 +6.0 % FSR Differential Nonlinearity (DNL) Full −0.8 ±0.3 +0.8 −0.8 ±0.4 +0.8 LSB Integral Nonlinearity (INL) Full −1.0 ±0.4 +1.0 −1.2 ±0.5 +1.2 LSB TEMPERATURE DRIFT Offset Error Full ±2 ±2 ppm/°C INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Full 0.98 0.99 1.01 0.98 0.99 1.01 V Load Regulation at 1.0 mA (V REF = 1 V) Full 2 2 mV Input Resistance Full 7.5 7.5 kΩ INPUT REFERRED NOISE V REF = 1.0 V 25°C 0.36 0.49 LSB rms ANALOG INPUTS Differential Input Voltage (V REF = 1 V) Full 2 2 V p-p Common-Mode Voltage Full 0.9 0.9 V Differential Input Resistance 5.2 5.2 kΩ Differential Input Capacitance Full 3.5 3.5 pF POWER SUPPLYAVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V DRVDD Full 1.7 1.8 1.9 1.7 1.8 1.9 V I AVDD (Eight Channels) Full 142 151 221 234 mA I DRVDD (Eight Channels, ANSI-644 Mode) Full 51 79 58 85 mA I DRVDD (Eight Channels, Reduced Range Mode) 25°C 36 43 mA TOTAL POWER CONSUMPTION Total Power Dissipation (Eight Channels, ANSI-644 Mode) Full 347 414 502 574 mW Total Power Dissipation (Eight Channels, Reduced Range Mode) 25°C 320 475 mW Power-Down Dissipation 25°C 1 1 mW Standby Dissipation 2 25°C 72 98 mW1 See the AN-835 Application Note , Understanding High Speed ADC Testing and Evaluation , for definitions and for details on how these tests were completed. 2Can be controlled via the SPI.AD9637Data SheetRev. 0 | Page 4 of 40AC SPECIFICATIONSAVDD = 1.8 V , DRVDD = 1.8 V , 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 2.AD9637-40 AD9637-80Parameter 1Temp M in Typ M ax M in Typ M ax Unit SIGNAL-TO-NOISE RATIO (SNR) f IN = 9.7 MHz 25°C 72.0 71.5 dBFS f IN = 19.7 MHz Full 70.0 72.0 71.0 71.5 dBFS f IN = 30.5 MHz 25°C 72.0 71.5 dBFS f IN = 63.5 MHz 25°C 71.5 dBFS f IN = 69.5 MHz 25°C 71.5 dBFS f IN = 123.5 MHz 25°C 70.5 dBFS SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) f IN = 9.7 MHz 25°C 71.0 70.5 dBFS f IN = 19.7 MHz Full 69.0 71.0 70.0 70.5 dBFS f IN = 30.5 MHz 25°C 71.0 70.5 dBFS f IN = 63.5 MHz 25°C 70.5 dBFS f IN = 69.5 MHz 25°C 70.5 dBFS f IN = 123.5 MHz 25°C 69.5 dBFS EFFECTIVE NUMBER OF BITS (ENOB) f IN = 9.7 MHz 25°C 11.5 11.4 Bits f IN = 19.7 MHz Full 11.2 11.5 11.3 11.4 Bits f IN = 30.5 MHz 25°C 11.5 11.4 Bits f IN = 63.5 MHz 25°C 11.4 Bits f IN = 69.5 MHz 25°C 11.4 Bits f IN = 123.5 MHz 25°C 11.3 Bits SPURIOUS-FREE DYNAMIC RANGE (SFDR) f IN = 9.7 MHz 25°C 96 93 dBc f IN = 19.7 MHz Full 78 95 78 92 dBc f IN = 30.5 MHz 25°C 96 92 dBc f IN = 63.5 MHz 25°C 93 dBc f IN = 69.5 MHz 25°C 89 dBc f IN = 123.5 MHz 25°C 88 dBc WORST HARMONIC (SECOND OR THIRD) f IN = 9.7 MHz 25°C −99 −96 dBc f IN = 19.7 MHz Full −96 −78 −92 −78 dBc f IN = 30.5 MHz 25°C −98 −92 dBc f IN = 63.5 MHz 25°C −95 dBc f IN = 69.5 MHz 25°C −89 dBc f IN = 123.5 MHz 25°C −89 dBc WORST OTHER (EXCLUDING SECOND OR THIRD) f IN = 9.7 MHz 25°C −98 −97 dBFS f IN = 19.7 MHz Full −98 −86 −97 −86 dBFS f IN = 30.5 MHz 25°C −98 −97 dBFS f IN = 63.5 MHz 25°C −97 dBFS f IN = 69.5 MHz 25°C −97 dBFS f IN = 123.5 MHz 25°C −92 dBFSTWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS f IN1 = 8 MHz, f IN2 = 10 MHz 25°C 93 dBc f IN1 = 30 MHz, f IN2 = 32 MHz 25°C 85 dBcData Sheet AD9637Rev. 0 | Page 5 of 40 AD9637-40 AD9637-80CROSSTALK 25°C−98−96dBCrosstalk (Overrange Condition)225°C−89−89dBANALOG INPUT BANDWIDTH, FULL POWER 25°C 650 650 MHz1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.2 Overrange condition is specified with3 dB of the full-scale input range.DIGITAL SPECIFICATIONSAVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted.Table 3.Parameter1 TempM inTypM axUnit CLOCK INPUTS (CLK+, CLK−)Logic Compliance CMOS/LVDS/LVPECLDifferential Input Voltage2 Full0.2 3.6Vp-pInput Voltage Range Full AGND − 0.2 AVDD + 0.2 VInput Common-Mode Voltage Full 0.9 VInput Resistance (Differential) 25°C 15 kΩInput Capacitance 25°C 4 pFLOGIC INPUTS (PDWN, SYNC, SCLK)Logic 1 Voltage Full 1.2 AVDD + 0.2 VLogic 0 Voltage Full 0 0.8 VInput Resistance 25°C 30 kΩInput Capacitance 25°C 2 pFLOGIC INPUT (CSB)Logic 1 Voltage Full 1.2 AVDD + 0.2 VLogic 0 Voltage Full 0 0.8 VInput Resistance 25°C 26 kΩInput Capacitance 25°C 2 pFLOGIC INPUT (SDIO)Logic 1 Voltage Full 1.2 AVDD + 0.2 VLogic 0 Voltage Full 0 0.8 VInput Resistance 25°C 26 kΩInput Capacitance 25°C 5 pFLOGIC OUTPUT (SDIO)3Logic 1 Voltage (I OH = 800 μA) Full 1.79 VLogic 0 Voltage (I OL = 50 μA) Full 0.05 VDIGITAL OUTPUTS (D± x), ANSI-644Logic Compliance LVDSDifferential Output Voltage (V OD) Full247350454mVOutput Offset Voltage (V OS) Full1.131.211.38VOutput Coding (Default) Twos complementDIGITAL OUTPUTS (D± x), LOW POWER,REDUCED SIGNAL OPTIONLogic Compliance LVDSDifferential Output Voltage (V OD) Full150200250mVOutput Offset Voltage (V OS) Full1.131.211.38VOutput Coding (Default) Twos complement1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.2 This is specified for LVDS and LVPECL only.3 This is specified for 13 SDIO/DFS pins sharing the same connection.AD9637Data SheetRev. 0 | Page 6 of 40SWITCHING SPECIFICATIONSAVDD = 1.8 V , DRVDD = 1.8 V , 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 4.Parameter 1, 2 Temp M in Typ M ax Unit CLOCK 3 Input Clock Rate Full 10 640 MHz Conversion Rate Full 10 40/80 MSPS Clock Pulse Width High (t EH ) Full 12.5/6.25 ns Clock Pulse Width Low (t EL ) Full 12.5/6.25 ns OUTPUT PARAMETERS 3 Propagation Delay (t PD ) Full 2.3 ns Rise Time (t R ) (20% to 80%) Full 300 ps Fall Time (t F ) (20% to 80%) Full 300 ps FCO Propagation Delay (t FCO ) Full 1.5 2.3 3.1 ns DCO Propagation Delay (t CPD )4 Full t FCO + (t SAMPLE /24) nsDCO to Data Delay (t DATA )4Full (t SAMPLE /24) − 300 (t SAMPLE /24) (t SAMPLE /24) + 300 ps DCO to FCO Delay (t FRAME )4 Full (t SAMPLE /24) − 300 (t SAMPLE /24) (t SAMPLE /24) + 300 psData to Data Skew(t DATA-MAX − t DATA-MIN ) Full ±50 ±200 ps Wake-Up Time (Standby) 25°C 35 μsWake-Up Time (Power-Down)525°C 375 μs Pipeline Latency Full 16 ClockcyclesAPERTURE Aperture Delay (t A ) 25°C 1 ns Aperture Uncertainty (Jitter) 25°C 0.1 ps rms Out-of-Range Recovery Time 25°C 1 Clockcycles1 See the AN-835 Application Note , Understanding High Speed ADC Testing and Evaluation , for definitions and for details on how these tests were completed. 2Measured on standard FR-4 material. 3Can be adjusted via the SPI. 4t SAMPLE /24 is based on the number of bits divided by 2 because the delays are based on half duty cycles. t SAMPLE = 1/f S . 5Wake-up time is defined as the time required to return to normal operation from power-down mode.TIMING SPECIFICATIONSTable 5.ParameterDescription Limit Unit SYNC TIMING REQUIREMENTSt SSYNC SYNC to rising edge of CLK+ setup time 0.24 ns typ t HSYNCSYNC to rising edge of CLK+ hold time 0.40 ns typ SPI TIMING REQUIREMENTS See Figure 61t DS Setup time between the data and the rising edge of SCLK 2 ns min t DH Hold time between the data and the rising edge of SCLK 2 ns min t CLK Period of the SCLK40 ns min t S Setup time between CSB and SCLK 2 ns min t H Hold time between CSB and SCLK 2 ns min t HIGH SCLK pulse width high 10 ns min t LOW SCLK pulse width low10 ns min t EN_SDIO Time required for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 61)10 ns min t DIS_SDIOTime required for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 61)10ns minData SheetAD9637Rev. 0 | Page 7 of 40DCO–DCO+D– xD+ xCLK–CLK+05967-002Figure 2. Word-Wise DDR, 1× Frame, 12-Bit Output Mode (Default)10215-003CLK+D– xD+ xFigure 3. Word-Wise DDR, 1× Frame, 10-Bit Output Mode10215-004Figure 4. SYNC Input Timing RequirementsAD9637Data SheetRev. 0 | Page 8 of 40ABSOLUTE MAXIMUM RATINGSTable 6.Parameter RatingElectricalAVDD to AGND −0.3 V to +2.0 VDRVDD to AGND −0.3 V to +2.0 VDigital Outputs(D± x, DCO+, DCO−, FCO+, FCO−) to AGND −0.3 V to +2.0 V CLK+, CLK− to AGND −0.3 V to +2.0 VVIN+ x, VIN− x to AGND −0.3 V to +2.0 VSCLK/DTP , SDIO/DFS, CSB to AGND −0.3 V to +2.0 VSYNC, PDWN to AGND −0.3 V to +2.0 V RBIAS to AGND −0.3 V to +2.0 V VREF, SENSE to AGND −0.3 V to +2.0 V Environmental Operating Temperature Range (Ambient) −40°C to +85°C Maximum Junction Temperature 150°C Lead Temperature (Soldering, 10 sec) 300°C Storage Temperature Range (Ambient) −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operationalsection of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL CHARACTERISTICSThe exposed paddle must be soldered to the ground plane for the LFCSP package. Soldering the exposed paddle to the printedcircuit board (PCB) increases the reliability of the solder jointsand maximizes the thermal capability of the package.Table 7. Thermal Resistance Package Type Airflow Velocity(m/sec) θJA 1, 2 θJC 1, 3 θJB 1, 4 JT 1, 2 Unit 64-Lead LFCSP 9 mm × 9 mm(CP-64-4) 0 22.3 1.4 N/A 0.1 °C/W 1.0 19.5 N/A 11.8 0.2 °C/W 2.5 17.5 N/A N/A0.2 °C/W 1Per JEDEC 51-7, plus JEDEC 25-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3Per MIL-Std 883, Method 1012.1. 4Per JEDEC JESD51-8 (still air).Typical θJA is specified for a 4-layer PCB with a solid ground plane. As shown Table 7, airflow improves heat dissipation, which reduces θJA . In addition, metal in direct contact with the package leads from metal traces, through holes, ground, and power planes reduces θJA .ESD CAUTIONData SheetAD9637Rev. 0 | Page 9 of 40PIN CONFIGURATION AND FUNCTION DESCRIPTIONS17181920212223242526272829303132D – G D + G D – F D + F D –E D + E D C O –D C O +F C O –F C O +D – D D + D D – C D + C D – B D + B 64636261605958575655545352515049V I N + F V I N – F A V D D V I N – E V I N + E A V D D S Y N C V C M V R E F S E N S E R B I A S V I N + D V I N – D A V D D V I N – C V I N + CAVDD VIN+ B VIN– B AVDD VIN– A VIN+ A AVDD PDWN CSBSDIO/DFS SCLK/DTP AVDD DNC DRVDD D+ A D– A48474645444342414039383736353433NOTES1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.2. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND.10215-005Figure 5. Pin Configuration, Top ViewTable 8. Pin Function DescriptionsPin No. Mnemonic Description0, EPAGND,Exposed Pad Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to analog ground for proper operation. 1, 4, 7, 8, 11, 12, 37, 42, 45, 48, 51, 59, 62 AVDD1.8 V Analog Supply.13, 36 DNC Do Not Connect. Do not connect to this pin. 14, 35 DRVDD 1.8 V Digital Output Driver Supply. 2, 3 VIN+ G, VIN− G ADC G Analog Input True, ADC G Analog Input Complement. 5, 6 VIN− H, VIN+ H ADC H Analog Input Complement, ADC H Analog Input True. 9, 10 CLK−, CLK+ Input Clock Complement, Input Clock True. 15, 16 D− H, D+ H ADC H Digital Output Complement, ADC H Digital Output True. 17, 18 D− G, D+ G ADC G Digital Output Complement, ADC G Digital Output True. 19, 20 D− F, D+ F ADC F Digital Output Complement, ADC F Digital Output True. 21, 22 D− E, D+ E ADC E Digital Output Complement, ADC E Digital Output True. 23, 24 DCO−, DCO+ Data Clock Digital Output Complement, Data Clock Digital Output True. 25, 26 FCO−, FCO+ Frame Clock Digital Output Complement, Frame Clock Digital Output True. 27, 28 D− D, D+ D ADC D Digital Output Complement, ADC D Digital Output True. 29, 30 D− C, D+ C ADC C Digital Output Complement, ADC C Digital Output True. 31, 32 D− B, D+ B ADC B Digital Output Complement, ADC B Digital Output True. 33, 34 D− A, D+ A ADC A Digital Output Complement, ADC A Digital Output True. 38 SCLK/DTP Serial Clock (SCLK)/Digital Test Pattern (DTP). 39 SDIO/DFS Serial Data Input/Output (SDIO)/Data Format Select (DFS). 40 CSB Chip Select Bar. 41 PDWN Power-Down. 43, 44 VIN+ A, VIN− A ADC A Analog Input True, ADC A Analog Input Complement. 46, 47 VIN− B, VIN+ B ADC B Analog Input Complement, ADC B Analog Input True. 49, 50 VIN+ C, VIN− C ADC C Analog Input True, ADC C Analog Input Complement.AD9637 Data SheetPin No. Mnemonic Description52, 53 VIN− D, VIN+ D ADC D Analog Input Complement, ADC D Analog Input True.54 RBIAS Sets analog current bias. Connect to 10 kΩ (1% tolerance) resistor to ground.55 SENSE Reference Mode Selection.56 VREF Voltage Reference Input/Output.57 VCM Analog Output Voltage at Midsupply. Sets common mode of the analog inputs.58 SYNC Digital Input. SYNC input to clock divider. 30 kΩ internal pull-down.60, 61 VIN+ E, VIN− E ADC E Analog Input True, ADC E Analog Input Complement.63, 64 VIN− F, VIN+ F ADC F Analog Input Complement, ADC F Analog Input True.Rev. 0 | Page 10 of 40分销商库存信息:ANALOG-DEVICESAD9637BCPZ-40AD9637BCPZ-80AD9637BCPZRL7-40 AD9637BCPZRL7-80AD9637-80EBZ。

IC datasheet pdf-CD54AC273, CD74AC273,CD54ACT273, CD74ACT273,pdf(Octal D Flip-Flop)

Data sheet acquired from Harris SemiconductorSCHS249BFeatures•Buffered Inputs•Typical Propagation Delay- 6.5ns at V CC = 5V , T A = 25o C, C L = 50pF•Exceeds 2kV ESD Protection MIL-STD-883, Method 3015•SCR-Latchup-Resistant CMOS Process and Circuit Design •Speed of Bipolar FAST™/AS/S with Signiﬁcantly Reduced Power Consumption •Balanced Propagation Delays•AC Types Feature 1.5V to 5.5V Operation and Balanced Noise Immunity at 30% of the Supply •±24mA Output Drive Current -Fanout to 15 FAST™ ICs-Drives 50Ω Transmission LinesPinoutCD54AC273, CD54ACT273(CDIP)CD74AC273, CD74ACT273(PDIP , SOIC)TOP VIEWDescriptionThe ’AC273and ’ACT273devices are octal D-type ﬂip-ﬂops with reset that utilize advanced CMOS logic rmation at the D input is transferred to the Q output on the positive-going edge of the clock pulse.All eight ﬂip-ﬂops are controlled by a common clock (CP)and a common reset (MR).Resetting is accomplished by a low voltage level independent of the clock.1112131415161718201910987654321MR Q0D0D1Q1Q2D3D2Q3GND V CC D7D6Q6Q7Q5D5D4Q4CPOrdering InformationPART NUMBER TEMPERATURERANGE PACKAGE CD74AC273E0o C to 70o C -40o C to 85o C -55o C to 125o C 20 Ld PDIPCD54AC273F3A -55o C to 125o C 20 Ld CDIP CD74ACT273E0o C to 70o C -40o C to 85o C -55o C to 125o C 20 Ld PDIPCD54ACT273F3A -55o C to 125o C 20 Ld CDIP CD74AC273M0o C to 70o C -40o C to 85o C -55o C to 125o C 20 Ld SOICCD74ACT273M 0o C to 70o C -40o C to 85o C -55o C to 125o C20 Ld SOICNOTES:1.When ordering,use the entire part number.Add the suffix 96to obtain the variant in the tape and reel.2.Wafer and die for this part number is available which meets allelectrical specifications.Please contact your local sales office for ordering information.August 1998 - Revised July 2002CD54AC273, CD74AC273CD54ACT273, CD74ACT273Octal D Flip-Flop with ResetFunctional DiagramTRUTH TABLE INPUTSOUTPUTSRESET (MR)CLOCK CP DATA Dn Qn L X X L H ↑H H H ↑L L HLXQ0H =High level (steady state),L =Low level (steady state),X =Irrel-evant,↑=Transition from Low to High level,Q0=The level of Q before the indicated steady-state input conditions were estab-lished.Q0Q1Q2Q3Q4Q5Q6Q7RESET MRD0D1D2D3D4D5D6D7CLOCKCPDATA INPUTSDATAOUTPUTSAbsolute Maximum Ratings Thermal InformationDC Supply Voltage, V CC. . . . . . . . . . . . . . . . . . . . . . . .-0.5V to 6V DC Input Diode Current, I IKFor V I < -0.5V or V I > V CC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, I OKFor V O < -0.5V or V O > V CC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC Output Source or Sink Current per Output Pin, I OFor V O > -0.5V or V O < V CC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA DC V CC or Ground Current, I CC or I GND (Note 3) . . . . . . . . .±100mA Operating ConditionsTemperature Range, T A . . . . . . . . . . . . . . . . . . . . . .-55o C to 125o C Supply Voltage Range, V CC (Note 4)AC T ypes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V ACT T ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V DC Input or Output Voltage, V I, V O . . . . . . . . . . . . . . . . .0V to V CC Input Rise and Fall Slew Rate, dt/dvAC T ypes, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . .50ns (Max) AC T ypes, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . .20ns (Max) ACT T ypes, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . .10ns (Max)Thermal Resistance,θJA(Typical, Note 5)E Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69o C/W M Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58o C/W Maximum Junction T emperature (Plastic Package) . . . . . . . . . .150o C Maximum Storage Temperature Range . . . . . . . . . .-65o C to 150o C Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300o CCAUTION:Stresses above those listed in“Absolute Maximum Ratings”may cause permanent damage to the device.This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.NOTES:3.For up to 4 outputs per device, add±25mA for each additional output.4.Unless otherwise specified, all voltages are referenced to ground.5.The package thermal impedance is calculated in accordance with JESD 51.DC Electrical SpeciﬁcationsPARAMETER SYMBOLTESTCONDITIONS VCC(V)25o C-40o C TO85o C-55o C TO125o CUNITS V I(V)I O(mA)MIN MAX MIN MAX MIN MAXAC TYPESHigh Level Input Voltage V IH-- 1.5 1.2- 1.2- 1.2-V3 2.1- 2.1- 2.1-V5.5 3.85- 3.85- 3.85-V Low Level Input Voltage V IL-- 1.5-0.3-0.3-0.3V3-0.9-0.9-0.9V5.5- 1.65- 1.65- 1.65V High Level Output Voltage V OH V IH or V IL-0.05 1.5 1.4- 1.4- 1.4-V-0.053 2.9- 2.9- 2.9-V-0.05 4.5 4.4- 4.4- 4.4-V-43 2.58- 2.48- 2.4-V-24 4.5 3.94- 3.8- 3.7-V-75(Note 6, 7)5.5-- 3.85---V-50(Note 6, 7)5.5---- 3.85-VLow Level Output VoltageV OLV IH or V IL0.05 1.5-0.1-0.1-0.1V 0.053-0.1-0.1-0.1V 0.05 4.5-0.1-0.1-0.1V 123-0.36-0.44-0.5V 24 4.5-0.36-0.44-0.5V 75(Note 6, 7) 5.5--- 1.65--V 50(Note 6, 7)5.5----- 1.65V Input Leakage Current I I V CC or GND - 5.5-±0.1-±1-±1µA Quiescent Supply Current MSI I CCV CC or GND5.5-8-80-160µAACT TYPESHigh Level Input Voltage V IH -- 4.5 to 5.52-2-2-V Low Level Input Voltage V IL -- 4.5 to 5.5-0.8-0.8-0.8V High Level Output VoltageV OHV IH or V IL-0.05 4.5 4.4- 4.4- 4.4-V -24 4.5 3.94- 3.8- 3.7-V -75(Note 6, 7) 5.5-- 3.85---V -50(Note 6, 7)5.5---- 3.85-V Low Level Output VoltageV OLV IH or V IL0.05 4.5-0.1-0.1-0.1V 24 4.5-0.36-0.44-0.5V 75(Note 6, 7) 5.5--- 1.65--V 50(Note 6, 7)5.5----- 1.65V Input Leakage Current I I V CC or GND - 5.5-±0.1-±1-±1µA Quiescent Supply Current MSII CC V CC or GND 0 5.5-8-80-160µA Additional Supply Current per Input Pin TTL Inputs High 1 Unit Load ∆I CCV CC -2.1- 4.5 to 5.5- 2.4- 2.8-3mANOTES:6.Test one output at a time for a 1-second maximum duration.Measurement is made by forcing current and measuring voltage to minimize power dissipation.7.Test verifies a minimum 50Ω transmission-line-drive capability at 85o C, 75Ω at 125o C.ACT Input Load TableINPUT UNIT LOADDn 0.5MR 0.57CP1NOTE:Unit load is ∆I CC limit specified in DC Electrical Specifications T able, e.g., 2.4mA max at 25o C.DC Electrical Speciﬁcations(Continued)PARAMETERSYMBOL TEST CONDITIONSV CC (V)25o C -40o C TO 85o C -55o C TO 125o C UNITS V I (V)I O (mA)MIN MAX MIN MAX MIN MAXPrerequisite For Switching FunctionPARAMETER SYMBOL V CC (V)-40o C TO 85o C-55o C TO 125o CUNITS MIN MAX MIN MAXAC TYPESData to CP Set-Up Time t SU 1.52-2-ns3.3(Note 9)2-2-ns5(Note 10)2-2-ns Hold Time t H 1.52-2-ns3.32-2-ns52-2-ns Removal Time,MR to CP t REM 1.52-2-ns3.32-2-ns52-2-ns MR Pulse Width t W 1.555-63-ns3.3 6.1-7-ns5 4.4-5-ns CP Pulse Width t W 1.555-63-ns3.3 6.1-7-ns5 4.4-5-ns CP Frequency f MAX 1.59-8-MHz3.381-71-MHz5114-100-MHz ACT TYPESData to CP Set-Up Time t SU5(Note 10)2-2-ns Hold Time t H52-2-ns Removal Time MR to CP t REM52-2-ns MR Pulse Width t W5 4.4-5-ns CP Pulse Width t W5 5.3-6-ns CP Frequency f MAX597-85-MHz Switching Speciﬁcations Input t r, t f = 3ns, C L= 50pF (Worst Case)PARAMETER SYMBOL V CC (V)-40o C TO 85o C-55o C TO 125o CUNITS MIN TYP MAX MIN TYP MAXAC TYPESPropagation Delay, CP to Qn t PLH, t PHL 1.5--154--169ns3.3(Note 9)4.9-17.2 4.7-18.9ns5(Note 10)3.5-12.3 3.4-13.5nsPropagation Delay,MR to Qnt PLH , t PHL1.5--154--169ns 3.3 4.9-17.2 4.7-18.9ns 53.5-12.3 3.4-13.5ns Input CapacitanceC I ---10--10pF Power Dissipation Capacitance C PD (Note 11)--45--45-pFACT TYPES Propagation Delay,CP to Qnt PLH , t PHL 5(Note 10)3.5-12.3 3.4-13.5ns Propagation Delay,MR to Qn t PLH , t PHL5 3.5-12.3 3.4-13.5ns Input CapacitanceC I ---10--10pF Power Dissipation Capacitance C PD (Note 11)--45--45-pFNOTES:8.Limits tested 100%.9.3.3V Min is at 3.6V, Max is at 3V.10.5V Min is at 5.5V, Max is at 4.5V.11.C PD is used to determine the dynamic power consumption per flip-flop.AC: P D = C PD V CC 2 f i =∑ (C L V CC 2 f o )ACT:P D =C PD V CC 2f i +∑(C L V CC 2f o )+V CC ∆I CC where f i =input frequency,f o =output frequency,C L =output load capacitance,V CC = supply voltage.FIGURE 1.PROPAGATION DELAY TIMES AND CLOCKPULSE WIDTH FIGURE 2.PREREQUISITE AND PROPAGATION DELAYTIMES FOR MASTER RESETSwitching Speciﬁcations Input t r , t f = 3ns, C L = 50pF (Worst Case)(Continued)PARAMETERSYMBOL V CC (V)-40o C TO 85o C-55o C TO 125o CUNITS MIN TYP MAX MIN TYP MAX 90%t f t r V SV S V SV SV St PLHt PHLt W 10%10%CP INPUT LEVEL QMR CPINPUT LEVELV SQV St REMV SV St PLHt WGNDINPUT(Q)FIGURE 3.PREREQUISITE FOR CLOCKDV S V S V SV S V S V St H (H)t SU (L)t H (L)t SU (H)CPOUTPUT LEVELDUT OUTPUTR L (NOTE)OUTPUT LOAD500ΩC L 50pFNOTE:For AC Series Only: When V CC = 1.5V , R L = 1k Ω.FIGURE 4.PROPAGATION DELAY TIMESACACT Input LevelV CC 3V Input Switching Voltage, V S 0.5 V CC 1.5V Output Switching Voltage, V S0.5 V CC0.5 V CCPACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)CD54AC273F3A ACTIVE CDIP J201TBD A42N/A for Pkg Type CD54ACT273F3A ACTIVE CDIP J201TBD A42N/A for Pkg Type CD74AC273E ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeCD74AC273EE4ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeCD74AC273M ACTIVE SOIC DW2025Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74AC273M96ACTIVE SOIC DW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74AC273M96E4ACTIVE SOIC DW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74AC273M96G4ACTIVE SOIC DW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74AC273ME4ACTIVE SOIC DW2025Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74AC273MG4ACTIVE SOIC DW2025Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273E ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeCD74ACT273EE4ACTIVE PDIP N2020Pb-Free(RoHS)CU NIPDAU N/A for Pkg TypeCD74ACT273M ACTIVE SOIC DW2025Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273M96ACTIVE SOIC DW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273M96E4ACTIVE SOIC DW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273M96G4ACTIVE SOIC DW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273ME4ACTIVE SOIC DW2025Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273MG4ACTIVE SOIC DW2025Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273PW ACTIVE TSSOP PW2070Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273PWE4ACTIVE TSSOP PW2070Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273PWG4ACTIVE TSSOP PW2070Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273PWR ACTIVE TSSOP PW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273PWRE4ACTIVE TSSOP PW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273PWRG4ACTIVE TSSOP PW202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273SM96ACTIVE SSOP DB202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMCD74ACT273SM96E4ACTIVE SSOP DB202000Green(RoHS&CU NIPDAU Level-1-260C-UNLIMOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)no Sb/Br)CD74ACT273SM96G4ACTIVE SSOP DB202000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.TAPE AND REELINFORMATION*All dimensionsare nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant CD74AC273M96SOIC DW 202000330.024.410.813.0 2.712.024.0Q1CD74ACT273M96SOIC DW 202000330.024.410.813.0 2.712.024.0Q1CD74ACT273PWR TSSOP PW 202000330.016.4 6.957.1 1.68.016.0Q1CD74ACT273SM96SSOPDB202000330.016.48.27.52.512.016.0Q1PACKAGE MATERIALS INFORMATION11-Mar-2008*Alldimensions are nominal DevicePackage Type Package Drawing Pins SPQ Length (mm)Width (mm)Height (mm)CD74AC273M96SOIC DW 202000346.0346.041.0CD74ACT273M96SOIC DW 202000346.0346.041.0CD74ACT273PWRTSSOP PW 202000346.0346.033.0CD74ACT273SM96SSOP DB 202000346.0346.033.0PACKAGE MATERIALS INFORMATION 11-Mar-2008Pack Materials-Page 2IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing 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IC datasheet pdf-AM26LV31C,AM26LV31I,pdf(LOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE DRIVERS)

FEATURESD OR NS PACKAGE(TOP VIEW)DESCRIPTION/ORDERING INFORMATIONAM26LV31C,AM26LV31ILOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE DRIVERSSLLS201G–MAY 1995–REVISED MAY 2005•Switching Rates up to 32MHz•Operate From a Single 3.3-V Supply •Propagation Delay Time ...8ns Typ •Pulse Skew Time ...500ps Typ•High Output-Drive Current ...±30mA•Controlled Rise and Fall Times ...3ns Typ •Differential Output Voltage With 100-ΩLoad ...1.5V Typ•Ultra-Low Power Dissipation –dc,0.3mW Max–32MHz All Channels (No Load),385mW Typ •Accept 5-V Logic Inputs With 3.3-V Supply •Low-Voltage Pin-to-Pin CompatibleReplacement for AM26C31,AM26LS31,MB571•High Output Impedance in Power-Off Condition•Driver Output Short-Protection Circuit •Package Options Include Plastic Small-Outline (D,NS)PackagesThe AM26LV31C and AM26LV31I are BiCMOS quadruple differential line drivers with 3-state outputs.They are designed to be similar to TIA/EIA-422-B and ITU Recommendation V.11drivers with reduced supply-voltage range.The devices are optimized for balanced-bus transmission at switching rates up to 32MHz.The outputs have very high current capability for driving balanced lines such as twisted-pair transmission lines and provide a high impedance in the power-off condition.The enable function is common to all four drivers and offers the choice of active-high or active-low enable inputs.The AM26LV31C and AM26LV31I are designed using Texas Instruments proprietary LinIMPACT-C60™technology,facilitating ultra-low power consumption without sacrificing speed.These devices offer optimum performance when used with the AM26LV32quadruple line receivers.The AM26LV31C is characterized for operation from 0°C to 70°C.The AM26LV31I is characterized for operation from –45°C to 85°CORDERING INFORMATIONT APACKAGE (1)ORDERABLE PART NUMBER TOP-SIDE MARKING AM26LV31CD SOIC –DTape and reelAM26LV31C AM26LV31CDR 0°C to 70°CAM26LV31CNS SOIC –NS Tape and reel 26LV31AM26LV31CNSR AM26LV31ID SOIC –DTape and reelAM26LV31I AM26LV31IDR –45°C to 85°CAM26LV31INS SOIC –NSTape and reel 26LV31IAM26LV31INSR(1)Package drawings,standard packing quantities,thermal data,symbolization,and PCB design guidelines are available at /sc/package.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.4Z4Y 3Z 3Y 2Z 2Y 1Z 1Y4A3A2A1AG GAll resistor values are nominal.AM26LV31C,AM26LV31ILOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE DRIVERSSLLS201G–MAY 1995–REVISED MAY 2005FUNCTION TABLE (1)ENABLES OUTPUTSINPUT A G G Y Z H H X H L L H X L H H X L H L L X L L H X LHZZ(1)H =high level,L =low level,X =irrelevant,Z =high impedance (off)LOGIC DIAGRAM (POSITIVE LOGIC)SCHEMATIC (EACH DRIVER)Absolute Maximum Ratings(1) Recommended Operating Conditions Electrical Characteristics AM26LV31C,AM26LV31ILOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE DRIVERSSLLS201G–MAY1995–REVISED MAY2005over operating free-air temperature range(unless otherwise noted)MIN MAX UNITV CC Supply voltage range(2)–0.36VV I Input voltage range–0.36VV O Output voltage range–0.36VD package73θJA Package thermal impedance(3)°C/WNS package64 Lead temperature1,6mm(1/16in)from case for10s260°CT stg Storage temperature range–65150°C (1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratingsonly,and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.(2)All voltage values are with respect to GND.(3)The package thermal impedance is calculated in accordance with JESD51-7.MIN NOM MAX UNIT V CC Supply voltage3 3.3 3.6VV IH High-level input voltage2VV IL Low-level input voltage0.8VI OH High-level output current–30mAI OL Low-level output current30mAAM26LV31C070T A Operating free-air temperature°CAM26LV31I–4585over recommended operating supply-voltage and free-air temperature ranges(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP(1)MAX UNITV IK Input clamp voltage I I=18mA–1.5VV OH High-level output voltage V IH=2V,I OH=–12mA 1.85 2.3VV OL Low-level output voltage V IL=0.8V,I OH=12mA0.8 1.05V|V OD|Differential output voltage(2)0.95 1.5VV OC Common-mode output voltage 1.3 1.55 1.8VR L=100ΩChange in magnitude of∆|V OC|±0.2V common-mode output voltage(2)I O Output current with power off V O=–0.25V or6V,V CC=0±100µAOff-state(high-impedance state)I OZ V O=–0.25V or6V,G=0.8V or G=2V±100µAoutput currentI H High-level input current V CC=0or3V,V I=5.5V 10µAI L Low-level input current V CC=3.6V,V I=0–10µAI OS Short-circuit output current V CC=3.6V,V O=0–200mAI CC Supply current(all drivers)V I=V CC or GND,No load100µAPower-dissipation capacitanceC pd No load160pF(all drivers)(3)(1)All typical values are at V CC=3.3V,T A=25°C.(2)∆|V OD|and∆|V OC|are the changes in magnitude of V OD and V OC,respectively,that occur when the input is changed from a high level toa low level.(3)C pd determines the no-load dynamic current consumption.I S=C pd×V CC×f+I CCSR +90%ǒV OH *V OL Ǔ*10%ǒV OH *V OL Ǔt r,the differential slew rate of V OD is 2 SR.Switching CharacteristicsAM26LV31C,AM26LV31ILOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE DRIVERSSLLS201G–MAY 1995–REVISED MAY 2005V CC =3.3V,T A =25°CPARAMETERTEST CONDITIONS MIN TYP (1)MAX UNIT t PLH Propagation delay time,low-to high-level output See Figure 24812ns t PHL Propagation delay time,high-to low-level output 4812ns t t Transition time (t r or t f )3ns SR Slew rate,single-ended output voltage See Note(2)and Figure 20.31V/ns t PZH Output-enable time to high level See Figure 31020ns t PZL Output-enable time to low level See Figure 41020ns t PHZ Output-disable time from high level See Figure 31020ns t PLZ Output-disable time from low level See Figure 41020ns t sk(p)Pulse skew f =32MHz,See Note(3)0.51.5ns t sk(o)Skew limitf =32MHz 1.5ns t sk(lim)Skew limit (device to device)f =32MHz,See Note(4)3ns(1)All typical values are at V CC =3.3V,T A =25°C.(2)Slew rate is defined by:(3)Pulse skew is defined as the |t PLH -t PHL |of each channel of the same device.(4)Skew limit (device to device)is the maximum difference in propagation delay times between any two channels of any two devices.PARAMETER MEASUREMENT INFORMATIONG GZOutput, V OInputt PLH t PHLV CC0 V50%50%PROPAGATION DELAY TIMESYAOutput, V Ot rt f V OH90%90%RISE AND FALL TIMES10%10%V OLNOTES: A.C L includes probe and jig capacitance.B.The input pulse is supplied by a generator having the following characteristics: PRR = 32 MHz, Z O ≈ 50 Ω, 50% duty cycle,t r and t f ≤ 2 ns.10%10%90%90%YZt ft rV OL V OH AM26LV31C,AM26LV31ILOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE DRIVERSSLLS201G–MAY 1995–REVISED MAY 2005Figure 1.Differential and Common-Mode Output VoltagesFigure 2.Test Circuit and Voltage Waveforms,t PHL and t PLHPARAMETER MEASUREMENT INFORMATIONInput t PZHt PHZ V CC 50%50%0 VOutput V OH50%VOLTAGE WAVEFORMSV off ≈00.3 VNOTES: A.C L includes probe and jig capacitance.B.The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, Z O = 50 Ω, 50% duty cycle,t r and t f (10% to 90%) ≤ 2 ns.C.T o test the active-low enable G, ground G and apply an inverted waveform to G.S1= 110 ΩOutput TEST CIRCUITAM26LV31C,AM26LV31ILOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE DRIVERSSLLS201G–MAY 1995–REVISED MAY 2005Figure 3.Test Circuit and Voltage Waveforms,t PZH and t PHZPARAMETER MEASUREMENT INFORMATIONInputtPZLt PLZV CC50%50%0 VOutputV OL50%VOLTAGE WAVEFORMSV off ≈V CC0.3 VNOTES: A.C L includes probe and jig capacitance.B.The input pulse is supplied by a generator having the following characteristics: PRR = 1 MHz, Z O = 50 Ω, 50% duty cycle,t r and t f (10% to 90%) ≤ 2 ns.C.T o test the active-low enable G, ground G and apply an inverted waveform to G.ΩOutputTEST CIRCUITV AM26LV31C,AM26LV31ILOW-VOLTAGE HIGH-SPEED QUADRUPLE DIFFERENTIAL LINE DRIVERSSLLS201G–MAY 1995–REVISED MAY 2005Figure 4.Test Circuit and Voltage Waveforms,t PZL and t PLZPACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)AM26LV31CD ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31CDE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31CDG4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31CDR ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31CDRE4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31CDRG4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM AM26LV31CNSLE OBSOLETE SO NS16TBD Call TI Call TIAM26LV31CNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31CNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31CNSRG4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31ID ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31IDE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31IDG4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31IDR ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31IDRE4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31IDRG4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31INSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31INSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMAM26LV31INSRG4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIM(1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS),Pb-Free(RoHS Exempt),or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free(RoHS Exempt):This component has a RoHS exemption for either1)lead-based flip-chip solder bumps used between the die and package,or2)lead-based die adhesive used between the die and leadframe.The component is otherwise considered Pb-Free(RoHS compatible)as defined above.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.TAPE AND REELINFORMATION*All dimensionsare nominalDevicePackage Type Package Drawing Pins SPQReel Diameter (mm)Reel Width W1(mm)A0(mm)B0(mm)K0(mm)P1(mm)W (mm)Pin1Quadrant AM26LV31CDR SOIC D 162500330.016.4 6.510.3 2.18.016.0Q1AM26LV31CNSR SO NS 162000330.016.48.210.5 2.512.016.0Q1AM26LV31IDR SOIC D 162500330.016.4 6.510.3 2.18.016.0Q1AM26LV31INSRSONS162000330.016.48.210.52.512.016.0Q1PACKAGE MATERIALS INFORMATION19-Mar-2008*Alldimensions are nominal DevicePackage Type Package Drawing Pins SPQ Length (mm)Width (mm)Height (mm)AM26LV31CDRSOIC D 162500333.2345.928.6AM26LV31CNSRSO NS 162000346.0346.033.0AM26LV31IDRSOIC D 162500333.2345.928.6AM26LV31INSR SO NS 162000346.0346.033.0PACKAGE MATERIALS INFORMATION 19-Mar-2008Pack Materials-Page 2IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this 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DF9A-9P-1V(22);DF9A-9S-1V(22);DF9-9S-1V(32);DF9A-11S-1V(22);DF9A-11P-1V(22);中文规格书,Datasheet资料

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LCD (Liquid Crystal Display), Mobile phone, Note PC
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A135
The product information in this catalog is for reference only. Please request the Engineering Drawing for the most current and accurate design information. All non-RoHDS pFr9oduScetsriheasveqb1eemn dmiscoPnittincuhed,SoMr wTill BbeodaisrcdonttionueBdosoaornd. PlCeaosencnheecckttoher(pSrotdaunctdsastradtusInontethrefaHicroeseCwoebnsniteeRcotHoSrseCarocmh apt wliwawn.htirwosiet-hcoVnnEecStoArs.FcoPmD, oIr-1co)ntact your Hirose sales representative.
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IC datasheet pdf-L293,L293D,pdf(Quadruple Half-H Drivers)

D Peak Output Current 2 A Per Channel (1.2 A for L293D)DOutput Clamp Diodes for Inductive Transient Suppression (L293D)description/ordering informationThe L293 and L293D are quadruple high-current half-H drivers. The L293 is designed to provide bidirectional drive currents of up to 1 A at voltages from 4.5 V to 36 V. The L293D is designed to provide bidirectional drive currents of up to 600-mA at voltages from 4.5 V to 36 V. Both devices are designed to drive inductive loads such as relays, solenoids, dc and bipolar stepping motors, as well as other high-current/high-voltage loads in positive-supply applications.All inputs are TTL compatible. Each output is a complete totem-pole drive circuit, with a Darlington transistor sink and a pseudo-Darlington source. Drivers are enabled in pairs, with drivers 1 and 2 enabled by 1,2EN and drivers 3 and 4enabled by 3,4EN. When an enable input is high, the associated drivers are enabled, and their outputs are active and in phase with their inputs. When the enable input is low, those drivers are disabled, and their outputs are off and in the high-impedance state. With the proper data inputs, each pair of drivers forms a full-H (or bridge)reversible drive suitable for solenoid or motor applications.ORDERING INFORMATIONT APACKAGE †ORDERABLEPART NUMBER TOP-SIDE MARKING HSOP (DWP)Tube of 20L293DWP L293DWP C to 70PDIP (N)Tube of 25L293N L293N 0°C to 70°C PDIP (NE)Tube of 25L293NE L293NE PDIP (NE)Tube of 25L293DNEL293DNE†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at /sc/package.PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.123456789101112131428272625242322212019181716151,2EN1A 1Y NC NC NCNC NC 2Y 2A V CC2V CC14A 4Y NC NC NCNC NC 3Y 3A 3,4ENL293...DWP PACKAGE(TOP VIEW)HEAT SINK AND GROUND HEAT SINK AND GROUNDdescription/ordering information (continued)On the L293, external high-speed output clamp diodes should be used for inductive transient suppression.A V CC1 terminal, separate from V CC2, is provided for the logic inputs to minimize device power dissipation.The L293and L293D are characterized for operation from 0°C to 70°C.block diagramV CC2V CC1NOTE: Output diodes are internal in L293D.FUNCTION TABLE(each driver)INPUTS†A EN OUTPUTYH H HL H LX L ZH = high level, L = low level, X = irrelevant, Z = high impedance (off)†In the thermal shutdown mode, the output is in the high-impedance state, regardless of the input levels.logic diagram1A 1,2EN2A3A 3,4EN4A 1Y 2Y 3Y 4Yschematics of inputs and outputs (L293)InputV CC2OutputGND TYPICAL OF ALL OUTPUTSEQUIVALENT OF EACH INPUT V CC1CurrentSourceGNDschematics of inputs and outputs (L293D)InputV CC2OutputGND TYPICAL OF ALL OUTPUTSEQUIVALENT OF EACH INPUTV CC1CurrentSourceGNDabsolute maximum ratings over operating free-air temperature range (unless otherwise noted)†Supply voltage, V CC1(see Note 1) 36 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Output supply voltage, V CC236 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Input voltage, V I7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Output voltage range, V O −3V toV CC2 + 3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Peak output current, I O (nonrepetitive, t ≤ 5 ms): L293 ±2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Peak output current, I O (nonrepetitive, t ≤ 100 µs): L293D ±1.2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous output current, I O: L293 ±1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Continuous output current, I O: L293D ±600 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Package thermal impedance, θJA (see Notes 2 and 3):DWP package TBD°C/W. . . . . . . . . . . . . . . . . . . . . . .N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . .NE package TBD°C/W. . . . . . . . . . . . . . . . . . . . . . . . .Maximum junction temperature, T J 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Storage temperature range, T stg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, andfunctional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is notimplied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.NOTES: 1.All voltage values are with respect to the network ground terminal.2.Maximum power dissipation is a function of T J(max), q JA, and T A. The maximum allowable power dissipation at any allowableambient temperature is P D = (T J(max) − T A)/q JA. Operating at the absolute maximum T J of 150°C can affect reliability.3.The package thermal impedance is calculated in accordance with JESD 51-7.recommended operating conditionsMIN MAX UNITSupply voltage V CC1 4.57Supply voltageV CC2V CC136VHigh level input voltage V CC1≤ 7 V 2.3V CC1VV IH High-level input voltageV CC1≥ 7 V 2.37VV IL Low-level output voltage−0.3† 1.5VT A Operating free-air temperature070°C†The algebraic convention, in which the least positive (most negative) designated minimum, is used in this data sheet for logic voltage levels. electrical characteristics, V CC1 = 5 V, V CC2 = 24 V, T A = 25°CPARAMETER TEST CONDITIONS MIN TYP MAX UNITV OH High-level output voltage L293: I OH = −1 AL293D: I OH = −0.6 AV CC2 − 1.8V CC2 − 1.4VV OL Low-level output voltage L293: I OL= 1 AL293D: I OL = 0.6 A1.2 1.8VV OKH High-level output clamp voltage L293D: I OK = −0.6 A V CC2+1.3V V OKL Low-level output clamp voltage L293D: I OK = 0.6 A 1.3VHigh level input current A7V0.2100I IH High-level input currentEN V I = 7 V0.210µALow level input current A−3−10I IL Low-level input currentEN V I = 0−2−100µA All outputs at high level1322I= 0All outputs at low level3560I CC1Logic supply current O 0All outputs at high impedance824mAAll outputs at high level1424I Output supply current I = 0All outputs at low level26mA CC2p pp y OAll outputs at high impedance24 switching characteristics, V CC1 = 5 V, V CC2 = 24 V, T A = 25°CTEST CONDITIONS L293NE, L293DNEPARAMETER TEST CONDITIONSMIN TYP MAXUNIT t PLH Propagation delay time, low-to-high-level output from A input800nst PHL Propagation delay time, high-to-low-level output from A input=30pF See Figure1400nst TLH Transition time, low-to-high-level output C L = 30 pF, See Figure 1300nst THL Transition time, high-to-low-level output300nsswitching characteristics, V CC1 = 5 V, V CC2 = 24 V, T A = 25°CL293DWP, L293NL293DNPARAMETER TEST CONDITIONSMIN TYP MAXUNIT t PLH Propagation delay time, low-to-high-level output from A input750nst PHL Propagation delay time, high-to-low-level output from A input=30pF See Figure1200nst TLH Transition time, low-to-high-level output C L = 30 pF, See Figure 1100nst THL Transition time, high-to-low-level output350nsPARAMETER MEASUREMENT INFORMATIONTEST CIRCUITOH VOLTAGE WAVEFORMSOLNOTES: A.C L includes probe and jig capacitance.B.The pulse generator has the following characteristics: t r≤ 10 ns, t f≤ 10 ns, t w = 10 µs, PRR = 5 kHz, Z O = 50 Ω.Figure 1. Test Circuit and Voltage WaveformsAPPLICATION INFORMATION24 V5 V10 k ΩV CC1V CC2Control AControl B4, 5, 12, 13GNDThermal ShutdownMotor1683611144Y 3Y 2Y 1Y 1,2EN1A 2A 3,4EN3A 4A 15109721Figure 2. Two-Phase Motor Driver (L293)APPLICATION INFORMATION24 V5 V10 k ΩV CC1V CC21681,2EN11A 22A 73,4EN93A 104A 15Control AControl B4, 5, 12, 13GNDThermal ShutdownMotor1Y 32Y 63Y 114Y 14Figure 3. Two-Phase Motor Driver (L293D)APPLICATION INFORMATIONEN3A M14A M2H H Fast motor stopH RunH L RunL Fast motor stop LXFree-running motorstopXFree-running motor stopL = low, H = high, X = don’t careEN 1A 2A FUNCTIONH L H Turn rightH H L Turn left H L LFast motor stop H H H Fast motor stop LXXFast motor stopL = low, H = high, X = don’t careV CC2Figure 4. DC Motor Controls (connections to ground and tosupply voltage)GNDV CC2V CC1ENFigure 5. Bidirectional DC Motor ControlGNDAPPLICATION INFORMATION0.22V CC2D1−D8 = SES5001Figure 6. Bipolar Stepping-Motor Controlmounting instructionsThe Rthj-amp of the L293 can be reduced by soldering the GND pins to a suitable copper area of the printed circuit board or to an external heat sink.Figure 9 shows the maximum package power P TOT and the θJA as a function of the side of two equal square copper areas having a thickness of 35 µm(see Figure 7). In addition, an external heat sink can be used (see Figure 8).During soldering, the pin temperature must not exceed 260°C, and the soldering time must not exceed 12 seconds.The external heatsink or printed circuit copper area must be connected to electrical ground.L293, L293D QUADRUPLE HALF-H DRIVERS SLRS008C − SEPTEMBER 1986 − REVISED NOVEMBER 200411POST OFFICE BOX 655303 • DALLAS, TEXAS 75265APPLICATION INFORMATIONFigure 7. Example of Printed Circuit Board Copper Area(used as heat sink)Figure 8. External Heat Sink Mounting Example (θJA = 25°C/W)L293, L293D QUADRUPLE HALF-H DRIVERS SLRS008C − SEPTEMBER 1986 − REVISED NOVEMBER 200412POST OFFICE BOX 655303 •DALLAS, TEXAS 75265APPLICATION INFORMATION310201020P 4MAXIMUM POWER AND JUNCTIONvsTHERMAL RESISTANCE 30T O T − P o w e r D i s s i p a t i o n − W 602004080θJ A − T h e r m a l R e s i s t a n c e −°C /W 40Side − mm Figure 95053102−500504MAXIMUM POWER DISSIPATION vs AMBIENT TEMPERATURE100T A − Ambient Temperature −°CFigure 10150P T O T − P o w e r D i s s i p a t i o n − WPACKAGING INFORMATIONOrderable Device Status (1)Package Type PackageDrawing Pins Package Qty Eco Plan (2)Lead/Ball FinishMSL Peak Temp (3)Samples(Requires Login)L293DDWP OBSOLETE SOIC DW28TBD Call TI Call TI Samples Not Available L293DDWPTR OBSOLETE SOIC DW28TBD Call TI Call TI Samples Not Available L293DN OBSOLETE PDIP N16TBD Call TI Call TI Samples Not Available L293DNE ACTIVE PDIP NE1625Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type Contact TI Distributoror Sales Office L293DNEE4ACTIVE PDIP NE1625Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type Contact TI Distributoror Sales Office L293DSP OBSOLETE16TBD Call TI Call TI Samples Not Available L293DSP883B OBSOLETE16TBD Call TI Call TI Samples Not Available L293DSP883C OBSOLETE UTR TBD Call TI Call TI Samples Not Available L293DWP OBSOLETE SOIC DW28TBD Call TI Call TI Replaced by L293DNE L293DWPG4OBSOLETE SOIC DW28TBD Call TI Call TI Replaced by L293DNE L293DWPTR OBSOLETE SO PowerPAD DWP28TBD Call TI Call TI Samples Not Available L293N OBSOLETE PDIP N16TBD Call TI Call TI Replaced by L293DNE L293NE ACTIVE PDIP NE1625Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type Contact TI Distributoror Sales Office L293NEE4ACTIVE PDIP NE1625Pb-Free (RoHS)CU NIPDAU N / A for Pkg Type Contact TI Distributoror Sales Office L293NG4OBSOLETE PDIP N16TBD Call TI Call TI Replaced by L293DNE(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check /productcontent for the latest availability information and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Addendum-Page 1Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.Addendum-Page 2IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries(TI)reserve the right to make corrections,modifications,enhancements,improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty.Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty.Except where mandated by government requirements,testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design.Customers are responsible for their products and applications using TI components.To minimize the risks associated with customer products and applications,customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license,either express or implied,is granted under any TI patent right,copyright,mask work right, or other TI intellectual property right relating to any combination,machine,or process in which TI products or services are rmation published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement e of such information may require a license from a third party under the patents or other intellectual property of the third party,or a license from TI under the patents or other intellectual property of TI.Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties,conditions,limitations,and notices.Reproduction of this information with alteration is an unfair and deceptive business practice.TI is not responsible or liable for such altered rmation of third parties may be subject to additional restrictions.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice.TI is not responsible or liable for any such statements.TI products are not authorized for use in safety-critical applications(such as life support)where a failure of the TI product would reasonably be expected to cause severe personal injury or death,unless officers of the parties have executed an agreement specifically governing such use.Buyers represent that they have all necessary expertise in the safety and regulatory ramifications of their applications,and acknowledge and agree that they are solely responsible for all legal,regulatory and safety-related requirements concerning their products and any use of TI products in such safety-critical applications,notwithstanding any applications-related information or support that may be provided by TI.Further,Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety-critical applications.TI products are neither designed nor intended for use in military/aerospace applications or environments unless the TI products are specifically designated by TI as military-grade or"enhanced plastic."Only products designated by TI as military-grade meet military specifications.Buyers acknowledge and agree that any such use of TI products which TI has not designated as military-grade is solely at the Buyer's risk,and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO/TS16949requirements.Buyers acknowledge and agree that,if they use any non-designated products in automotive applications,TI will not be responsible for any failure to meet such requirements.Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDLP®Products Communications and /communicationsTelecomDSP Computers and /computersPeripheralsClocks and Timers /clocks Consumer Electronics /consumer-appsInterface Energy /energyLogic Industrial /industrialPower Mgmt Medical /medicalMicrocontrollers Security /securityRFID Space,Avionics&/space-avionics-defenseDefenseRF/IF and ZigBee®Solutions /lprf Video and Imaging /videoWireless /wireless-appsMailing Address:Texas Instruments,Post Office Box655303,Dallas,Texas75265Copyright©2010,Texas Instruments Incorporated。

DS9637ACN中文资料

DS9637ADual Differential Line ReceiverGeneral DescriptionThe DS9637A is a Schottky dual differential line receiver which has been specifically designed to satisfy the require-ments of EIA Standards RS-422and RS-423.In addition,the DS9637A satisfies the requirements of MIL-STD 188-114and is compatible with the International Standard CCITT rec-ommendations.The DS9637A is suitable for use as a line re-ceiver in digital data systems,using either single ended or differential,unipolar or bipolar transmission.It requires a single 5V power supply and has Schottky TTL compatible outputs.The DS9637A has an operational input common mode range of ±7V either differentially or to ground.Featuresn Dual channel n Single 5V supplyn Satisfies EIA standards RS-422and RS423n Built-in ±35mV hysteresisn High input common mode voltage range n High input impedance n TTL compatible outputs n Schottky technologynExtended temperature rangeConnection Diagram8–Lead DIP and SO-8PackageDS009621-1Top ViewOrder Number DS9637ACM or DS9637ACN See NS Package Number M08A or N08E For Complete Military Product Specifications,refer to the appropriate SMD or MDS.Order Number DS9637AMJ/883See NS Package Number J08AMay 1998DS9637A Dual Differential Line Receiver©1998National Semiconductor Corporation Absolute Maximum Ratings(Note2)If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Storage Temperature RangeCeramic DIP−65˚C to+175˚C Molded DIP−65˚C to+150˚C Lead TemperatureCeramic DIP(Soldering,30seconds)300˚C Molded DIP and SO Package(Soldering,10seconds)265˚C Maximum Power Dissipation(Note1)at25˚CCavity Package1300mW Molded Package930mW SO Package810mW V CC Lead Potential to Ground−0.5V to7.0V Input Potential to Ground±15V Differential Input Voltage±15V Output Potential to Ground−0.5V to+5.5V Output Sink Current50mARecommended Operating ConditionsDS9637AM Min Max Units Supply Voltage(V CC) 4.5 5.5V Operating Temperature(T A)−55+125˚C DS9637ACSupply Voltage(V CC) 4.75 5.25V Operating Temperature(T A)0+70˚C Note1:Derate cavity package8.7mW/˚C above25˚C;derate molded DIP package7.5mW/˚C above25˚C;derate SO package6.5mW/˚C above25˚C.Electrical Characteristics(Notes3,4)Over recommended operating temperature and supply voltage ranges,unless otherwise specifiedSymbol Parameter Conditions Min Typ Max Units V TH Differential Input−7.0V≤V CM≤+7.0V−0.2+0.2V Threshold Voltage(Note6)V TH(R)Differential Input−7.0V≤V CM≤+7.0V−0.4+0.4V Threshold Voltage(Note7)I I Input Current V I=10V,0V≤V CC≤+5.5V 1.1 3.25mA(Note8)V I=−10V,0V≤V CC≤+5.5V−1.6−3.25V OL Output Voltage LOW I OL=20mA,V CC=Min0.350.5V V OH Output Voltage HIGH I OH=−1.0mA,V CC=Min 2.5 3.5V I OS Output Short Circuit V O=0V,V CC=Max−40−75−100mACurrent(Note5)I CC Supply Current V CC=Max,V I+=0.5V,3550mAV I−=GNDV HYST Input Hysteresis V CM=±7.0V(See Curves)70mV Note2:“Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be guaranteed.They are not meant to imply that the devices should be operated at these limits.The tables of“Electrical Characteristics”provide conditions for actual device operation.Note3:Unless otherwise specified Min/Max limits apply across the−55˚C to+125˚C temperature range for DS9637AM and across the0˚C to+70˚C range for the DS9637ASC.All typicals are given for V CC=5V and T A=25˚C.Note4:All currents into the device pins are positive;all currents out of the device pins are negative.All voltages are referenced to ground unless otherwise specified.Note5:Only one output at a time should be shorted.Note6:V DIFF(Differential Input Voltage)=(V I+)−(V I−).V CM(Common Mode Input Voltage)=V I+or V I−.Note7:500Ω±1%in series with inputs.Note8:The input not under test is tied to ground.Switching CharacteristicsV CC=5.0V,T A=25˚CSymbol Parameter Conditions Min Typ Max Units t PLH Propagation Delay Time See AC Test Circuit1525ns Low to Hight PHL Propagation Delay Time See AC Test Circuit1325ns High to Low2Switching Characteristics(Continued)Typical Input/Output Transfer CharacteristicsDS009621-2FIGURE 1.Equivalent CircuitDS009621-3DS009621-43AC Test Circuit and WaveformsTypical ApplicationsDS009621-5Notes:C L includes jig and probe capacitance.All diodes are FD700or equivalent.FIGURE 2.DS009621-6V IAmplitude:1.0V Offset:0.5VPulse Width:100ns PRR:5.0MHz t r =t f ≤5.0nsFIGURE 3.DS009621-7Notes:R T ≥50Ωfor RS-422operation.R T combined with input impedance of receivers must be greater than 90Ω.FIGURE 4.RS-422System Application (FIPS 1020)Differential Simplex Bus Transmission 4Physical Dimensions inches(millimeters)unless otherwise notedCeramic Dual-In-Line Package(J)Order Number DS9637AMJ/883NS Package Number J08AMolded Surface Mount Package(M)Order Number DS9637ACMNS Package Number M08A5Physical Dimensions inches(millimeters)unless otherwise noted(Continued)LIFE SUPPORT POLICYNATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DE-VICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMI-CONDUCTOR CORPORATION.As used herein:1.Life support devices or systems are devices or sys-tems which,(a)are intended for surgical implant intothe body,or(b)support or sustain life,and whose fail-ure to perform when properly used in accordancewith instructions for use provided in the labeling,canbe reasonably expected to result in a significant injuryto the user.2.A critical component in any component of a life supportdevice or system whose failure to perform can be rea-sonably expected to cause the failure of the life supportdevice or system,or to affect its safety or effectiveness.National SemiconductorCorporationAmericasTel:1-800-272-9959Fax:1-800-737-7018Email:support@National SemiconductorEuropeFax:+49(0)180-5308586Email:europe.support@Deutsch Tel:+49(0)180-5308585English Tel:+49(0)180-5327832Français Tel:+49(0)180-5329358Italiano Tel:+49(0)180-5341680National SemiconductorAsia Pacific CustomerResponse GroupTel:65-2544466Fax:65-2504466Email:sea.support@National SemiconductorJapan Ltd.Tel:81-3-5620-6175Fax:81-3-5620-6179Molded Dual-In-Line Package(N)Order Number DS9637ACNNS Package Number N08EDS9637ADualDifferentialLineReceiverNational does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.。

IC datasheet pdf-24LCS22A pdf datasheet

—
400
4.5V ≤ VCC ≤ 5.5V
2
THIGH
Clock high time
4000 600
—
ns 2.5V ≤ VCC ≤ 5.5V
—
4.5V ≤ VCC ≤ 5.5V
3Leabharlann TLOWClock low time
4700 1300
—
ns 2.5V ≤ VCC ≤ 5.5V
—
4.5V ≤ VCC ≤ 5.5V
for monitor identification, including recovery to DDC1
• 2 Kbit Serial EEPROM Low-power CMOS technology:
- 1 mA active current, typical - 10 μA standby current, typical at 5.5V • 2-wire serial interface bus, I2C™ compatible
—
V VCC ≥ 2.7V (Note)
D4
VIL
Low-level input voltage
—
0.2 VCC V VCC ≤ 2.7V (Note)
D5
VHYS
Hysteresis of Schmitt Trigger .05 VCC
—
Inputs
V (Note)
D6
VOL1
Low-level output voltage
TABLE 1-1: DC CHARACTERISTICS
DC CHARACTERISTICS
Vcc = +2.5V to 5.5V Industrial (I): TA = -40°C to +85°C

IC datasheet pdf-TPA6203A1,pdf(1.25-W Mono Fully Differential Audio Power Amplifier)

RECOMMENDED OPERATING CONDITIONS
MIN Supply voltage, VDD High-level input voltage, VIH Low-level input voltage, VIL Common-mode input voltage, VIC Operating free-air temperature, TA Load impedance, ZL SHUTDOWN SHUTDOWN VDD = 2.5 V, 5.5 V, CMRR ≤ -60 dB 0.5 -40 6.4 8 2.5 2 0.8 VDD-0.8 85 TYP MAX 5.5 UNIT V V V V °C Ω
1.25-W MONO FULLY DIFFERENTIAL AUDIO POWER AMPLIFIER
1
FEATURES
APPLICATIONS
• Designed for Wireless or Cellular Handsets and PDAs
• 1.25 W Into 8 Ω From a 5-V Supply at THD = 1% (Typical) • Low Supply Current: 1.7 mA Typical • Shutdown Control < 10 µA • Only Five External Components – Improved PSRR (90 dB) and Wide Supply Voltage (2.5 V to 5.5 V) for Direct Battery Operation – Fully Differential Design Reduces RF Rectification – Improved CMRR Eliminates Two Input Coupling Capacitors – C(BYPASS) Is Optional Due to Fully Differential Design and High PSRR • Avaliable in a 2 mm x 2 mm MicroStar Junior ™ BGA Package (GQV, ZQV) • Available in 3 mm x 3 mm QFN Package (DRB) • Available in an 8-Pin PowerPAD™ MSOP (DGN)

IC datasheet pdf-TAS5705,pdf(20-W stereo Digital Audio Power Amplifier)

TAS5705................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009 20-W STEREO DIGITAL AUDIO POWER AMPLIFIER WITH EQ AND DRCCheck for Samples:TAS5705FEATURES Sample Rates•Audio Input/Output–Thermal and Short-Circuit Protection –20-W Into an8-ΩLoad From an18-V Supply•Benefits–Wide Power-Supply Range From(8V to–EQ:Speaker Equalization Improves Audio 23V)Performance–Efficient Class-D Operation Eliminates–DRC:Dynamic Range Compression.Need for Heat Sinks Enables Power Limiting,SpeakerProtection,Easy Listening,Night-Mode –Requires Only Two Power-Supply RailsListening–Two Serial Audio Inputs(Four Audio–Autobank Switching:Preload Coefficients Channels)for Different Sample Rates.No Need to –Supports32-kHz–192-kHz Sample RatesWrite Any Coefficients to the Part When (LJ/RJ/I2S)Sample Rate Changes.–Headphone PWM Outputs–Autodetect:Automatically Detects –Subwoofer PWM Outputs Sample-Rate Changes.No Need for •Audio/PWM Processing External Microprocessor Intervention –Independent Channel Volume Controls With24-dB to–100-dB Range DESCRIPTION–Soft Mute(50%Duty Cycle)The TAS5705is a20-W,efficient,digital audio poweramplifier for driving stereo bridge-tied speakers.Two –Programmable Dynamic Range Controlserial data inputs allow processing of up to four –16Adaptable Biquads for Speaker EQdiscrete audio channels and seamless integration to –Seven Biquads for Left and Right most digital audio processors and MPEG decoders.Channels The device accepts a wide range of input data andclock rates.A fully programmable data path allows –Two Biquads for Subwoofer Channelthese channels to be routed to the internal speaker –Adaptive Coefficients for DRC Filtersdrivers or output via the line-level subwoofer or –Programmable Input and Output Mixers headphone PWM outputs.–DC Blocking FiltersThe TAS5705is a slave-only device receiving clocks –Loudness Compensation for Subwoofer from external sources.The TAS5705operates at a384-kHz switching rate for32-,48-,96-,and192-kHz –Automatic Sample Rate Detection anddata and352.8-kHz switching rate for44.1-,88.2-Coefficient Banking for DRC and EQand176.4-kHz data.The8×oversampling combined •General Featureswith the fourth-order noise shaper provides a flat –Serial Control Interface Operational Without noise floor and excellent dynamic range from20Hz MCLK to20kHz.–Factory-Trimmed Internal OscillatorEnables Automatic Detection of IncomingPlease be aware that an important notice concerning availability,standard warranty,and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.Digital is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.PRODUCTION DATA information is current as of publication date.Copyright©2008–2009,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasInstruments standard warranty.Production processing does notnecessarily include testing of all parameters.TAS5705SLOS549A–JUNE2008–REVISED SIMPLIFIED APPLICATION DIAGRAMB0264-012Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705TAS5705 ................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009 FUNCTIONAL VIEWCopyright©2008–2009,Texas Instruments Incorporated Submit Documentation Feedback3Product Folder Link(s):TAS5705TAS5705SLOS549A–JUNE2008–REVISED Figure1.Power Stage Functional Block Diagram4Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705BKND_ERR VALIDDVDDD V S SD V S S O S D I N 1S D I N 2L R C L K S C L K MCLK M U TE H P S E L O S C _R E SP D N S D A S C L V R _D I GV R E G _E N S T E S T T E S T 2HPL_PWM HPR_PWM SUB_PWM–SUB_PWM+GNDGND GVDD_CD V D D _B V D D _B V D D _C V D D _C PVDD_D PVDD_D G N D _A BG N D _A B G N D _C D G N D _C D VREG U T _AU T _B U T _B U T _C U T _C OUT_D U T _DS T _B S T _C BST_D P0071-01PAP Package (Top View)TAS5705 ................................................................................................................................................SLOS549A –JUNE 2008–REVISED SEPTEMBER 200964-PIN,HTQFP PACKAGE (TOP VIEW)TERMINAL FUNCTIONSTERMINAL TYPE5-V TERMINATIONDESCRIPTION(1)TOLERANT(2)NAME NO.AVDD 10P 3.3-V analog power supply.Needs close decoupling capacitor.AVSS 11P Analog 3.3-V supply groundBKND_ERR35DIPullupActive-low.A back-end error sequence is generated by applying logic LOW to this terminal.This pin is connected to an external power stage.If no external power stage is used,connect this pin directly to DVDD.BST_A 4P High-side bootstrap supply for half-bridge A BST_B 57P High-side bootstrap supply for half-bridge B BST_C 56P High-side bootstrap supply for half-bridge C BST_D 45PHigh-side bootstrap supply for half-bridge D(1)TYPE:A =analog;D =3.3-V digital;P =power/ground/decoupling;I =input;O =output(2)All pullups are 20-μA weak pullups and all pulldowns are 20-μA weak pulldowns.The pullups and pulldowns are included to assure proper input logic levels if the terminals are left unconnected (pullups →logic 1input;pulldowns →logic 0input).Devices that drive inputs with pullups must be able to sink 50μA while maintaining a logic-0drive level.Devices that drive inputs with pulldowns must be able to source 50μA while maintaining a logic-1drive level.Copyright ©2008–2009,Texas Instruments IncorporatedSubmit Documentation Feedback5Product Folder Link(s):TAS5705TAS5705SLOS549A–JUNE2008–REVISED TERMINAL FUNCTIONS(continued)TERMINAL TYPE5-V TERMINATIONDESCRIPTION(1)TOLERANT(2)NAME NO.DVDD15,33P 3.3-V digital power supplyDVSS20P Digital groundDVSSO26P Oscillator groundFAULT9DO Pullup Overtemperature,overcurrent,and undervoltage fault reporting.Active-low indicates fault.If high,normal operation.GND41,42P Analog ground for power stageGVDD_AB5P Gate drive internal regulated output for AB channelsGVDD_CD44P Gate drive internal regulated output for CD channelsHPL_PWM37DO Headphone left-channel PWM output.HPR_PWM38DO Headphone right-channel PWM output.HPSEL30DI5-V Headphone select,active-high.When a logic high is applied,deviceenters headphone mode and speakers are MUTED(HARD MUTE).When a logic LOW is applied,device is in speaker mode andheadphone outputs become line outputs or are disabled.When in lineout mode,this terminal functionality is disabled(see system controlregister2.LRCLK22DI5-V Input serial audio data left/right clock(sampling rate clock)MCLK34DI5-V MCLK is the clock master input.The input frequency of this clock canrange from4.9MHz to49.2MHz.MUTE21DI5-V Pullup Performs a soft mute of outputs,active-low.A logic low on this pinsets the outputs equal to50%duty cycle.A logic high on this pinallows normal operation.The mute control provides a noiselessvolume ramp to silence.Releasing mute provides a noiseless ramp toprevious volume.OC_ADJ8AO Analog overcurrent programming.Requires22-kΩresistor to ground. OSC_RES19AO Oscillator trim resistor.Connect an18.2-kΩ,1%tolerance resistor toDVSSO.OUT_A1,64O Output,half-bridge AOUT_B60,61O Output,half-bridge BOUT_C52,53O Output,half-bridge COUT_D48,49O Output,half-bridge DPDN17DI5-V Pullup Power down,active-low.PDN powers down all logic,stops all clocks,and stops output switching whenever a logic low is applied.WhenPDN is released,the device powers up all logic,starts all clocks,andperforms a soft start that returns to the previous configurationdetermined by register settings.PGND_AB62,63P Power ground for half-bridges A and BPGND_CD50,51P Power ground for half-bridges C and DPLL_FLTM12AO PLL negative loop filter terminalPLL_FLTP13AI PLL positive loop filter terminalPVDD_A2,3P Power supply input for half-bridge output A(8V–23V)PVDD_B58,59P Power supply input for half-bridge output B(8V–23V)PVDD_C54,55P Power supply input for half-bridge output C(8V–23V)PVDD_D46,47P Power supply input for half-bridge output D(8V–23V)RESET16DI5-V Pullup Reset,active-low.A system reset is generated by applying a logiclow to this terminal.RESET is an asynchronous control signal thatrestores the DAP to its default conditions,sets the VALID outputslow,and places the PWM in the hard-mute state(stops switching).Master volume is immediately set to full attenuation.Upon the releaseof RESET,if PDN is high,the system performs a4–5-ms deviceinitialization and sets the volume at mute.SCL29DI5-V I2C serial control clock input6Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705TAS5705 ................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009TERMINAL FUNCTIONS(continued)TERMINAL TYPE5-V TERMINATIONDESCRIPTION(1)TOLERANT(2)NAME NO.SCLK23DI5-V Serial audio data clock(shift clock).SCLK is the serial audio portinput data bit clock.SDA28DIO5-V I2C serial control data interface input/outputSDIN125DI5-V Serial audio data1input is one of the serial data input ports.SDIN1supports three discrete(stereo)data formats.SDIN224DI5-V Serial audio data2input is one of the serial data input ports.SDIN2supports three discrete(stereo)data formats.SSTIMER6AI Controls ramp time of OUT_X for pop-free operation.Leave this pinfloating for BD mode.Requires capacitor of2.2nF to GND in ADmode.The capacitor determines the ramp time of PWM outputs from0%to50%.For2.2nF,start/stop time is~10ms.STEST31DI Test pin.Connect directly to GND.SUB_PWM–39DO Subwoofer negative PWM outputSUB_PWM+40DO Subwoofer positive PWM outputTEST17DI Test pin.Connect directly to GND.TEST232DI Test pin.Connect directly to DVDD.VALID36DO Output indicating validity of ALL PWM channels,active-high.This pinis connected to an external power stage.If no external power stage isused,leave this pin floating.VR_ANA14P Internally regulated1.8-V analog supply voltage.This terminal mustnot be used to power external devices.VR_DIG27P Internally regulated1.8V digital supply voltage.This terminal must notbe used to power external devices.VREG43P 3.3Regulator output.Not to be used as s supply or connected to anyother components other than decoupling caps.Add decouplingcapacitors with pins42and41.VREG_EN18DI Pulldown Voltage regulator enable.Connect directly to GND.ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range(unless otherwise noted)(1)VALUE UNIT DVDD,AVDD–0.3to3.6V Supply voltagePVDD_X–0.3to30VOC_ADJ–0.3to4.2VInput voltage 3.3-V digital input–0.5to DVDD+0.5V 5-V tolerant(2)digital input–0.5to DVDD+2.5VOUT_x to PGND_X32(3)VBST_x to PGND_X43(3)VInput clamp current,I IK(V I<0or V I>1.8V)±20mA Output clamp current,I OK(V O<0or V O>1.8V)±20mA Operating free-air temperature0to85°C Operating junction temperature range0to150°C Storage temperature range,T stg–40to125°C (1)Stresses beyond those listed under absolute ratings may cause permanent damage to the device.These are stress ratings only andfunctional operation of the device at these or any other conditions beyond those indicated under recommended operation conditions are not implied.Exposure to absolute-maximum conditions for extended periods may affect device reliability.(2)5-V tolerant inputs are SCLK,LRCLK,MCLK,SDIN1,SDIN2,SDA,SCL,and HPSEL.(3)DC voltage+peak ac waveform measured at the pin should be below the allowed limit for all conditions.Copyright©2008–2009,Texas Instruments Incorporated Submit Documentation Feedback7Product Folder Link(s):TAS5705TAS5705SLOS549A–JUNE2008–REVISED DISSIPATION RATINGSDERATING FACTOR T A≤25°C T A=70°C T A=85°C PACKAGEABOVE T A=25°C POWER RATING POWER RATING POWER RATING10-mm×10-mm QFP40mW/°C5W 3.2W 2.6W RECOMMENDED OPERATING CONDITIONSMIN NOM MAX UNIT Digital/analog supply voltage DVDD,AVDD3 3.3 3.6VHalf-bridge supply voltage PVDD_X823VV IH High-level input voltage 3.3-V TTL,5-V tolerant2 5.5VV IL Low-level input voltage 3.3-V TTL,5-V tolerant0.8VT A Operating ambient temperature range085°CT J Operating junction temperature range0150°CR L(BTL)68Load impedance Output filter:L=15μH,C=0.68μFΩR L(SE) 3.24L O(BTL)10Minimum output inductance underOutput-filter inductanceμHshort-circuit conditionL O(SE)10PWM OPERATION AT RECOMMENDED OPERATING CONDITIONSPARAMETER TEST CONDITIONS MODE VALUE UNIT32–kHz data rate±2%12×sample rate384kHz Output sample rate2×–1×44.1-,88.2-,176.4-kHz data rate±2%8×,4×,and2×sample rates352.8kHz oversampled48-,96-,192-kHz data rate±2%8×,4×,and2×sample rates384kHz PLL INPUT PARAMETERS AND EXTERNAL FILTER COMPONENTSPARAMETER TEST CONDITIONS MIN TYP MAX UNITf MCLKI Frequency,MCLK(1/t cyc2) 4.949.2MHzMCLK duty cycle40%50%60%MCLK minimum high time8nsMCLK minimum low time8nsLRCLK allowable drift before LRCLK reset4MCLKs External PLL filter capacitor C1SMD0603Y5V47nFExternal PLL filter capacitor C2SMD0603Y5V 4.7nFExternal PLL filter resistor R SMD0603,metal film470Ω8Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705TAS5705 ................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009 ELECTRICAL CHARACTERISTICSDC CharacteristicsT A=25°,PVCC_X=18V,DVDD=AVDD=3.3V,R L=8Ω,BTL mode(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITV OH High-level output voltage 3.3-V TTL and5-V tolerant(1)I OH=–4mA 2.4VV OL Low-level output voltage 3.3-V TTL and5-V tolerant(1)I OL=4mA0.5V3.3-V TTL V I=V IL±2I IL(2)Low-level input currentμA5-V tolerant(1)V I=0V,DVDD=3V±23.3-V TTL V I=V IH±2I IH(2)High-level input currentμA5-V tolerant V I=5.5V,DVDD=3V±20Normal Mode6583Digital supply voltage(DVDD,Power down(PDN=823I DD Digital supply current mAAVDD)low)Reset(RESET=low)2338.5I PVDD Analog supply current No load(all PVDD inputs)3060Power down(PDN=5 6.3I PVDD(PDN)Power-down current No load(all PVDD inputs)mAlow)I PVDD(RESET)Reset current No load(all PVDD inputs)Reset(RESET=low)5 6.3Drain-to-source resistance,180T J=25°C,includes metallization resistanceLSr DS(on)mΩDrain-to-source resistance,T J=25°C,includes metallization resistance180HSI/O ProtectionV uvp Undervoltage protection limit PVDD falling7.2VV uvp,hyst Undervoltage protection limit PVDD rising7.6V OTE(3)Overtemperature error150°C Extra temperature dropOTE HYST(3)required to recover from30°C errorOLPC Overload protection counter f PWM=384kHz0.63msResistor—programmable,max.current, 4.5I OC Overcurrent limit protection AR OCP=22kΩI OCT Overcurrent response time150nsResistor tolerance=5%for typical value;the minimumOC programming resistorR OCP resistance should not be less than20kΩ.This value is2022kΩrangenot adjustable.It must be fixed at22kΩ.Internal pulldown resistor at Connected when RESET is active to provide bootstrapR PD3kΩthe output of each half-bridge capacitor charge.(1)5-V tolerant inputs are PDN,RESET,MUTE,SCLK,LRCLK,MCLK,SDIN1,SDIN2,SDA,SCL,and HPSEL.(2)I IL or I IH for pins with internal pullup can go up to50μA.(3)Specified by designCopyright©2008–2009,Texas Instruments Incorporated Submit Documentation Feedback9Product Folder Link(s):TAS5705TAS5705SLOS549A–JUNE2008–REVISED AC Characteristics(BTL)PVDD_X=18V,BTL mode,R L=8Ω,R OC=22KΩ,C BST=33nF,audio frequency=1kHz,AES17filter,f PWM=384kHz,T A=25°C(unless otherwise noted).All performance is in accordance with recommended operating conditions,unless otherwise specified.PARAMETER TEST CONDITIONS MIN TYP MAX UNITPVDD=18V,10%THD,1-kHz input signal20.0PVDD=18V,7%THD,1-kHz input signal18.6PVDD=12V,10%THD,1-kHz input9signalP O Power output per channel WPVDD=12V,7%THD,1-kHz input signal8.3PVDD=8V,10%THD,1-kHz input signal 3.9PVDD=8V,7%THD,1-kHz input signal 3.7PVDD=18V;P O=10W(half-power)0.12%THD+N Total harmonic distortion+noise PVDD=12V;P O=4.5W(half-power)0.1%PVDD=8V;P O=2W(half-power)0.24%V n Output integrated noise A-weighted50μV Crosstalk P O=1W,f=1kHz–73dBA-weighted,f=1kHz,maximum power atSNR Signal-to-noise ratio(1)105dBTHD<0.1%P D Power dissipation due to idle losses(I PVDD_X)P O=0W,4channels switching(2)0.6W(1)SNR is calculated relative to0-dBFS input level.(2)Actual system idle losses are affected by core losses of output inductors.AC Characteristics(Single-Ended Output)PVDD_X=18V,SE mode,R L=4Ω,R OC=22kΩ,C BST=33-nF,audio frequency=1kHz,AES17filter,f PWM=384kHz, ambient temperature=25°C(unless otherwise noted).All performance is in accordance with recommended operating conditions,unless otherwise specified.PARAMETER TEST CONDITIONS MIN TYP MAX UNITPVDD=18V,10%THD10PVDD=18V,7%THD9P O Power output per channel WPVDD=12V,10%THD 4.5PVDD=12V,7%THD4PVDD=18V,Po=5W(half-power)0.2THD+Total harmonic distortion+noise%N PVDD=12V,Po=2.25W(half-power)0.2V n Output integrated noise A-weighted50μV SNR Signal-to-noise ratio(1)A-weighted105dB DNR Dynamic range A-weighted,input level=–60dBFS using TAS5086modulator105dBPower dissipation due to idleP D P O=0W,4channels switching(2)0.6W losses(IPVDD_X)(1)SNR is calculated relative to0-dBFS input level.(2)Actual system idle losses are affected by core losses of output inductors.10Submit Documentation Feedback Copyright©2008–2009,Texas Instruments IncorporatedProduct Folder Link(s):TAS5705SERIAL AUDIO PORTS SLAVE MODEover recommended operating conditions(unless otherwise noted)TESTPARAMETER MIN TYP MAX UNITCONDITIONSf SCLKIN Frequency,SCLK32×f S,48×f S,64×f S C L=30pF 1.02412.288MHz t su1Setup time,LRCLK to SCLK rising edge10ns t h1Hold time,LRCLK from SCLK rising edge10ns t su2Setup time,SDIN to SCLK rising edge10ns t h2Hold time,SDIN from SCLK rising edge10ns LRCLK frequency3248192kHz SCLK duty cycle40%50%60%LRCLK duty cycle40%50%60%SCLK SCLK rising edges between LRCLK rising edges3264edgest(edge)SCLK LRCLK clock edge with respect to the falling edge of SCLK–1/41/4periodFigure2.Slave Mode Serial Data Interface TimingSCLSDAT0027-01 SCLSDAStart ConditionStopConditionT0028-01I2C SERIAL CONTROL PORT OPERATIONTiming characteristics for I2C Interface signals over recommended operating conditions(unless otherwise noted)PARAMETER TEST CONDITIONS MIN MAX UNIT f SCL Frequency,SCL No wait states400kHz t w(H)Pulse duration,SCL high0.6μs t w(L)Pulse duration,SCL low 1.3μs t r Rise time,SCL and SDA300ns t f Fall time,SCL and SDA300ns t su1Setup time,SDA to SCL100ns t h1Hold time,SCL to SDA0ns t(buf)Bus free time between stop and start condition 1.3μs t su2Setup time,SCL to start condition0.6μs t h2Hold time,start condition to SCL0.6μs t su3Setup time,SCL to stop condition0.6μs C L Load capacitance for each bus line400pFFigure3.SCL and SDA TimingFigure4.Start and Stop Conditions TimingRESETVALIDtStart systemSystem initialization.Enable via I C.2T0029-05PDNVALIDt T0030-04RESET TIMING (RESET)Control signal parameters over recommended operating conditions (unless otherwise noted)PARAMETERMIN TYP MAX UNIT t d(VALID_LOW)Time to assert VALID (reset to power stage)low 100ns t w(RESET)Pulse duration,RESET active 100200ns t d(I2C_ready)Time to enable I 2C3.5ms t d(run)Device start-up time (after start-up command via I 2C)10msNOTE:On power up,it is recommended that the TAS5705be held LOW for at least 100μs after DVDD has reached3.0V.RESET assertion is ignored if applied while part is powered downFigure 5.Reset TimingPOWER-DOWN (PDN)TIMINGControl signal parameters over recommended operating conditions (unless otherwise noted)PARAMETERMINTYP MAXUNIT t d(VALID_LOW)Time to assert VALID (reset to power stage)low 725μs t d(STARTUP)Device startup time650μs t wMinimum pulse duration required1μsNOTE:PDNZ assertion is ignored if applied when part is in RESETFigure 6.Power-Down TimingDVDD PVDDT0317-01DVDDRESETPDNT0318-01Figure7.Power Up and Power Down of Power SuppliesNOTE:t power_down=time to wait before powering down the supplies after assertion=725μs+power-stage stop time defined by register0x1AFigure8.Terminal Control and DVDDBKND_ERRVALIDVOLUMEMUTET0032-03BACK-END ERROR (BKND_ERR)Control signal parameters over recommended operating conditions (unless otherwise noted)PARAMETERMIN TYP MAX UNIT t w(ER)Minimum pulse duration,BKND_ERR active (active-low)350nst p(valid_high)Programmable.Time to stay in the VALID (reset to the power stage)low state.After t p(valid_high),the TAS5705attempts to bring the system out of the VALID low state if 300ms BKND_ERR is high.t p(valid_low)Time TAS5705takes to bring VALID (reset to the power stage)low after BKND_ERR ns400assertion.Figure 9.Error Recovery TimingMUTE TIMING Control signal parameters over recommended operating conditions (unless otherwise noted)PARAMETERMINTYP MAXUNIT Volume ramp time (=number of steps ×step size).Number of steps is defined by volume t d(VOL)configuration register 0x0E (see Volume Configuration Register ).Step size =4LRCLKs if 1024stepsf S ≤48kHz;else 8LRCLKs if f S ≤96kHz ;else 16LRCLKsFigure 10.Mute TimingHP VolumeHPSELVALIDSpkr VolumeSpkr VolumeHPSELVALIDHP VolumeHEADPHONE SELECT (HPSEL)PARAMETERMIN MAX UNIT t w(MUTE)Pulse duration,HPSEL active 350ns t d(VOL)Soft volume update timeSee(1)ms t (SW)Switch-over time (controlled by start/stop period register,0x1A)0.2ms(1)Defined by the volume slew rate setting (see the volume configuration register ,0x0E).Figure 11and Figure 12show functionality when bit 4in the HP configuration register is set to DISABLE (not in line-out mode).See register 0x05for details.If bit 4is not set,than the HP PWM outputs are not disabled when HPSEL is brought low.Figure 11.HPSEL Timing for Headphone InsertionFigure 12.HPSEL Timing for Headphone Extractionf − Frequency − Hz 201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %20kG0030.0010.01100.11f − Frequency − Hz 201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %20kG0020.0010.01100.11f − Frequency − Hz201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %20kG0010.0010.01100.11P O − Output Power − W0.010.1110T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %40G006TYPICAL CHARACTERISTICS,BTL CONFIGURATIONTOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsFREQUENCYFREQUENCYFigure 13.Figure 14.TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsFREQUENCY OUTPUT POWERFigure 15.Figure 16.P O − Output Power − W 0.010.111040G005P O − Output Power − W 0.010.111040G004P O − Total Output Power − W0.00.51.01.52.02.53.0510152025303540G008P O − Output Power (Per Channel) − W010203040506070809010002468101214161820E f f i c i e n c y − %G007TOTAL HARMONIC DISTORTION +NOISE (BTL)TOTAL HARMONIC DISTORTION +NOISE (BTL)vsvsOUTPUT POWEROUTPUT POWERFigure 17.Figure 18.EFFICIENCYSUPPLY CURRENTvsvsOUTPUT POWERTOTAL OUTPUT POWERFigure 19.Figure 20.PVDD − Supply Voltage − V051015202568101214161820P O − O u t p u t P o w e r − WG009−100−95−90−85−80−75−70−65−60 f − Frequency − Hz C r o s s t a l k − d BG012201001k10k 20kOUTPUT POWERCROSSTALKvsvsSUPPLY VOLTAGEFREQUENCYFigure 21.Figure 22.f − Frequency − Hz 201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0011020k0.1G01210.01f − Frequency − Hz 201001k10k T H D +N − T o t a l H a r m o n i c D i s t o r t i o n + N o i s e − %0.0011020k0.1G01210.01V CC − Supply Voltage − V369121518510152025P O − O u t p u t P o w e r − WG014P O − Output Power − W 0.010.111040G013TYPICAL CHARACTERISTICS,SE CONFIGURATIONTOTAL HARMONIC DISTORTION +NOISETOTAL HARMONIC DISTORTION +NOISEvsvsFREQUENCYFREQUENCYFigure 23.Figure 24.TOTAL HARMONIC DISTORTION +NOISEOUTPUT POWERvsvsOUTPUT POWER SUPPLY VOLTAGEFigure 25.Figure 26.TAS5705 ................................................................................................................................................SLOS549A–JUNE2008–REVISED SEPTEMBER2009DETAILED DESCRIPTIONPOWER SUPPLYTo facilitate system design,the TAS5705needs only a3.3-V digital supply in addition to the(typical)18-V power-stage supply.An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally,all circuitry requiring a floating voltage supply,e.g.,the high-side gate drive,is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.In order to provide good electrical and acoustical characteristics,the PWM signal path for the output stage is designed as identical,independent half-bridges.For this reason,each half-bridge has separate bootstrap pins (BST_X),and power-stage supply pins(PVDD_X).The gate drive voltages(GVDD_AB and GVDD_CD)are derived from the PVDD voltage.Separate,internal voltage regulators reduce and regulate the PVDD voltage to a voltage appropriate for efficient gave drive operation.Special attention should be paid to placing all decoupling capacitors as close to their associated pins as possible.In general,inductance between the power-supply pins and decoupling capacitors must be avoided.For a properly functioning bootstrap circuit,a small ceramic capacitor must be connected from each bootstrap pin (BST_X)to the power-stage output pin(OUT_X).When the power-stage output is low,the bootstrap capacitor is charged through an internal diode connected between the gate-drive power-supply pin(GVDD_X)and the bootstrap pin.When the power-stage output is high,the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver.In an application with PWM switching frequencies in the range from352kHz to384kHz,it is recommended to use33-nF ceramic capacitors, size0603or0805,for the bootstrap supply.These33-nF capacitors ensure sufficient energy storage,even during minimal PWM duty cycles,to keep the high-side power stage FET(LDMOS)fully turned on during the remaining part of the PWM cycle.Special attention should be paid to the power-stage power supply;this includes component selection,PCB placement,and routing.As indicated,each half-bridge has independent power-stage supply pins(PVDD_X).For optimal electrical performance,EMI compliance,and system reliability,it is important that each PVDD_X pin is decoupled with a100-nF ceramic capacitor placed as close as possible to each supply pin.The TAS5705is fully protected against erroneous power-stage turnon due to parasitic gate charging.SYSTEM POWER-UP/POWER-DOWN SEQUENCEPowering UpThe outputs of the H-bridges remain in a low-impedance state until the internal gate-drive supply voltage (GVDD_XY)and external VREG voltages are above the undervoltage protection(UVP)voltage threshold(see the DC Characteristics section of this data sheet).It is recommended to hold PVDD_X low until DVDD(3.3V)is powered up while powering up the device.This allows an internal circuit to charge the external bootstrap capacitors by enabling a weak pulldown of the half-bridge output.The output impedance is approximately3kΩ. This means that the TAS5705should be held in reset for at least100μs to ensure that the bootstrap capacitors are charged.This also assumes that the recommended0.033-μF bootstrap capacitors are used.Changes to bootstrap capacitor values change the bootstrap capacitor charge time.See Figure7and Figure8.Powering DownApply PDN(assert low).Wait for the power stage to shut down.Power down PVDD.Then power down DVDD. Then de-assert See Figure8for recommended timing.ERROR REPORTINGThe pin is an active-low,open-drain output.Its function is for protection-mode signaling to a system-control device.Any fault resulting in device shutdown is signaled by the pin going low(see Table1).。

IC datasheet pdf-OPA4830,pdf(Quad, Low-Power, Single-Supply, Wideband Operational Amplifier)

Copyright © 2006–2008, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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Copyright © 2006–2008, Texas Instruments Incorporated
OPA4830
.................................................................................................................................................... SBOS350A – DECEMBER 2006 – REVISED MAY 2008
APPLICATIONS
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LA5667PDF资料下载_LA5667DATASHEET文档

MOX-5-122004J - MOX-5-122005F - MOX-5-122006F - MOX-5-122506F - MOX5-12-2506F - MOX5-12-250MEGO -MOX5-123.49MEG1 - MOX-5-123004J - MOX512349MEG1 - MOX5-12349MEG1 - MOX-5-124003J - MOX-5-124005J - MOX-5-124006J - MOX-5-124006P - MOX-5-125005K - MOX-5-125006J - MOX-5-125605J - MOX-5-126004J - MOX-5-126604F - MOX-5-126904F - MOX-5-127604F - MOX-5-128504J - MOX513 - MOX-5-1310 - MOX-5-131003F - MOX-5-131004F - MOX5-13-100-5 - MOX-5-131005F - MOX-5-131007F - MOX-5-131007G - MOX5-131007G - MOX5131007J - MOX-5-131007J - MOX5-13-1007J - MOX-5-131007K -MOX-5-131008F - MOX-5-131009F - MOX5-13-100MEG-5 - MOX5-13-10MEG-5 - MOX-5-131506F - MOX-5-131507J -MOX-5-132003F - MOX-5-132006F - MOX-5-132006J - MOX-5-132006K - MOX-5-133003K - MOX-5-133006F - MOX-5-133205F - MOX-5-133205F1 - MOX-5-133205G - MOX-5-134003J - MOX-5-134005F - MOX-5-13-4005F - MOX-5-134005J - MOX-5-134006F - MOX-5-13-40MEG-1P - MOX5-13-40MEG-1PC - MOX-5-13-40MEG-1PCT - MOX5-13-40MEG-1PCT - MOX-5-135003F -MOX5136504J - MOX-5-136504J - MOX-5-136504J1 - MOX5136MEG1 - MOX-5-13-6MEG-1 - MOX-5-137503J - MOX5-153J -MOX5183J - MOX5-183J - MOX5-1R0J - MOX5202J - MOX5-202J - MOX5-221J - MOX5-223J - MOX5297F - MOX5-297F - MOX52R2J - MOX5-2R2J - MOX5-3-5 - MOX5-6.6MEG-1PCT - MOX-5-622005F - MOX-5-625004K - MOX-5-625004KE - MOX5821J - MOX5-821J - MOX-5-931008J1 - MOX5R15J - MOX5-R15J - MOX5-R200J - MOX5RD - MOX-5RD - MOX68EM05F32 - MOX68EM05JB4 -MOX68EM05JP7 - MOX68EM08BD48 - MOX68EML05SB7 - MOX68EML08GP32 - MOX68EML08SR12 - MOX68PA08XL36BFU -MOX-5-122003FIC供应：859-302、2N3415D26、NAS43DD3-77N、50398SMC50398、SPX2810AR25T、859303、2N3415D26Z、NAS43DD378、50399、SPX2810AR-2-5T、859-303、2N3415-D26Z、NAS43DD3-78、503990-1、SPX2810AR-2-5-T、85930-3、2N3415D26Z0、NAS43DD378FC、503990-2、SPX2810AR-25TR、859304、2N3415D26Z2N3415、NAS43DD3-78FC、503991、SPX2810AR-2-5TR 。

2-963211-1中文资料

2-963211-1 Product DetailsHome | Customer Support | Suppliers | Site Map | Privacy Policy | Browser Support© 2008 Tyco Electronics Corporation All Rights Reserved SearchProducts Documentation Resources My Account Customer Support Home > Products > By Type > Product Feature Selector > Product Details2-963211-1Active Timer ConnectorsAlways EU RoHS/ELV Compliant (Statement of Compliance)Product Highlights:?Tab Header?Connector Type = Junior Power Timer?Number of Positions = 6?Pre-Tinned Tab Plating?Phosphor Bronze Tab MaterialView all Features | Find SimilarProductsCheck Pricing &AvailabilitySearch for ToolingProduct FeatureSelectorContact Us AboutThis ProductQuick LinksDocumentation & Additional InformationProduct Drawings:? 6 pos. tabheader, 3mm(PDF, English)Catalog Pages/Data Sheets:?None AvailableProduct Specifications:?None AvailableApplication Specifications:?None AvailableInstruction Sheets:?None AvailableCAD Files:?None AvailableList all Documents Related Products: ?ToolingProduct Features (Please use the Product Drawing for all design activity)Product Type Features:?Product Type = Tab Header?Connector Type = Junior Power Timer ?Number of Positions = 6Electrical Characteristics:?Tab Material = Phosphor BronzeBody Related Features:?Centerline (mm [in]) = 5.00 [0.197]Contact Related Features:?Tab Plating = Pre-Tinned Housing Related Features:?Housing Color = Gray?Housing Material = PBT - GF 30Industry Standards:?RoHS/ELV Compliance = RoHS compliant, ELVcompliant?Lead Free Solder Processes = Not relevant forlead free process?RoHS/ELV Compliance History = Always wasRoHS compliantOther:?Brand = AMPProvide Website Feedback | Contact Customer Support。

AU6987 DataBook V1.0.1_111110

AU6987USB2.0 Universal Flash DiskController Technical Reference ManualRev. 1.0.125 July. 2010AU6987USB2.0 Universal Flash DiskControllerRev. 1.0.125 July. 2010AU6987 USB2.0 Universal Flash Disk Controller V1.0.1 C o p y r i g h tCopyright © 1997 - 2009. Alcor Micro, Corp. All Rights Reserved. No part of this data sheet may be reproduced, transmitted, transcribed, stored in a retrieval system or translated into any language or computer language, in any form or by any means, electronic, mechanical, magnetic, optical, chemical, manual or otherwise, without prior written permission from Alcor Micro, Corp.T r a d e m a r k A c k n o w l e d g e m e n t sThe company and product names mentioned in this document may be the trademarks or registered trademarks of their manufacturers.D i s c l a i m e rAlcor Micro, Corp. reserves the right to change this product without prior notice. Alcor Micro, Corp. makes no warranty for the use of its products and bears no responsibility for any errors that appear in this document. Specifications are subject to change without prior notice.R e v i s i o n H i s t o r yDate Revision DescriptionJuly 2009 0.90 Preliminary ReleaseJuly 2010 1.0.1 Official ReleaseC o n t a c t I n f o r m a t i o n:Web site: /Taiwan China ShenZhen OfficeAlcor Micro, Corp. Rm.2407-08, Industrial Bank Building9F., No.66, Sanchong Rd., No.4013, Shennan Road,Nangang District, Taipei 115, ShenZhen,China. 518026Taiwan, R.O.C.Phone: 886-2-2653-5000 Phone: (0755) 8366-9039Fax: 886-2-2786-8567 Fax: (0755) 8366-9101San Jose Office Los Angeles Office2025 Gateway Place, Suite 335 8351 Elm Ave, Suite 103San Jose, CA 95110 Rancho Cucamonga, CA 91730USA USA Phone: (408) 453-9530 Phone: (909) 483-8821Fax: (408) 453-9523 Fax: (909) 944-0464AU6987 USB2.0 Universal Flash Disk Controller V1.0.1 <Memo>AU6987 USB2.0 Universal Flash Disk Controller V1.0.1Table of Contents1. Introduction (3)1.1 Description (3)1.2 Features (3)2. Application Block Diagram (5)3. Pin Assignment (6)4. System Architecture and Reference Design (12)4.1 AU6987 Block Diagram (12)5. Electrical Characteristics (13)5.1 Absolute Maximum Ratings (13)5.2 Recommended Operating Conditions (13)5.3 General DC Characteristics (13)5.4 DC Electrical Characteristics of 3.3V I/O Cells (14)5.5 USB Transceiver Characteristics (14)6. Mechanical Information (18)7. Abbreviations (20)iAU6987 USB2.0 Universal Flash Disk Controller V1.0.1 List of FiguresFigure 2.1 Block Diagram (5)Figure 3.1 AU6987-GHL Pin Assignment Diagram (6)Figure 3.2 AU6987-GIL Pin Assignment Diagram (9)Figure 4.1 AU6987 Block Diagram (12)Figure 6.1 48 LQFP Mechanical Information Diagram (18)Figure 6.2 64 LQFP Mechanical Information Diagram (19)List of TablesTable 3.1 AU6987-GHL Pin Descriptions (7)Table 3.3 AU6987-GIL Pin Descriptions (10)Table 5.1 Absolute Maximum Ratings (13)Table 5.2 Recommended Operating Conditions (13)Table 5.3 General DC Characteristics (13)Table 5.4 DC Electrical Characteristics of 3.3V I/O Cells (14)Table 5.5 Electrical characteristics (14)Table 5.6 Static characteristic：Digital pin (15)Table 5.7 Static characteristic：Analog I/O pins（DP/DM） (15)Table 5.8 Dynamic characteristic：Analog I/O pins（DP/DM） (16)iiAU6987 USB2.0 Universal Flash Disk Controller V1.0.1 1. Introduction1.1D e s c r i p t i o nThe AU6987 USB 2.0 Flash Disk Controller is the best high performance solutions for SLC, MLC, TLC NAND and AG-AND with multiple dies data flash. Its high-speed read (32MB/Sec) and write access performance enable users to transfer and backup data effectively. Besides, AU6987 is certified by USB-IF (USB Implementers Forum), WHQL (Window Hardware Quality Labs) and EMI tests to guarantee the quality and reliability for end-users.With multiple functions integrated into one chip and external components built inside, AU6987 is pledged to deliver the best performance benchmark and to further reduce the BOM cost of end products adopting this solution. It provides dual channel access and ISP (In-System Programming) technologies, which are the most important features to allow manufacturers building high performance UFD easily and to have the flexibility of adopting different source of flash chips. Same as its siblings of product family, AU6987 features the auto-run function to prompt the designated AP automatically when plugging into PC. In addition to being as a removable storage device, AU6987 can also be configured as a bootable disk for system recovery. Also, its random access performance exceed the minimum requirement of Read Boost feature found in Microsoft Vista operating system, in which randomly access blocks of information are saved into UFD for boosting up the average performance.To enhance the usefulness and manageability of UFD further, Alcor Micro develops a smart application program iStar (Partition/Password Operation Tool) as a handy utility in managing partition, password and security. Having iStar as the companion of UFD, the data in a UFD could be protected from unauthorized access successfully.1.2F e a t u r e sz PCBs are pin compatible in AU6986, AU6986T.z Integrate build-in regulatorz 30bit/1024Bytes BCH ECC enginesz Supports SLC , MLC and TLC dual channel with high performancez Improve read performance reach 32MB/Secz Supports firmware upgrade mechanism(ISP, In-System Programming)z Integrates hardware DMA engine to tune up the operation performancez Integrates multi-bit ECC correction mechanismz Complies with the standards defined in USB v2.0, USB Device Class Definition for Mass Storage and Bulk-Transport v1.0z Works with default driver under the environments of Windows ME, Windows 2000, Windows XP, Mac 9.2, Mac OS X. Using Alcor Micro’s vendor driver forthe environment under Windows 98SEz Concurrent bus operation using multiple FIFO for better performancez Integrates into flash memory power control switchz Supports bad block managementz Supports dynamic serial number modification via mass production software z Supports software write protectionz Support Auto Run function3AU6987 USB2.0 Universal Flash Disk Controller V1.0.1 z Support erasable and read-only mode AP Diskz Companion application program with UFD – iStar available for users¾ To have UFD partition management function¾ To do password protection for the security in data access¾ To guard data files with software write protection function¾ To lock up PC by UFD as the keyz Available in 48-pin LQFP 7x7mm package to support 4CE pin flashx2pcs z Available in 64-pin LQFP 7x7mm package to support 4CE pin flashx4pcs 4AU6987 USB2.0 Universal Flash Disk Controller V1.0.1 2. Application Block DiagramThe following figure shows the application diagram of a typical flash disk product with AU6987. By connecting the flash disk to a desktop or notebook PC through USB bus, AU6987 is then turned into a bus-powered, high speed USB disk, which can be used as a bridge for data transfer between Desktop PC and Notebook PC.Figure 2.1 Block Diagram5AU6987 USB2.0 Universal Flash Disk Controller V1.0.13. Pin AssignmentDepending on the application, the AU6987 is available in two different packages. Below figure shows signal name for each pin and the table in the page after describes each pin in detail.Figure 3.1 AU6987-GHL Pin Assignment Diagram6Table 3.1 AU6987-GHL Pin DescriptionsPin # Pin Name I/O Description1 GND GND Ground2 VDD I 1.8V power3 DM I/O USB DM4 DP I/O USB DP5 REXT I External resistor 330 to ground6 VD33 I 3.3V power7 VS33P GND Ground8 VSSA GND Ground9 XI I 12 MHz oscillator input10 XO O 12 MHz oscillator output11 VDDA I 1.8V power for PLL12 AGND5V I Ground13 AVDD5V I 5V input power pin14 VDD3V O 3.3V output power pin15 V18 O 1.8V output for Core16 WPN O Flash Write Protect Pin( Low Active)17 VDDH I 3.3V input power pin18 VSSH GND Ground19 GPO O blanking when system access20 FMWP I Flash Write Protect Pin by Firmware(High Active)21 FMENABN3 O Flash 3 select pin22 FMENABN2 O Flash 2 select pin23 FMENABN1 O Flash 1 select pin24 FMENABN0 O Flash 0 select pin25 FMRBN1 I Flash 1 ready pin26 FMRBN2 I Flash 2 ready pin27 FMDATH7 I/O Flash high data 7 pin28 FMDATH6 I/O Flash high data 6 pin29 FMDATH5 I/O Flash high data 5 pin30 FMDATH4 I/O Flash high data 4 pin31 FMDATH3 I/O Flash high data 3 pin7Pin # Pin Name I/O Description32 FMDATH2 I/O Flash high data 2 pin33 FMDATH1 I/O Flash high data 1 pin34 FMDATH0 I/O Flash high data 0 pin35 FMRDN O Flash read signal36 FMWRN O Flash write signal37 FMDATL7 I/O Flash low data 7 pin38 FMDATL6 I/O Flash low data 6 pin39 FMDATL5 I/O Flash low data 5 pin40 FMDATL4 I/O Flash low data 4 pin41 FMDATL3 I/O Flash low data 3 pin42 FMDATL2 I/O Flash low data 2 pin43 FMDATL1 I/O Flash low data 1 pin44 FMDATL0 I/O Flash low data 0 pin45 FMCLE O Flash command latch pin46 FMALE O Flash address latch pin47 FMRBN3 I Flash 3 ready pin48 FMRBN0 I Flash 0 ready pin89The following figure shows signal name of each pin in 64-pin package and the table in the page after describes each pin in detail.Figure 3.2 AU6987-GIL Pin Assignment DiagramTable 3.3 AU6987-GIL Pin DescriptionsPin # Pin Name I/O Description1 NC - NC2 NC - NC3 NC - NC4 FMENABN4 O Flash 4 select pin5 FMENABN5 O Flash 5 select pin6 GND GND Ground7 VDD I 1.8V power8 DM I/O USB DM9 DP I/O USB DP10 REXT I External resistor 330 to ground11 VD33 I 3.3V power12 VS33P GND Ground13 VSSA GND Ground14 XI I 12 MHz oscillator input15 XO O 12 MHz oscillator output16 VDDA I 1.8V power for PLL17 AGND5V I Ground18 AVDD5V I 5V input power pin19 VDD3V O 3.3V output power pin20 V18 O 1.8V output for Core21 WPN O Flash Write Protect Pin( Low Active)22 VDDHM I 3.3V input power pin23 VSSHM GND Ground24 FMENABN7 O Flash 7 select pin25 FMENABN6 O Flash 6 select pin26 GPO O blanking when system access27 FMWP I Flash Write Protect Pin by Firmware(High Active)28 FMENABN3 O Flash 3 select pin29 FMENABN2 O Flash 2 select pin30 FMENABN1 O Flash 1 select pin31 FMENABN0 O Flash 0 select pin32 NC - NC1011Pin #Pin NameI/ODescription33 NC I Hardware test T0 34 NC I Hardware test T1 35 NC I Hardware test T2 36 NC - -37 FMRBN1 I Flash 1 ready pin 38 FMRBN2 I Flash 2 ready pin39 FMDATH7 I/O Flash high data 7 pin 40 FMDATH6 I/O Flash high data 6 pin 41 FMDATH5 I/O Flash high data 5 pin 42 FMDATH4 I/O Flash high data 4 pin 43 FMDATH3 I/O Flash high data 3 pin 44 FMDATH2 I/O Flash high data 2 pin 45 FMDATH1 I/O Flash high data 1 pin 46 FMDATH0 I/O Flash high data 0 pin 47 FMRDN O Flash read signal 48 FMWRN O Flash write signal 49 FMDATL7 I/O Flash low data 7 pin 50 FMDATL6 I/O Flash low data 6 pin 51 FMDATL5 I/O Flash low data 5 pin 52 FMDATL4 I/O Flash low data 4 pin 53 FMDATL3 I/O Flash low data 3 pin 54 FMDATL2 I/O Flash low data 2 pin 55 FMDATL1 I/O Flash low data 1 pin 56 FMDATL0 I/O Flash low data 0 pin 57 FMCLE O Flash command latch pin 58 FMALE O Flash address latch pin 59 FMRBN3 I Flash 3 ready pin 60 FMRBN0 I Flash 0 ready pin 61 NC - NC 62 NC - NC 63 NC - NC 64NC-NC4. System Architecture and Reference Design4.1A U6987B l o c k D i a g r a mFigure 4.1 AU6987 Block Diagram1.8V SIEUSB Upstream PortSupport NANDFlash Memory 125. Electrical Characteristics5.1A b s o l u t e M a x i m u m R a t i n g sTable 5.1 Absolute Maximum RatingsSymbol Parameter Rating UnitsV DDH Power Supply -0.3 to V DDH +0.3 VV IN Input Signal Voltage -0.3 to 3.6 VV OUT Output Signal Voltage-0.3 to V DDH +0.3 VT STG Storage Temperature-40 to 150 O C5.2 Recommended Operating ConditionsTable 5.2 Recommended Operating ConditionsSymbol Parameter Min. Typ. Max. UnitsA DD5V Power Supply 4.75 5.0 5.25 VV DDH Power Supply 3.0 3.3 3.6 V V DD Digital Supply 1.62 1.8 1.98 V V IN Input Signal Voltage 0 3.3 3.6 V T OPR Operating Temperature 0 70 O C 5.3G e n e r a l D C C h a r a c t e r i s t i c sTable 5.3 General DC CharacteristicsSymbol Parameter Conditions Min.Typ. Max. UnitsI IN Input current No pull-up orpull-down-10 ±1 10 μAI OZ Tri-state leakage current-10 ±1 10 μA C IN Input capacitance Pad Limit 2.8 ρF C OUT Output capacitance Pad Limit 2.8 ρFC BID Bi-directional buffercapacitancePad Limit 2.8 ρF135.4D C E l e c t r i c a l C h a r a c t e r i s t i c s o f3.3V I/O C e l l sTable 5.4 DC Electrical Characteristics of 3.3V I/O CellsLimitsSymbol Parameter ConditionsMin.Typ. Max.Unit V DDH Power supply 3.3V I/O 3.0 3.3 3.6 V V il Input low voltage 0.8 VV ih Input high voltage LVTTL2.0 VV ol Output low voltage ∣I ol∣=2~16mA 0.4 V V oh Output high voltage ∣I oh∣=2~16mA 2.4 V R pu Input pull-up resistance PU=high, PD=low55 75 110 KΩR pd Input pull-down resistance PU=low, PD=high40 75 150 KΩI in Input leakage current V in= V DDH or 0 -10 ±1 10 μAI oz Tri-state output leakagecurrent-10 ±1 10 μA5.5U S B T r a n s c e i v e r C h a r a c t e r i s t i c sTable 5.5 Electrical characteristicsSymbol Parameter Conditions Min.Typ. Max.Unit VD33 Analog supply Voltage 3.0 3.3 3.6 V VDDUVDDADigital supply Voltage 1.62 1.8 1.98 VI CC Operating supply current High speed operatingat 480 MHz55mAI CC (susp)Suspend supply currentIn suspend mode,current with 1.5kΩpull-up resistor on pinRPU disconnected120μA1415Table 5.6 Static characteristic ：Digital pin Symbol ParameterConditionsMin. Typ. Max. UnitInput levelsV IL Low-level input voltage 0.8 V V IHHigh-level input voltage2.0VOutput levelsV OL Low-level output voltage 0.2 V V OHHigh-level output voltageVDDH-0.2VVD33=3.0V~3.6V ；VDDU,VDDA=1.62V~1.98V ；Temp=0℃~70℃Table 5.7 Static characteristic ：Analog I/O pins （DP/DM ）Symbol Parameter Conditions Min.Typ. Max. UnitUSB2.0 Transceiver （HS ）Input Levels （differential receiver ）V HSDIFFHigh speed differential input sensitivity ∣V I （DP ）-V I （DM ）∣measured at theconnection asapplication circuit300 mV V HSCM High speed data signalingcommon mode voltagerange -50 500 mV Squelch detected 100 mV V HSSQHigh speed squelch detection thresholdNo squelch detected150mVDisconnectiondetected625 mVV HSDSCHigh speed disconnection detection threshold Disconnection notdetected 525 mVOutput LevelsV HSOI High speed idle leveloutput voltage(differential) -10 10 mVV HSOL High speed low leveloutput voltage(differential) -10 10 mVV HSOH High speed high leveloutput voltage(differential) -360 400 mVV CHIRPJChirp-J output voltage（differential ） 700 1100 mV V CHIRPKChirp-K output voltage（differential ）-900 -500 mV ResistanceEquivalent resistanceused as internal chiponly3 6 9 R DRVDriver output impedanceOverall resistance including external resistor 40.5 45 49.5Ω TerminationV TERMTermination voltage for pull-up resistor on pin RPU3.0 3.6 VUSB1.1 Transceiver （FS/LS ） Input Levels （differential receiver ）V DI Differential inputsensitivity∣V I （DP ）-V I （DM ）∣ 0.2 VV CMDifferential commonmode voltage0.8 2.5 VInput Levels （single-ended receivers ）V SE Single ended receiverthreshold0.8 2.0 VOutput levels V OL Low-level output voltage 0 0.3 V V OHHigh-level output voltage2.83.6VVD33=3.0V~3.6V ；VDDU,VDDA=1.62V~1.98V ；Temp=0℃~70℃Table 5.8 Dynamic characteristic ：Analog I/O pins （DP/DM ）SymbolParameterConditionsMin.Typ.Max.UnitDriver Characteristics High-Speed Modet HSR High-speed differentialrise time500 ps t HSFHigh-speed differential falltime500 psFull-Speed Modet FR Rise timeCL=50pF ；10 to 90﹪of ∣V OH -V OL ∣； 4 20 ns t FF Fall timeCL=50pF ；90 to 10﹪of ∣V OH -V OL ∣； 4 20 ns t FRMADifferential rise/fall timematching （t FR / t FF ）Excluding the firsttransition from idle mode90 110 ％ V CRS Output signal crossovervoltageExcluding the firsttransition from idlemode1.32.0 V Low-Speed Mode1617t LR Rise time CL=200pF-600pF ；10 to 90﹪of∣V OH -V OL ∣；75 300 ns t LF Fall time CL=200pF-600pF ；90 to 10﹪of∣V OH -V OL ∣；75 300 ns t LRMA Differential rise/fall time matching （t LR / t LF ） Excluding the first transition from idle mode80 125 ％ V CRS Output signal crossover voltage Excluding the first transition from idle mode1.32.0 V V OHHigh-level output voltage2.83.6 V6. Mechanical InformationFigure 6.1 48 LQFP Mechanical Information Diagram19Figure 6.2 64 LQFP Mechanical Information Diagram7. AbbreviationsIn this chapter some of the terms and abbreviations used throughout the technical reference manual are listed as follows.SIE Serial Interface EngineCF Compact FlashMD Micro DriveSMC SmartMedia CardMS Memory StickSD Secure DigitalMMC Multimedia CardUTMI USB Transceiver Macrocell InterfaceAbout Alcor Micro, Corp.Alcor Micro, Corp. designs, develops and markets highly integrated and advanced peripheral semiconductor, and software driver solutions for the personal computer and consumer electronics markets worldwide. We specialize in USB solutions and focus on emerging technology such as USB and IEEE 1394. The company offers a range of semiconductors including controllers for USB hub, integrated keyboard/USB hub and USB Flash memory card reader…etc. Alcor Micro, Corp. is based in Taipei, Taiwan, with sales offices in Taipei, Japan, Korea and California. Alcor Micro is distinguished by its ability to provide innovative solutions for spec-driven products. Innovations like single chip solutions for traditional multiple chip products and on-board voltage regulators enable the company to provide cost-efficiency solutions for the computer peripheral device OEM customers worldwide.。

HSMP-382x, 482x Surface Mount RF PIN Switch and Li

HSMP-382x, 482xSurface Mount RF PIN Switch and Limiter DiodesData SheetFeatures∙ Diodes Optimized for:Low Current Switching Low Distortion Attenuating ∙ Power Limiting/Circuit Protection∙ Surface Mount SOT-23 and SOT-323 Packages Single and Dual VersionsTape and Reel Options Available ∙ Low Failure in Time (FIT) Rate [1]∙ Lead-freeNote:1. For more information see the Surface Mount PIN Reliability Data Sheet.Package Lead Code Identifi cation, SOT-323 (Top View)Description/ApplicationsThe HSMP-382x series is o ptimized for switch i ng ap-plications where ultra-low resistance is required. The HSMP-482x diode is ideal for limiting and low induc-tance switching applications up to 1.5 GHz.A SPICE model is not available for PIN diodes as SPICE does not provide for a key PIN diode characteristic, carrier lifetime.Package Lead Code Identifi cation, SOT-23 (Top View)SERIESAbsolute Maximum Ratings [1] T C = +25°CSymbol ParameterUnitSOT-23SOT-323I fForward Current (1 μs Pulse) Amp 1 1P IV PeakInverse Voltage V 5050T j Junction Temperature °C 150 150T stgStorage Temperature°C-65 to 150-65 to 150θjc ThermalResistance [2] °C/W 500 150Notes:1. Operation in excess of any one of these conditions may result in permanent damage to the device.2. T C = +25°C, where T C is defi ned to be the temperature at the package pins where contact ismade to the circuit board.Minimum Maximum Typical Maximum Typical Part Package Breakdown Series Total Total Total Number Marking Lead Voltage Resistance Capacitance Capacitance Inductance HSMP- Code Code Confi gurationV BR (V) R S (Ω) C T (pF) C T (pF) L T (nH)4820 FA A Dual Anode 500.60.75 1.2 1.0 482B FAA Dual Anode Test Conditions V R = V BRI F = 10 mA f = 1 MHzf = 1 MHz f = 500 MHz –Measure V R = 20 VV R = 0 V3 GHzI R ≤ 10 μAHigh Frequency (Low Inductance, 500 MHz – 3 GHz) PIN DiodesElectrical Specifi cations T C = 25°CPackage Minimum Maximum Maximum Part Number Marking Lead Breakdown Series Resistance Total Capacitance HSMP- Code Code Confi guration Voltage V BR (V) R S (Ω) C T (pF) 3820 F00 Single 500.60.83822 F2 2 Series 3823 F3 3 Common Anode 3824 F44 Common CathodeT est ConditionsV R = V BR f = 100 MHzf = 1 MHzMeasure I F = 10 mA V R = 20 VI R ≤ 10 μATypical Parameters at T C = 25°CPart NumberSeries ResistanceCarrier LifetimeReverse Recovery TimeTotal CapacitanceHSMP- R S (Ω)τ (ns)T rr (ns)C T (pF)382x1.570 7 0.60 @ 20 VT est Conditions f = 100 MHz I F = 10 mAV R = 10 VI F = 10 mAI F = 20 mA90% RecoveryTypical Parameters at T C = 25°C (unless otherwise noted), Single DiodeTypical Applications for Multiple Diode ProductsRF 2Figure 7. Simple SPDT Switch, Using Only Positive Current.Figure 8. High Isolation SPDT Switch, Dual Bias.RF COMMONRF 1Typical Applications for Multiple Diode Products, continuedBIASFigure 9. Switch Using Both Positive and Negative Bias Current.Figure 10. Very High Isolation SPDT Switch, Dual Bias.Figure 11. High Isolation SPST Switch (Repeat Cells as Required.Figure 12. Power Limiter Using HSMP-3822 Diode Pair. See Application Note 1050 for details.RF 2Typical Applications for HSMP-482x Low Inductance SeriesMicrostrip Series Connection for HSMP-482x SeriesIn order to take full advantage of the low inductance of the HSMP-482x series when using them in series applications, both lead 1 and lead 2 should be connected together, as shown in Figure 14.Figure 16. Equivalent Circuit.Co-Planar Waveguide Shunt Connection for HSMP-482x SeriesCo-Planar waveguide, with ground on the top side of the printed circuit board, is shown in Figure 17. Since it eliminates the need for via holes to ground, it off ers lower shunt parasitic inductance and higher maximum attenuation when compared to a microstrip circuit. SeeAN1050 for details.GROUND BY TWOVIA HOLES3Figure 13. Internal Connections.Figure 14. Circuit Layout.Microstrip Shunt Connections for HSMP-482x SeriesIn Figure 15, the center conductor of the microstrip line is interrupted and leads 1 and 2 of the HSMP-482x diode are placed across the resulting gap. This forces the 0.5 nH lead inductance of leads 1 and 2 to appear as part of a low pass fi lter, reducing the shunt parasitic inductance and increasing the maximum available attenuation. The 0.3 nH of shunt inductance external to the diodeis created by the via holes, and is a good estimate for 0.032" thick material.Figure 15. Circuit Layout, HSMP-482x Limiter.Figure 17. Circuit Layout.Figure 18. Equivalent Circuit.Center ConductorAssembly InformationSOT-323 PCB FootprintA recommended PCB pad layout for the miniature SOT-323 (SC-70) package is shown in Figure 19 (dimensions are in inches). This layout provides ample allowance for package placement by automated assembly equipment without adding parasitics that could impair the performance.0.079Dimensions in inches0.0310.8Dimensions ininches mmFigure 19. Recommended PCB Pad Layout for Avago’s SC70 3L/SOT-323 Products.SOT-23 PCB FootprintFigure 20. Recommended PCB Pad Layout for Avago’s SOT-23 Products.SMT AssemblyReliable assembly of surface mount components is a complex process that involves many material, process, and equipment factors, including: method of heating (e.g., IR or vapor phase refl ow, wave soldering, etc.) circuit board material, conductor thickness and pattern, type of solder alloy, and the thermal conductivity and thermal mass of components. Components with a low mass, such as the SOT-323/-23 package, will reach solder refl ow temperatures faster than those with a greater mass. Avago’s diodes have been qualifi ed to the time-temperature profi le shown in Figure 21. This profi le is representative of an IR refl ow type of surface mount assembly process.After ramping up from room temperature, the circuit board with components attached to it (held in place with solder paste) passes through one or more preheat zones.The preheat zones increase the temperature of the board and components to prevent thermal shock and begin evaporating solvents from the solder paste. The refl ow zone briefl y elevates the temperature suffi ciently to produce a refl ow of the solder. The rates of change of temperature for the ramp-up and cool-down zones are chosen to be low enough to not cause d eformation o f t he b oard o r d amage t o c omponents due to thermal shock. The maximum temperature in the refl ow zone (T MAX ) should not exceed 260°C. These parameters are typical for a surface mount assembly process for Avago diodes. As a general guideline, the circuit board and components should be exposed only to the minimum temperatures and times necessary to achieve a uniform refl ow of solder.Figure 21. Surface Mount Assembly Profi le.25T e m p e r a t u r eT Lead-Free Refl ow Profi le Recommendation (IPC/JEDEC J-STD-020C)Refl ow ParameterLead-Free AssemblyAverage ramp-up rate (Liquidus Temperature (T S(max) to Peak)3°C/ second max PreheatTemperature Min (T S(min))150°C Temperature Max (T S(max))200°CTime (min to max) (t S )60-180 seconds Ts(max) to TL Ramp-up Rate 3°C/second maxTime maintained above:Temperature (T L )217°CTime (t L )60-150 secondsPeak Temperature (T P ) 260+0/-5°C Time within 5 °C of actual Peak temperature (t P )20-40 seconds Ramp-down Rate6°C/second max Time 25 °C to Peak Temperature8 minutes maxNote 1: All temperatures refer to topside of the package, measured on the package body surfacePackage CharacteristicsLead Material .......................................................Copper (SOT-323); Alloy 42 (SOT-23)Lead Finish ............................................................................Tin 100% (Lead-free option)Maximum Soldering Temperature ...............................................260°C for 5 seconds Minimum Lead Strength ..............................................................................2 pounds pull Typical Package Inductance ..........................................................................................2 nH Typical Package Capacitance .................................................0.08 pF (opposite leads)Ordering InformationSpecify part number followed by option. For example: HSMP - 382x - XXXBulk or Tape and Reel Option Part Number; x = Lead CodeSurface Mount PINOption Descriptions-BLKG = Bulk, 100 pcs. per antistatic bag-TR1G = Tape and Reel, 3000 devices per 7" reel -TR2G = Tape and Reel, 10,000 devices per 13" reelTape and Reeling conforms to Electronic Industries RS-481, “Taping of Surface Mounted Components for Automated Placement.”Package DimensionsOutline 23 (SOT-23)Outline SOT-323 (SC-70)e2E1A1Notes:XXX-package marking Drawings are not to scaleDIMENSIONS (mm)MIN.0.790.0000.300.082.731.150.891.780.452.100.45MAX.1.200.1000.540.203.131.501.022.040.602.700.69SYMBOL A A1B C D E1e e1e2ELE1A1Notes:XXX-package marking Drawings are not to scaleDIMENSIONS (mm)MIN.0.800.000.150.081.801.101.800.26MAX.1.000.100.400.252.251.402.400.46SYMBOL A A1B C D E1e e1E L1.30 typical 0.65 typicalTape Dimensions and Product Orientation For Outline SOT-23Device OrientationFor Outlines SOT-23/323DESCRIPTIONSYMBOL SIZE (mm)SIZE (INCHES)LENGTH WIDTH DEPTH PITCHBOTTOM HOLE DIAMETERA 0B 0K 0P D 13.15 ± 0.102.77 ± 0.101.22 ± 0.104.00 ± 0.101.00 + 0.050.124 ± 0.0040.109 ± 0.0040.048 ± 0.0040.157 ± 0.0040.039 ± 0.002CAVITYDIAMETER PITCH POSITIOND P 0E1.50 + 0.104.00 ± 0.101.75 ± 0.100.059 + 0.0040.157 ± 0.0040.069 ± 0.004PERFORATIONWIDTH THICKNESSW t18.00 +0.30 –0.100.229 ± 0.0130.315 +0.012 –0.0040.009 ± 0.0005CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION)CAVITY TO PERFORATION (LENGTH DIRECTION)F P 23.50 ± 0.052.00 ± 0.050.138 ± 0.0020.079 ± 0.002DISTANCE BETWEEN CENTERLINETape Dimensions and Product Orientation For Outline SOT-323For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5989-4026EN AV02-1395EN - April 24, 2012(CARRIER TAPE THICKNESS)DESCRIPTIONSYMBOL SIZE (mm)SIZE (INCHES)LENGTH WIDTH DEPTH PITCHBOTTOM HOLE DIAMETER A 0B 0K 0P D 1 2.40 ± 0.102.40 ± 0.101.20 ± 0.104.00 ± 0.101.00 + 0.250.094 ± 0.0040.094 ± 0.0040.047 ± 0.0040.157 ± 0.0040.039 + 0.010CAVITYDIAMETER PITCH POSITION D P 0E 1.55 ± 0.054.00 ± 0.101.75 ± 0.100.061 ± 0.0020.157 ± 0.0040.069 ± 0.004PERFORATIONWIDTH THICKNESS W t 18.00 ± 0.300.254 ± 0.020.315 ± 0.0120.0100 ± 0.0008CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION)CAVITY TO PERFORATION (LENGTH DIRECTION)F P 23.50 ± 0.052.00 ± 0.050.138 ± 0.0020.079 ± 0.002DISTANCEFOR SOT-323 (SC70-3 LEAD)An8C MAX FOR SOT-363 (SC70-6 LEAD)10C MAXANGLEWIDTHTAPE THICKNESS C T t5.4 ± 0.100.062 ± 0.0010.205 ± 0.0040.0025 ± 0.00004COVER TAPE。