ZL30100中文资料

1Features•Supports Telcordia GR-1244-CORE Stratum 4 and Stratum 4E•Supports ITU-T G.823 and G.824 for 2048kbit/s and 1544kbit/s interfaces•Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces •Simple hardware control interface•Accepts two input references and synchronizes to any combination of 8kHz, 1.544MHz, 2.048MHz, 8.192MHz or 16.384MHz inputs•Provides a range of clock outputs: 1.544MHz,2.048MHz, 16.384MHz and either 4.096MHz and 8.192MHz or 32.768MHz and 65.536MHz •Provides 5 styles of 8kHz framing pulses •Holdover frequency accuracy of 1.5 x 10-7•Lock, Holdover and selectable Out of Range indication•Selectable loop filter bandwidth of 1.8Hz or 922Hz •Less than 0.6 ns pp intrinsic jitter on all output clocks •External master clock source: clock oscillator or crystalApplications•Synchronization and timing control for multi-trunk DS1/E1 systems such as DSLAMs, gateways and PBXs•Clock and frame pulse source for ST-BUS, GCI and other time division multiplex (TDM) buses •Line Card synchronization for PDH systemsOctober 2004ZL30100T1/E1 System SynchronizerData SheetFigure 1 - Functional Block DiagramReference MonitorMode ControlVirtual ReferenceIEEE 1149.1aFeedbackTIE Corrector EnableState MachineFrequency Select MUXTIE Corrector CircuitMODE_SEL1:0TCK REF1RSTREF_SELTIE_CLRC1.5oC4/C65o C8/C32o C16o F4/F65o F8/F32o F16oOSCo OSCi Master ClockTDOREF0TDI TMS TRSTHOLDOVER BW_SEL HMS LOCK REF_FAIL0REF_FAIL1DPLLOUT_SELC2oE1SynthesizerDS1SynthesizerMUXOOR_SEL Ordering InformationZL30100QDC64 pin TQFP-40°C to +85°CDescriptionThe ZL30100 T1/E1 System Synchronizer contains a digital phase-locked loop (DPLL), which provides timing and synchronization for multi-trunk T1 and E1 transmission equipment.The ZL30100 generates ST-BUS and other TDM clock and framing signals that are phase locked to one of two input references. It helps ensure system reliability by monitoring its references for accuracy and stability and by maintaining stable output clocks during reference switching operations and during short periods when a reference is unavailable.The ZL30100 is intended to be the central timing and synchronization resource for network equipment that complies with Telcordia, ETSI, ITU-T and ANSI network specifications.Table of Contents1.0 Change Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.1 Reference Select Multiplexer (MUX). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.2 Reference Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.3 Time Interval Error (TIE) Corrector Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123.4 Digital Phase Lock Loop (DPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153.5 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.6 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163.7 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164.0 Control and Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164.1 Out of Range Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164.2 Loop Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.3 Output Clock and Frame Pulse Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.4 Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.4.1 Freerun Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .174.4.2 Holdover Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184.4.3 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184.5 Reference Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .195.0 Measures of Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205.2 Jitter Generation (Intrinsic Jitter). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205.3 Jitter Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205.4 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205.5 Frequency Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.6 Holdover Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.7 Pull-in Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.8 Lock Range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.9 Phase Slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.10 Time Interval Error (TIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.11 Maximum Time Interval Error (MTIE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.12 Phase Continuity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .215.13 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .216.0 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226.1 Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257.0 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267.2 Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31List of FiguresFigure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4 - Behaviour of the Dis/Requalify Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5 - DS1 Mode Out-of-Range Limits (OOR_SEL=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6 - E1 Mode Out-of-Range Limits (OOR_SEL=1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 7 - Timing Diagram of Hitless Reference Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 8 - Timing Diagram of Hitless Mode Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 9 - DPLL Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 10 - Mode Switching in Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 11 - Reference Switching in Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 12 - Recommended Power Supply Decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 13 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Figure 14 - Crystal Oscillator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 15 - Power-Up Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 16 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Figure 17 - Input to Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 18 - Output Timing Referenced to F8/F32o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301.0 Changes SummaryChanges from June 2004 Issue to September 2004 Issue. Page, section, figure and table numbers refer to this issue.Page Item Change1Text Jitter changed to 0.6 ns from 0.5 ns6Figure 2Added note specifying not e-Pad7Table “Pin Description“Added information about Schmitt trigger feedback paths toC1.5o, C2o, C16o, and F8/F32o10Section 3.2Added text about input pulse width restriction15Section 3.4Added details to "Lock Indicator" on LOCK pin behaviour19Section 4.5Added text and Figure 11 explaining LOCK pin behaviour20Section 5.0Added Jitter definition26Table “Absolute Maximum Ratings*“Corrected package power rating27Table “DC Electrical Characteristics*“Corrected current consumptionCorrected input voltage characteristics to reflect Schmitt triggerCorrected input leakage current to reflect internal pull-upsCorrected output voltage note to reflect two pad strengths28Table “AC Electrical Characteristics* -Added explanatory noteInput timing for REF0 and REF1references (see Figure 17)“Changed jitter numbers32Table “Performance Characteristics*:Output Jitter Generation - ANSIT1.403 Conformance“Changed jitter number32Table “Performance Characteristics*:Output Jitter Generation - ITU-TG.812 Conformance“Changed jitter numbers, removed UI column32Table “Performance Characteristics* -Unfiltered Intrinsic Jitter“2.0 Physical Description2.1 Pin ConnectionsFigure 2 - Pin Connections (64 pin TQFP, please see Note 1)Note 1: The ZL30100 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30100does not use the e-Pad TQFP .ZL3010034363840424446486462605856525054161412108642OSCo NC GND OUT_SEL C1.5o MODE_SEL1V DD AV DD IC NC RSTNC AGNDF4/F65o V DD REF1NC ICC 8/C 32o N C C 2o A G N DA V D DN C F 8/F 32o C 4/C 65o REF_SEL1820222426303228C 16o F16o TIE_CLR OOR_SELICOSCi A V D DA V D DA V D DA V C O R EA G N D A G N D A G N D NC NC IC ICMODE_SEL0NC BW_SELREF0V C O R EL O C K H M ST R S T G N DT D O T M S H O L D O V E R I C T C K T D I V C O R EA V C O R EG N D R E F _F A I L 0R E F _F A I L 12.2 Pin DescriptionPin DescriptionPin # Name Description1GND Ground. 0 V.2V CORE Positive Supply Voltage. +1.8 V DC nominal.3LOCK Lock Indicator (Output). This output goes to a logic high when the PLL is frequencylocked to the selected input reference.4HOLDOVER Holdover (Output). This output goes to a logic high whenever the PLL goes intoholdover mode.5REF_FAIL0Reference 0 Failure Indicator (Output). A logic high at this pin indicates that the REF0 reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or thatit is exhibiting abrupt phase or frequency changes.6IC Internal bonding Connection. Leave unconnected.7REF_FAIL1Reference 1 Failure Indicator (Output). A logic high at this pin indicates that the REF1 reference frequency has exceeded the out-of-range limit set by the OOR_SEL pin or thatit is exhibiting abrupt phase or frequency changes.8TDO Test Serial Data Out (Output). JTAG serial data is output on this pin on the falling edge of TCK. This pin is held in high impedance state when JTAG scan is not enabled.9TMS Test Mode Select (Input). JTAG signal that controls the state transitions of the TAPcontroller. This pin is internally pulled up to V DD. If this pin is not used then it should beleft unconnected.10TRST Test Reset (Input). Asynchronously initializes the JTAG TAP controller by putting it in the Test-Logic-Reset state. This pin should be pulsed low on power-up to ensure thatthe device is in the normal functional state. This pin is internally pulled up to V DD. Ifthis pin is not used then it should be connected to GND.11TCK Test Clock (Input): Provides the clock to the JTAG test logic. If this pin is not used then it should be pulled down to GND.12V CORE Positive Supply Voltage. +1.8 V DC nominal.13GND Ground. 0 V.14AV CORE Positive Analog Supply Voltage. +1.8 V DC nominal.15TDI Test Serial Data In (Input). JTAG serial test instructions and data are shifted in on this pin. This pin is internally pulled up to V DD. If this pin is not used then it should be leftunconnected.16HMS Hitless Mode Switching (Input). The HMS circuit controls phase accumulation during the transition from Holdover or Freerun mode to Normal mode on the same reference. Alogic low at this pin will cause the ZL30100 to maintain the delay stored in the TIEcorrector circuit when it transitions from Holdover or Freerun mode to Normal mode. Alogic high on this pin will cause the ZL30100 to measure a new delay for its TIE correctorcircuit thereby minimizing the output phase movement when it transitions from Holdoveror Freerun mode to Normal mode.17MODE_SEL0Mode Select 0 (Input). This input combined with MODE_SEL1 determines the mode(Normal, Holdover or Freerun) of operation, see Table4 on page17.18MODE_SEL1Mode Select 1 (Input). See MODE_SEL0 pin description.Pin # Name Description19RST Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300ns after the power supply pins have reachedthe minimum supply voltage. When the RST pin goes high, the device will transitioninto a Reset state for 3ms. In the Reset state all outputs will be forced into highimpedance.20OSCo Oscillator Master Clock (Output). For crystal operation, a 20MHz crystal is connected from this pin to OSCi. This output is not suitable for driving other devices. For clockoscillator operation, this pin must be left unconnected.21OSCi Oscillator Master Clock (Input). For crystal operation, a 20MHz crystal is connected from this pin to OSCo. For clock oscillator operation, this pin must be connected to aclock source.22IC Internal Connection. Leave unconnected.23GND Ground. 0V.24NC No internal bonding Connection. Leave unconnected.25V DD Positive Supply Voltage. +3.3 V DC nominal.26OUT_SEL Output Selection (Input).This input selects the signals on the combined output clock and frame pulse pins, see Table3 on page17.27IC Internal Connection. Connect this pin to ground.28IC Internal Connection. Connect this pin to ground.29AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.30NC No internal bonding Connection. Leave unconnected.31NC No internal bonding Connection. Leave unconnected.32C1.5o Clock 1.544MHz (Output). This output is used in DS1 applications.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.33AGND Analog Ground. 0 V34AGND Analog Ground. 0 V35AV CORE Positive Analog Supply Voltage. +1.8 V DC nominal.36AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.37AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.38NC No internal bonding Connection. Leave unconnected.39NC No internal bonding Connection. Leave unconnected.40AGND Analog Ground.0V41AGND Analog Ground.0V42C4/C65o Clock 4.096MHz or 65.536MHz (Output). This output is used for ST-BUS operation at2.048Mbps, 4.096Mbps or 65.536MHz (ST-BUS 65.536Mbps). The output frequency isselected via the OUT_SEL pin.Pin # Name Description43C8/C32o Clock 8.192MHz or 32.768MHz (Output). This output is used for ST-BUS and GCI operation at 8.192Mbps or for operation with a 32.768MHz clock. The output frequencyis selected via the OUT_SEL pin.44AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.45AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.46C2o Clock 2.048MHz (Output). This output is used for standard E1 interface timing and for ST-BUS operation at 2.048Mbps.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.47C16o Clock 16.384MHz (Output). This output is used for ST-BUS operation with a16.384MHz clock.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.48F8/F32o Frame Pulse (Output). This is an 8kHz 122ns active high framing pulse (OUT_SEL=0) or it is an 8kHz 31ns active high framing pulse (OUT_SEL=1), which marks thebeginning of a frame.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.49F4/F65o Frame Pulse ST-BUS 2.048Mbps or ST-BUS at 65.536MHz clock (Output). Thisoutput is an 8kHz 244ns active low framing pulse (OUT_SEL=0), which marks thebeginning of an ST-BUS frame. This is typically used for ST-BUS operation at2.048Mbps and 4.096Mbps. Or this output is an 8kHz 15ns active low framing pulse(OUT_SEL=1), typically used for ST-BUS operation with a clock rate of 65.536MHz.50F16o Frame Pulse ST-BUS 8.192Mbps (Output). This is an 8kHz 61ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used for ST-BUSoperation at 8.192Mbps.51AGND Analog Ground.0V52IC Internal Connection. Connect this pin to ground.53REF_SEL Reference Select (Input). This input selects the input reference that is used forsynchronization, see Table5 on page19. This pin is internally pulled down to GND.54NC No internal bonding Connection. Leave unconnected.55REF0Reference (Input). This is one of two (REF0, REF1) input reference sources used for synchronization. One of five possible frequencies may be used: 8kHz, 1.544MHz,2.048MHz, 8.192MHz or 16.384MHz. This pin is internally pulled down to GND.56NC No internal bonding Connection. Leave unconnected.57REF1Reference (Input). See REF0 pin description.58NC No internal bonding Connection. Leave unconnected.Pin # Name Description59IC Internal Connection. Connect this pin to ground.60OOR_SEL Out Of Range Selection (Input). This pin selects the out of range reference rejection limits, see Table1 on page16.61V DD Positive Supply Voltage. +3.3 V DC nominal.62NC No internal bonding Connection. Leave unconnected.63TIE_CLR TIE Corrector Circuit Reset (Input). A logic low at this input resets the Time IntervalError (TIE) correction circuit resulting in a realignment of the input phase with the outputphase.64BW_SEL Filter Bandwidth Selection (Input). This pin selects the bandwidth of the DPLL loopfilter, see Table2 on page17. Set continuously high to track jitter on the input referenceclosely or set temporarily high to allow the ZL30100 to quickly lock to the input reference.3.0 Functional DescriptionThe ZL30100 is a DS1/E1 System Synchronizer providing timing (clock) and synchronization (frame) signals to interface circuits for DS1 and E1 Primary Rate Digital Transmission links, see Table 1. Figure 1 is a functional block diagram which is described in the following sections.3.1 Reference Select Multiplexer (MUX)The ZL30100 accepts two simultaneous reference input signals and operates on their rising edges. One of them, the primary reference (REF0) or the secondary reference (REF1) signal can be selected as input to the TIE corrector circuit based on the reference selection (REF_SEL) input.3.2 Reference MonitorThe input references are monitored by two independent reference monitor blocks, one for each reference. The block diagram of a single reference monitor is shown in Figure 3. For each reference clock, the frequency is detected and the clock is continuously monitored for three independent criteria that indicate abnormal behavior of the reference signal, for example; long term drift from its nominal frequency or excessive jitter. To ensure proper operation of the reference monitor circuit, the minimum input pulse width restriction of 15nsec must be observed.•Reference Frequency Detector: This detector determines whether the frequency of the reference clock is 8kHz, 1.544MHz, 2.048MHz, 8.192MHz or 16.384MHz and provides this information to the various monitor circuits and the phase detector circuit of the DPLL.•Precise Frequency Monitor: This circuit determines whether the frequency of the reference clock is within the applicable out-of-range limits selected by the OOR_SEL pin, see Figure 5, Figure 6 and Table 1. It will take the precise frequency monitor up to 10 s to qualify or disqualify the input reference.•Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of approximately 30 µs to quickly detect large frequency changes.•Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock.Figure 3 - Reference Monitor CircuitExceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into Holdover mode and feed a timer that disqualifies the reference input signal when the failures are present for more than 2.5s. The single cycle and coarse frequency failures must be absent for 10s to let the timer requalify the input reference signal as valid. Multiple failures of less than 2.5s each have an accumulative effect and will disqualify the reference eventually. This is illustrated in Figure 4.Figure 4 - Behaviour of the Dis/Requalify TimerWhen the incoming signal returns to normal (REF_FAIL=0), the DPLL returns to Normal mode with the output signal locked to the input signal. Each of the monitors has a build-in hysteresis to prevent flickering of the REF_FAIL status pin at the threshold boundaries. The precise frequency monitor and the timer do not affect the mode (Holdover/Normal) of the DPLL. Reference Frequency Detector Single Cycle Monitor Precise Frequency MonitorCoarse Frequency Monitor dis/requalify timerREF0 / REF1OR OR REF_DIS= reference disrupted.This is an internal signal.Mode select state machine HOLDOVERREF_DIS REF_FAIL0 / REF_FAIL12.5 s10 scurrent REFtimerREF_FAILSCM or CFM failureHOLDOVERFigure 5 - DS1 Mode Out-of-Range Limits (OOR_SEL=0)Figure 6 - E1 Mode Out-of-Range Limits (OOR_SEL=1)3.3 Time Interval Error (TIE) Corrector CircuitThe TIE corrector circuit eliminates phase transients on the output clock that may occur during reference switching or the recovery from Holdover mode to Normal mode.On the recovery from Holdover mode (dependent on the HMS pin) or when switching to another reference input, the TIE corrector circuit measures the phase delay between the current phase (feedback signal) and the phase of the selected reference signal. This delay value is stored in the TIE corrector circuit. This circuit creates a new virtual reference signal that is at the same phase position as the feedback signal. By using the virtual reference, the PLL minimizes the phase transient it experiences when it switches to another reference input or recovers from Holdover mode.。