R1973BBLKGILGR1;中文规格书,Datasheet资料
LM73CIMK-1中文资料
LM732.7V,SOT-23,11-to-14Bit Digital Temperature Sensor with 2-Wire InterfaceGeneral DescriptionThe LM73is an integrated,digital-output temperature sensor featuring an incremental Delta-Sigma ADC with a two-wire interface that is compatible with the SMBus and I 2C ®inter-faces.The host can query the LM73at any time to read temperature.Available in a 6-pin SOT-23package,the LM73occupies very little board area while operating over a wide temperature range (-40˚C to 150˚C)and providing ±1.0˚C accuracy from -10˚C to 80˚C.The user can optimize be-tween the conversion time and the sensitivity of the LM73by programming it to report temperature in any of four different resolutions.Defaulting to 11-bit mode (0.25˚C/LSB),the LM73measures temperature in a maximum time of 14ms,making it ideal for applications that require temperature data very soon after power-up.In its maximum resolution,14-bit mode (0.03125˚C/LSB),the LM73is optimized to sense very small changes in temperature.A single multi-level address line selects one of three unique device addresses.An open-drain ALERT output goes active when the temperature exceeds a programmable limit.Both the data and clock lines are filtered for excellent noise toler-ance and reliable communication.Additionally,a time-out feature on the clock and data lines causes the LM73to automatically reset these lines if either is held low for an extended time,thus exiting any bus lock-up condition without processor intervention.Applicationsn Portable Electronics n Notebook Computers n Automotiven System Thermal Management nOffice ElectronicsKey Specificationsj Supply Voltage 2.7V to 5.5Vj Supply Currentoperating 320µA (typ)495µA (max)shutdown8µA (max)1.9µA (typ)j Temperature −10˚C to 80˚C ±1.0˚C (max)Accuracy−25˚C to 115˚C ±1.5˚C (max)−40˚C to 150˚C±2.0˚C (max)j Resolution 0.25˚C to 0.03125˚Cj Conversion Time11-bit (0.25˚C)14ms (max)14-bit (0.03125˚C)112ms (max)Featuresn Single address pin offers choice of three selectable addresses per version for a total of six possible addresses.n SMBus and I 2C-compatible two-wire interface n Supports 400kHz operationn Shutdown mode with one-shot feature available for very low average power consumptionn Programmable digital temperature resolution from 11bits to 14bits.n Fast conversion rate ideal for quick power up and measuring rapidly changing temperaturen Open-drain ALERT output pin goes active whentemperature is above a programmed temperature limit n Very stable,low-noise digital ouput.n UL Recognized ComponentTypical Application20147803I 2C is a registered trademark of Philips Electronics N.V.CorporationJuly 2006LM732.7V,SOT-23,11-to-14Bit Digital Temperature Sensor with 2-Wire Interface©2006National Semiconductor Corporation Simplified Block Diagram20147801Connection DiagramSOT23-620147802TOP VIEWL M 73 2Ordering InformationPart Number PackageMarkingNS PackageNumberTransportMediaSMBus Device AddressAddress Pin Device AddressLM73CIMK-0T730MK06A(Thin SOT23-6)1000Units onTape and ReelFloatGroundV DD100100010010011001010LM73CIMKX-0T730MK06A(Thin SOT23-6)3000Units onTape and ReelFloatGroundV DD100100010010011001010LM73CIMK-1T731MK06A(Thin SOT23-6)1000Units onTape and ReelFloatGroundV DD100110010011011001110LM73CIMKX-1T731MK06A(Thin SOT23-6)3000Units onTape and ReelFloatGroundV DD100110010011011001110Note1:Available in RoHS-compliant packages.More details at .Pin DescriptionsLabel Pin#Type Equivalent Circuit FunctionADDR1Logic Input,threelevels Address Select Input:One of three device addresses is selected by connecting to ground,left floating,or connecting to V DD.GND2Ground GroundV DD3Power Supply VoltageSMBCLK4CMOS LogicInput Serial Clock:SMBus clock signal. Operates up to400kHz.Low-pass filtered.ALERT5Open-DrainOutput Digital output which goes active whenever the measured temperature exceeds a programmable temperature limit.SMBDAT6Open-DrainInput/OutputSerial Data:SMBus bi-directionaldata signal used to transfer serialdata synchronous to the SMBCLK.Low-pass filtered.LM733Absolute Maximum Ratings (Note 2)Supply Voltage −0.3V to 6.0VVoltage at Any Pin −0.3V to (V DD +0.5V)Input Current at Any Pin (Note 3)±5mAStorage Temperature −65˚C to +150˚CESD Susceptibility (Note 5)Human Body Model 2000V Machine Model200VSoldering process must comply with National Semiconductor’s Reflow Temperature Profilespecifications.Refer to /packaging.(Note 4)Operating Ratings(Note 2)Specified Temperature Range T MIN ≤T A ≤T MAX -40˚C ≤T A ≤+150˚CSupply Voltage Range (V DD )+2.7V to +5.5VTemperature-to-Digital Converter CharacteristicsUnless otherwise noted,these specifications apply for V DD =2.7V to 5.5V.Boldface limits apply for T A =T J =T MIN to T MAX ;all other limits T A =T J =+25˚C,unless otherwise noted.T A is the ambient temperature.T J is the junction temperature.ParameterConditionsTypical Limits Units (Note 6)(Note 7)(Limit)Accuracy (Note 8)V DD =2.7V to V DD =4.5V T A =−10˚C to 80˚C ±1.0˚C (max)T A =−25˚C to 115˚C ±1.5˚C (max)T A =−40˚C to 150˚C ±2.0˚C (max)V DD >4.5V to V DD =5.5VT A =−10˚C to 80˚C ±1.5˚C (max)T A =−25˚C to 115˚C ±2.0˚C (max)T A =−40˚C to 150˚C±2.5˚C (max)ResolutionRES1Bit =0,RES0Bit =011Bits 0.25˚C/LSB RES1Bit =0,RES0Bit =112Bits 0.125˚C/LSB RES1Bit =1,RES0Bit =013Bits 0.0625˚C/LSB RES1Bit =1,RES0Bit =114Bits 0.03125˚C/LSB Temperature Conversion Time (Note 9)RES1Bit =0,RES0Bit =010.114ms (max)RES1Bit =0,RES0Bit =120.228ms (max)RES1Bit =1,RES0Bit =040.456ms (max)RES1Bit =1,RES0Bit =180.8112ms (max)Quiescent CurrentContinuous Conversion Mode,SMBus inactive 320495µA (max)Shutdown,bus-idle timers on 120175µA (max)Shutdown,bus-idle timers off1.98µA (max)Power-On Reset ThresholdMeasured on V DD input,falling edge0.9V (min)L M 73 4Logic Electrical CharacteristicsDIGITAL DC CHARACTERISTICSUnless otherwise noted,these specifications apply for V DD=2.7V to5.5V.Boldface limits apply for T A=T J=T MIN to T MAX; all other limits T A=T J=+25˚C,unless otherwise noted.T A is the ambient temperature.T J is the junction temperature.Symbol Parameter Conditions Typical Limits Units(Note6)(Note7)(Limit) SMBDAT,SMBCLK INPUTSV IH Logical“1”Input Voltage0.7*V DD V(min)V IL Logical“0”Input Voltage0.3*V DD V(max)V IN;HYST SMBDAT and SMBCLK Digital InputHysteresis0.07*V DD VI IH Logical“1”Input Current V IN=V DD0.012µA(max) I IL Logical“0”Input Current V IN=0V–0.01–2µA(max) C IN Input Capacitance5pF SMBDAT,ALERT OUTPUTSI OH High Level Output Current V OH=V DD0.012µA(max) V OL SMBus Low Level Output Voltage I OL=3mA0.4V(max) ADDRESS INPUTV IH;ADDRESS Address Pin High Input Voltage V DD minus0.100V(min)V IL;ADDRESS Address Pin Low Input Voltage0.100V(max)I IH;ADDRESS Address Pin High Input Current V IN=V DD0.012µA(max) I IL;ADDRESS Address Pin Low Input Current V IN=0V–0.01–2µA(max) SMBus DIGITAL SWITCHING CHARACTERISTICSUnless otherwise noted,these specifications apply for V DD=+2.7V to+5.5V,C L(load capacitance)on output lines=400pF. Boldface limits apply for T A=T J=T MIN to T MAX;all other limits T A=T J=+25˚C,unless otherwise noted.Symbol Parameter Conditions Typical Limits Units(Note6)(Note7)(Limit)f SMB SMBus Clock Frequency400100kHz(max) Hz(min)t LOW SMBus Clock Low Time300ns(min) t HIGH SMBus Clock High Time300ns(min) t F;SMBO Output Fall Time(Note10)C L=400pFI PULL-UP≤3mA250ns(max)t TIMEOUT SMBDAT and SMBCLK Time Low for Reset of Serial Interface(Note11)1545ms(min)ms(max)t SU;DAT Data In Setup Time to SMBCLK High100ns(min)t HD;DATI Data Hold Time:Data In Stable after SMBCLKLow0ns(min)t HD;DATO Data Hold Time:Data Out Stable afterSMBCLK Low30ns(min)t HD;STA Start Condition SMBDAT Low to SMBCLKLow(Start condition hold before the first clockfalling edge)60ns(min)t SU;STO Stop Condition SMBCLK High to SMBDATLow(Stop Condition Setup)50ns(min)t SU;STA SMBus Repeated Start-Condition Setup Time,SMBCLK High to SMBDAT Low50ns(min)t BUF SMBus Free Time Between Stop and StartConditions1.2µs(min)t POR Power-On Reset Time(Note12)1ms(max)LM735SMBus Communication20147809Note 2:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.DC and AC electrical specifications do not apply when operating the device beyond its rated operating conditions.Note 3:When the input voltage (V I )at any pin exceeds the power supplies (V I <GND or V I >V DD ),the current at that pin should be limited to 5mA.Note 4:Reflow temperature profiles are different for lead-free and non-lead-free packages.Note 5:Human body model,100pF discharged through a 1.5k Ωresistor.Machine model,200pF discharged directly into each pin.Note 6:Typicals are at T A =25˚C and represent most likely parametric norm.Note 7:Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).Note 8:Local temperature accuracy does not include the effects of self-heating.The rise in temperature due to self-heating is the product of the internal power dissipation of the LM73and the thermal resistance.Note 9:This specification is provided only to indicate how often temperature data is updated.The LM73can be read at any time without regard to conversion state (and will yield last conversion result).Note 10:The output fall time is measured from (V IL;MAX -0.15V)to (V IH;MIN +0.15V).Note 11:Holding the SMBDAT and/or SMBCLK lines Low for a time interval greater than t TIMEOUT will reset the LM73’s SMBus state machine,setting SMBDAT and SMBCLK pins to a high impedance state.Note 12:Represents the time from V DD reaching the power-on-reset level to the LM73communications being functional.After an additional time equal to one temperature conversion time,valid temperature will be available in the Temperature Register.Note 13:A write to an invalid pointer address is not allowed.If the master writes an invalid address to the Pointer Register,(1)the LM73will not acknowledge the address and (2)the Pointer Register will continue to contain the last value stored in it.L M 73 6Typical Performance CharacteristicsAccuracy vs.TemperatureOperating Current vs.Temperature2014782020147821Shutdown Current vs.Temperature Typical Output Noise2014782220147823LM7371.0Functional DescriptionThe LM73is a digital temperature sensor that senses the temperature of its die using a sigma-delta analog-to-digital converter and stores the temperature in the Temperature Register.The LM73’s 2-wire serial interface is compatible with SMBus 2.0and I 2C.Please see the SMBus 2.0speci-fication for a detailed description of the differences between the I 2C bus and SMBus.The temperature resolution is programmable,allowing the host system to select the optimal configuration between sensitivity and conversion time.The LM73can be placed in shutdown to minimize power consumption when tempera-ture data is not required.While in shutdown,a 1-shot con-version mode allows system control of the conversion rate for ultimate flexibility.The LM73features the following registers.See Section 2.0for a complete list of the pointer address,content,and reset state of each register.1.Pointer Register2.Temperature Register3.Configuration Register4.T HIGH Register5.T LOW Register6.Control/Status Register7.Identification Register1.1POWER-ON RESETThe power-on reset (POR)state is the point at which the supply voltage rises above the power-on reset threshold (specified in the electrical specifications table),generating an internal reset.Each of the registers contains a defined value upon POR and this data remains there until any of the following occurs:1.The first temperature conversion is completed,causing the Temperature Register and various status bits to be updated internally,depending on the value of the mea-sured temperature2.The master writes different data to any R/W bits3.The LM73is powered down1.2ONE-SHOT CONVERSIONThe LM73features a one-shot conversion bit,which is used to initiate a single conversion and comparison cycle when the LM73is in shutdown mode.While the LM73is in shut-down mode,writing a "1"to the One-Shot bit in the Configu-ration Register will cause the LM73to perform a single temperature conversion and update the Temperature Regis-ter and the affected status bits.Operating the LM73in this one-shot mode allows for extremely low average-power con-sumption,making it ideal for low-power applications.When the One-Shot bit is set,the LM73initiates a tempera-ture conversion.After this initiation,but before the comple-tion of the conversion and resultant register updates,the LM73is in a "one-shot"state.During this state,the Data Available (DAV)flag in the Control/Status register is "0"and the Temperature Register contains the value 8000h (-256˚C).All other registers contain the data that waspresent before initiating the one-shot conversion.After the temperature measurement is complete,the DAV flag will be set to "1"and the temperature register will contain the result-ant measured temperature.1.3TEMPERATURE DATA FORMATThe resolution of the temperature data and the size of the data word are user-selectable through bits RES1and RES0in the Control/Status Register.By default,the LM73tem-perature stores the measured temperature in an 11-bit (10bits plus sign)word with one least significant bit (LSB)equal to 0.25˚C.The maximum word size is 14bits (13-bits plus sign)with a resolution of 0.03125˚C/LSB.CONTROL BIT DATA FORMATRES1RES0WORD SIZE RESOLUTION 0011bits 0.25˚C/LSB 0112bits 0.125˚C/LSB 1013bits 0.0625˚C/LSB 1114bits0.03125˚C/LSBThe temperature data is reported in 2’s complement format.The word is stored in the 16-bit Temperature Register and is left justified in this register.Unused temperature-data bits are always reported as "0".11-bit (10-bit plus sign)Temperature Digital Output BinaryHex +150˚C 01001011000000004B00h +25˚C 00001100100000000C80h +1˚C 00000000100000000080h +0.25˚C 00000000001000000020h 0˚C 00000000000000000000h −0.25˚C 1111111111100000FFE0h −1˚C 1111111110000000FF80h −25˚C 1111001110000000F380h −40˚C1110110000000000EC00h12-bit (11-bit plus sign)Temperature Digital Output BinaryHex +150˚C 01001011000000004B00h +25˚C 00001100100000000C80h +1˚C 00000000100000000080h +0.125˚C 00000000000100000010h 0˚C 00000000000000000000h −0.125˚C 1111111111110000FFF0h −1˚C 1111111110000000FF80h −25˚C 1111001110000000F380h −40˚C1110110000000000EC00h L M 73 81.0Functional Description(Continued)13-bit(12-bit plus sign)Temperature Digital OutputBinary Hex +150˚C01001011000000004B00h+25˚C00001100100000000C80h+1˚C00000000100000000080h +0.0625˚C00000000000010000008h 0˚C00000000000000000000h −0.0625˚C1111111111111000FFF8h −1˚C1111111110000000FF80h−25˚C1111001110000000F380h−40˚C1110110000000000EC00h14-bit(13-bit plus sign)Temperature Digital OutputBinary Hex +150˚C01001011000000004B00h+25˚C00001100100000000C80h+1˚C00000000100000000080h +0.03125˚C00000000000001000004h 0˚C00000000000000000000h −0.03125˚C1111111111111100FFFCh −1˚C1111111110000000FF80h−25˚C1111001110000000F380h−40˚C1110110000000000EC00h1.4SMBus INTERFACEThe LM73operates as a slave on the SMBus.The SMBDAT line is bidirectional.The SMBCLK line is is an input only.The LM73never drives the SMBCLK line and it does not support clock stretching.The LM73uses a7-bit slave address.It is available in two versions.Each version can be configured for one of three unique slave addresses,for a total of six unique address.Part NumberAddress PinDevice AddressLM73-0FloatGroundV DD 1001000 1001001 1001010LM73-1FloatGroundV DD 100110010011011001110The SMBDAT output is an open-drain output and does nothave internal pull-ups.A“high”level will not be observed onthis pin until pull-up current is provided by some externalsource,typically a pull-up resistor.Choice of resistor valuedepends on many system factors but,in general,the pull-upresistor should be as large as possible without effecting theSMBus desired data rate.This will minimize any internaltemperature reading errors due to internal heating of theLM73.The LM73features an integrated low-pass filter on both theSMBCLK and the SMBDAT line.These filters increase com-munications reliability in noisy environments.If either the SMBCLK or SMBDAT line is held low for a timegreater than t TIMEOUT(see Logic Electrical Characteristicsfor the value of t TIMEOUT),the LM73state machine will resetto the SMBus idle state,releasing the data line.Once theSMBDAT is released high,the master may initiate an SMBusstart.1.5ALERT FUNCTIONThe ALERT output is an over-temperature indicator.At theend of every temperature conversion,the measured tem-perature is compared to the value in the T HIGH Register.Ifthe measured temperature exceeds the value stored inT HIGH,the ALERT output goes active(see Figure Figure1).This over-temperature condition will also cause the ALRT-_STAT bit in the Control/Status Register to change value(this bit mirrors the logic level of the ALERT pin).The ALERT pin and the ALRT_STAT bit are cleared whenany of the following occur:1.The measured temperature falls below the value storedin the T LOW Register2.A"1"is written to the ALERT Reset bit in the Configura-tion Register3.The master resets it through an SMBus Alert ResponseAddress(ARA)procedureIf ALERT has been cleared by the master writing a"1"to theALERT Reset bit,while the measured temperature still ex-ceeds the T HIGH setpoint,ALERT will go active again afterthe completion of the next temperature conversion.Each temperature reading is associated with a TemperatureHigh(THI)and a Temperature Low(TLOW)flag in theControl/Status Register.A digital comparison determineswhether that reading is above the T HIGH setpoint or belowthe T LOW setpoint.If so,the corresponding flag is set.Alldigital comparisons to the T HIGH,and T LOW values are basedon an11-bit temperature comparison.Regardless of theresolution setting of the LM73,the lower three temperatureLSBs will not affect the state of the ALERT output,THI flag,and TLOW flag.LM7391.0Functional Description(Continued)1.6COMMUNICATING with the LM73The data registers in the LM73are selected by the Pointer Register.At power-up the Pointer Register is set to “00h”,the location for the Temperature Register.The Pointer Register latches the last location it was set to.Note that all Pointer Register bits are decoded;any incorrect pointer values will not be acknowledged and will not be stored in the Pointer Register (Note 13).A Write to the LM73will always include the address byte and the pointer byte.A Read from the LM73can take place either of two ways:1.If the location latched in the Pointer Register is correct (that is,the Pointer Register is pre-set prior to the read),then the read can simply consist of an address byte,followed by retrieving the data byte.Most of the time it is expected that the Pointer Register will point to Tempera-ture Registers because that will be the data most fre-quently read from the LM73.2.If the Pointer Register needs to be set,then an address byte,pointer byte,repeat start,and another address byte will accomplish a read.The data byte is read out of the LM73by the most significant bit first.At the end of a read,the LM73can accept either an Acknowledge or No Acknowledge bit from the Master.No Acknowledge is typically used as a signal to the slave that the Master has read its last byte.20147816FIGURE 1.ALERT Temperature Response clearedwhen temperature crosses T LOW20147817FIGURE 2.ALERT Temperature Response cleared bywriting a "1"to the ALERT Reset Bit.L M 73 101.0Functional Description(Continued)20147810(a)Typical Read from a 2-Byte Register with Preset Pointer20147811(b)Typical Pointer Set Followed by Immediate Read of a 2-Byte Register20147812(c)Typical Read from a 1-Byte Register with Preset Pointer20147813(d)Typical Pointer Set Followed by Immediate Read of a 1-Byte Register.FIGURE 3.Reading from the LM73LM73111.0Functional Description(Continued)20147814(a)Typical 1-Byte Write20147815(b)Typical 2-Byte Write FIGURE 4.Writing to the LM73L M 73 12LM73 2.0LM73RegistersThe LM73’s internal registers are selected by the Pointer register.The Pointer register latches the last location that it was set to.The pointer register and all internal registers are described below.All registers reset at device power up.2.1POINTER REGISTERThe diagram below shows the Pointer Register,the six internal registers to which it points,and their associated pointer addresses.20147807P7P6P5P4P3P2P1P000000Register SelectBits Name Description7:3Not Used Must write zeros only.2:0Register Select Pointer address.Points todesired register.See tablebelow.P2P1P0REGISTER(Note13)000Temperature001Configuration010T HIGH011T LOW100Control/Status111Identification132.0LM73Registers(Continued)2.2TEMPERATURE DATA REGISTER Pointer Address 00h (Read Only)Reset State:7FFCh (+255.96875˚C)One-Shot State:8000h (-256˚C)D15D14D13D12D11D10D9D8SIGN 128˚C 64˚C 32˚C 16˚C 8˚C 4˚C 2˚C D7D6D5D4D3D2D1D01˚C 0.5˚C0.25˚C 0.125˚C0.0625˚C0.03125˚CreservedreservedBits NameDescription15:2Temperature DataRepresents the temperature that was measured by the most recent temperature conversion.On Power-up,this data is invalid until the Data Available (DAV)bit in the Control/Status register is high (after the completion of the first temperature conversion).The resolution is user-progammable from 11-bit resolution (0.25˚C/LSB)through 14-bit resolution (0.03125˚C/LSB).The desired resolution is programmed with bits 5and 6of the Control/Status register.1:0Not UsedReturn zeros upon read.2.3CONFIGURATION REGISTER Pointer Address 01h (R/W)Reset State:40hD7D6D5D4D3D2D1D0PD reservedALRT EN ALRT POLALRT RSTONE SHOTreservedBits NameDescription7Full Power Down Writing a 1to this bit puts the LM73in shutdown mode for power conservation.Writing a 0puts the LM73into normal mode.6reserved User must write only a 1to this bit5ALERT EnableA 0in this location enables the ALERT output.A 1disables it.This bit also controls the ALERT Status bit (the Control/Status Register,Bit 3)since that bit reflects the state of the Alert pin.4ALERT Polarity When set to 1,the ALERT pin and ALERT Status bit are active-high.When 0,it is active-low.3ALERT Reset Writing a 1to this bit resets the ALERT pin and the ALERT Status bit.It will always be 0when read.2One ShotWhen in shutdown mode (Bit 7is 1),initiates a single temperature conversion and update of the temperature register with new temperature data.Has no effect when in continuous conversion mode (i.e.,when Bit 7is 0).Always returns a 0when read.1:0ReservedUser must write only a 0to these bits.2.4T HIGH UPPER-LIMIT REGISTER Pointer Address 02h (R/W)Reset State:7FE0h (+255.75˚C)D15D14D13D12D11D10D9D8SIGN 128˚C 64˚C 32˚C 16˚C 8˚C 4˚C 2˚C D7D6D5D4D3D2D1D01˚C 0.5˚C0.25˚C reservedBits Name Description15:5Upper-Limit Temperature If the measured temperature that is stored in this register exceeds this user-programmable upper temperature limit,the ALERT pin will go active and the THIGH flag in the Control/Status register will be set to 1.Two’s complement format.4:0ReservedReturns zeros upon read.Recommend writing zeros only in these bits.L M 73142.0LM73Registers(Continued)2.5T LOW LOWER-LIMIT REGISTERPointer Address03h(R/W)Reset State:8000h(–256˚C)D15D14D13D12D11D10D9D8 SIGN128˚C64˚C32˚C16˚C8˚C4˚C2˚C D7D6D5D4D3D2D1D0 1˚C0.5˚C0.25˚C reservedBits Name Description15:5Lower-LimitTemperature If the measured temperature that is stored in the temperature register falls below thisuser-programmable lower temperature limit,the ALERT pin will be deactivated and the T LOW flag in the Control/Status register will be set to1.Two’s complement format.4:0Reserved Returns zeros upon read.Recommend writing zeros only in these bits.2.6CONTROL/STATUS REGISTERPointer Address04h(R/W)Reset State:08hD7D6D5D4D3D2D1D0 TO_DIS RES1RES0reserved ALRT_STAT THI TLOW DAV Bits Name Description7Time-Out Disable Disable the time-out feature on the SMBDAT and SMBCLK lines if set to1.Setting this bitturns off the bus-idle timers,enabling the LM73to operate at lowest shutdown current.6:5TemperatureResolution Selects one of four user-programmable temperature data resolutions 00:0.25˚C/LSB,11-bit word(10bits plus sign)01:0.125˚C/LSB,12-bit word(11bits plus sign)10:0.0625˚C/LSB,13-bit word(12bits plus sign)11:0.03125˚C/LSB,14-bit word(13bits plus sign)4reserved Always returns zero when read.Recommend customer write zero only.3ALERT Pin Status Value is0when ALERT output is low.Value is1when ALERT output is high.The ALERToutput is reset under any of the following conditions:(1)Cleared by writing a1to the ALERTReset bit in the configuration register,(2)Measured temperature falls below the T LOW limit,or(3)cleared via the ARA sequence.Recommend customer write zero only.2Temperature HighFlag Bit is set to1when the measured temperature exceeds the T HIGH limit stored in the programmable T HIGH register.Flag is reset to0when both of the following conditions are met:(1)measured temperature no longer exceeds the programmed T HIGH limit and(2)upon reading the Control/Status register.If the temperature is not longer above the T HIGH limit,this status bit remains set until it is read by the master so that the system can check the history of what caused the ALERT output to go active.This bit is not cleared after every read if the measured temperature is still above the T HIGH limit.1Temperature LowFlag Bit is set to1when the measured temperature falls below the T LOW limit stored in the programmable T LOW register.Flag is reset to0when both of the following conditions are met:(1)measured temperature is no longer below the programmed T LOW limit and(2)upon reading the Control/Status register.If the temperature is no longer below the T LOW limit,the status bit remains set until it is read by the master so that the system can check the history of what cause the ALERT output to go active.This bit is not cleared after every read if temperature is still below T LOW limit.0Data Available Flag This bit is0when the LM73is in the process of converting a new temperature.It is1whenthe conversion is done.After initiating a temperature conversion while operating in theone-shot mode,this status bit can be monitored to indicate when the conversion is done.After triggering the one-shot conversion,the data in the temperature register is invalid untilthis bit is high(that is,after completion of the conversion).On power-up,the LM73is incontinuous conversion mode;while in continuous conversion mode(the default mode afterpower-on reset)this bit will always be high.Recommend customer write zero only.LM7315。
SP73贴片电感规格书
Reviesd: 07/14/2020
3/8
SMD Power Inductor
SP73 Series
SHENZHEN CODACA ELECTRONIC CO., LTD
This product is not authorized for use in any application related to safety. Specification subject to change without notice.Please check web site for latest information.
■ All data is tested based on 25℃ ambient temperature. 所有数据基于环境温度 25℃条件下测试。
※1 Inductance measure condition at 1kHz, 0.25V. 电感测试条件为 1kHz, 0.25V。
※2 Saturation current：the actual value of DC current when the inductance decrease 20% of its initial value. 饱和电流：电感值下降其初始值的 20%时所加载的实际直流电流值。
Inductance (μH) 电感值 ※1
1.00 ±20% 2.20 ±20% 3.30 ±20% 4.70 ±20% 6.80 ±20% 8.20 ±20% 10.0 ±10% 12.0 ±10% 15.0 ±10% 18.0 ±10% 22.0 ±10% 27.0 ±10% 33.0 ±10% 39.0 ±10% 47.0 ±10% 56.0 ±10% 68.0 ±10% 82.0 ±10% 100 ±10% 120 ±10% 150 ±10% 180 ±10% 220 ±10% 270 ±10% 330 ±10% 390 ±10% 470 ±10% 560 ±10% 680 ±10% 820 ±10% 1,000 ±10%
IRLML0100TRPBF;中文规格书,Datasheet资料
0.1
TJ = 25°C
VDS = 50V ≤60µs PULSE WIDTH
0.01
1.5
2.0
2.5
3.0
3.5
VGS, Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
RDS(on) , Drain-to-Source On Resistance (Normalized)
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ID , Drain Current (A)
IRLML0100TRPbF
2.0
RD
VDS
1.5
VGS RG
D.U.T.
+-VDD
1.0
VGS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
0.5
Fig 10a. Switching Time Test Circuit
Application(s) • Load/ System Switch Features and Benefits Features
Industry-standard pinout Compatible with existing Surface Mount Techniques RoHS compliant containing no lead, no bromide and no halogen MSL1
PD - 97157
IRLML0100TRPbF
HEXFET® Power MOSFET
VDS
100
V
VGS Max
± 16
V
G1
RDS(on) max
博布里克洗手间设备产品数据手册说明书
The manufacturer reserves the right to, and does from time to time, make changes and improvements in designs and dimensions. © 2008 by Bobrick Washroom Equipment, Inc.materialS:Stiles c—3/4'' (19mm) thick, Solid Color Reinforced Composite with GraffitiOff ™ surface thermoset and integrally fused into one homogenous piece. Surface, edge, core are to be the same color. Leveling device: 7 gauge, 3/16" (5mm) thick, corrosion-resistant, chromate-treated, double zinc-plated steel angle leveling bar bolted to stile; furnished with 3/8'' (10mm) stainless steel diameter threaded wedge anchor, hex nuts, lock washer, flat washers, and shoe retainers. Shoe: 18-8 S, type-304, 22-gauge (0.8mm) stainless steel with satin finish; 4'' (102mm) high.Panels —1/2'' (13mm) thick, Solid Color Reinforced Composite with GraffitiOff ® surface thermoset and integrally fused into one homogeneous piece. Surface, edge, core are to be the same color.doors —3/4'' (19mm) thick, Solid Color Reinforced Composite with GraffitiOff ® surface thermoset and integrally fused into one homogeneous piece. Surface, edge, core are to be the same color.Posts (for 1093 Series screens only) — 1-1/4'' (32mm) square tubing; 18-8 S, type-304, 18-gauge (1.2mm) stainless steel with satin finish. Floor and ceiling connections are constructed of 18-8 S, type-304, heavy-gauge stainless steel. Furnished in 10-ft (305-cm) lengths; to be cut in field to job specifications.Headrail (for 1092 Series compartments only) —Extruded anodized aluminum with satin finish. Enclosed construction with sloping top. Face has raised grip-resistant edge.Designer's Notes: Headrails with integral curtain tracks and hooks are available for compartments without doors. Optional vinyl curtains are available.Wall Posts —1" x 1-1/2" (25 x 38mm) tubing; 18-8 S, type-304, 16-gauge (1.6mm) stainless steel with satin-finish. 58" (147cm) high, pre-drilled for door hardware.Heavy-duty Hardware (standard) — Hinges, door latches, door keepers, clothes hooks, door stop plates, and mounting brackets are constructed of 18-8 S, type-304, heavy-gauge stainless steel with satin finish. Threaded inserts are factory installed for securing hinges, door stop plates, and door latches. Theft-resistant, stainless steel pin-in-head Torx screws are furnished for door hardware and all mounting brackets. Barrel hinge is adjustable to adjust door swing of unoccupied toilet compartment from partially open to fully closed. Toilet compartment door is locked from inside by sliding door latch into keeper. Threaded inserts are factory installed to secure door hinges, latch and door stops. Two door stops prevents door from being kicked in/out beyond stile by vandals. Mounting screws for stile to panel bracket, latch keeper, and coat hook connections are through-bolted.institutional Hardware (.67 option) —Hinges, door latches, door keepers, clothes hook, U-channels, door stop plates and angle brackets are constructed of 18-8 S, type-304, heavy-gauge stainless steel with satin finish: one-piece, full-height hinge is 16 gauge (1.6mm); one-piece door keeper is 11 gauge (3.2mm);one-piece, full-height U-channels and angle brackets are 18 gauge (1.2mm). U-channels secure panels to stiles, and angle brackets secure panels and stiles to walls. Door latch slides on a shock-resistant nylon track. Two door stops prevent door from being kicked in/out beyond stile by vandals. Theft-resistant, stainless steel pin-in-head Torx screws are furnished for door hardware, U-channels, and angle brackets. Doors are equipped with a self-closing hinge. Threaded inserts are factory installed to secure door hinge, latch, and doorstops. Mounting screws for stile-to-panel brackets and latch keeper connections are through-bolted. To specify institutional hardware, add suffix .67 to series number. Example: specify 1092.67 for overhead-braced partitions furnished with institutional hardware, including factory-installed threaded inserts for door hardware attachment.inStallation:Bobrick installation instructions are packed with each shipment and are available also in advance on request.notes:1. Ceiling-hung and floor-to-ceiling toilet compartments require structural members (not furnished by Bobrick) in ceiling. For suggested types of ceiling supportsystems, see Bobrick Advisory Bulletin TB-32.2. Wall backing is required to secure the mounting brackets of panels, stiles, and wall posts. For suggested wall backing, see Bobrick Advisory Bulletin TB-46.3. Floor-anchored stiles are furnished with expansion shields and threaded rods. The expansion shields require minimum 2'' (50mm) penetration into minimum3'' (75mm) thick structural concrete.4. Bobrick stainless steel partition-mounted washroom accessories are available for mounting in panels between two compartments. See current Bobrick Catalogfor description of accessories. Cutouts in panels can be pre-cut for Bobrick models at factory if location and size of all cutouts and Bobrick model numbers are furnished at time of order.GUarantee:Bobrick toilet partitions including all hardware and mounting brackets are guaranteed to be free from defects in material and workmanship for a period of one year from date of purchase. Any products returned to Bobrick under this guarantee will be repaired or replaced at no charge. 10-Year Warranty: Bobrick ex-tends a ten-year limited warranty from date of purchase for SierraSeries® Solid Color Reinforced Composite partition panels, doors, and stiles against breakage, warpage, delamination and corrosion when materials are properly installed, and normally used.SpeCiFiCation:Water-resistant, solid color reinforced composite ____________________ (insert one: toilet partitions, dressing compartments, shower dividers, urinal screens) shall be _______________ (insert one: overhead-braced toilet partition or floor anchored, wall-hung, post-to-ceiling urinal screens). Stiles, panels and doors shall be constructed of Solid Color Reinforced Composite with GraffitiOff ® surface thermoset and integrally fused into one homogeneous piece. Surface, edges and core are to be same color. Solid Color Reinforced Composite material shall be covered by a 10-year limited warranty against breakage, warpage, corrosion, and delamination. Stiles and doors shall be 3/4'' (19mm) thick; panels shall be 1/2'' (13mm) thick. All units shall meet ICC and NFPA Class B or UBC Class II, ASTME 84 Fire-Resistance Standards. Stiles shall have leveling device that is concealed by a one-piece, type-304, satin-finish stainless steel shoe that is 4'' (102mm) high.Stiles, panels and doors shall be __________ (insert color name and number from current Bobrick catalog). Headrails for overhead-braced compartments shall be anodized aluminum with satin finish. **All door hardware and mounting brackets shall be type-304 stainless steel with satin finish. All doors shall be supplied with three hinges. Threaded inserts shall be factory installed for securing door hinges, latches and door stops. Theft-resistant, stainless steel pin-in-head Torx screws shall be furnished for door hardware and all mounting brackets. Through bolts shall be used for securing latch keeper, clothes hook and panel-to-stile brackets. A clothes hook shall be furnished for each door with heavy duty hardware option. Hinges shall be adjustable to hold doors of unoccupied compartments partially open or fully closed. Two door stops shall be furnished for each door to prevent it from being kicked in/out beyond stile by vandals. Manufacturer's service and parts manual shall be provided to the building owner/manager upon completion of project.**To specify Institutional hardware, replace end of specification paragraph with: .67 option All door hardware, U-channels, and angle brackets shall be type-304 stainless steel with satin finish: one-piece, full-height hinges shall be 16 gauge (1.6mm); one-piece door keepers shall be 11 gauge (3.2mm); one-piece, full-height U-channels and angle brackets shall be 18 gauge (1.2mm). U-channels shall be furnished to secure panels to stiles, and angle brackets furnished to secure panels and stiles to walls. Doors shall be equipped with a self-closing hinge. Two door stops shall be furnished for each door to prevent it from being kicked in/out beyond stile by vandals. A clothes hook shall be furnished for each door. Theft-resistant, stainless steel pin-in-head, Torx screws shall be furnished for door hardware, U-channels, and angle brackets. Through bolts shall be used for securing latch keeper and panel- to-stiles brackets. Threaded inserts shall be factory installed to secure all door hinges, latches, and doorstops. Manufacturer's service and parts manual shall be provided to the building owner/manager upon request._________________ (insert one: toilet Partitions, dressing Compartments, Shower dividers, Urinal Screens) shall be ____________________ Series (insert series number) of Bobrick Washroom equipment, inc., Clifton Park, new York; Jackson, tennessee; Los Angeles, California; Bobrick Washroom equipment Company, Scarborough, ontario; Bobrick Washroom equipment Pty. Ltd., Australia; and Bobrick Washroom equipment Limited, United Kingdom.The illustrations and descriptions herein are applicable to production as of the date of this Technical Data Sheet. 1090 Revised 8/08 Printed in U.S.A. The manufacturer reserves the right to, and does from time to time, make changes and improvements in designs and dimensions. © 2008 by Bobrick Washroom Equipment, Inc.。
LG iGX样本(中文版)
-Solution Leader in Electrics& Automation
STARVERT G X
紧凑高性能变频器
0.4~22kW 3Phase 380~480Volts
Automatiom Equipment
New Name of
小心选择电流断路器. 当变频器上电的时候，可能有大 的浪涌电流涌入
为了使变频器长时间运行在高性能状态下,请把变频器安 装在正确的方向的适当的位置,留出适当的空间.不正确的 端子接线会导致设备的损坏.
有必要的情况下再安装。 如果安装了，不要用它来 启动和停止变频器。否则， 容易缩短产品的使用寿命。
控制连线
安全警告
为了您的安全，请在操作前先阅读说明书 请联系授权的服务人员进行检查、维修、调整 请由专业人员进行拆除维修
LS产电的30年
LS产电在不断地变革和成长中积累了丰富的经验。 同时具备了面临激烈竞争及挑战时也能生存并发展的强大组织力量。
取得飞跃和成长的企业 1974年 金星机电(株)创立 1987年 金星产电(株)设立 1994年 企业上市
电气及自动化领域的领先者 1995年 商号变更为LG产电(株) 1996年 取得了韩国最早变频器领域
的ISO9001认证 1998年 低压电器生产突破1亿台
第二次质的飞跃 1999年 合并LG金属(株) 1999年 转让铜管和自动销售机事业 2003年 内部调整，归属于LG电缆 2005年 更名为LS产电
动能缓冲
电源突降或瞬时掉电的情况下，变频器会出现欠压故障并保护停机。使 用此功能后，变频器在电源出现问题时会根据减速方式或直流电压参考方式 控制输出频率，利用电机产生的回馈能量维持直流侧电压以延长出现欠压保 护的时间，实现电源突降或瞬时掉电的情况下变频器能持续工作。
PMEG4020ER,115;中文规格书,Datasheet资料
PMEG4020ER_1
Product data sheet
/
Rev. 01 — 22 October 2009
© NXP B.V. 2009. All rights reserved.
4 of 13
NXP Semiconductors
PMEG4020ER
2 A low VF MEGA Schottky barrier rectifier
7. Characteristics
Table 7. Characteristics Tj = 25 °C unless otherwise specified.
Symbol Parameter
Conditions
VF
forward voltage
IF = 0.1 A
IF = 1 A
IF = 2 A
IR
Version SOD123W
4. Marking
Table 4. Marking codes Type number PMEG4020ER
Marking code BE
5. Limiting values
Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).
2 A low VF MEGA Schottky barrier rectifier
2. Pinning information
Table 2. Pin 1 2
Pinning Description cathode anode
[1] The marking bar indicates the cathode.
PMEG2005AEL,315;中文规格书,Datasheet资料
1.Product profile1.1General descriptionPlanar Maximum Efficiency General Application (MEGA) Schottky barrier diode with an integrated guard ring for stress protection encapsulated in a SOD882 leadless ultra small plastic package.1.2FeaturesForward current: 0.5AReverse voltage: 20V Ultra low forward voltageLeadless ultra small plastic packagePower dissipation comparable to SOT231.3ApplicationsUltra high-speed switching Voltage clamping Protection circuitsLow voltage rectificationHigh efficiency DC-to-DC conversionLow power consumption applications1.4Quick reference dataPMEG2005AEL0.5A ultra low V F MEGA Schottky barrier rectifier in leadless ultra small SOD882 packageRev. 03 — 15 January 2010Product data sheetTable 1.Quick reference dataSymbol Parameter Value Unit I F forward current 0.5A V Rreverse voltage20V2.Pinning information[1]The marking bar indicates the cathode.3.Ordering information4.Marking5.Limiting valuesTable 2.Discrete pinningPin Description Simplified outline Symbol1cathode [1]2anode001aaa332Bottom viewTop view21sym00112Table 3.Ordering informationType number Package NameDescriptionVersion PMEG2005AEL-leadless ultra small plastic package; 2 terminals; body 1.0×0.6×0.5mmSOD882Table 4.MarkingType number Marking code PMEG2005AELF2Table 5.Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).Symbol Parameter Conditions Min Max Unit V R continuous reverse voltage -20V I F continuous forward current-0.5A I FRM repetitive peak forward current t p ≤1ms; δ≤0.25- 2.5A I FSM non-repetitive peak forward currentt =8ms square wave-3A T j junction temperature[1]-150°C T amb operating ambient temperature [1]−65+150°C T stgstorage temperature−65+150°C[1]For Schottky barrier diodes thermal run-away has to be considered, as in some applications the reverse power losses P R are a significant part of the total power losses. Nomograms for determining the reverse power losses P R and I F(AV) rating will be available on request.6.Thermal characteristics[1]Refer to SOD882 standard mounting conditions (footprint), FR4 with 60μm copper strip line.[2]For Schottky barrier diodes thermal run-away has to be considered, as in some applications the reverse power losses P R are a significant part of the total power losses. Nomograms for determining the reverse power losses P R and I F(AV) rating will be available on request.7.Characteristics[1]Pulse test: t p ≤300μs; δ≤0.02.Table 6.Thermal characteristics Symbol ParameterConditions Value Unit R th(j-a)thermal resistance from junction to ambientin free air[1][2]500K/WTable 7.CharacteristicsT amb =25°C unless otherwise specified.Symbol Parameter Conditions Typ Max Unit V Fcontinuous forward voltagesee Figure 1;I F =0.1mA 2560mV I F =1mA 75110mV I F =10mA 135190mV I F =100mA 220290mV I F =500mA375440mV I Rcontinuous reverse currentsee Figure 2;[1]V R =10V 210600μA V R =20V3701500μA C ddiode capacitanceV R =1V; f =1MHz; see Figure 31925pF8.Package outlineLeadless ultra small plastic package; 2 terminals; body 1.0 x 0.6 x 0.5 mm SOD882Fig 4.Package outline9.Revision historyTable 8.Revision historyDocument ID Release date Data sheet status Change notice SupersedesPMEG2005AEL_320100115Product data-PMEG2005AEL_2 Modifications:•This data sheet was changed to reflect the new company name NXP Semiconductors,including new legal definitions and disclaimers. No changes were made to the technicalcontent.PMEG2005AEL_220040427Product data-PMEG2005AEL_1 PMEG2005AEL_120040419Product data--10.Legal information10.1Data sheet status[1]Please consult the most recently issued document before initiating or completing a design. [2]The term ‘short data sheet’ is explained in section “Definitions”.[3]The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL .10.2DefinitionsDraft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness ofinformation included herein and shall have no liability for the consequences of use of such information.Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.10.3DisclaimersGeneral — Information in this document is believed to be accurate andreliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information.Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including withoutlimitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof.Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure ormalfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmentaldamage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in theCharacteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability.Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at /profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unlessexplicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.Quick reference data — The Quick reference data is an extract of theproduct data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.10.4TrademarksNotice: All referenced brands, product names, service names and trademarks are the property of their respective owners.11.Contact informationFor more information, please visit: For sales office addresses, please send an email to: salesaddresses@Document status [1][2]Product status [3]DefinitionObjective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheetProductionThis document contains the product specification.12.Contents1Product profile. . . . . . . . . . . . . . . . . . . . . . . . . . 11.1General description . . . . . . . . . . . . . . . . . . . . . 11.2Features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.4Quick reference data . . . . . . . . . . . . . . . . . . . . 12Pinning information. . . . . . . . . . . . . . . . . . . . . . 23Ordering information. . . . . . . . . . . . . . . . . . . . . 24Marking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 26Thermal characteristics . . . . . . . . . . . . . . . . . . 37Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 38Package outline. . . . . . . . . . . . . . . . . . . . . . . . . 59Revision history. . . . . . . . . . . . . . . . . . . . . . . . . 610Legal information. . . . . . . . . . . . . . . . . . . . . . . . 710.1Data sheet status . . . . . . . . . . . . . . . . . . . . . . . 710.2Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710.3Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . . 710.4Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 711Contact information. . . . . . . . . . . . . . . . . . . . . . 712Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Please be aware that important notices concerning this document and the product(s)described herein, have been included in section ‘Legal information’.© NXP B.V.2010.All rights reserved.For more information, please visit: For sales office addresses, please send an email to: salesaddresses@分销商库存信息: NXPPMEG2005AEL,315。
LG变频器iGA说明书
海拔, 振动 大气压力
最大海拔高度 1,000m 以下,最大 5.9m/sec2 (0.6G) 或更低 70 ~ 106 kPa
(2) 接线
不要安装电力电容器，浪涌抑制器，或 RFI 滤波器在变频器的输出侧。 连接到电机的输出电缆（U， V， W） 的连接方式将会影响到电机的旋转方向。 不正确的端子接线可能引起设备的损坏。 端子的正负极接反可能会损坏变频器。 只有熟悉 LG 变频器的人员才可以对变频器进行接线和检查。 先安装变频器再进行接线，否则，你可能受到电击或人身伤害。
CHAPTER 3 - 配线 ............................................................................................. 错误!未定义书签。 3.1 端子配线 .................................................................................................... 错误!未定义书签。 3.2 电源端子块连线说明................................................................................... 错误!未定义书签。 3.3 控制端子说明 ............................................................................................. 错误!未定义书签。 3.4 PNP/NPN 选择和通讯项的连接 ...........................................................................................3-6
MUR2100EG;MUR2100ERLG;中文规格书,Datasheet资料
1.0E−07
25°C 1.0E−08
1000
0
200
400
600
800
VR, REVERSE VOLTAGE (V) Figure 4. Typical Reverse Current
1000
PF(AV), AVERAGE POWER DISSIPATION (A)
4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5
MUR2100E
NOTE 3. − AMBIENT MOUNTING DATA
Data shown for thermal resistance, junction−to−ambient
(RqJA) for the mountings shown is to be used as typical guideline values for preliminary engineering or in case the tie point temperature cannot be measured.
Unit
Maximum Thermal Resistance, Junction−to−Ambient
RqJA (Note 3) °C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Pulse Test: Pulse Width = 300 ms, Duty Cycle ≤ 2.0%.
NYC0102BLT1G;中文规格书,Datasheet资料
IGT
−
−
200
mA
Gate Trigger Voltage (VD = 12 V, RL = 100 W, TC = 25°C)
VGT
−
−
0.8
V
Holding Current (IT = 50 mA, RGK = 1 kW, TC = 25°C)
IH
−
−
6.0
mA
Gate Non−Trigger Voltage (VD = VDRM, RL = 3.3 kW, TC = 125°C)
TJ
−40 to
°C
+125
Storage Temperature Range
Tstg
−40 to
°C
+150
THERMAL CHARACTERISTICS
Characteristic
Symbol Max
Unit
Total Device Dissipation FR− 5 Board TA = 25°C
PD
225
mW
Thermal Resistance, Junction−to−Ambient RqJA
380
°C/W
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
TPS65910AA1RSLR;中文规格书,Datasheet资料
TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109 SWCS046O–MARCH2010–REVISED JULY2012 Integrated Power Management Unit Top SpecificationCheck forSamples:TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103,TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109FEATURES APPLICATIONSThe purpose of the TPS65910device is to•Portable and handheld systemsprovide the following resources:•OMAP3power management•Embedded power controllerDESCRIPTION•Two efficient step-down dc-dc converters forThe TPS65910is an integrated power-management processor coresIC available in48-QFN package and dedicated to •One efficient step-down dc-dc converter for I/Oapplications powered by one Li-Ion or Li-Ion polymer powerbattery cell or3-series Ni-MH cells,or by a5-V input;•One efficient step-up5-V dc-dc converter it requires multiple power rails.The device providesthree step-down converters,one step-up converter,•SmartReflex™compliant dynamic voltageand eight LDOs and is designed to support the management for processor coresspecific power requirements of OMAP-based •8LDO voltage regulators and one RTC LDOapplications.(internal purpose)Two of the step-down converters provide power for •One high-speed I2C interface for general-dual processor cores and are controllable by a purpose control commands(CTL-I2C)dedicated class-3SmartReflex interface for optimum •One high-speed I2C interface for SmartReflex power savings.The third converter provides power for Class3control and command(SR-I2C)the I/Os and memory in the system.•Two enable signals multiplexed with SR-I2C,The device includes eight general-purpose LDOs configurable to control any supply state and providing a wide range of voltage and current processor cores supply voltage capabilities;they are fully controllable by the I2Cinterface.The use of the LDOs is flexible;they are •Thermal shutdown protection and hot-dieintended to be used as follows:Two LDOs are detectiondesignated to power the PLL and video DAC supply •A real-time clock(RTC)resource with:rails on the OMAP based processors,four general-–Oscillator for32.768-kHz crystal or32-kHz purpose auxiliary LDOs are available to provide built-in RC oscillator power to other devices in the system,and two LDOsare provided to power DDR memory supplies in –Date,time and calendarapplications requiring these memories.–Alarm capabilityIn addition to the power resources,the device •One configurable GPIOcontains an embedded power controller(EPC)to •DC-DC switching synchronization through manage the power sequencing requirements of the internal or external3-MHz clock OMAP systems and an(RTC).Figure1shows the top-level diagram of the device.Please be aware that an important notice concerning availability,standard warranty,and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PRODUCTION DATA information is current as of publication date.Copyright©2010–2012,Texas Instruments Incorporated Products conform to specifications per the terms of the TexasPSWCS046-001Ci Co Ci Ci Ci (VCCIO)Ci (VCC2)Ci (VCC1)TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109SWCS046O –MARCH 2010–REVISED JULY 2012Figure 1.48-QFN Top-Level Diagram2Submit Documentation Feedback Copyright ©2010–2012,Texas Instruments IncorporatedTPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109 SWCS046O–MARCH2010–REVISED JULY2012 Table1.SUPPORTED PROCESSORS AND CORRESPONDING PART NUMBERSCompatible Processor(1)Part Number(1)TI processor-AM335x with DDR2TPS65910AA1RSLTI processor-AM335x with DDR3TPS65910A3A1RSL TI processors-AM1705/07,AM1806/08,AM3505/17,AM3703/15,DM3730/25,TPS65910A1RSL OMAP-L137/38,OMAP3503/15/25/30,TMS320C6742/6/8Samsung-S5PV210,S5PC110TPS659101A1RSLRockchip-RK29xx TPS659102A1RSLSamsung-S5PC100TPS659103A1RSLSamsung-S5P6440TPS659104A1RSLTI processors-DM643x,DM644x TPS659105A1RSLReserved TPS659106A1RSLFreescale-i.MX27,Freescale-i.MX35TPS659107A1RSLFreescale-i.MX508TPS659108A1RSLFreescale-i.MX51TPS659109A1RSL(1)The RSL package is available in tape and reel.See for details for corresponding part numbers,quantities and ordering information. ABSOLUTE MAXIMUM RATINGSover operating free-air temperature range(unless otherwise noted)Stresses beyond those listed under below may cause permanent damage to the device.These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated below are not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.The absolute maximum ratings for the TPS65910device are listed below:PARAMETER MIN MAX UNITVoltage range on pins/balls VCC1,VCC2,VCCIO,VCC3,VCC4,–0.37VVCC5,VCC6,VCC7Voltage range on pins/balls VDDIO–0.3 3.6VVoltage range on pins/balls OSC32KIN,OSC32KOUT,BOOT1,–0.3VRTC MAX+0.3VBOOT0Voltage range on pins/balls SDA_SDI,SCL_SCK,SDASR_EN2,–0.3VDDIO MAX+0.3VSCLSR_EN1,SLEEP,INT1,CLK32KOUT,NRESPWRONVoltage range on pins/balls PWRON–0.37VVoltage range on pins/balls PWRHOLD(1)GPIO_CKSYNC(2)–0.37V Functional junction temperature range–45150°CPeak output current on all other terminals than power resources–55mA(1)I/O supplied from VDDIO but which can be driven from to a VBAT voltage level(2)I/O supplied from VRTC but can be driven to a VBAT voltage levelTHERMAL CHARACTERISTICSover operating free-air temperature range(unless otherwise noted)DERATINGTA<25°C Power FACTOR ABOVE TA=70°C Power TA=85°C Power Package Rθja(°C/W)Rating(W)25°C(W)Rating(W)(mW/°C)RSL48-QFN37 2.637 1.481The thermal resistance RθJP junction-to-power PAD of the RSL package is1.1°C/WThe value of thermal resistance RθJA junction-to-ambient was measured on a high K.Copyright©2010–2012,Texas Instruments Incorporated Submit Documentation Feedback3TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109SWCS046O–MARCH2010–REVISED RECOMMENDED OPERATING CONDITIONSover operating free-air temperature range(unless otherwise noted)Lists of the recommended operating maximum ratings for the TPS65910device are given below.Note1:VCC7should be connected to the highest supply that is connected to the device VCCx pin.The exception is thatVCC2and VCC4can be higher than VCC7.Note2:VCC2and VCC4must be connected together(to the same voltage).Note3:If VDD3boost is used,VAUX33must be set to2.8V or higher and enabled before VDD3.PARAMETER TEST CONDITIONS MIN NOM MAX UNITV CC:Input voltage range on pins/balls VCC1,VCC2,VCCIO,VCC3,VCC4,VCC5,2.73.6 5.5VVCC7V CCP:Input voltage range on pins/balls VCC6 1.7 3.6 5.5VInput voltage range on pins/balls VDDIO 1.65 1.8/3.3 3.45VInput voltage range on pins/balls PWRON0 3.6 5.5VInput voltage range on pins/balls SDA_SDI,SCL_SCK,SDASR_EN2,SCLSR_EN1,1.65VDDIO 3.45V SLEEPInput voltage range on pins/balls PWRHOLD,GPIO_CKSYNC 1.65VDDIO 5.5VInput voltage range on balls BOOT1,BOOT0,OSC32KIN 1.65VRTC 1.95VOperating free-air temperature,T A–402785°CJunction temperature T J–4027125°CStorage temperature range–6527150°CLead temperature(soldering,10s)260°CPower ReferencesVREF filtering capacitor C O(VREF)Connected from VREF to REFGND100nFVDD1SMPSInput capacitor C I(VCC1)X5R or X7R dielectric10µFFilter capacitor C O(VDD1)X5R or X7R dielectric41012µFC O filter capacitor ESR f=3MHz10300mΩInductor L O(VDD1) 2.2µHL O inductor dc resistor DCR L125mΩVDD2SMPSInput capacitor C I(VCC2)X5R or X7R dielectric10µFFilter capacitor C O(VDD2)X5R or X7R dielectric41012µFC O filter capacitor ESR f=3MHz10300mΩInductor L O(VDD2) 2.2µHL O inductor dc resistor DCR L125mΩVIO SMPSInput capacitor C I(VIO)X5R or X7R dielectric10µFFilter capacitor C O(VIO)X5R or X7R dielectric41012µFC O filter capacitor ESR f=3MHz10300mΩInductor L O(VIO) 2.2µHL O inductor dc resistor DCR L125mΩVDIG1LDOInput capacitor C I(VCC6)X5R or X7R dielectric 4.7µFFiltering capacitor C O(VDIG1)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVDIG2LDOFiltering capacitor C O(VDIG2)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVPLL LDOInput capacitor C I(VCC5)X5R or X7R dielectric 4.7µFFiltering capacitor C O(VPLL)0.8 2.2 2.64µF4Submit Documentation Feedback Copyright©2010–2012,Texas Instruments IncorporatedTPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109 SWCS046O–MARCH2010–REVISED JULY2012 RECOMMENDED OPERATING CONDITIONS(continued)over operating free-air temperature range(unless otherwise noted)Lists of the recommended operating maximum ratings for the TPS65910device are given below.Note1:VCC7should be connected to the highest supply that is connected to the device VCCx pin.The exception is thatVCC2and VCC4can be higher than VCC7.Note2:VCC2and VCC4must be connected together(to the same voltage).Note3:If VDD3boost is used,VAUX33must be set to2.8V or higher and enabled before VDD3.PARAMETER TEST CONDITIONS MIN NOM MAX UNITC O filtering capacitor ESR0500mΩVDAC LDOFiltering capacitor C O(VDAC)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVMMC LDOInput capacitor C I(VCC4)X5R or X7R dielectric 4.7µFFiltering capacitor C O(VMMC)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVAUX33LDOFiltering capacitor C O(VAUX33)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVAUX1LDOInput capacitor C I(VCC3)X5R or X7R dielectric 4.7µFFiltering capacitor C O(VAUX1)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVAUX2LDOFiltering capacitor C O(VAUX2)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVRTC LDOInput capacitor C I(VCC7)X5R or X7R dielectric 4.7µFFiltering capacitor C O(VRTC)0.8 2.2 2.64µFC O filtering capacitor ESR0500mΩVDD3SMPSInput capacitor C I(VDD3)X5R or X7R dielectric 4.7µFFilter capacitor C O(VDD3)X5R or X7R dielectric41012µFC O filter capacitor ESR f=1MHz10300mΩInductor L O(VDD3) 2.8 4.7 6.6µHL O inductor DC resistor DCR L50500mΩBackup BatteryBattery or superCap supplying VBACKUP5102000mF Backup battery capacitor C BBCapacitor supplying VBACKUP140µF5to15mF101500Series resistorsΩ100to2000mF515I2C InterfacesSDA_SDI,SCL_SCK,SDASR_EN2,Connected to VDDIO 1.2kΩSCLSR_EN1external pull-up resistorCrystal Oscillator(connected from OSC32KIN to OSC32KOUT)Crystal frequency@specified load cap value32.768kHzCrystal tolerance@27°C–20020ppmOscillator contribution(not including crystalFrequency Temperature coefficient.–0.50.5ppm/°Cvariation)Secondary temperature coefficient–0.04–0.035–0.03ppm/°C2Voltage coefficient–22ppm/V Copyright©2010–2012,Texas Instruments Incorporated Submit Documentation Feedback5TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109SWCS046O–MARCH2010–REVISED RECOMMENDED OPERATING CONDITIONS(continued)over operating free-air temperature range(unless otherwise noted)Lists of the recommended operating maximum ratings for the TPS65910device are given below.Note1:VCC7should be connected to the highest supply that is connected to the device VCCx pin.The exception is thatVCC2and VCC4can be higher than VCC7.Note2:VCC2and VCC4must be connected together(to the same voltage).Note3:If VDD3boost is used,VAUX33must be set to2.8V or higher and enabled before VDD3.PARAMETER TEST CONDITIONS MIN NOM MAX UNIT Max crystal series resistor@Fundamental frequency90kΩCrystal load capacitor According to crystal data sheet612.5pFLoad crystal oscillator Coscinparallel mode Including parasitic PCB capacitor1225pF,CoscoutQuality factor800080000ESD SPECIFICATIONSover operating free-air temperature range(unless otherwise noted)TI STANDARD ESD METHOD STANDARD REFERENCE PERFORMANCEREQUIREMENTS Human body model(HBM)EIA/JESD22-A114D2000V2000VCharge device model(CDM)EIA/JESD22-C101C500V500V6Submit Documentation Feedback Copyright©2010–2012,Texas Instruments IncorporatedTPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109 SWCS046O–MARCH2010–REVISED JULY2012 I/O PULLUP AND PULLDOWN CHARACTERISTICSover operating free-air temperature range(unless otherwise noted)(1)PARAMETER TEST CONDITIONS MIN TYP MAX UNITSDA_SDI,SCL_SCK,SDASR_EN2,SCLSR_EN1Programmable pullup(DFT,default Grounded,VDDIO=1.8V–45%8+45%kΩinactive)SLEEP programmable pulldown(default active)@1.8V,VRTC=1.8V2 4.510µA@1.8V,VRTC=1.8V,VCC7=2.72 4.510VPWRHOLD programmable pulldown(defaultµA active)@5.5V,VRTC=1.8V,VCC7=5.571430VBOOT0,BOOT1programmable pulldown(default@1.8V,VRTC=1.8V2 4.510µA active)NRESPWRON pulldown@1.8V,VCC7=5.5V,OFF state2 4.510µA32KCLKOUT pulldown(disabled in Active-sleep@1.8V,VRTC=1.8V,OFF state2 4.510µA state)PWRON programmable pullup(default active)Grounded,VCC7=5.5V–40–31–15µAGPIO_CKSYNC programmable pullup(defaultGrounded,VRTC=1.8V–27–18–9µA active)(1)The internal pullups on the CTL-I2C and SR-I2C balls are used for test purposes or when the SR-I2C interface is not used.Discretepullups to the VIO supply must be mounted on the board in order to use the I2C interfaces.The internal I2C pullups must not be used for functional applicationsCopyright©2010–2012,Texas Instruments Incorporated Submit Documentation Feedback7TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109SWCS046O–MARCH2010–REVISED DIGITAL I/O VOLTAGE ELECTRICAL CHARACTERISTICSover operating free-air temperature range(unless otherwise noted)PARAMETER MIN TYP MAX UNITRelated I/O:PWRONLow-level input voltage V IL0.3x VCC7V High-level input voltage V IH0.7x VCC7VRelated I/Os:PWRHOLD,GPIO_CKSYNCLow-level input voltage V IL0.45VVDDIO/VHigh-level input voltage V IH 1.3VCC7VCC7Related I/Os:BOOT0,BOOT1,OSC32KINLow-level input voltage V IL0.35x VRTC V High-level input voltage V IH0.65x VRTC VRelated I/Os:SLEEPLow-level input voltage V IL0.35x VDDIO V High-level input voltage V IH0.65x VDDIO VRelated I/Os:NRESPWRON,INT1,32KCLKOUTLow-level output voltage V OL I OL=100µA0.2VI OL=2mA0.45V High-level output voltage V OH I OH=100µA VDDIO–0.2VI OH=2mA VDDIO–0.45VRelated Open-Drain I/Os:GPIO0Low-level output voltage V OL I OL=100µA0.2VI OL=2mA0.45VI2C-Specific Related I/Os:SCL,SDA,SCLSR_EN1,SDASR_EN2Low-level input voltage V IL–0.50.3x VDDIO V High-level input voltage V IH0.7x VDDIO V Hysteresis0.1x VDDIO VLow-level output voltage V OL@3mA(sink current),VDDIO=1.8V0.2×VDDIO VLow-level output voltage V OL@3mA(sink current),VDDIO=3.3V0.4x VDDIO V8Submit Documentation Feedback Copyright©2010–2012,Texas Instruments IncorporatedTPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109 SWCS046O–MARCH2010–REVISED JULY2012 I2C INTERFACE AND CONTROL SIGNALSover operating free-air temperature range(unless otherwise noted)NO.PARAMETER TEST CONDITIONS MIN TYP MAXINT1rise and fall times,C L=5to35pF510nsNRESPWRON rise and fall times,C L=5to35pF510nsSLAVE HIGH–SPEED MODESCL/SCLSR_EN1and SDA/SDASR_EN2rise and fall1080nstime,C L=10to100pFData rate 3.4MbpsI3t su(SDA-SCLH)Setup time,SDA valid to SCL high10nsI4t h(SCLL-SDA)Hold time,SDA valid from SCL low070nsI7t su(SCLH-SDAL)Setup time,SCL high to SDA low160nsI8t h(SDAL-SCLL)Hold time,SCL low from SDA low160nsI9t su(SDAH-SCLH)Setup time,SDA high to SCL high160nsSLAVE FAST MODESCL/SCLSR_EN1and SDA/SDASR_EN2rise and fall20+250nstime,C L=10to400pF0.1×C LData rate400KbpsI3t su(SDA-SCLH)Setup time,SDA valid to SCL high100nsI4t h(SCLL-SDA)Hold time,SDA valid from SCL low00.9µsI7t su(SCLH-SDAL)Setup time,SCL high to SDA low0.6µsI8t h(SDAL-SCLL)Hold time,SCL low from SDA low0.6µsI9t su(SDAH-SCLH)Setup time,SDA high to SCL high0.6µsSLAVE STANDARD MODESCL/SCLSR_EN1and SDA/SDASR_EN2rise and fall250nstime,C L=10to400pFData rate100KbpsI3t su(SDA-SCLH)Setup time,SDA valid to SCL high250nsI4t h(SCLL-SDA)Hold time,SDA valid from SCL low0µsI7t su(SCLH-SDAL)Setup time,SCL high to SDA low 4.7µsI8t h(SDAL-SCLL)Hold time,SCL low from SDA low4µsI9t su(SDAH-SCLH)Setup time,SDA high to SCL high4µsSWITCHING CHARACTERISTICSSLAVE HIGH–SPEED MODEI1t w(SCLL)Pulse duration,SCL low160nsI2t w(SCLH)Pulse duration,SCL high60nsSLAVE FAST MODEI1t w(SCLL)Pulse duration,SCL low 1.3µsI2t w(SCLH)Pulse duration,SCL high0.6µsSLAVE STANDARD MODEI1t w(SCLL)Pulse duration,SCL low 4.7µsI2t w(SCLH)Pulse duration,SCL high4µs Copyright©2010–2012,Texas Instruments Incorporated Submit Documentation Feedback9TPS65910,TPS65910A,TPS65910A3,TPS659101,TPS659102,TPS659103TPS659104,TPS659105,TPS659106,TPS659107,TPS659108,TPS659109SWCS046O–MARCH2010–REVISED POWER CONSUMPTIONover operating free-air temperature range(unless otherwise noted)All current consumption measurements are relative to the FULL chip,all VCC inputs set to VBAT voltage.PARAMETER TEST CONDITIONS MIN TYP MAX UNITDevice BACKUP state VBAT=2.4V,VBACKUP=0V,1116µA VBAT=0V,VBACKUP=3.2V69Device OFF state VBAT=3.6V,CK32K clock runningBOOT[1:0]=00:32-kHz RC oscillator16.523BOOT[1:0]=01:32-kHz quartz or bypass oscillator,BOOT0P1520=0µA BOOT[1:0]=01,Backup Battery Charger on,VBACKUP=3.23242VVBAT=5V,CK32K clock running:2028BOOT[1:0]=00:RC oscillatorDevice SLEEP state VBAT=3.6V,CK32K clock running,PWRHOLDP=0BOOT[1:0]=00,3DC-DCs on,5LDOs and VRTC on,no load295µA BOOT[1:0]=01,3DC-DCs on,3LDOs and VRTC on,no load,279BOOT0P=0Device ACTIVE state VBAT=3.6V,CK32K clock running,PWRHOLDP=0BOOT[1:0]=00,3DC-DCs on,5LDOs and VRTC on,no load1BOOT[1:0]=01,3DC-DCs on,3LDOs and VRTC on,no load,0.9mABOOT0P=0BOOT[1:0]=00,3DC-DCs on PWM mode(VDD1_PSKIP=VDD2_PSKIP=VIO_PSKIP=0),5LDOs and VRTC on,no21loadPOWER REFERENCES AND THRESHOLDSover operating free-air temperature range(unless otherwise noted)PARAMETER TEST CONDITIONS MIN TYP MAX UNITOutput reference voltage(VREFDevice in active or low-power mode–1%0.85+1%V terminal)Main battery charged Measured on VCC7terminalthreshold VMBCH(programmable)Triggering monitored through NRESPRWONVMBCH_VSEL=11,BOOT[1:0]=11or003VMBCH_VSEL=10 2.9VVMBCH_VSEL=01 2.8VMBCH_VSEL=00bypassedMain battery discharged Measured on VCC7terminal(MTL prg)VMBCH–V threshold VMBDCH(programmable)Triggering monitored through INT1100mVMain battery low threshold VMBLO Measured on VCC7terminal(Triggering2.5 2.6 2.7V (MB comparator)monitored on terminal NRESPWRON)VBACKUP=0V,measured on terminal VCC7Main battery high threshold VMBHI 2.6 2.753(MB comparator)VVBACKUP=3.2V,measured on terminal VCC7 2.5 2.553Main battery not present threshold Measured on terminal VCC71.92.1 2.2V VBNPR(Triggering monitored on terminal VRTC)V CC=3.6VGround current(analog references+comparators+backup battery Device in OFF state8µA switch)Device in ACTIVE or SLEEP state2010Submit Documentation Feedback Copyright©2010–2012,Texas Instruments Incorporated分销商库存信息: TITPS65910AA1RSLR。
FSL106MR;中文规格书,Datasheet资料
Description
The FSL106MR integrated Pulse Width Modulator (PWM) and SenseFET is specifically designed for highperformance offline Switch-Mode Power Supplies (SMPS) with minimal external components. FSL106MR includes integrated high-voltage power switching regulators that combine an avalanche-rugged SenseFET with a current-mode PWM control block. The integrated PWM controller features include: UnderVoltage Lockout (UVLO) protection, Leading-Edge Blanking (LEB), a frequency generator for EMI attenuation, an optimized gate turn-on/turn-off driver, Thermal Shutdown (TSD) protection, and temperaturecompensated precision current sources for loop compensation and fault protection circuitry. The FSL106MR offers good soft-start performance. When compared to a discrete MOSFET and controller or RCC switching converter solution, the FSL106MR reduces total component count, design size, and weight; while increasing efficiency, productivity, and system reliability. This device provides a basic platform that is well suited for the design of cost-effective flyback converters. Maximum Output Power(1) 230VAC ± 15%(2) Adapter(3) 7W
IXGQ85N33PCD1;中文规格书,Datasheet资料
TJ - Degrees Centigrade
Fig. 6. Input Adm ittance
I C - Amperes
140 120 100 80 60 40 20 0 TJ = 125 ºC 25 ºC - 40 ºC 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5
V C E - Volts
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T J - Degrees Centigrade
IXYS reserves the right to change limits, test conditions and dimensions.
4.0 3.5 3.0 2.5 2.0 1.5 1.0 5 6 7 8 9
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© 2006 IXYS CORPORATION, All rights reserved /
IXGQ85N33PCD1
TO-3P
TC = 25°C, IGBT chip capability TJ ≤ 150°C, tp ≤ 1 μs, D ≤ 1% TJ ≤ 150°C, tp < 10 μs Lead current limit VGE = 15 V, TVJ = 150°C, RG = 20 Ω Clamped inductive load, VCE < 300 V TC = 25°C
LM395T;中文规格书,Datasheet资料
LM195,LM395LM195/LM395 Ultra Reliable Power TransistorsLiterature Number: SNOSBO4BLM195/LM395Ultra Reliable Power TransistorsGeneral DescriptionThe LM195/LM395are fast,monolithic power integrated circuits with complete overload protection.These devices,which act as high gain power transistors,have included on the chip,current limiting,power limiting,and thermal over-load protection making them virtually impossible to destroy from any type of overload.In the standard TO-3transistor power package,the LM195will deliver load currents in ex-cess of 1.0A and can switch 40V in 500ns.The inclusion of thermal limiting,a feature not easily avail-able in discrete designs,provides virtually absolute protec-tion against overload.Excessive power dissipation or inad-equate heat sinking causes the thermal limiting circuitry to turn off the device preventing excessive heating.The LM195offers a significant increase in reliability as well as simplifying power circuitry.In some applications,where protection is unusually difficult,such as switching regulators,lamp or solenoid drivers where normal power dissipation is low,the LM195is especially advantageous.The LM195is easy to use and only a few precautions need be observed.Excessive collector to emitter voltage can de-stroy the LM195as with any power transistor.When the device is used as an emitter follower with low source imped-ance,it is necessary to insert a 5.0k resistor in series with the base lead to prevent possible emitter follower oscilla-tions.Although the device is usually stable as an emitter follower,the resistor eliminates the possibility of trouble with-out degrading performance.Finally,since it has good high frequency response,supply bypassing is recommended.For low-power applications (under 100mA),refer to the LP395Ultra Reliable Power Transistor.The LM195/LM395are available in the standard TO-3,Kovar TO-5,and TO-220packages.The LM195is rated for opera-tion from −55˚C to +150˚C and the LM395from 0˚C to +125˚C.Featuresn Internal thermal limitingn Greater than 1.0A output current n 3.0µA typical base current n 500ns switching time n 2.0V saturationn Base can be driven up to 40V without damage n Directly interfaces with CMOS or TTL n100%electrical burn-inSimplified Circuit006009011.0Amp Lamp Flasher00600916©2004National Semiconductor Corporation TO-3Metal Can Package 00600902Bottom ViewOrder Number LM195K/883See NS Package Number K02A(Note 5)TO-220Plastic Package00600903Case is EmitterTop ViewOrder Number LM395T See NS Package Number T03BTO-5Metal Can Package00600904Bottom ViewOrder Number LM195H/883See NS Package Number H03B(Note 5)L M 19 2please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Collector to Emitter VoltageLM19542V LM39536V Collector to Base VoltageLM19542V LM39536V Base to Emitter Voltage(Forward)LM195 LM39542V36VPower Dissipation Internally LimitedOperating Temperature RangeLM195−55˚C to+150˚CLM3950˚C to+125˚CStorage Temperature Range−65˚C to+150˚CLead Temperature(Soldering,10sec.)260˚CPreconditioning100%Burn-In In Thermal LimitElectrical Characteristics(Note2)Parameter Conditions LM195LM395UnitsMin Typ Max Min Typ MaxCollector-Emitter Operating Voltage I Q≤I C≤I MAX4236V (Note4)Base to Emitter Breakdown Voltage0≤V CE≤V CEMAX423660V Collector CurrentTO-3,TO-220V CE≤15V 1.2 2.2 1.0 2.2ATO-5V CE≤7.0V 1.2 1.8 1.0 1.8A Saturation Voltage I C≤1.0A,T A=25˚C 1.8 2.0 1.8 2.2V Base Current0≤I C≤I MAX3.0 5.0 3.010µA0≤V CE≤V CEMAXQuiescent Current(I Q)V be=02.0 5.0 2.010mA0≤V CE≤V CEMAXBase to Emitter Voltage I C=1.0A,T A=+25˚C0.90.9V Switching Time V CE=36V,R L=36Ω,500500nsT A=25˚CThermal Resistance Junction to TO-3Package(K) 2.3 3.0 2.3 3.0˚C/W Case(Note3)TO-5Package(H)12151215˚C/WTO-220Package(T)46˚C/WNote1:“Absolute Maximum Ratings”indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.Note2:Unless otherwise specified,these specifications apply for−55˚C≤T j≤+150˚C for the LM195and0˚C≤+125˚C for the LM395.Note3:Without a heat sink,the thermal resistance of the TO-5package is about+150˚C/W,while that of the TO-3package is+35˚C/W.Note4:Selected devices with higher breakdown available.Note5:Refer to RETS195H and RETS195K drawings of military LM195H and LM195K versions for specifications.3Collector Characteristics Short Circuit Current0060093300600934Bias Current Quiescent Current0060093500600936Base Emitter Voltage Base Current0060093700600938L M 19 4Saturation Voltage Response Time0060093900600940 Response Time10V Transfer Function006009410060090736V Transfer Function Transconductance00600908006009095Small Signal FrequencyResponse00600910Schematic Diagram0060091L M 19 61.0Amp Voltage Follower00600912*Solid TantalumPower PNP Time Delay00600913*Protects against excessive base drive**Needed for stability006009141.0MHz Oscillator0060091571.0Amp Negative Regulator00600917†Solid Tantalum1.0Amp Positive Voltage Regulator00600918†Solid TantalumL M 19 8Fast Optically Isolated Switch Optically Isolated Power Transistor0060091900600920CMOS or TTL Lamp Interface Two Terminal Current Limiter006009210060092240V Switch00600923*Drive Voltage 0V to ≥10V ≤42V6.0V Shunt Regulator with Crowbar Two Terminal 100mA Current Regulator00600924006009259分销商库存信息: NATIONAL-SEMICONDUCTOR LM395T。
ADA-4643 Datasheet说明书
ADA-4643Silicon Bipolar Darlington Amplifi erData SheetAttention: Observe precautions forhandling electrostatic sensitive devices.ESD Machine Model (Class A)ESD Human Body Mode (Class 1B)Refer to Avago Application Note A004R:Electrostatic Discharge, Damage and Control.RFinGNDRFout & VdGND DescriptionAvago Technologies’ ADA-4643 is an economical, easy-to-use, general purpose silicon bipolar RFIC gain block am-plifi ers housed in a 4-lead SC-70 (SOT-343) surface mount plastic package which requires only half the board space of a SOT-143 package.The Darlington feedback structure provides inherent broad bandwidth performance, resulting in useful ope-rating frequency up to 2.5 GHz. This is an ideal device forsmall-signal gain cascades or IF amplifi cation. ADA-4643 is fabricated using Avago’s HP25 silicon bipolarprocess, which employs a double-diff used single poly-silicon process with self-aligned submicron emitter geometry. The process is capable of simultaneous high f T and high NPN breakdown (25 GHz f T at 6 V BVCEO). The process utilizes industry standard device oxide isolation technologies and submicron aluminum multilayer inter-connect to achieve superior performance, high uniformity, and proven reliability.Surface Mount PackageSOT-343Pin Connections and Package MarkingNote:Top View. Package marking provides orientation and identifi cation.“2T” = Device Code“x” = Date code character identifi es month of manufacture.V CC = 5 VRF inputRF Features∙ Small Signal gain amplifi er∙ Operating frequency DC – 2.5 GHz ∙ Unconditionally stable ∙ 50 Ohms input & output∙ Flat, Broadband Frequency Response up to 1 GHz∙ Operating Current: 20 to 60 mA ∙ Industry standard SOT-343 package∙ Lead-free option available Specifi cations900 MHz, 3.5 V, 35 mA (typ.)∙ 17 dB associated gain ∙ 13.4 dBm P 1dB ∙ 28.3 dBm OIP 3∙ 4 dB noise fi gure∙ VSWR < 2.2 throughput operating frequency ∙ Single supply, typical I d = 35 mAApplications∙ Cellular/PCS/WLL base stations ∙ Wireless data/WLAN ∙ Fiber-optic systems ∙ ISMTypical Biasing Confi gurationADA-4643 Electrical Specifi cationsT A = 25° C, Zo = 50 Ω, Pin = -25 dBm, I d = 35 mA (unless specifi ed otherwise)SymbolParameter and Test Condition:I d = 35 mA, Zo = 50 ΩFrequencyUnitsMin.Typ.Max.Std. Dev.V d Device Voltage I d = 35 mA V 3.2 3.5 3.9Gp Power Gain (|S 21|)2100 MHz 900 MHz [1,2]dB15.517.517.018.5∆Gp Gain Flatness 100 to 900 MHz 0.1 to 2 GHz dB 0.51.8F 3dB 3 dB BandwidthGHz3.2VSWR in Input Voltage Standing Wave Ratio0.1 to 6 GHz2.0:1VSWR out Output Voltage Standing Wave Ratio 0.1 to 6 GHz 1.6:1NF 50 Ω Noise Figure100 MHz 900 MHz [1,2]dB 3.94.00.070.1P 1dB Output Power at 1dB Gain Compression 100 MHz 900 MHz [1,2]dBm 14.713.4OIP 3Output 3rd Order Intercept Point100 MHz [3]900 MHz [1,2]dBm 29.028.3DV/dTDevice Voltage Temperature Coeffi cientmV/°C-5.3Notes:1. Typical value determined from a sample size of 500 parts from 3 wafers.2. Measurement obtained using production test board described in the block diagram below.3. I) 900 MHz OIP 3 test condition: F1 = 900 MHz, F2 = 905 MHz and Pin = -25 dBm per tone. II) 100 MHz OIP 3 test condition: F1 = 100 MHz, F2 = 105 MHz and Pin = -25 dBm per tone.ADA-4643 Absolute Maximum Ratings [1]SymbolParameterUnitsAbsolute MaximumI d Device CurrentmA 70P diss Total Power Dissipation [2]mW 270P in max.RF Input Power dBm 18T j Channel Temperature ︒C 150T STG Storage Temperature ︒C -65 to 150θjcThermal Resistance [3]︒C/W152Notes:1. Operation of this device above any one of these parameters may cause permanent damage.2. Ground lead temperature is 25° C. Derate 6.6 mW/°C for TL >109° C.3. Junction-to-case thermal resistance measured using 150° C Liquid Crystal Measurement method.Block diagram of 900 MHz production test board used for V d , Gain, P 1dB , OIP 3, and NF measurements.Circuit losses have been de-embedded from actual measurements.Product Consistency Distribution Charts at 900 MHz, I d= 35 mAGAIN (dB)300250200150100500V d (V)300250200150100500*********************************=15.5,Nominal=17,USL=18.5Figure 2. V d *********************=3.2,Nominal=3.5,USL=3.9Notes:1. Statistics distribution determined from a sample size of 500 parts taken from 3 diff erent wafers.2. Future wafers allocated to this product may have typical values anywhere between the minimum and maximum specifi cation limits.ADA-4643 Typical Performance Curves (at 25° C, unless specifi ed otherwise)Figure 3. Gain vs. Frequency at I d = 35 mA.Figure 4. P 1dB vs. Frequency at I d = 35 mA.Figure 5. OIP 3 vs. Frequency at I d = 35 mA.Figure 6. NF vs. Frequency at I d = 35 mA.Figure 7. Id vs. V d and Temperature.Figure 8. Gain vs. I d and Temperature at 900 MHz.FREQUENCY (GHz)G A I N (d B )62135420151050FREQUENCY (GHz)P 1d B (d B m )06213542015105FREQUENCY (GHz)O I P 3 (d B m )062135430252015105FREQUENCY (GHz)0621354N F (d B )65432V d (V)I d (m A )706050403020100I d (mA)G A I N (d B )18171615141312Figure 9. P 1dB vs. I d and Temperature at 900 MHz.Figure 10. OIP 3 vs. I d and Temperature at 900 MHz.Figure 11. NF vs. I d and Temperature at 900 MHz.Figure 12. Gain vs. I d and Frequency (GHz).Figure 13. P 1dB vs. I d and Frequency (GHz).Figure 14. OIP 3 vs. I d and Frequency (GHz).I d (mA)O I P 3 (d B m )0.10.50.91.52.02.53456403530252015105I d (mA)P 1d B (d B m )20151050-5-10I d (mA)O I P 3 (d B m )I d (mA)N F (d B )16543210I d (mA)G A I N (d B )402010303030302018161412108I d (mA)P 1d B (d B m )2520151050-5-10Figure 15. NF vs. I d and Frequency (GHz).Figure 16. Input Return Loss vs. I d and Frequency (GHz).Figure 17. Output Return Loss vs. I d and Frequency (GHz).I d (mA)N F (d B )65.554.543.53FREQUENCY (GHz)I R L(d B )-5-10-15-20FREQUENCY (GHz)O R L (d B )0-5-10-15-20-25Freq. GHz11 211222K Mag. Ang. dB Mag. Ang. Mag. Ang. Mag. Ang.0.10.172 1.1 17.2 7.246 175.9 0.093 -0.8 0.245 -4.1 1.10.5 0.202 10 17.04 7.113 160.2 0.091 -4.5 0.245 -12.6 1.10.9 0.277 12.3 16.67 6.814 144.7 0.088 -7.4 0.269 -20.4 1.11.0 0.286 9.9 16.56 6.726 141.1 0.087 -7.9 0.274 -23.1 1.11.5 0.349 -2.8 15.98 6.292 124.2 0.083 -9.3 0.28 -37.6 1.11.9 0.375 -11.3 15.54 5.984 111.4 0.080 -9.5 0.273 -48.9 1.22.0 0.382 -13.8 15.44 5.918 108.3 0.080 -9.5 0.271 -51.7 1.22.5 0.397 -24.2 14.93 5.581 93.20.078-8.9 0.249 -65.8 1.23.0 0.402 -34.7 14.475.29 78.60.078 -7.8 0.22 -81.7 1.33.5 0.394 -46 14.025.021 64.2 0.079 -6.6 0.192 -100.9 1.34.0 0.378 -58.7 13.58 4.775 50 0.082 -5.4 0.176 -123.8 1.34.5 0.361 -73.1 13.16 4.55 35.9 0.087 -4.6 0.179 -148.6 1.35.0 0.340 -89.3 12.64 4.284 21.9 0.094 -4.9 0.191 -169.9 1.35.5 0.328 -107.1 12.15 4.05 8.3 0.102 -5.9 0.212 173.3 1.26.0 0.318 -124.8 11.6 3.803 -5.4 0.112 -8.3 0.233 158.2 1.26.5 0.299 -141.1 11.09 3.584 -18.6 0.124 -11.5 0.25 141.6 1.17.0 0.274 -159.7 10.56 3.371 -32 0.138 -16.5 0.27 123 1.17.5 0.243 177.3 9.96 3.149 -45.6 0.150 -22.8 0.3 103.6 1.18.0 0.222 148.7 9.29 2.914 -59.1 0.161 -30 0.337 84.8 1.18.5 0.226 119.9 8.41 2.632 -71.8 0.168 -36.7 0.381 70.1 1.19.0 0.26 95.4 7.62 2.406 -83.7 0.177 -43 0.429 58.4 1.19.5 0.305 75.2 6.67 2.155-96.1 0.187 -49.9 0.48148.4 1.110.0 0.356 60.1 5.82 1.954 -107.1 0.195-57.3 0.529 39.7 1Notes:1. S-parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the input lead.The output reference plane is at the end of the output lead.Freq. GHz11211222K Mag. Ang. dB Mag. Ang. Mag. Ang. Mag. Ang.0.1 0.151 1.6 17.51 7.504 175.9 0.091 -0.8 0.223 -4.1 1.10.5 0.185 13.1 17.35 7.367 160.1 0.09 -4.2 0.224 -11.7 1.10.9 0.265 14.9 16.98 7.06 144.6 0.087 -7 0.251 -19 1.11.0 0.272 12.4 16.86 6.97 140.9 0.086 -7.5 0.256 -21.7 1.11.50.340 -0.7 16.27 6.511 123.9 0.082 -8.8 0.264 -36.2 1.11.9 0.367 -9.5 15.82 6.178 111 0.080 -9.1 0.259 -47.6 1.22.0 0.373 -12.1 15.72 6.107 108 0.079 -9.1 0.256-50.3 1.22.5 0.39 -22.7 15.19 5.745 92.8 0.078 -8.5 0.236 -64.4 1.23.0 0.395 -33 14.715.436 78.3 0.077 -7.3 0.209 -80.4 1.33.5 0.387 -44.3 14.235.149 63.9 0.079 -6 0.181 -99.9 1.34.0 0.370 -57.4 13.79 4.89 49.9 0.082 -4.8 0.166 -123.4 1.34.5 0.353 -71.6 13.36 4.657 35.9 0.087-3.9 0.17 -148.9 1.35.0 0.332 -87.7 12.84 4.383 21.9 0.093 -4.2 0.185 -170.6 1.25.5 0.319 -106 12.34 4.141 8.3 0.102 -5.1 0.207 172.5 1.26.0 0.310 -123.6 11.8 3.889 -5.4 0.112 -7.5 0.23 157.5 1.26.5 0.293 -140.2 11.28 3.666 -18.6 0.124 -10.8 0.248 140.9 1.17.0 0.266 -158.8 10.75 3.449 -32 0.138 -15.8 0.27 122.3 1.17.5 0.238 177.8 10.15 3.219 -45.5 0.151 -22.2 0.301 103 1.18.0 0.217 148.5 9.48 2.979 -59 0.161 -29.3 0.34 84.3 1.18.5 0.222 119.5 8.62 2.697 -71.7 0.169 -36.1 0.385 69.6 1.19.0 0.256 95 7.81 2.458 -83.4 0.178 -42.5 0.434 57.9 1.19.5 0.300 74.9 6.88 2.208 -95.8 0.188 -49.5 0.486 47.9 110.0 0.357 59.1 6.01 1.996 -107.2 0.196 -56.9 0.53439.2 1Notes:1. S-parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the input lead.The output reference plane is at the end of the output lead.Freq. GHz11211222K Mag. Ang. dB Mag. Ang. Mag. Ang. Mag. Ang.0.1 0.137 2.417.72 7.691 175.9 0.09-0.70.207 -4 1.10.5 0.174 15.317.567.547 1600.089 -4 0.209-10.9 1.10.9 0.25717.417.19 7.234 144.5 0.086 -6.8 0.238-17.6 1.11.0 0.267 14.717.087.144140.80.085 -7.2 0.243 -20.3 1.11.50.334 0.716.47 6.664 123.70.081 -8.50.253-34.8 1.11.9 0.36 -8.416.01 6.317 110.70.079 -8.7 0.249 -46.1 1.12.0 0.367-10.915.91 6.241107.70.079 -8.7 0.247-48.9 1.22.5 0.386-21.615.36 5.86292.5 0.077 -8.1 0.227 -62.9 1.23.0 0.39 -32.114.865.534 78 0.077 -7 0.201 -78.9 1.23.5 0.382-43.414.385.237 63.6 0.078 -5.70.174 -98.4 1.34.0 0.365 -56.4 13.93 4.97149.7 0.081 -4.5 0.159-122.3 1.34.5 0.348 -70.813.5 4.732 35.7 0.086-3.6 0.164-148.3 1.35.0 0.327 -86.8 12.97 4.45 21.7 0.093 -3.9 0.179-170.4 1.25.5 0.314 -105.112.48 4.205 8.20.101-4.8 0.202172.6 1.26.0 0.304-122.811.93 3.947 -5.5 0.112 -7.1 0.226 157.6 1.26.5 0.287 -139.6 11.41 3.721 -18.70.124 -10.40.245 140.9 1.17.0 0.26-159.1 10.88 3.498 -32 0.138 -15.40.268122.3 1.17.5 0.232177.610.28 3.264 -45.6 0.151 -21.80.3 102.9 1.18.0 0.213147.8 9.6 3.02 -59.10.161 -28.90.339 84.2 1.18.5 0.218120.28.7 2.724 -71.7 0.169 -35.80.385 69.5 1.19.0 0.2694.27.95 2.498 -83.70.179-42.10.434 57.9 1.19.5 0.30374 6.98 2.233 -96.20.189-49.20.48747.9 110.0 0.35259.4 6.14 2.027-107.1 0.196 -56.60.53539.1 1Notes:1. S-parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the input lead.The output reference plane is at the end of the output lead.Freq. GHz11211222K Mag. Ang. dB Mag. Ang. Mag. Ang. Mag. Ang.0.1 0.126 2.4 17.88 7.834 175.9 0.089 -0.7 0.194 -3.8 1.10.5 0.165 18.1 17.73 7.696 159.9 0.088 -3.8 0.196 -9.9 1.10.9 0.252 19.6 17.36 7.377 144.3 0.085 -6.4 0.227 -16.1 1.11.0 0.261 16.4 17.24 7.28 140.6 0.085 -6.9 0.233 -18.8 1.11.5 0.33 2 16.63 6.787 123.3 0.081 -8.2 0.244 -33.2 1.11.9 0.359 -7.4 16.16 6.424 110.3 0.079 -8.4 0.241 -44.4 1.12.0 0.365 -9.8 16.05 6.343 107.2 0.078 -8.4 0.239 -47.2 1.12.5 0.386 -21 15.49 5.948 91.9 0.077 -7.8 0.221 -61 1.23.0 0.387 -31.5 14.985.61 77.4 0.077 -6.7 0.195 -76.8 1.23.5 0.381 -43 14.495.301 63.1 0.078 -5.5 0.168 -96.2 1.34.0 0.363 -56 14.025.025 49 0.081 -4.3 0.153 -120.3 1.34.5 0.344 -70.7 13.58 4.777 35 0.086 -3.5 0.157 -146.9 1.35.0 0.323 -87.3 13.04 4.488 21 0.093 -3.7 0.172 -169.4 1.25.5 0.31 -105.8 12.54 4.235 7.5 0.101 -4.6 0.195 173.4 1.26.0 0.301 -123.6 11.98 3.971 -6.2 0.111 -6.9 0.22 158.2 1.26.5 0.281 -140.6 11.44 3.735 -19.4 0.124 -10.2 0.239 141.4 1.17.0 0.257 -159.9 10.9 3.507 -32.7 0.138 -15.2 0.262 122.5 1.17.5 0.228 176.3 10.29 3.271 -46.3 0.151 -21.5 0.294 103 1.18.0 0.212 145.6 9.61 3.022 -59.8 0.161 -28.6 0.333 84.3 1.18.5 0.218 117.8 8.72 2.728 -72.4 0.169 -35.6 0.38 69.5 1.19.0 0.257 92.7 7.94 2.494 -84.1 0.178 -41.8 0.429 57.9 1.19.5 0.302 72.9 6.98 2.234 -96.4 0.189 -48.9 0.482 47.9 110.0 0.359 57.7 6.11 2.02 -107.7 0.196 -56.4 0.531 39.2 1Notes:1. S-parameters are measured on a microstrip line made on 0.025 inch thick alumina carrier. The input reference plane is at the end of the input lead.The output reference plane is at the end of the output lead.11Ordering InformationPart NumberNo. of DevicesContainerADA-4643-TR1 3000 7” ReelADA-4643-TR2 10000 13” ReelADA-4643-BLK 100 antistatic bag ADA-4643-TR1G 3000 7” ReelADA-4643-TR2G 10000 13” Reel ADA-4643-BLKG 100antistatic bagNote: For lead-free option, the part number will have the character “G” at the end.Package DimensionsOutline 43SOT-343 (SC70 4-lead)Recommended PCB Pad Layout for Avago’s SC70 4L/SOT-343 ProductsDIMENSIONS (mm)MIN.1.151.851.800.800.800.000.150.550.100.10MAX.1.352.252.401.101.000.100.400.700.200.46SYMBOL E D HE A A2A1b b1c LNOTES:1. All dimensions are in mm.2. Dimensions are inclusive of plating.3. Dimensions are exclusive of mold flash & metal burr.4. All specifications comply to EIAJ SC70.5. Die is facing up for mold and facing down for trim/form, ie: reverse trim/form.6. Package surface to be mirror finish.1.30(0.051)Dimensions inmm (inches)(0.039)For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5989-3753EN AV02-3598EN - June 8, 2012(COVER TAPE THICKNESS)DESCRIPTIONSYMBOL SIZE (mm)SIZE (INCHES)LENGTH WIDTH DEPTH PITCHBOTTOM HOLE DIAMETERA 0B 0K 0P D 12.40 ± 0.102.40 ± 0.101.20 ± 0.104.00 ± 0.101.00 + 0.250.094 ± 0.0040.094 ± 0.0040.047 ± 0.0040.157 ± 0.0040.039 + 0.010CAVITYDIAMETER PITCH POSITIOND P 0E 1.50 ± 0.104.00 ± 0.101.75 ± 0.100.061 + 0.0020.157 ± 0.0040.069 ± 0.004PERFORATIONWIDTHTHICKNESS W t 18.00 + 0.30 - 0.100.254 ± 0.020.315 + 0.0120.0100 ± 0.0008CARRIER TAPE CAVITY TO PERFORATION (WIDTH DIRECTION)CAVITY TO PERFORATION (LENGTH DIRECTION)FP 23.50 ± 0.052.00 ± 0.050.138 ± 0.0020.079 ± 0.002DISTANCEWIDTHTAPE THICKNESSC T t 5.40 ± 0.100.062 ± 0.0010.205 + 0.0040.0025 ± 0.0004COVER TAPE Device OrientationTape DimensionsFor Outline 4TUSER FEEDEND VIEWTOP VIEW。
TERIDIAN 73S1209F Evaluation Board User 说明书
Simplifying System Integration TM73S1209FEvaluation Board User GuideAugust 19, 2009Rev. 1.3UG_1209F_03473S1209F Evaluation Board User Guide UG_1209F_034 © 2009 Teridian Semiconductor Corporation. All rights reserved.Teridian Semiconductor Corporation is a registered trademark of Teridian Semiconductor Corporation. Simplifying System Integration is a trademark of Teridian Semiconductor Corporation.Microsoft, Windows and Vista are registered trademarks of Microsoft Corporation.Signum is a trademark of Signum Systems Corporation.Keil is a trademark of ARM® Ltd.All other trademarks are the property of their respective owners.Teridian Semiconductor Corporation makes no warranty for the use of its products, other than expressly contained in the Company’s warranty detailed in the Teridian Semiconductor Corporation standard Terms and Conditions. The company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice and does not make any commitment to update the information contained herein. Accordingly, the reader is cautioned to verify that this document is current by comparing it to the latest version on or by checking with your sales representative.Teridian Semiconductor Corp., 6440 Oak Canyon, Suite 100, Irvine, CA 92618TEL (714) 508-8800, FAX (714) 508-8877, UG_1209F_034 73S1209F Evaluation Board User GuideTable of Contents1Introduction (4)1.1Evaluation Kit Contents (5)1.2Evaluation Board Features (5)1.3Recommended Equipment and Test Tools (5)2Evaluation Board Setup (6)2.1Connecting the Evaluation Board with an Emulation Tool (7)2.2Loading User Code into the Evaluation Board (8)3Using the PCCID Application (10)3.1Host Demonstration Software Installation (10)4Evaluation Board Hardware Description (11)4.1Jumpers, Switches and Modules (11)4.2Test Points (16)4.3Schematic (17)4.4PCB Layouts (18)4.5Bill of Materials (24)4.6Schematic Information (27)4.6.1Reset Circuit (27)4.6.2Oscillators (27)4.6.3LCD (28)4.6.4Smart Card Interface (29)5Ordering Information (30)6Related Documentation (30)7Contact Information (30)Revision History (31)FiguresFigure 1: 73S1209F Evaluation Board (4)Figure 2: 73S1209F Evaluation Board Basic Connections (6)Figure 3: 73S1209F Evaluation Board Basic Connections with ADM-51 ICE (7)Figure 4: Emulator Window Showing RESET and ERASE Buttons (9)Figure 5: Emulator Window Showing Erased Flash Memory and File Load Menu (9)Figure 6: 73S1209F Evaluation Board Jumper, Switch and Module Locations (15)Figure 7: 73S1209F Evaluation Board Electrical Schematic (17)Figure 8: 73S1209F Evaluation Board Top View (Silkscreen) (18)Figure 9: 73S1209F Evaluation Board Bottom View (Silkscreen) (19)Figure 10: 73S1209F Evaluation Board Top Signal Layer (20)Figure 11: 73S1209F Evaluation Board Middle Layer 1 – Ground Plane (21)Figure 12: 73S1209F Evaluation Board Middle Layer 2 – Supply Plane (22)Figure 13: 73S1209F Evaluation Board Bottom Signal Layer (23)Figure 14: External Components for RESET (27)Figure 15: Oscillator Circuit (27)Figure 16: LCD Connections (28)Figure 17: Smart Card Connections (29)TablesTable 1: Flash Programming Interface Signals (8)Table 2: Evaluation Board Jumper, Switch and Module Description (11)Table 3: Evaluation Board Test Point Description (16)Table 4: 73S1209F Evaluation Board Bill of Materials (24)73S1209F Evaluation Board User Guide UG_1209F_034 1 IntroductionThe Teridian Semiconductor Corporation (TSC) 73S1209F Evaluation Board is used to demonstrate the capabilities of the 73S1209F Smart Card Controller device. It has been designed to operate either as a standalone or as a development platform.The 73S1209F Evaluation Board can be programmed to run any of the Teridian turnkey applications or a user-developed custom application. Teridian provides its USB CCID application preloaded on the board and an EMV testing application on the CD.Applications can be downloaded through the In-Circuit-Emulator (ICE) or through the TSC Flash Programmer Model TFP2. As a development tool, the evaluation board can operate in conjunction with an ICE to develop and debug 73S1209F based embedded applications.The 73S1209F Evaluation Board uses the same PWB as the 73S1215F. The 73S1215F hassome features that the 73S1209F does not contain. These include the 32 kHz oscillator, USBinterface, LED2 and LED3. These features are depopulated on the 73S1209F.Figure 1: 73S1209F Evaluation BoardUG_1209F_034 73S1209F Evaluation Board User Guide 1.1 Evaluation Kit ContentsThe 73S1209F Evaluation Kit contains the following:•73S1209F Evaluation Board: 4-layer, rectangular PWB as shown in Figure 1 (identification number E1215N12C1 Rev C), containing the 73S1209F with the preloaded turnkey program PCCID.•12 VDC/1,000 mA universal wall transformer with 2.1 mm plug ID (CUI Inc. – EPAS-101W-12). •Serial cable: DB9, male/female, 2 meter length (Digi-Key AE1379-ND).•CD containing documentation (data sheet, and user guides), Software API libraries, evaluation code, and utilities.1.2 Evaluation Board FeaturesThe 73S1209F Evaluation Board (see Figure 1) includes the following:•RS-232 interface•Dual smart card interface•ICE/Programmer interface• 2 line x 16 character LCD module• 6 x 5 Keypad• 2 LEDs1.3 Recommended Equipment and Test ToolsThe following equipment and tools (not provided) are recommended for use with the 73S1209F Evaluation Kit:•For functional evaluation: PC with Microsoft® Windows® XP or Vista®.•For software development (MPU code)▪Signum™ ICE (In Circuit Emulator): ADM-51. Refer to/Signum.htm.▪Keil™ 8051 C Compiler Kit: CA51. Refer to /c51/ca51kit.htm and /product/sales.htm73S1209F Evaluation Board User Guide UG_1209F_0342 Evaluation Board SetupFigure 2 shows the basic connections of the evaluation board with the external equipment.The power supply can come from two sources:• A regulated lab power supply connected to the banana plugs J2, J3 and J5. In this case, the board main switch S1 has no effect.•Any AC-DC converter block (default), able to generate a DC power supply of 7 V min / 12 V max / 400 mA. In this case, the board main switch S1 connects or disconnects the supply to the board.The communication with an external host is accommodated via a standard RS-232 serial interface (TX/RX only).The board is loaded by default with the PCCID application. It requires a PC to be connected through its serial port. When powered-up, the board is able to run with the PC Exerciser host application. Refer to the 73S1209F Evaluation Board Quick Start Guide to setup and run the PCCID application.Figure 2: 73S1209F Evaluation Board Basic Connections+7 V to +12 V 400 mA Power Supply:1) Lab DC dual (3.3 V,5 V) supply or 2) Non-regulated DC Block 12+2.7 V to +3.6 V 400 mA +4.0 V to+6.5 V 400 mAUG_1209F_034 73S1209F Evaluation Board User Guide 2.1 Connecting the Evaluation Board with an Emulation ToolThe 73S1209F Evaluation Board has been designed to operate with an In-Circuit-Emulator (ICE) from Signum Systems (model ADM-51). Figure 3 shows the connections between the ICE and the evaluation board. The Signum System POD has a ribbon cable that must be directly attached to connector J11. Signum Systems offers different POD options depending on user needs. The standard pod allows users to perform typical emulator functions such as symbolic debugging, in-line breakpoints, memory examination/modification, etc. Other pod options enable code trace capability and/or complex breakpoints at an additional cost.Figure 3: 73S1209F Evaluation Board Basic Connections with ADM-51 ICE73S1209F Evaluation Board User Guide UG_1209F_0342.2 Loading User Code into the Evaluation BoardHardware Interface for ProgrammingThe signals listed in Table 1 are necessary for communication between the TFP2 or ICE and the73S1209F.Table 1: Flash Programming Interface SignalsThese signals, along with 3.3 V and GND are available on the emulator header J11. Production modules may be equipped with much simpler programming connectors, e.g. a 5x1 header.Programming of the flash memory requires either the Signum Systems ADM51 in-circuit emulator or the TSC Flash Programmer Model TFP2 provided by Teridian.Loading Code with the In-Circuit EmulatorIf firmware exists in the 73S1209F flash memory, the memory must be erased before loading a new file into memory. In order to erase the flash memory, the RESET button in the emulator software must be clicked followed by the ERASE button (see Figure 4).Once the flash memory is erased, the new file can be loaded using the Load command in the File menu. The dialog box shown in Figure 5 makes it possible to select the file to be loaded by clicking the Browse button. Once the file is selected, pressing the OK button loads the file into the flash memory of the IC.At this point, the emulator probe (cable) can be removed. Once the 73S1209F device is reset using the reset button on the evaluation board, the new code starts executing.Loading Code with the TSC Flash Programmer Model TFP2Follow the instructions given in the TSC Flash Programmer Model TFP2 User's Manual.UG_1209F_034 73S1209F Evaluation Board User GuideFigure 4: Emulator Window Showing RESET and ERASE ButtonsFigure 5: Emulator Window Showing Erased Flash Memory and File Load MenuRESET BUTTONERASE BUTTON73S1209F Evaluation Board User Guide UG_1209F_034 3 Using the PCCID ApplicationThe PCCID firmware is pre-installed on the 73S1209F Evaluation Board. It requires a PC with the serial RS-232 port. When powered-up, the board is able to run the PCCID demonstration host application which allows:•Smart card activation and deactivation, in ISO or EMV mode.•Smart card APDU commands to be exchanged with the smart card inserted in the board.•Starting a test sequence in order to test and evaluate the board performance against an EMV test environment.3.1 Host Demonstration Software InstallationInstallation on Windows XPFollow these steps to install the software on a PC running Windows XP:•Extract “PCCID V z.zz Release.zip” (where z.zz is the latest version of the firmware release).o Create an install directory. For example: “C:\TSC\”.o Unzip “PCCID V z.zz Release.zip” to the just created folder. All applications and documentation needed to run the board with a Windows PC will be loaded to this folder.•Plug the supplied adapter into the 5V DC jack and a wall outlet.•Connect the serial cable between the host system and the 73S1209F Evaluation Board.•Press the ON/OFF switch to turn the board on.•Run “TSCP-CCID.exe” (located in the path - x:\yyy\ PCCID V z.zz Release\Host Applications\Windows App\App\Bin\Release) on the host system to execute the host demonstration application (where x refers to the drive, yyy refers to the directory the installation .zip file wasexpanded to and z.zz is the latest version of the firmware release).At this point the application window should appear. For additional information regarding the use of the Teridian Host application, refer to the Pseudo-CCID Host GUI Users Guide (UG_12xxF_037).UG_1209F_034 73S1209F Evaluation Board User Guide 4 Evaluation Board Hardware Description4.1 Jumpers, Switches and ModulesTable 2 describes the 73S1209F Evaluation Board jumpers, switches and modules. The Item # in Table 2 references Figure 6. The default setting refers to setup for running USB-CCID application.Table 2: Evaluation Board Jumper, Switch and Module Description273S1209F Evaluation Board User Guide UG_1209F_034UG_1209F_034 73S1209F Evaluation Board User Guide73S1209F Evaluation Board User Guide UG_1209F_03473S1209F Evaluation Board User’s Guide UG_1209F_034 4.2 Test PointsThe test point numbers listed in Table 3 refer to the test point numbers shown in the electrical schematic and in the silkscreen of the PCB.Table 3: Evaluation Board Test Point DescriptionTP22 is not populated with the 73S1209F.UG_1209F_034 73S1209F Evaluation Board User Guide 4.6 Schematic InformationThis section provides recommendations on proper schematic design that will help in designing circuits that are functional and compatible with the PCCID software library APIs.4.6.1 Reset CircuitThe 73S1209F Evaluation Board provides a reset pushbutton that can be used when prototyping and debugging software. The RESET pin should be supported by the external components shown in Figure 14. R8 should be around 10 Ω. The capacitor C27 should be 10 µF. R8 and C27 should be mounted as close as possible to the IC.C43 (1000 pF) is shown for EFT protection and is optional.Figure 14: External Components for RESET4.6.2 OscillatorsThe 73S1209F contains an oscillator for the primary system clock. The system clock should use a12 MHz crystal to provide the proper system clock rates for the serial and smart card interfaces. The system oscillator requires a 1 MΩ parallel resistor to insure proper oscillator startup (Figure 15).Figure 15: Oscillator CircuitRev. 1.3 2773S1209F Evaluation Board User Guide UG_1209F_034 4.6.3 LCDThe 73S1209F does not contain an on-chip LCD controller. However, an LCD module (with built-in controller) can be used with the 73S1209F via use of specific USR (GPIO) pins. The LCD API libraries support up to a 2 line/16 character display. Figure 16 shows the basic connection for this type of LCD. The LCD module must connect to the USR pins as shown and it requires an external brightness adjust circuit.73S1209FFigure 16: LCD Connections28 Rev. 1.3UG_1209F_034 73S1209F Evaluation Board User Guide 4.6.4 Smart Card InterfaceThe smart card interface on the 73S1209F requires few external components for proper operation. Figure 17 shows the recommended smart card interface connections.•The RST and CLK signals should have 27 pF capacitors at the smart card connector.•It is recommended that a 0 Ω resistor be added in series with the CLK signal. If necessary, in noisy environments, this resistor can be replaced with a small resistor to create a RC filter on the CLK signal to reduce CLK noise. This filter is used to soften the clock edges and provide a cleaner clock for those environments where this could be problematic.•The VCC output must have a 1.0 µF capacitor at the smart card connector for proper operation. •The VPC input is the power supply input for the smart card power. It is recommended that both a10 µF and a 0.1 µF capacitor are connected to provide proper decoupling for this input.•The PRES input on the 73S1209F contains a very weak pull down resistor. As a result, an additional external pull down resistor is recommended to prevent any system noise from triggering a false card event. The same holds true for the PRES input, except a pull up resistor is utilized as the logic is inverted from the PRES input.The smart card interface layout is important. The following guidelines should be followed to provide the optimum smart card interface operation:•Route auxiliary signals away from card interface signals•Keep CLK signal as short as possible and with few bends in the trace. Keep route of the CLK trace to one layer (avoid vias to other plane). Keep CLK trace away from other traces especially RST and VCC. Filtering of the CLK trace is allowed for noise purpose. Up to 30 pF to ground is allowed at the CLK pin of the smart card connector. Also, the zero ohm series resistor, R7, can be replaced for additional filtering (no more than 100 Ω).•Keep VCC trace as short as possible. Make trace a minimum of 0.5 mm thick. Also, keep VCC away from other traces especially RST and CLK.•Keep CLK trace away from VCC and RST traces. Up to 30 pF to ground is allowed for filtering •Keep 0.1 µF close to VDD pin of the device and directly take other end to ground•Keep 10 µF and 0.1 µF capacitors close to VPC pin of the device and directly take other end to ground•Keep 1.0 µF close to VCC pin of the smart card connector and directly take other end to ground 1215Figure 17: Smart Card ConnectionsRev. 1.3 2973S1209F Evaluation Board User Guide UG_1209F_034 5 Ordering Information6 Related DocumentationThe following 73S1209F documents are available from Teridian Semiconductor Corporation:73S1209F Data Sheet73S1209F Evaluation Board Quick Start GuideTSC Flash Programmer Model TFP2 User's Manual7 Contact InformationFor more information about Teridian Semiconductor products or to check the availability of the 73S1209F contact us at:6440 Oak Canyon RoadSuite 100Irvine, CA 92618-5201Telephone: (714) 508-8800FAX: (714) 508-8878Email:************************For a complete list of worldwide sales offices, go to .30 Rev. 1.3UG_1209F_034 73S1209F Evaluation Board User Guide Revision HistoryRev. 1.3 31。
VLA106-15242;中文规格书,Datasheet资料
DC/DC ConverterVLA106-15242Powerex, Inc., 173 Pavilion Lane, Y oungwood, Pennsylvania 15697 (724) 925-72721Rev. 01/10Description:VLA106-15242 is a DC-DC converter. Its output power is 2.4W and the input is isolated from the output. The over-current protection circuit is built-in. This device is used for on-board power supplies in industrial control equipment.Features:£ Input Voltage Range: 12.0 to 18.0V DC£ Output: +24V , 100mA (Output Power: 2.4W)£ Thin Profile, Lightweight Design £ Electrical Isolation Voltage Between Input and Output: 2500 V rms for 1 Minute£ Built in Over-current Protection CircuitApplication:On-board power supplies such as industrial equipment and control equipment.Outline Drawing and Circuit Diagram Dimensions Inches Millimeters A 1.3 33.0 B 0.945 24.0 C 0.71 18.0 D 1.0 25.4 E 0.22 5.5 F 0.53 13.5 G 0.18 4.5 H 0.10 2.54 J 0.18±0.06 4.5±1.5 K 0.02+0.004/-0.002 0.5+0.1/-0.05 L0.01+0.01/-0.002 0.25+0.2/-0.05 Note: All dimensions listed are maximums except D./VLA106-15242Isolated DC/DC ConverterPowerex, Inc., 173 Pavilion Lane, Y oungwood, Pennsylvania 15697 (724) 925-7272Rev. 01/102Absolute Maximum Ratings, T a = 25°C unless otherwise specifiedCharacteristicsSymbol VLA106-15242Units Input Voltage (Between Pins 8, 9, and 10, 11) V IN 18 Volts Output Current (Between Pins 3 and 1) I O 100 mA Operating Temperature (No Condensation)* T opr -20 ~ 70 °C Storage Temperature (No Condensation) T stg -20 to 85 °C Input-Output Isolation Voltage (AC, 1 Minute) V ISO2500V rms*Please refer to derating characteristics.Electrical and Mechanical Characteristics, T a = 25°C, V IN = 24V unless otherwise specifiedCharacteristics Symbol Test ConditionsMin. Typ. Max. Units Input Voltage V IN Recommended Range12 15 18 Volts Output Voltage 1 V O1 Between Pins 3 and 1, I O = 0 ~ 100mA22.8 24.0 25.2 Volts Output Voltage 2 V O2 Between Pins 2 and 1, 7.798.28.61VoltsBetween Pins 3 and 2 : No LoadInput Regulation R eg-I Between Pins 3 and 1, ——50mVI O = 100mA, V IN = 12.0 ~ 18.0V Load Regulation R eg-L Between Pins 3 and 1, I O = 0 ~ 100mA — — 50 mV Ripple Voltage V P-P Between Pins 3 and 1, I O = 100mA — — 150 mV EfficiencyhBetween Pins 3 and 1, I O = 100mA—75—%E F F I C I E N C Y , h , (%)EFFICIENCY VS. OUTPUT CURRENTCHARACTERISTICS 100806040200OUTPUT VOLTAGE VS. OUTPUT CURRENTCHARACTERISTICSEFFICIENCY VS. INPUT VOLTAGECHARACTERISTICS 048121620048121620321620242812840INPUT VOLTAGE, V IN , (VOLTS) O U T P U T V O L T A G E , V O , (V O L T S )INPUT VOLTAGE, V IN , (VOLTS)AMBIENT TEMPERATURE, (°C)-103010110507090/分销商库存信息: POWEREXVLA106-15242。
LB1973JA-AH;中文规格书,Datasheet资料
LB1973JATwo-channel H-Bridge DriverOverviewThe LB1973JA is a two-channel H-bridge driver that supports for low saturation draive operation. It is optimal forH-bridge drive of stepping motors (AF and zoom) in portable equipment such as camera cell phones.Features• Two-channel H-bridge driver • 2 phase excitation, 1-2 phase excitation drive are possible• 2ch simultaneous connection is possible • The range of the operation voltage is wide.(1.8V to 7.5V)• Parallel input interface • Built-in thermal protectionSpecificationsAbsolute Maximum Ratings at Ta = 25°CParameter Symbol Conditions Ratings UnitMaximum supply voltage V CC max -0.3 to +8.0 VOutput voltage V OUT max - V SF to V CC+V SF VInput voltage V IN max -0.3 to +8.0 VSpark killer Di order direction electric I SF max 1000 mAGround pin source current I GND Perchannel 1000 mAAllowable power dissipation Pd max *Mounted on a bord 800 mWOperating temperature Topr -20 to +85 °CStorage temperature Tstg -40 to +150 °C* Mounted on a Specified board : 114.3mm×76.1mm×1.6mm, glass epoxyCaution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current, highvoltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.Allowable Operating Ratings at Ta = 25°CParameter Symbol Conditions Ratings UnitSupply voltage V CC 1.8 to 7.5V7.5VtoHigh-level input voltage V IH R IN = 1kΩ 1.3Low-level input voltage V IL R IN = 1kΩ-0.3 to +0.5VElectrical Characteristics at Ta = 25°C, V CC = 1.9VParameter Symbol ConditionsRatingsUnit min typ maxSource current I CCO1 V CC = 1.9V,IN1 to IN4 = Low level 0.01 1μAI CCO2 V CC = 3V,IN1 to IN4 = Low level 0.01 1μAI CC1 IN1 = High level,IN2 to IN4 = Low level 18 25mAI CC2 IN1 = High level,IN2 to IN4 = Low level,V CC= 3V19 27.5mAOutput saturation voltage1 (single connection) V OUT11 I OUT = 270mA,V CC = 1.9V to 3.6V,Ta = -20 to 85°CV OUT = Upper Tr and Under TrIN1 = High level, IN2 to IN4 = Low levelSupplementation: Standard similar as for IN2to IN4 = High level0.2 0.3VV OUT12 I OUT = 350mA,V CC = 1.9V to 3.6V,Ta = -20 to 85°CV OUT = Upper Tr and Under TrIN1 = High level, IN2 to IN4 = Low levelSupplementation: Standard similar as for IN2to IN4 = High level0.25 0.4VOutput saturation voltage2 (parallel connection) V OUT21 I OUT = 270mA,V CC = 1.9V to 3.6V,Ta = -20 to 85°CV OUT = Upper Tr and Under TrOUT1-3,OUT2-4 short. IN1 and IN3 = Highlevel, IN2 and IN4 = Low levelSupplementation: Standard similar as for IN2and IN4 = High level0.12 0.2VV OUT22 I OUT = 500mA,V CC = 1.9V to 3.6V,Ta = -20 to 85°CV OUT = Upper Tr and Under TrOUT1-3,OUT2-4 short. IN1 and IN3 = Highlevel,IN2 and IN4 = Low levelSupplementation: Standard similar as for IN2and IN4 = High level0.2 0.35VOutput electric current with theparasitic elementI PA V IN = 1.9 to 3.6V, Ta = -20 to 85°C *1 9mA Input current I IN V IN = 1.9V 32 70μAThemal shutdown operation temperature Ttsd *2:Designguarantee 140 °CTemperature hysteresis width ∆T *2:Designguarantee 20 °C Spark killer DiodeReverse current I S(leak) V CC-OUT = 8V, V IN = Low level 10μA Forword voltage V SF I SF = 400mA, V IN = Low level 1.7V*1: Output electric current with the parasitic element_I PA: The current value that the off ch(-free) output is pulled at the time of one side ch drive by a parasiticelement*2: Design guarantee value and does not measure* VSF: The current order direction voltage true in a timePackage Dimensionsunit : mm (typ)Pin AssignmentTruth TableInput OutputModeIN1 IN2 IN3 IN4 OUT1 OUT2 OUT3 OUT4 Low Low Low Low Off Off Off Off Standby mode High Low- - High Low - -Channel 1, forwardLow High Low High Channel 1,reverse - - High Low - -High Low Channel 2, forward Low High Low High Channel 2, reverse High High --The logic output for the first high-level input is produced.- - High HighO U T 1O U T 2O U T 3O U T 4I N 2G N DI N 1I N 3I N 4V C C(Top View)N CN CN CN CN CN C A l l o w a b l e p o w e r d i s s i p a t i o n ,P d m a x - WAmbient temperature, Ta -- CStepping motor control example (1) Timing chart for 2-phase drive(2) Timing chart for 1-2 phase driveIN1IN3I N2IN4Channel 1output modeForward Standby Standby Reverse Forward StandbyStandbyForward Reverse Forward Channel 2output modeForward Reverse Forward Reverse IN1IN3I N2IN4OFF OFF OFF OFF Channel 1output mode Channel 2output modeForward Standby Standby Reverse Forward StandbyStandbyForward Reverse ForwardBlock DiagramThis catalog provides information as of March, 2012. Specifications and information herein are subject to change without notice.VIN2IN1IN3IN4分销商库存信息: ONSEMILB1973JA-AH。