彩灯实验报告

设计八彩灯控制器
要求：
1、设计一个彩灯控制器，使彩灯（LED管）能连续发出四种以上不同的显示形式；
2、随着彩灯显示形式的变化，发出不同的音响声。

设计提示:
1、彩灯显示的不同形式可由不同进制计数器驱动LED显示完成；
2、音响由选择不同频率CP脉冲驱动扬声器形成；
3、彩灯显示形式由实验箱中拨码开关控制。

实验程序
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY caidengkongzhiqi IS
PORT
(
clk1,rst,clk2 : IN std_logic;
caideng : OUT std_logic_vector(7 downto 0);
cz:in std_logic_vector(1 downto 0);
speaker: out std_logic );
END caidengkongzhiqi;
ARCHITECTURE one OF caidengkongzhiqi IS
COMPONENT counter_8
PORT
(
clk,rst : IN std_logic;
count_out : OUT integer range 0 to 7
);
END COMPONENT ;
COMPONENT caidengkongzhi
PORT
(
Ins :in std_logic_vector(1 downto 0);
Input : IN INTEGER RANGE 0 TO 7;
Rst :in std_logic;
output : OUT std_logic_vector(7 downto 0));
END COMPONENT ;
COMPONENT fenpinqi
(
clk,rst : IN std_logic;
clk_10,clk_4,clk_6,clk_8 : OUT std_logic
);
END COMPONENT ;
COMPONENT xzq4_1
PORT
(
Rst :in std_logic;
Inp :in std_logic_vector(1 downto 0);
in1,in2,in3,in4 : In std_logic;
output : OUT std_logic
);
END COMPONENT ;
SIGNAL s,g,m,n,k :std_logic;
SIGNAL f:INTEGER RANGE 0 TO 31;
SIGNAL w:integer range 0 to 3;
BEGIN
u1: counter_8 port map (clk=>clk1, rst=>rst, count_out =>f);
u2: caidengkongzhi port map (ins=>cz,input=>f, rst=>rst, output =>caideng);
u3: fenpinqi port map (clk=>clk2, rst=>rst, clk_10=>g, clk_4=>m, clk_6=>n, clk_8=>k);
u4: xzq4_1 port map (inp=>cz, rst=>rst, in1=>g, in2=>m, in3=>n, in4=>k, output=>speaker);
END one;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY fenpinqi IS
PORT
(
clk,rst : IN std_logic;
clk_10,clk_4,clk_6,clk_8 : OUT std_logic
);
END fenpinqi;
ARCHITECTURE cd OF fenpinqi IS
begin
p1:process(clk,rst)
variable a:integer range 0 to 20;
if rst='1' then
clk_4<='0';
a:=0;
else
if clk'event and clk='1'then
if a>=3 then
a:=0;
clk_4<='1';
else
a:=a+1;
clk_4<='0';
end if;
end if;
end if;
end process p1;
p2:process(clk,rst)
variable b:integer range 0 to 20;
begin
if rst='1' then
clk_6<='0';
b:=0;
else
if clk'event and clk='1'then
if b>=5 then
b:=0;
clk_6<='1';
else
b:=b+1;
clk_6<='0';
end if;
end if;
end if;
end process p2;
p3:process(clk,rst)
variable c:integer range 0 to 20;
begin
if rst='1' then
clk_8<='0';
c:=0;
else
if clk'event and clk='1'then
if c>=7 then
c:=0;
clk_8<='1';
else
c:=c+1;
clk_8<='0';
end if;
end if;
end if;
end process p3;
p4:process(clk,rst)
variable d:integer range 0 to 20;
begin
if rst='1' then
clk_10<='0';
d:=0;
else
if clk'event and clk='1'then
if d>=9 then
d:=0;
clk_10<='1';
else
d:=d+1;
clk_10<='0';
end if;
end if;
end if;
end process p4;
end cd;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY xzq4_1 IS
PORT
(
rst:in std_logic;
inp:in std_logic_vector(1 downto 0);
in1,in2,in3,in4 : In std_logic;
output : OUT std_logic
);
END xzq4_1;
ARCHITECTURE a OF xzq4_1 IS
BEGIN
PROCESS (rst,inp)
BEGIN
if(rst='1') then output<='0';
else
case inp is
when "00"=>output<=in1;
when "01"=>output<=in2;
when "10"=>output<=in3;
when "11"=>output<=in4;
when others=>null;
end case;
end if;
END PROCESS;
END a;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY counter_8 IS
PORT
(
clk,rst : IN std_logic;
count_out : OUT integer range 0 to 7 );
END counter_8;
ARCHITECTURE a OF counter_8 IS
BEGIN
PROCESS (rst,clk)
variable temp:integer range 0 to 8;
BEGIN
IF rst='1' THEN
temp:=0;
ELSIF (clk'event and clk='1') THEN
temp:=temp+1;
if(temp=8) then
temp:=0;
end if;
END IF;
count_out<=temp;
END PROCESS;
END a;
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY caidengkongzhi IS
PORT( ins :in std_logic_vector(1 downto 0);
input : IN INTEGER RANGE 0 TO 7;
rst:in std_logic;
output : OUT std_logic_vector(7 downto 0)); END caidengkongzhi;
ARCHITECTURE a OF caidengkongzhi IS
BEGIN
PROCESS (input)
BEGIN
if rst='1' then output<="00000000";
else
If(ins="00") then
case input is
when 0=>output<="10000000";
when 1=>output<="01000000";
when 2=>output<="00100000";
when 3=>output<="00010000";
when 4=>output<="00001000";
when 5=>output<="00000100";
when 6=>output<="00000010";
when 7=>output<="00000001";
when others=>null;
end case;
Elsif(ins="01") then
case input is
when 0=>output<="00010000";
when 1=>output<="00110000";
when 2=>output<="00111000";
when 3=>output<="01111000";
when 4=>output<="01111100";
when 5=>output<="01111110";
when 6=>output<="11111110";
when 7=>output<="11111111";
when others=>null;
end case;
Elsif(ins="10")then
case input is
when 0=>output<="10000001";
when 1=>output<="11000001";
when 2=>output<="11000011";
when 3=>output<="11100011";
when 4=>output<="11100111";
when 5=>output<="11110111";
when 6=>output<="11111111";
when 7=>output<="10000001";
when others=>null;
end case;
Else
case input is
when 0=>output<="00000011";
when 1=>output<="00000110";
when 2=>output<="00001100";
when 3=>output<="00011000";
when 4=>output<="00110000";
when 5=>output<="01100000";
when 6=>output<="11000000";
when 7=>output<="10000001";
when others=>null;
end case;
end if;
end if;
end process;
end a;
原理图
管脚配置图
波形仿真图四选一选择器
分频器
八进制计数器。