UL635H256s2K35G1资料

Power Control
VCC VSS
VCC
Store/ Recall
Control
Software Detect
A0 - A13
G
E W
Operating Mode
E
W
G
DQ0 - DQ7
Standby/not selected
H
*
*
Internal Read
L
H
H
High-Z High-Z
Read
Symbol
Conditions
VCC
tc = 35 ns
tc = 45 ns
VIL
-2 V at Pulse Width 10 ns permitted
VIH
UL635H256
Min.
3.0 2.7 -0.3 2.2
Max.
3.6 3.6 0.8 VCC+0.3
Unit
V V V V
DC Characteristics
• Operating temperature range:
0 to 70 °C
-40 to 85 °C
• QS 9000 Quality Standard • ESD protection > 2000 V
(MIL STD 883C M3015.7-HBM)
• RoHS compliance and Pb- free • Package:SOP28 (330 mil)
volatile static RAM 32768 x 8 bits
• 35 and 45 ns Access Times • 15 and 20 ns Output Enable
Access Times
• ICC = 8 mA typ. at 200 ns Cycle
Time
• Automatic STORE to EEPROM
March 31, 2006
STK Control #ML0059
1
Rev 1.0
元器件交易网
UL635H256
Block Diagram
A5 A6 A7 A8 A9 A11 A12 A13 A14
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
Input Buffers
L
H
L
Data Outputs Low-Z
Write
L
L
*
Data Inputs High-Z
* H or L Characteristics
All voltages are referenced to VSS = 0 V (ground). All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Pin Configuration
Pin Description
A14 A12
A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1
28
2
27
3
26
4
25
5
24
6
23
7 SOP 22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
Top View
VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
G A11
A9 A8 A13 W n. c. VCC n. c. A14 A12 A7 A6 A5 A4 A3
1
32
2
31
3
30
4
29
5
28
6
27
7
26
8 TSOP 25
9
24
10
23
11
22
12
21
பைடு நூலகம்
13
20
14
19
15
18
16
17
Top View
n.c. A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 n.c.
Operating Temperature
C-Type
Ta
0
K-Type
-40
70
°C
85
°C
Storage Temperature
Tstg
-65
150
°C
a: Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
The UL635H256 has two separate modes of operation: SRAM mode and nonvolatile mode. In SRAM mode, the memory operates as an ordinary static RAM. In nonvolatile operation, data is transferred in parallel from SRAM to EEPROM or from EEPROM to SRAM. In this mode SRAM functions are disabled. The UL635H256 is a fast static RAM (35 and 45 ns), with a nonvolatile electrically erasable PROM (EEPROM) element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) take place automatically upon power down using charge stored in system capacitance. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on powerup.
The UL635H256 combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity. STORE cycles also may be initiated under user control via a software sequence. Once a STORE cycle is initiated, further input or output are disabled until the cycle is completed. Because a sequence of addresses is used for STORE initiation, it is important that no other read or write accesses intervene in the sequence or the sequence will be aborted. RECALL cycles may also be initiated by a software sequence. Internally, RECALL is a two step procedure. First, the SRAM data is cleared and second, the nonvolatile information is transferred into the SRAM cells. The RECALL operation in no way alters the data in the EEPROM cells. The nonvolatile data can be recalled an unlimited number of times.
元器件交易网
Obsolete - Not Recommended for New Designs
UL635H256
Low Voltage PowerStore 32K x 8 nvSRAM
Features
Description
• High-performance CMOS non-
Absolute Maximum Ratingsa
Symbol
Min.
Max.
Unit
Power Supply Voltage
VCC
-0.5
4.6
V
Input Voltage
VI
-0.3
VCC+0.5
V
Output Voltage
VO
-0.3
VCC+0.5
V
Power Dissipation
PD
1
W
on Power Down using system
capacitance
• Software initiated STORE • Automatic STORE Timing • 106 STORE cycles to EEPROM • 100 years data retention in
EEPROM
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V, with the exception of the tdis-times and ten-times, in which cases transition is measured ± 200 mV from steady-state voltage.
STK Control #ML0059
2
Rev 1.0
March 31, 2006
元器件交易网
Recommended Operating Conditions Power Supply Voltage
Input Low Voltage Input High Voltage
Signal Name
A0 - A14 DQ0 - DQ7 E G W VCC VSS
Signal Description
Address Inputs Data In/Out Chip Enable Output Enable Write Enable Power Supply Voltage Ground
Symbol
Conditions
C-Type
K-Type
Unit
Min. Max. Min. Max.
Operating Supply Currentb
ICC1
• Automatic RECALL on Power Up • Software RECALL Initiation • Unlimited RECALL cycles from
EEPROM
• Wide voltage range: 2.7 ... 3.6 V
(3.0 ... 3.6 V for 35 ns type)
Row Decoder
EEPROM Array 512 x (64 x 8)
STORE
SRAM Array
RECALL
512 Rows x 64 x 8 Columns
Column I/O Column Decoder
A0 A1 A2 A3 A4 A10
Truth Table for SRAM Operations