SATURATED TYPE LOGICAL CIRCUIT
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专利名称：SATURATED TYPE LOGICAL CIRCUIT 发明人：KIYOZUKA NOBORU,MORI SUSUMU 申请号：JP20285181
申请日：19811216
公开号：JPS58104532A
公开日：
19830622
专利内容由知识产权出版社提供
摘要：PURPOSE:To attain high-speed operation of a saturated type logical circuit, by improving an active pull-down circuit. CONSTITUTION:A saturated logical circuit is formed with a PNP input transistor (TR)Q1 connected to a power supply via an emitter resistor
R1, a level shift TRQ2, a phase split stage TRQ3, and a common emitter output TRQ4. The emitter of TRQ7 the base of which is connected to the collector of the level shift TRQ2 via a resistor R3, is grounded, the collector is connected to the base of the output TRQ4 via a resistor R8, and the anode and cathode of a diode D2 are connected between the base of the TRQ7 and the collector of the PNP input TRQ1, and the collector of the PNP input TRQ1 is grounded via a resistor R4. The collector potential of the level shift TRQ2 is detected, allowing to interrupt/ conduct the TRQ7 in conducting/interrupting the output TRQ4.
申请人：NIPPON DENKI KK
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