COMPLEMENTARY ACCUMULATION-MODE JFET INTEGRATED CI

专利名称：COMPLEMENTARY ACCUMULATION-MODE JFET INTEGRATED CIRCUIT TOPOLOGY
USING WIDE (> 2eV) BANDGAP
SEMICONDUCTORS
发明人：CASADY, Jeffrey, B.,BLALOCK,
Benjamin,SADDOW, Stephen, E.,MAZZOLA,
Michael, S.
申请号：EP02725064.6
申请日：20020304
公开号：EP1397838A2
公开日：
20040317
专利内容由知识产权出版社提供
摘要：A method and device produced for design, construction, and use of integrated circuits in wide bandgap semiconductors, including methods for fabrication of n-channel and p-channel junction field effect transistors on a single wafer or die, such that the produced devices may have pinchoff voltages of either positive or negative polarities. A first layer of either p-type or n-type is formed as a base. An alternating, channel layer of either n-type or p-type is then formed, followed by another layer of the same type as the first layer. Etching is used to provide contacts for the gates, source, and drain of the device. In one variation, pinchoff voltage is controlled via dopant level and thickness the channel region. In another variation, pinchoff voltage is controlled by variation of dopant level across the channel layer; and in another variation, pinchoff voltage is controlled by both thickness and variation of dopant level.
申请人：Mississippi State University
地址：306 Bowen Hall,Hardy Road Mississippi State, MS 39762 US 国籍：US
代理机构：Collins, John David
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