msp430G2553头文件

合集下载

msp430g2553.h文档

/********************************************************************* Standard register and bit definitions for the Texas Instruments* MSP430 microcontroller.* This file supports assembler and C development for* MSP430G2553 devices.* Texas Instruments, Version 1.0* Rev. 1.0, Setup********************************************************************/#ifndef __MSP430G2553#define __MSP430G2553#define __MSP430_HEADER_VERSION__ 1062#ifdef __cplusplusextern"C" {#endif/*----------------------------------------------------------------------------*//* PERIPHERAL FILE MAP /*----------------------------------------------------------------------------*//* External references resolved by a device-specific linker commandfile */#define SFR_8BIT(address) extern volatile unsigned char address#define SFR_16BIT(address) extern volatile unsigned int address/************************************************************* STANDARD BITS************************************************************/#define BIT0 (0x0001)#define BIT1 (0x0002)#define BIT2 (0x0004)#define BIT3 (0x0008)#define BIT4 (0x0010)#define BIT5 (0x0020)#define BIT6 (0x0040)#define BIT7 (0x0080)#define BIT8 (0x0100)#define BIT9 (0x0200)#define BITA (0x0400)#define BITB (0x0800)#define BITC (0x1000)#define BITD (0x2000)#define BITE (0x4000)#define BITF (0x8000)/************************************************************* STATUS REGISTER BITS************************************************************/#define C (0x0001)#define Z (0x0002)#define N (0x0004)#define V (0x0100)#define GIE (0x0008)#define CPUOFF (0x0010)#define OSCOFF (0x0020)#define SCG0 (0x0040)#define SCG1 (0x0080)/* Low Power Modes coded with Bits 4-7 in SR */#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define LPM0 (CPUOFF)#define LPM1 (SCG0+CPUOFF)#define LPM2 (SCG1+CPUOFF)#define LPM3 (SCG1+SCG0+CPUOFF)#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)/* End #defines for assembler */#else/* Begin #defines for C */#define LPM0_bits (CPUOFF)#define LPM1_bits (SCG0+CPUOFF)#define LPM2_bits (SCG1+CPUOFF)#define LPM3_bits (SCG1+SCG0+CPUOFF)#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)#include"in430.h"#define LPM0 _bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */#define LPM0_EXIT _bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */#define LPM1 _bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */#define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */#define LPM2 _bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */#define LPM3 _bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */#define LPM3_EXIT _bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */#define LPM4 _bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */#define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */#endif/* End #defines for C *//************************************************************* PERIPHERAL FILE MAP************************************************************//************************************************************* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS************************************************************/ SFR_8BIT(IE1); /* Interrupt Enable 1 */#define WDTIE (0x01) /* Watchdog Interrupt Enable */#define OFIE (0x02) /* Osc. Fault Interrupt Enable */#define NMIIE (0x10) /* NMI Interrupt Enable */#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */SFR_8BIT(IFG1); /* Interrupt Flag 1 */#define WDTIFG (0x01) /* Watchdog Interrupt Flag */#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */#define PORIFG (0x04) /* Power On Interrupt Flag */#define RSTIFG (0x08) /* Reset Interrupt Flag */#define NMIIFG (0x10) /* NMI Interrupt Flag*/SFR_8BIT(IE2); /* Interrupt Enable 2 */#define UC0IE IE2#define UCA0RXIE (0x01)#define UCA0TXIE (0x02)#define UCB0RXIE (0x04)#define UCB0TXIE (0x08)SFR_8BIT(IFG2); /* Interrupt Flag 2 */#define UC0IFG IFG2#define UCA0RXIFG (0x01)#define UCA0TXIFG (0x02)#define UCB0RXIFG (0x04)#define UCB0TXIFG (0x08)/************************************************************* ADC10************************************************************/#define __MSP430_HAS_ADC10__ /* Definition to show that Module is available */SFR_8BIT(ADC10DTC0); /* ADC10 Data Transfer Control 0 */SFR_8BIT(ADC10DTC1); /* ADC10 Data Transfer Control 1 */SFR_8BIT(ADC10AE0); /* ADC10 Analog Enable 0 */SFR_16BIT(ADC10CTL0); /* ADC10 Control 0 */ SFR_16BIT(ADC10CTL1); /* ADC10 Control 1 */ SFR_16BIT(ADC10MEM); /* ADC10 Memory */ SFR_16BIT(ADC10SA); /* ADC10 Data Transfer Start Address *//* ADC10CTL0 */#define ADC10SC (0x001) /* ADC10 Start Conversion */#define ENC (0x002) /* ADC10 Enable Conversion */#define ADC10IFG (0x004) /* ADC10 Interrupt Flag */#define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */#define ADC10ON (0x010) /* ADC10 On/Enable */ #define REFON (0x020) /* ADC10 Reference on */#define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */#define MSC (0x080) /* ADC10 Multiple SampleConversion */#define REFBURST (0x100) /* ADC10 Reference Burst Mode */#define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */#define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */#define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select Bit: 0 */#define ADC10SHT1 (0x1000) /* ADC10 Sample Hold Select Bit: 1 */#define SREF0 (0x2000) /* ADC10 Reference Select Bit: 0 */#define SREF1 (0x4000) /* ADC10 Reference Select Bit: 1 */#define SREF2 (0x8000) /* ADC10 Reference Select Bit: 2 */#define ADC10SHT_0 (0*0x800u) /* 4 x ADC10CLKs */ #define ADC10SHT_1 (1*0x800u) /* 8 x ADC10CLKs */ #define ADC10SHT_2 (2*0x800u) /* 16 x ADC10CLKs */ #define ADC10SHT_3 (3*0x800u) /* 64 x ADC10CLKs */ #define SREF_0 (0*0x2000u) /* VR+ = AVCC and VR- = AVSS */#define SREF_1 (1*0x2000u) /* VR+ = VREF+ and VR- = AVSS */#define SREF_2 (2*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */#define SREF_3 (3*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */#define SREF_4 (4*0x2000u) /* VR+ = AVCC and VR- = VREF-/VEREF- */#define SREF_5 (5*0x2000u) /* VR+ = VREF+ and VR- = VREF-/VEREF- */#define SREF_6 (6*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */#define SREF_7 (7*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- *//* ADC10CTL1 */#define ADC10BUSY (0x0001) /* ADC10 BUSY */#define CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */#define CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */#define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select Bit: 0 */#define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select Bit: 1 */#define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select Bit: 0 */#define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select Bit: 1 */#define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select Bit: 2 */#define ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */#define ADC10DF (0x0200) /* ADC10 Data Format 0:binary 1:2's complement */#define SHS0 (0x0400) /* ADC10 Sample/Hold Source Bit: 0 */#define SHS1 (0x0800) /* ADC10 Sample/Hold Source Bit: 1 */#define INCH0 (0x1000) /* ADC10 Input Channel Select Bit: 0 */#define INCH1 (0x2000) /* ADC10 Input Channel Select Bit: 1 */#define INCH2 (0x4000) /* ADC10 Input Channel Select Bit: 2 */#define INCH3 (0x8000) /* ADC10 Input Channel Select Bit: 3 */#define CONSEQ_0 (0*2u) /* Single channel single conversion */#define CONSEQ_1 (1*2u) /* Sequence of channels */#define CONSEQ_2 (2*2u) /* Repeat single channel */#define CONSEQ_3 (3*2u) /* Repeat sequence of channels */#define ADC10SSEL_0 (0*8u) /* ADC10OSC */#define ADC10SSEL_1 (1*8u) /* ACLK */#define ADC10SSEL_2 (2*8u) /* MCLK */#define ADC10SSEL_3 (3*8u) /* SMCLK */#define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select 0 */#define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select 1 */#define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select 2 */#define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select 3 */#define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select 4 */#define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select 5 */#define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select 6 */#define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select 7 */#define SHS_0 (0*0x400u) /* ADC10SC */#define SHS_1 (1*0x400u) /* TA3 OUT1 */#define SHS_2 (2*0x400u) /* TA3 OUT0 */#define SHS_3 (3*0x400u) /* TA3 OUT2 */#define INCH_0 (0*0x1000u) /* Selects Channel 0 */#define INCH_1 (1*0x1000u) /* Selects Channel 1 */#define INCH_2 (2*0x1000u) /* Selects Channel 2 */#define INCH_3 (3*0x1000u) /* Selects Channel 3 */#define INCH_4 (4*0x1000u) /* Selects Channel 4 */#define INCH_5 (5*0x1000u) /* Selects Channel 5 */#define INCH_6 (6*0x1000u) /* Selects Channel 6 */#define INCH_7 (7*0x1000u) /* Selects Channel 7 */#define INCH_8 (8*0x1000u) /* Selects Channel 8 */#define INCH_9 (9*0x1000u) /* Selects Channel 9 */#define INCH_10 (10*0x1000u) /* Selects Channel 10 */#define INCH_11 (11*0x1000u) /* Selects Channel 11 */#define INCH_12 (12*0x1000u) /* Selects Channel 12 */#define INCH_13 (13*0x1000u) /* Selects Channel 13 */#define INCH_14 (14*0x1000u) /* Selects Channel 14 */#define INCH_15 (15*0x1000u) /* Selects Channel 15 *//* ADC10DTC0 */#define ADC10FETCH (0x001) /* This bit should normally be reset */#define ADC10B1 (0x002) /* ADC10 block one */ #define ADC10CT (0x004) /* ADC10 continuous transfer */#define ADC10TB (0x008) /* ADC10 two-block mode */#define ADC10DISABLE (0x000) /* ADC10DTC1 *//************************************************************* Basic Clock Module************************************************************/#define __MSP430_HAS_BC2__ /* Definition to show that Module is available */SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */#define MOD0 (0x01) /* Modulation Bit 0 */ #define MOD1 (0x02) /* Modulation Bit 1 */#define MOD2 (0x04) /* Modulation Bit 2 */ #define MOD3 (0x08) /* Modulation Bit 3 */ #define MOD4 (0x10) /* Modulation Bit 4 */ #define DCO0 (0x20) /* DCO Select Bit 0 */ #define DCO1 (0x40) /* DCO Select Bit 1 */ #define DCO2 (0x80) /* DCO Select Bit 2 */ #define RSEL0 (0x01) /* Range Select Bit 0 */#define RSEL1 (0x02) /* Range Select Bit 1 */#define RSEL2 (0x04) /* Range Select Bit 2 */#define RSEL3 (0x08) /* Range Select Bit 3 */#define DIVA0 (0x10) /* ACLK Divider 0 */ #define DIVA1 (0x20) /* ACLK Divider 1 */ #define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */#define XT2OFF (0x80) /* Enable XT2CLK */#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */#define DIVS0 (0x02) /* SMCLK Divider 0 */ #define DIVS1 (0x04) /* SMCLK Divider 1 */ #define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */#define DIVM0 (0x10) /* MCLK Divider 0 */ #define DIVM1 (0x20) /* MCLK Divider 1 */ #define SELM0 (0x40) /* MCLK Source Select 0 */#define SELM1 (0x80) /* MCLK Source Select 1 */#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */#define DIVS_1 (0x02) /* SMCLK Divider 1: /2*/#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */#define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */#define SELM_2 (0x80) /* MCLK Source Select 2: XT2CLK/LFXTCLK */#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */#define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */ #define XCAP1 (0x08) /* XIN/XOUT Cap 1 */ #define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */#define XT2S0 (0x40) /* Mode 0 for XT2 */ #define XT2S1 (0x80) /* Mode 1 for XT2 */ #define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */#define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5pF */#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */#define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal *//************************************************************* Comparator A************************************************************/#define __MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */SFR_8BIT(CACTL1); /* Comparator A Control 1 */SFR_8BIT(CACTL2); /* Comparator A Control 2 */SFR_8BIT(CAPD); /* Comparator A Port Disable */#define CAIFG (0x01) /* Comp. A Interrupt Flag */#define CAIE (0x02) /* Comp. A Interrupt Enable */#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */#define CAON (0x08) /* Comp. A enable */ #define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */Reference Enable */#define CAEX (0x80) /* Comp. A Exchange Inputs */#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 : 0.25*Vcc */#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/#define CAOUT (0x01) /* Comp. A Output */ #define CAF (0x02) /* Comp. A Enable Output Filter */#define P2CA0 (0x04) /* Comp. A +Terminal Multiplexer */#define P2CA1 (0x08) /* Comp. A -Terminal Multiplexer */#define P2CA2 (0x10) /* Comp. A -Terminal Multiplexer */#define P2CA3 (0x20) /* Comp. A -Terminal Multiplexer */#define P2CA4 (0x40) /* Comp. A +Terminal Multiplexer */#define CASHORT (0x80) /* Comp. A Short + and - Terminals */#define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */Input Buffer of Port Register .7 *//************************************************************* * Flash Memory*************************************************************/ #define __MSP430_HAS_FLASH2__ /* Definition to show that Module is available */SFR_16BIT(FCTL1); /* FLASH Control 1 */ SFR_16BIT(FCTL2); /* FLASH Control 2 */ SFR_16BIT(FCTL3); /* FLASH Control 3 */ #define FRKEY (0x9600) /* Flash key returned by read */#define FWKEY (0xA500) /* Flash key for write */#define FXKEY (0x3300) /* for use with XOR instruction */#define ERASE (0x0002) /* Enable bit for Flash segment erase */#define MERAS (0x0004) /* Enable bit for Flash mass erase */#define WRT (0x0040) /* Enable bit for Flash write */#define BLKWRT (0x0080) /* Enable bit for Flash segment write */#define SEGWRT (0x0080) /* old definition */ /* Enable bit for Flash segment write */#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */#ifndef FN2#define FN2 (0x0004)#endif#ifndef FN3#define FN3 (0x0008)#endif#ifndef FN4#define FN4 (0x0010)#endif#define FN5 (0x0020)#define FSSEL0 (0x0040) /* Flash clock select 0 *//* to distinguish from USART SSELx */#define FSSEL1 (0x0080) /* Flash clock select 1 */#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */#define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */#define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */#define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */#define BUSY (0x0001) /* Flash busy: 1 */#define KEYV (0x0002) /* Flash Key violation flag */#define ACCVIFG (0x0004) /* Flash Access violation flag */#define WAIT (0x0008) /* Wait flag for segment write */#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */#define EMEX (0x0020) /* Flash Emergency Exit */#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */#define FAIL (0x0080) /* Last Program or Erase failed *//************************************************************* DIGITAL I/O Port1/2 Pull up / Pull down Resistors************************************************************/#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */SFR_8BIT(P1IN); /* Port 1 Input */ SFR_8BIT(P1OUT); /* Port 1 Output */ SFR_8BIT(P1DIR); /* Port 1 Direction */SFR_8BIT(P1IFG); /* Port 1 InterruptSFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */SFR_8BIT(P1SEL); /* Port 1 Selection */SFR_8BIT(P1SEL2); /* Port 1 Selection 2 */SFR_8BIT(P1REN); /* Port 1 Resistor Enable */SFR_8BIT(P2IN); /* Port 2 Input */ SFR_8BIT(P2OUT); /* Port 2 Output */ SFR_8BIT(P2DIR); /* Port 2 Direction */SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */SFR_8BIT(P2SEL); /* Port 2 Selection */SFR_8BIT(P2SEL2); /* Port 2 Selection 2 */SFR_8BIT(P2REN); /* Port 2 Resistor Enable *//************************************************************* DIGITAL I/O Port3 Pull up / Pull down Resistors************************************************************/#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */SFR_8BIT(P3IN); /* Port 3 Input */ SFR_8BIT(P3OUT); /* Port 3 Output */ SFR_8BIT(P3DIR); /* Port 3 Direction */SFR_8BIT(P3SEL); /* Port 3 Selection */SFR_8BIT(P3SEL2); /* Port 3 Selection 2 */SFR_8BIT(P3REN); /* Port 3 Resistor/************************************************************* Timer0_A3************************************************************/#define __MSP430_HAS_TA3__ /* Definition to show that Module is available */SFR_16BIT(TA0IV); /* Timer0_A3 Interrupt Vector Word */SFR_16BIT(TA0CTL); /* Timer0_A3 Control */SFR_16BIT(TA0CCTL0); /* Timer0_A3 Capture/Compare Control 0 */SFR_16BIT(TA0CCTL1); /* Timer0_A3 Capture/Compare Control 1 */SFR_16BIT(TA0CCTL2); /* Timer0_A3 Capture/Compare Control 2 */SFR_16BIT(TA0R); /* Timer0_A3 */SFR_16BIT(TA0CCR0); /* Timer0_A3 Capture/Compare 0 */SFR_16BIT(TA0CCR1); /* Timer0_A3 Capture/Compare 1 */SFR_16BIT(TA0CCR2); /* Timer0_A3 Capture/Compare 2 *//* Alternate register names */#define TAIV TA0IV /* Timer A Interrupt Vector Word */#define TACTL TA0CTL /* Timer A Control */ #define TACCTL0 TA0CCTL0 /* Timer ACapture/Compare Control 0 */#define TACCTL1 TA0CCTL1 /* Timer ACapture/Compare Control 1 */#define TACCTL2 TA0CCTL2 /* Timer ACapture/Compare Control 2 */#define TAR TA0R /* Timer A */#define TACCR0 TA0CCR0 /* Timer ACapture/Compare 0 */#define TACCR1 TA0CCR1 /* Timer ACapture/Compare 1 */#define TACCR2 TA0CCR2 /* Timer ACapture/Compare 2 */#define TAIV_ TA0IV_ /* Timer A InterruptVector Word */#define TACTL_ TA0CTL_ /* Timer A Control */ #define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */#define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */#define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */#define TAR_ TA0R_ /* Timer A */#define TACCR0_ TA0CCR0_ /* Timer A Capture/Compare 0 */#define TACCR1_ TA0CCR1_ /* Timer A Capture/Compare 1 */#define TACCR2_ TA0CCR2_ /* Timer A Capture/Compare 2 *//* Alternate register names 2 */#define CCTL0 TACCTL0 /* Timer ACapture/Compare Control 0 */#define CCTL1 TACCTL1 /* Timer ACapture/Compare Control 1 */#define CCTL2 TACCTL2 /* Timer ACapture/Compare Control 2 */#define CCR0 TACCR0 /* Timer ACapture/Compare 0 */#define CCR1 TACCR1 /* Timer ACapture/Compare 1 */#define CCR2 TACCR2 /* Timer ACapture/Compare 2 */#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */#define CCR0_ TACCR0_ /* Timer ACapture/Compare 0 */#define CCR1_ TACCR1_ /* Timer ACapture/Compare 1 */#define CCR2_ TACCR2_ /* Timer ACapture/Compare 2 */#define TASSEL1 (0x0200) /* Timer A clock source select 1 */#define TASSEL0 (0x0100) /* Timer A clock source select 0 */#define ID1 (0x0080) /* Timer A clock input divider 1 */#define ID0 (0x0040) /* Timer A clock input divider 0 */#define MC1 (0x0020) /* Timer A mode control 1 */#define MC0 (0x0010) /* Timer A mode control 0 */#define TACLR (0x0004) /* Timer A counter clear */#define TAIE (0x0002) /* Timer A counter interrupt enable */#define TAIFG (0x0001) /* Timer A counter interrupt flag */#define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */#define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */#define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */#define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */#define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */#define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */#define CM1 (0x8000) /* Capture mode 1 */ #define CM0 (0x4000) /* Capture mode 0 */select 1 */#define CCIS0 (0x1000) /* Capture input select 0 */#define SCS (0x0800) /* Capture sychronize */#define SCCI (0x0400) /* Latched capture signal (read) */#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */#define OUTMOD2 (0x0080) /* Output mode 2 */ #define OUTMOD1 (0x0040) /* Output mode 1 */ #define OUTMOD0 (0x0020) /* Output mode 0 */ #define CCIE (0x0010) /* Capture/compare interrupt enable */#define CCI (0x0008) /* Capture input signal (read) */#define OUT (0x0004) /* PWM Output signal if output mode 0 */#define COV (0x0002) /* Capture/compare overflow flag */#define CCIFG (0x0001) /* Capture/compare interrupt flag */#define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWM toggle/reset */#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */#define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */select: 2 - GND */#define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */#define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges *//* T0_A3IV Definitions */#define TA0IV_NONE (0x0000) /* No Interrupt pending */#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */ #define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */ #define TA0IV_6 (0x0006) /* Reserved */#define TA0IV_8 (0x0008) /* Reserved */#define TA0IV_TAIFG (0x000A) /* TA0IFG *//************************************************************* Timer1_A3************************************************************/#define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */SFR_16BIT(TA1IV); /* Timer1_A3 Interrupt Vector Word */SFR_16BIT(TA1CTL); /* Timer1_A3 Control */SFR_16BIT(TA1CCTL0); /* Timer1_A3 Capture/Compare Control 0 */SFR_16BIT(TA1CCTL1); /* Timer1_A3 Capture/Compare Control 1 */SFR_16BIT(TA1CCTL2); /* Timer1_A3 Capture/Compare Control 2 */SFR_16BIT(TA1R); /* Timer1_A3 */SFR_16BIT(TA1CCR0); /* Timer1_A3 Capture/Compare 0 */SFR_16BIT(TA1CCR1); /* Timer1_A3 Capture/Compare 1 */SFR_16BIT(TA1CCR2); /* Timer1_A3Capture/Compare 2 *//* Bits are already defined within the Timer0_Ax *//* T1_A3IV Definitions */#define TA1IV_NONE (0x0000) /* No Interrupt pending */#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */ #define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */ #define TA1IV_TAIFG (0x000A) /* TA1IFG *//************************************************************* USCI************************************************************/#define __MSP430_HAS_USCI__ /* Definition to show that Module is available */SFR_8BIT(UCA0CTL0); /* USCI A0 Control Register 0 */SFR_8BIT(UCA0CTL1); /* USCI A0 Control Register 1 */SFR_8BIT(UCA0BR0); /* USCI A0 Baud Rate 0 */SFR_8BIT(UCA0BR1); /* USCI A0 Baud Rate 1 */SFR_8BIT(UCA0MCTL); /* USCI A0 Modulation Control */SFR_8BIT(UCA0STAT); /* USCI A0 Status Register */SFR_8BIT(UCA0RXBUF); /* USCI A0 Receive Buffer */SFR_8BIT(UCA0TXBUF); /* USCI A0 Transmit Buffer */SFR_8BIT(UCA0ABCTL); /* USCI A0 LIN Control */SFR_8BIT(UCA0IRTCTL); /* USCI A0 IrDA Transmit Control */SFR_8BIT(UCA0IRRCTL); /* USCI A0 IrDA Receive Control */SFR_8BIT(UCB0CTL0); /* USCI B0 Control Register 0 */SFR_8BIT(UCB0CTL1); /* USCI B0 Control Register 1 */SFR_8BIT(UCB0BR0); /* USCI B0 Baud Rate 0 */SFR_8BIT(UCB0BR1); /* USCI B0 Baud Rate 1 */SFR_8BIT(UCB0I2CIE); /* USCI B0 I2C Interrupt Enable Register */SFR_8BIT(UCB0STAT); /* USCI B0 Status Register */SFR_8BIT(UCB0RXBUF); /* USCI B0 Receive Buffer */SFR_8BIT(UCB0TXBUF); /* USCI B0 Transmit Buffer */SFR_16BIT(UCB0I2COA); /* USCI B0 I2C Own Address */SFR_16BIT(UCB0I2CSA); /* USCI B0 I2C Slave Address */// UART-Mode Bits#define UCPEN (0x80) /* Async. Mode: Parity enable */#define UCPAR (0x40) /* Async. Mode: Parity 0:odd / 1:even */#define UCMSB (0x20) /* Async. Mode: MSB first 0:LSB / 1:MSB */#define UC7BIT (0x10) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */#define UCSPB (0x08) /* Async. Mode: Stop Bits 0:one / 1: two */#define UCMODE1 (0x04) /* Async. Mode: USCI Mode 1 */#define UCMODE0 (0x02) /* Async. Mode: USCI Mode 0 */#define UCSYNC (0x01) /* Sync-Mode0:UART-Mode / 1:SPI-Mode */// SPI-Mode Bits#define UCCKPH (0x80) /* Sync. Mode: Clock Phase */#define UCCKPL (0x40) /* Sync. Mode: Clock Polarity */#define UCMST (0x08) /* Sync. Mode: Master Select */。

msp430g2553_UART

#include "msp430g2553.h"#include "UART.h"#include "N5110.h"#define TXRX_FIFO 1#define AddressUse 1#ifndef uchar#define uchar unsigned char#endif#ifndef uint#define uint unsigned int#endifuchar get_bug = 0;/****************************************************************延时***************************************************************/ void UART_delay(uint x){uint a, b;for(a=x; a>0; a--)for(b=110; b>0; b--);}/***************************************************************** *名称：UART_Set()*功能：UART串口设置*入口参数：baud: 波特率1200 2400 4800 9600(默认) 19200 38400 57600 * mctl: 波特率修整* data: 数据位，8：8位，7：7位，默认8位* jiouwei: 奇偶位，'n':无（默认）,'o':奇校验,'e':偶校验* stop: 停止位，2:2位停止位，其他均为默认的1位* R_T: 收发模式，1：收；2：发；3：收发*出口参数：无*使用范例：UART_Set(9600,2,8,'n',1,3)*****************************************************************/ void UART_Set(uint baud,uchar mctl,uchar data,char jiouwei,uchar stop,uchar R_T) {UCA0CTL1 |=UCSWRST; //软件复位if(baud<=9600){UCA0CTL1 |= UCSSEL_1; //ACLK}{UCA0CTL1 |= UCSSEL_2; //SMCLK}switch(baud){case 1200: UCA0BR0 = 0X1B;//1200波特率//波特率计算UCA0BR1 = 0X6B; //波特率=BRCLK/N=(UBR+(M7+M6+M5+M4+M3+M2+M1+M0)/8)break; //例如：BRCLK=8MHz，要产生BITCLK=115200Hz，分频器的分频系数为8000 / 115.2 =69.44444444case 2400: UCA0BR0 = 0X0D;//2400波特率//所以设置分频器的计数值为69。

ADXL-MSP430G2553

#ifndef ADXL_G2553_H_#define ADXL_G2553_H_#define WORD unsigned short#define uchar unsigned char#define uint unsigned int/*#define SCL_1 P1OUT|=BIT5 //IIC时钟引脚定义#define SCL_0 P1OUT&=~BIT5#define SCL_OUT P1DIR|=BIT5#define SDA P1IN&BIT4#define SDA_1 P1OUT|=BIT4 //IIC数据引脚定义#define SDA_0 P1OUT&=~BIT4#define SDA_IN P1DIR&=~BIT4#define SDA_OUT P1DIR|=BIT4*/#define SCL_1 P1OUT|=BIT0 //IIC时钟引脚定义#define SCL_0 P1OUT&=~BIT0#define SCL_OUT P1DIR|=BIT0#define SDA P1IN&BIT1#define SDA_1 P1OUT|=BIT1 //IIC数据引脚定义#define SDA_0 P1OUT&=~BIT1#define SDA_IN P1DIR&=~BIT1#define SDA_OUT P1DIR|=BIT1#define SlaveAddress 0xA6 //定义器件在IIC总线中的从地址,根据ALT ADDRESS地址引脚不同修改//ALT ADDRESS引脚接地时地址为0xA6，接电源时地址为0x3A//接收数据缓存区//====================器件宏定义======================#define DEVID 0xe5 //器件ID#define THRESH_TAP 0x1d //敲击阈值#define OFSX 0x1e //X轴偏移#define OFSY 0x1f //Y轴偏移#define OFSZ 0x20 //Z轴偏移#define DUR 0x21 //敲击持续时间#define Latent 0x22 //敲击延迟#define Window 0x23 //敲击窗口#define THRESH_ACT 0x24 //活动阈值#define THRESH_INACT 0x25 //静止阈值#define TIME_INACT 0x26 //静止时间#define ACT_INACT_CTL 0x27 //轴使能控制活动和静止检测#define THRESH_FF 0x28 //自由落体阈值#define TIME_FF 0x29 //自由落体时间#define TAP_AXES 0x2a //单击/双击轴控制#define ACT_TAP_STATUS 0x2b //单机/双击源#define BW_RATE 0x2c //数据速率及功率模式控制#define POWER_CTL 0x2d //省电特性控制#define INT_ENABLE 0x2e //中断使能控制#define INT_MAP 0x2f //中断映射控制#define INT_SOURCE 0x30 //中断源#define DATA_FORMATE 0x31 //数据格式控制#define DATAX0 0x32 //X轴数据-低八位#define DATAX1 0x33 //X轴数据-高八位#define DATAY0 0x34 //Y轴数据-低八位#define DATAY1 0x35 //Y轴数据-高八位#define DATAZ0 0x36 //Z轴数据-低八位#define DATAZ1 0x37 //Z轴数据-高八位#define FIFO_CTL 0x38 //FIFO控制#define FIFO_STATUS 0x39 //FIFO状态extern void first_Angle(void);extern void Angle(void);extern void display_Angle(void);extern void display_XYZ(void);extern void Init_ADXL345();extern void Multiple_Read_ADXL345(void);#endif /* ADXL_G2553_H_ */#include"msp430g2553.h"#include <math.h>#include"ADXL345-G2553.h"#include "HT1621IO.h"char BUF[8];uchar ge,shi,bai,qian,wan; //显示变量int data_xyz[3];void delay_ADXL345(unsigned int k);void Init_ADXL345(void); //初始化ADXL345void conversion(uint temp_data);void Single_Write_ADXL345(uchar REG_Address,uchar REG_data); //单个写入数据uchar Single_Read_ADXL345(uchar REG_Address); //单个读取内部寄存器数据void Multiple_Read_ADXL345(void); //连续的读取内部寄存器数据void Delay5us();void Delay5ms();void ADXL345_Start();void ADXL345_Stop();void ADXL345_SendACK(char ack);char ADXL345_RecvACK();void ADXL345_SendByte(char dat);char ADXL345_RecvByte();//void ADXL345_ReadPage();//void ADXL345_WritePage();//*********************************************************void conversion(uint temp_data){temp_data=temp_data%10000; //取余运算qian=temp_data/1000;temp_data=temp_data%1000; //取余运算bai=temp_data/100;temp_data=temp_data%100; //取余运算shi=temp_data/10;/* if(qian==1){bai=9;shi=9;}*/}/*******************************/void delay_ADXL345(unsigned int k){unsigned int i,j;for(i=0;i<k;i++){for(j=0;j<12;j++){;}}}/**************************************延时5微秒(STC90C52RC@12M)不同的工作环境,需要调整此函数，注意时钟过快时需要修改当改用1T的MCU时,请调整此延时函数**************************************/void Delay5us(){__delay_cycles(60);}/**************************************延时5毫秒(STC90C52RC@12M)不同的工作环境,需要调整此函数当改用1T的MCU时,请调整此延时函数**************************************/void Delay5ms(){__delay_cycles(6000);}/**************************************起始信号**************************************/ void ADXL345_Start(){SCL_OUT;SDA_OUT;SDA_1; //拉高数据线_NOP();SCL_1; //拉高时钟线Delay5us(); //延时SDA_0; //产生下降沿Delay5us(); //延时SCL_0; //拉低时钟线}/**************************************停止信号**************************************/ void ADXL345_Stop(){SDA_OUT;SDA_0; //拉低数据线_NOP();SCL_1; //拉高时钟线Delay5us(); //延时SDA_1; //产生上升沿Delay5us(); //延时}/**************************************发送应答信号入口参数:ack (0:ACK 1:NAK)**************************************/ void ADXL345_SendACK(char ack){SDA_OUT;if(ack)SDA_1;elseSDA_0;_NOP();SCL_1; //拉高时钟线Delay5us(); //延时SCL_0; //拉低时钟线// Delay5us(); //延时SDA_1;}/**************************************接收应答信号**************************************/char ADXL345_RecvACK(){char ack;SDA_IN;SCL_0; //拉高时钟线Delay5us(); //延时SCL_1;if(SDA)ack=0; //读应答信号elseack=1;SCL_0; //拉低时钟线Delay5us(); //延时SDA_OUT;return ack ;}/**************************************向IIC总线发送一个字节数据**************************************/void ADXL345_SendByte(char dat){char i;SDA_OUT;for (i=0; i<8; i++) //8位计数器{Delay5us(); //延时if((dat&0x80)==0x80) //发送数据的最高位{SDA_1;}else{SDA_0;}//送数据口_NOP();SCL_1; //拉高时钟线Delay5us(); //延时SCL_0; //拉低时钟线dat<<=1;}ADXL345_RecvACK();}/**************************************从IIC总线接收一个字节数据**************************************/char ADXL345_RecvByte(){char i;char dat = 0;SDA_IN;_NOP();for (i=0; i<8; i++) //8位计数器{dat <<= 1;SCL_1; //拉高时钟线Delay5us(); //延时if(SDA)dat++;SCL_0; //拉低时钟线Delay5us(); //延时}return dat;}//******单字节写入*******************************************void Single_Write_ADXL345(uchar REG_Address,uchar REG_data){ADXL345_Start(); //起始信号ADXL345_SendByte(SlaveAddress); //发送设备地址+写信号ADXL345_SendByte(REG_Address); //内部寄存器地址，请参考中文pdf22页ADXL345_SendByte(REG_data); //内部寄存器数据，请参考中文pdf22页ADXL345_Stop(); //发送停止信号}//********单字节读取*****************************************uchar Single_Read_ADXL345(uchar REG_Address){ uchar REG_data;ADXL345_Start(); //起始信号ADXL345_SendByte(SlaveAddress); //发送设备地址+写信号ADXL345_SendByte(REG_Address); //发送存储单元地址，从0开始ADXL345_Start(); //起始信号ADXL345_SendByte(SlaveAddress+1); //发送设备地址+读信号REG_data=ADXL345_RecvByte(); //读出寄存器数据ADXL345_SendACK(1);ADXL345_Stop(); //停止信号return REG_data;}//*********************************************************////连续读出ADXL345内部加速度数据，地址范围0x32~0x37////*********************************************************//*********************************************************************** void Multiple_Read_ADXL345(void){uchar i;ADXL345_Start(); //起始信号ADXL345_SendByte(SlaveAddress); //发送设备地址+写信号ADXL345_SendByte(0x32); //发送存储单元地址，从0x32开始ADXL345_Start(); //起始信号ADXL345_SendByte(SlaveAddress+1); //发送设备地址+读信号for (i=0; i<6; i++) //连续读取6个地址数据，存储中BUF {BUF[i] = ADXL345_RecvByte(); //BUF[0]存储0x32地址中的数据if (i == 5){ADXL345_SendACK(1); //最后一个数据需要回NOACK }else{ADXL345_SendACK(0); //回应ACK}}ADXL345_Stop(); //停止信号Delay5ms();}//*****************************************************************//初始化ADXL345，根据需要请参考pdf进行修改************************void Init_ADXL345(){Single_Write_ADXL345(0x31,0x0B); //测量范围,正负16g，13位模式。

MSP430G2553学习笔记(数据手册)

MSP430G2553学习笔记(数据手册）MSP430G2553性能参数(DIP—20) 工作电压范围:1.8～3。

6V。

5种低功耗模式。

16位的RISC结构，62。

5ns指令周期.超低功耗：运行模式—230µA；待机模式—0.5µA；关闭模式—0.1µA；可以在不到1µs的时间里超快速地从待机模式唤醒.基本时钟模块配置：具有四种校准频率并高达16MHz的内部频率;内部超低功耗LF振荡器；32。

768KHz晶体；外部数字时钟源。

两个16 位Timer_A,分别具有三个捕获/比较寄存器。

用于模拟信号比较功能或者斜率模数（A/D)转换的片载比较器。

带内部基准、采样与保持以及自动扫描功能的10位200—ksps 模数(A/D）转换器。

16KB闪存,512B的RAM。

16个I/O口。

注意：MSP430G2553无P3口！MSP430G2553的时钟基本时钟系统的寄存器DCOCTL—DCO控制寄存器DCOxDCO频率选择控制1MODxDCO频率校正选择,通常令MODx=0注意：在MSP430G2553上电复位后，默认RSEL=7,DCO=3，通过数据手册查得DCO频率大概在0.8～1。

5MHz之间。

BCSCTL1—基本时钟控制寄存器1XT2OFF不用管，因为MSP430G2553内部没有XT2提供的HF时钟XTS不用管,默认复位后的0值即可DIV Ax设置ACLK的分频数00 /101 /210 /411 /8RSELxDCO频率选择控制2BCSCTL2-基本时钟控制寄存器2SELMxMCLK的选择控制位00 DCOCLK01 DCOCLK10 LFXT1CLK或者VLOCLK11 LFXT1CLK或者VLOCLK DIVMx设置MCLK的分频数00 /101 /210 /411 /8SELSSMCLK的选择控制位0 DCOCLK1 LFXT1CLK或者VLOCLK DIVSx设置SMCLK的分频数00 /101 /210 /411 /8DCORDCO直流发生电阻选择,此位一般设00 内部电阻1 外部电阻BCSCTL3—基本时钟控制寄存器3XT2Sx不用管LFXT1Sx00 LFXT1选为32。

MSP430G2553单片机的中断使用格式

端口1中断函数多中断中断源：P1IFG.0~P1IFG7进入中断后应首先判断中断源，退出中断前应清除中断标志，否则将再次引发中断#pragma vector=PORT1_VECTOR__interrupt void Port1(){ //以下为参考处理程序，不使用的端口应当删除其对于中断源的判断。

if((P1IFG&BIT0) == BIT0){ //处理P1IN.0中断P1IFG &= ~BIT0; //清除中断标志//以下填充用户代码}else if((P1IFG&BIT1) ==BIT1){//处理P1IN.1中断P1IFG &= ~BIT1; //清除中断标志//以下填充用户代码}else if((P1IFG&BIT2) ==BIT2){//处理P1IN.2中断P1IFG &= ~BIT2; //清除中断标志//以下填充用户代码}else if((P1IFG&BIT3) ==BIT3){//处理P1IN.3中断P1IFG &= ~BIT3; //清除中断标志//以下填充用户代码}else if((P1IFG&BIT4) ==BIT4){//处理P1IN.4中断P1IFG &= ~BIT4; //清除中断标志//以下填充用户代码}else if((P1IFG&BIT5) ==BIT5){//处理P1IN.5中断P1IFG &= ~BIT5; //清除中断标志//以下填充用户代码}else if((P1IFG&BIT6) ==BIT6){//处理P1IN.6中断P1IFG &= ~BIT6; //清除中断标志//以下填充用户代码}else{//处理P1IN.7中断P1IFG &= ~BIT7; //清除中断标志//以下填充用户代码}}端口2中断函数多中断中断源：P2IFG.0~P2IFG7进入中断后应首先判断中断源，退出中断前应清除中断标志，否则将再次引发中断*****************************************************************************/ #pragma vector=PORT2_VECTOR__interrupt void Port2(){//以下为参考处理程序，不使用的端口应当删除其对于中断源的判if((P2IFG&BIT0) == BIT0){//处理P2IN.0中断P2IFG &= ~BIT0; //清除中断标志//以下填充用户代码}else if((P2IFG&BIT1) ==BIT1){//处理P2IN.1中断P2IFG &= ~BIT1; //清除中断标志//以下填充用户代码 }else if((P2IFG&BIT2) ==BIT2){//处理P2IN.2中断 P2IFG &= ~BIT2; //清除中断标志//以下填充用户代码 }else if((P2IFG&BIT3) ==BIT3){//处理P2IN.3中断 P2IFG &= ~BIT3; //清除中断标志//以下填充用户代码}else if((P2IFG&BIT4) ==BIT4){//处理P2IN.4中断P2IFG &= ~BIT4; //清除中断标志//以下填充用户代码 }else if((P2IFG&BIT5) ==BIT5){//处理P2IN.5中断P2IFG &= ~BIT5; //清除中断标志//以下填充用户代码}else if((P2IFG&BIT6) ==BIT6){//处理P2IN.6中断P2IFG &= ~BIT6; //清除中断标志//以下填充用户代码}else{//处理P2IN.7中断P2IFG &= ~BIT7; //清除中断标志//以下填充用户代码}}USART0发送中断函数******************************************************************************/ #pragma vector=USART0TX_VECTOR__interrupt void Usart0Tx(){//以下填充用户代码}USART0接收中断函数******************************************************************************/ #pragma vector=USART0RX_VECTOR__interrupt void Usart0Rx(){//以下填充用户代码}USART1发送中断函数******************************************************************************/ #pragma vector=USART1TX_VECTOR__interrupt void Usart1Tx(){//以下填充用户代码}SART1接收中断函数******************************************************************************/ #pragma vector=USART1RX_VECTOR__interrupt void Ustra1Rx(){//以下填充用户代码}基本定时器中断函数******************************************************************************/ #pragma vector=BASICTIMER_VECTOR__interrupt void BasTimer(){//以下填充用户代码}定时器A中断函数多中断中断源：CC1~2 TA******************************************************************************/#pragma vector=TIMER0_A1_VECTOR__interrupt void TimerA1(){//以下为参考处理程序，不使用的中断源应当删除switch (__even_in_range(TAIV, 10)){case 2: //捕获/比较1中断//以下填充用户代码break;case 4: //捕获/比较2中断//以下填充用户代码break;case 10: //TAIFG定时器溢出中断//以下填充用户代码break;}}定时器A中断函数中断源：CC0******************************************************************************/ #pragma vector=TIMERA0_VECTOR__interrupt void TimerA0(){//以下填充用户代码}多中断源：CC1~6 TB******************************************************************************/ #pragma vector=TIMERB1_VECTOR__interrupt void TimerB1(){//以下为参考处理程序，不使用的中断源应当删除switch (__even_in_range(TBIV, 14)){case 2: //捕获/比较1中断//以下填充用户代码break;case 4: //捕获/比较2中断//以下填充用户代码break;case 6: //捕获/比较3中断//以下填充用户代码break;case 8: //捕获/比较4中断//以下填充用户代码break;case 10: //捕获/比较5中断//以下填充用户代码break;case 12: / /捕获/比较6中断//以下填充用户代码break;case 14: //TBIFG定时器溢出中断//以下填充用户代码break;}}中断源：CC0******************************************************************************/ #pragma vector=TIMERB0_VECTOR__interrupt void TimerB0(){//以下填充用户代码}AD转换器中断函数多中断源：摸拟0~7、VeREF+、VREF-/VeREF-、（AVcc-AVss）/2 没有处理ADC12TOV和ADC12OV中断标志******************************************************************************/ #pragma vector=ADC_VECTOR__interrupt void Adc(){//以下为参考处理程序，不使用的中断源应当删除if((ADC12IFG&BIT0)==BIT0){ //通道0//以下填充用户代码}else if((ADC12IFG&BIT1)==BIT1){ //通道1//以下填充用户代码}else if((ADC12IFG&BIT2)==BIT2){ //通道2//以下填充用户代码}else if((ADC12IFG&BIT3)==BIT3){ //通道3//以下填充用户代码}else if((ADC12IFG&BIT4)==BIT4){ //通道4//以下填充用户代码}else if((ADC12IFG&BIT5)==BIT5){ //通道5//以下填充用户代码}else if((ADC12IFG&BIT6)==BIT6){ //通道6//以下填充用户代码}else if((ADC12IFG&BIT7)==BIT7){ //通道7//以下填充用户代码 }else if((ADC12IFG&BIT8)==BIT8){ //VeREF+//以下填充用户代码 }else if((ADC12IFG&BIT9)==BIT9){ //VREF-/VeREF-//以下填充用户代码}else if((ADC12IFG&BITA)==BITA){ //温度//以下填充用户代码}else if((ADC12IFG&BITB)==BITB){ //（A Vcc-A Vss）/2//以下填充用户代码}}看门狗定时器中断函数******************************************************************************/ #pragma vector=WDT_VECTOR__interrupt void WatchDog(){//以下填充用户代码}比较器A中断函数******************************************************************************/ #pragma vector=COMPARA TORA_VECTOR__interrupt void ComparatorA(){//以下填充用户代码}不可屏蔽中断函数******************************************************************************/ #pragma vector=NMI_VECTOR__interrupt void Nmi(){//以下为参考处理程序，不使用的中断源应当删除if((IFG1&OFIFG)==OFIFG){ //振荡器失效IFG1 &= ~OFIFG;//以下填充用户代码}else if((IFG1&NMIIFG)==NMIIFG){ //RST/NMI不可屏蔽中断IFG1 &= ~NMIIFG;//以下填充用户代码}else //if((FCTL3&ACCVIFG)==ACCVIFG){ //存储器非法访问FCTL3 &= ~ACCVIFG;//以下填充用户代码}}中断优先级：优先级顺序从高到低为：PORT2_VECTOR (1 * 2u) /* 0xFFE2 Port 2 */PORT1_VECTOR (4 * 2u) /* 0xFFE8 Port 1 */TIMER0_A1_VECTOR (5 * 2u) /* 0xFFEA Timer A CC1-2, TA */TIMER0_A0_VECTOR (6 * 2u) /* 0xFFEC Timer A CC0 */ADC_VECTOR (7 * 2u) /* 0xFFEE ADC */USART0TX_VECTOR (8 * 2u) /* 0xFFF0 USART 0 Transmit */USART0RX_VECTOR (9 * 2u) /* 0xFFF2 USART 0 Receive */WDT_VECTOR (10 * 2u) /* 0xFFF4 Watchdog Timer */ COMPARATORA_VECTOR (11 * 2u) /* 0xFFF6 Comparator A */TIMERB1_VECTOR (12 * 2u) /* 0xFFF8 Timer B CC1-2, TB */TIMERB0_VECTOR (13 * 2u) /* 0xFFFA Timer B CC0 */NMI_VECTOR (14 * 2u) /* 0xFFFC Non-maska××e */RESET_VECTOR (15 * 2u) /* 0xFFFE Reset [Highest Priority] */。

基本时钟模块_MSP430G2553

基本时钟模块_MSP430G2553G2xxx系列DCO校准数据（校正寄存器）1MHz：CALBC1_1MHZCALDCO_1MHZ8MHz：CALBC1_8MHZCALDCO_8MHZ12MHz：CALBC1_12MHZCALDCO_12MHZ16MHz：CALBC1_16MHZCALDCO_16MHZ例：设置DCO频率为1MHzif(CALBC1_1MHZ==0xFF || CALDCO_1MHZ==0xFF)while(1);//校准数据是否被擦除，若是则CPU挂起。

BCSCTL1 = CALBC1_1MHZ;DCOCTL = CALDCO_1MHZ;基本时钟模块寄存器寄存器缩写形式类型初始状态DCO控制寄存器DCOCTL 读/写0x60（PUC）基本时钟系统控制器1 BCSCTL1 读/写0x87（POR）基本时钟系统控制器2 BCSCTL2 读/写由PUC复位基本时钟系统控制器3 BCSCTL3 读/写0x05（PUC）中断使能寄存器（特殊功能寄存器）IE1 读/写由PUC复位中断标致寄存器（特殊功能寄存器）IFG1 读/写由PUC复位说明：DCO的频率可以通过软件设定DCOx、MODx、RSELx相应位来调整，DCO频率是通过将f DCO和f DCO+1混频得到。

1、DCOCTL：DCO控制寄存器7 6 5 4 3 2 1 0DCOx MODxrw-0 rw-1 rw-1 rw-0 rw-0 rw-0 rw-0 rw-0 DCOx：DCO频率范围选择位，这些位可以用来在由RESLx设置决定的8个离散的频率范围中选择哪一个。

MODx：调制系数选择位，这些位用来决定在32个DCO时钟周期中f DCO+1占多少个，f DCO 占多少个。

注意：当MODx=0时调制器关闭，DCOx=7时，由于此时没有下一个更高的频率范围f DCO+1可用，因此MODx无效不可用。

2、BCSCTL1：基本时钟系统控制寄存器17 6 5 4 3 2 1 0 XT2OFF XTS(1)(2)DIVAx RSELxrw-(1) rw-(0) rw-(0) rw-(0) rw-0 rw-1 rw-1 rw-1 XT2OFF：第二晶振XT2(可选高频晶振)关闭控制位。

mps430G2553中文资料

时钟
I/O 封装类型
16
512 2x TA3
8
8
512 2x TA3
8
4
256 2x TA3
8
2
256 2x TA3
8
1
256 2x TA3
8
24
32 引脚 QFN 封装
28 引脚
24 TSSOP 封
LF，
装
-
1
DCO，
VLO
20 引脚
16 TSSOP 封
装
16
20 引脚 PDIP 封装
24
32 引脚 QFN 封装
引导加载器 (BSL)
嵌入式仿真模
块 (EEM)
1
1
1
1
1
1
1
1
1
1
表 1. 提供的选项(1)(2) (接下页)
ZHCS178E – APRIL 2011 – REVISED JANUARY 2012
闪存 (KB)
RAM (B)
Timer_A
COMP_A+ 通道
10 通道 ADC
USCI A0/B0
典型应用包括低成本传感器系统，此类系统负责捕获模拟信号、将之转换为数字值、随后对数据进行处理以进行显示或传送至主机系统。
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

MSP430G2553寄存器的中文注释

MSP430寄存器中文注释---P1/2口（带中断功能）/************************************************************ * DIGITAL I/O Port1/2 寄存器定义有中断功能************************************************************/ #define P1IN_ 0x0020 /* P1 输入寄存器 */const sfrb P1IN = P1IN_;#define P1OUT_ 0x0021/* P1 输出寄存器 */ sfrb P1OUT = P1OUT_;#define P1DIR_ 0x0022 /* P1 方向选择寄存器 */sfrb P1DIR = P1DIR_;#define P1IFG_ 0x0023 /* P1 中断标志寄存器*/sfrb P1IFG = P1IFG_;#define P1IES_ 0x0024 /* P1 中断边沿选择寄存器*/ sfrb P1IES = P1IES_;#define P1IE_ 0x0025 /* P1 中断使能寄存器 */sfrb P1IE = P1IE_;#define P1SEL_ 0x0026 /* P1 功能选择寄存器*/sfrb P1SEL = P1SEL_;#define P2IN_ 0x0028 /* P2 输入寄存器 */const sfrb P2IN = P2IN_;#define P2OUT_ 0x0029 /* P2 输出寄存器*/sfrb P2OUT = P2OUT_;#define P2DIR_ 0x002A /* P2 方向选择寄存器*/ sfrb P2DIR = P2DIR_;#define P2IFG_ 0x002B /* P2 中断标志寄存器 */sfrb P2IFG = P2IFG_;#define P2IES_ 0x002C /* P2 中断边沿选择寄存器 */ sfrb P2IES = P2IES_;#define P2IE_ 0x002D /* P2 中断使能寄存器 */sfrb P2IE = P2IE_;#define P2SEL_ 0x002E /* P2 功能选择寄存器 */sfrb P2SEL = P2SEL_;MSP430寄存器中文注释---P3/4口（无中断功能）/************************************************************* DIGITAL I/O Port3/4寄存器定义无中断功能************************************************************/#define P3IN_ 0x0018 /* P3 输入寄存器 */const sfrb P3IN = P3IN_;#define P3OUT_ 0x0019 /* P3 输出寄存器 */sfrb P3OUT = P3OUT_;#define P3DIR_ 0x001A /* P3 方向选择寄存器 */sfrb P3DIR = P3DIR_;#define P3SEL_ 0x001B /* P3 功能选择寄存器*/sfrb P3SEL = P3SEL_;#define P4IN_ 0x001C /* P4 输入寄存器 */const sfrb P4IN = P4IN_;#define P4OUT_ 0x001D /* P4 输出寄存器 */sfrb P4OUT = P4OUT_;#define P4DIR_ 0x001E /* P4 方向选择寄存器 */sfrb P4DIR = P4DIR_;#define P4SEL_ 0x001F /* P4 功能选择寄存器 */sfrb P4SEL = P4SEL_;/************************************************************* DIGITAL I/O Port5/6 I/O口寄存器定义PORT5和6 无中断功能************************************************************/#define P5IN_ 0x0030 /* P5 输入寄存器 */const sfrb P5IN = P5IN_;#define P5OUT_ 0x0031 /* P5 输出寄存器*/sfrb P5OUT = P5OUT_;#define P5DIR_ 0x0032 /* P5 方向选择寄存器*/ sfrb P5DIR = P5DIR_;#define P5SEL_ 0x0033 /* P5 功能选择寄存器*/ sfrb P5SEL = P5SEL_;#define P6IN_ 0x0034 /* P6 输入寄存器 */const sfrb P6IN = P6IN_;#define P6OUT_ 0x0035 /* P6 输出寄存器*/sfrb P6OUT = P6OUT_;#define P6DIR_ 0x0036 /* P6 方向选择寄存器*/ sfrb P6DIR = P6DIR_;#define P6SEL_ 0x0037 /* P6 功能选择寄存器*/ sfrb P6SEL = P6SEL_;MSP430寄存器中文注释--- 硬件乘法器/************************************************************硬件乘法器的寄存器定义************************************************************/ #define MPY_ 0x0130 /* 无符号乘法 */sfrw MPY = MPY_;#define MPYS_ 0x0132 /* 有符号乘法*/sfrw MPYS = MPYS_;#define MAC_ 0x0134 /* 无符号乘加 */sfrw MAC = MAC_;#define MACS_ 0x0136 /* 有符号乘加 */sfrw MACS = MACS_;#define OP2_ 0x0138 /* 第二乘数 */sfrw OP2 = OP2_;#define RESLO_ 0x013A /* 低6位结果寄存器 */sfrw RESLO = RESLO_;#define RESHI_ 0x013C /* 高6位结果寄存器 */sfrw RESHI = RESHI_;#define SUMEXT_ 0x013E /*结果扩展寄存器*/const sfrw SUMEXT = SUMEXT_;MSP430寄存器中文注释---看门狗和定时器/************************************************************* 看门狗定时器的寄存器定义************************************************************/#define WDTCTL_ 0x0120sfrw WDTCTL = WDTCTL_;#define WDTIS0 0x0001 /*选择WDTCNT的四个输出端之一*/#define WDTIS1 0x0002 /*选择WDTCNT的四个输出端之一*/#define WDTSSEL 0x0004 /*选择WDTCNT的时钟源*/#define WDTCNTCL 0x0008 /*清除WDTCNT端: 为1时从0开始计数*/#define WDTTMSEL 0x0010 /*选择模式0: 看门狗模式; 1: 定时器模式*/#define WDTNMI 0x0020 /*选择NMI/RST 引脚功能 0:为 RST; 1:为NMI*/#define WDTNMIES 0x0040 /*WDTNMI=1时.选择触发延 0:为上升延 1:为下降延*/ #define WDTHOLD 0x0080 /*停止看门狗定时器工作 0:启动;1:停止*/#define WDTPW 0x5A00 /* 写密码:高八位*//* SMCLK= 1MHz定时器模式 */#define WDT_MDLY_32 WDTPW+WDTTMSEL+WDTCNTCL /*TSMCLK*2POWER15=32ms 复位状态 */#define WDT_MDLY_8 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0 /*TSMCLK*2POWER13=8.192ms " */#define WDT_MDLY_0_5 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1 /*TSMCLK*2POWER9=0.512ms " */#define WDT_MDLY_0_064 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0 /*TSMCLK*2POWER6=0.512ms " *//* ACLK=32.768KHz 定时器模式*/#define WDT_ADLY_1000 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL /* TACLK*2POWER15=1000ms " */#define WDT_ADLY_250 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0 /* TACLK*2POWER13=250ms " */#define WDT_ADLY_16 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1 /* TACLK*2POWER9=16ms " */#define WDT_ADLY_1_9 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 /* TACLK*2POWER6=1.9ms " *//* SMCLK=1MHz看门狗模式 */#define WDT_MRST_32 WDTPW+WDTCNTCL /* TSMCLK*2POWER15=32ms 复位状态*/#define WDT_MRST_8 WDTPW+WDTCNTCL+WDTIS0 /* TSMCLK*2POWER13=8.192ms " */#define WDT_MRST_0_5 WDTPW+WDTCNTCL+WDTIS1 /* TSMCLK*2POWER9=0.512ms " */#define WDT_MRST_0_064 WDTPW+WDTCNTCL+WDTIS1+WDTIS0 /* TSMCLK*2POWER6=0.512ms " *//* ACLK=32KHz看门狗模式 */#define WDT_ARST_1000 WDTPW+WDTCNTCL+WDTSSEL /* TACLK*2POWER15=1000ms " */#define WDT_ARST_250 WDTPW+WDTCNTCL+WDTSSEL+WDTIS0 /* TACLK*2POWER13=250ms " */#define WDT_ARST_16 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1 /* TACLK*2POWER9=16ms " */#define WDT_ARST_1_9 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 /* TACLK*2POWER6=1.9ms " */MSP430寄存器中文注释---A/D采样寄存器定义/************************************************************* ADC12 A/D采样寄存器定义************************************************************//*ADC12转换控制类寄存器*/#define ADC12CTL0_ 0x0;' /* ADC12 Control 0 */sfrw ADC12CTL0 = ADC12CTL0_;#define ADC12CTL1_ 0x01A2 /* ADC12 Control 1 */sfrw ADC12CTL1 = ADC12CTL1_;/*ADC12中断控制类寄存器*/#define ADC12IFG_ 0x01A4 /* ADC12 Interrupt Flag */sfrw ADC12IFG = ADC12IFG_;#define ADC12IE_ 0x01A6 /* ADC12 Interrupt Enable */sfrw ADC12IE = ADC12IE_;#define ADC12IV_ 0x01A8 /* ADC12 Interrupt Vector Word */sfrw ADC12IV = ADC12IV_;/*ADC12存贮器类寄存器*/#define ADC12MEM_ 0x0140 /* ADC12 Conversion Memory */#ifndef __IAR_SYSTEMS_ICC#define ADC12MEM ADC12MEM_ /* ADC12 Conversion Memory (for assembler) */ #else#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */ #endif#define ADC12MEM0_ ADC12MEM_ /* ADC12 Conversion Memory 0 */sfrw ADC12MEM0 = ADC12MEM0_;#define ADC12MEM1_ 0x0142 /* ADC12 Conversion Memory 1 */sfrw ADC12MEM1 = ADC12MEM1_;#define ADC12MEM2_ 0x0144 /* ADC12 Conversion Memory 2 */sfrw ADC12MEM2 = ADC12MEM2_;#define ADC12MEM3_ 0x0146 /* ADC12 Conversion Memory 3 */sfrw ADC12MEM3 = ADC12MEM3_;#define ADC12MEM4_ 0x0148 /* ADC12 Conversion Memory 4 */sfrw ADC12MEM4 = ADC12MEM4_;#define ADC12MEM5_ 0x014A /* ADC12 Conversion Memory 5 */sfrw ADC12MEM5 = ADC12MEM5_;#define ADC12MEM6_ 0x014C /* ADC12 Conversion Memory 6 */sfrw ADC12MEM6 = ADC12MEM6_;#define ADC12MEM7_ 0x014E /* ADC12 Conversion Memory 7 */sfrw ADC12MEM7 = ADC12MEM7_;#define ADC12MEM8_ 0x0150 /* ADC12 Conversion Memory 8 */sfrw ADC12MEM8 = ADC12MEM8_;#define ADC12MEM9_ 0x0152 /* ADC12 Conversion Memory 9 */sfrw ADC12MEM9 = ADC12MEM9_;#define ADC12MEM10_ 0x0154 /* ADC12 Conversion Memory 10 */sfrw ADC12MEM10 = ADC12MEM10_;#define ADC12MEM11_ 0x0156 /* ADC12 Conversion Memory 11 */sfrw ADC12MEM11 = ADC12MEM11_;#define ADC12MEM12_ 0x0158 /* ADC12 Conversion Memory 12 */sfrw ADC12MEM12 = ADC12MEM12_;#define ADC12MEM13_ 0x015A /* ADC12 Conversion Memory 13 */sfrw ADC12MEM13 = ADC12MEM13_;#define ADC12MEM14_ 0x015C /* ADC12 Conversion Memory 14 */sfrw ADC12MEM14 = ADC12MEM14_;#define ADC12MEM15_ 0x015E /* ADC12 Conversion Memory 15 */sfrw ADC12MEM15 = ADC12MEM15_;/*ADC12存贮控制类寄存器*/#define ADC12MCTL_ 0x0080 /* ADC12 Memory Control */#ifndef __IAR_SYSTEMS_ICC#define ADC12MCTL ADC12MCTL_ /* ADC12 Memory Control (for assembler) */#else#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */ #endif#define ADC12MCTL0_ ADC12MCTL_ /* ADC12 Memory Control 0 */sfrb ADC12MCTL0 = ADC12MCTL0_;#define ADC12MCTL1_ 0x0081 /* ADC12 Memory Control 1 */sfrb ADC12MCTL1 = ADC12MCTL1_;#define ADC12MCTL2_ 0x0082 /* ADC12 Memory Control 2 */sfrb ADC12MCTL2 = ADC12MCTL2_;#define ADC12MCTL3_ 0x0083 /* ADC12 Memory Control 3 */sfrb ADC12MCTL3 = ADC12MCTL3_;#define ADC12MCTL4_ 0x0084 /* ADC12 Memory Control 4 */sfrb ADC12MCTL4 = ADC12MCTL4_;#define ADC12MCTL5_ 0x0085 /* ADC12 Memory Control 5 */sfrb ADC12MCTL5 = ADC12MCTL5_;#define ADC12MCTL6_ 0x0086 /* ADC12 Memory Control 6 */sfrb ADC12MCTL6 = ADC12MCTL6_;#define ADC12MCTL7_ 0x0087 /* ADC12 Memory Control 7 */sfrb ADC12MCTL7 = ADC12MCTL7_;#define ADC12MCTL8_ 0x0088 /* ADC12 Memory Control 8 */sfrb ADC12MCTL8 = ADC12MCTL8_;#define ADC12MCTL9_ 0x0089 /* ADC12 Memory Control 9 */sfrb ADC12MCTL9 = ADC12MCTL9_;#define ADC12MCTL10_ 0x008A /* ADC12 Memory Control 10 */sfrb ADC12MCTL10 = ADC12MCTL10_;#define ADC12MCTL11_ 0x008B /* ADC12 Memory Control 11 */sfrb ADC12MCTL11 = ADC12MCTL11_;#define ADC12MCTL12_ 0x008C /* ADC12 Memory Control 12 */sfrb ADC12MCTL12 = ADC12MCTL12_;#define ADC12MCTL13_ 0x008D /* ADC12 Memory Control 13 */sfrb ADC12MCTL13 = ADC12MCTL13_;#define ADC12MCTL14_ 0x008E /* ADC12 Memory Control 14 */sfrb ADC12MCTL14 = ADC12MCTL14_;#define ADC12MCTL15_ 0x008F /* ADC12 Memory Control 15 */sfrb ADC12MCTL15 = ADC12MCTL15_;/* ADC12CTL0 内8位控制寄存器位*/#define ADC12SC 0x001 /*采样/转换控制位*/#define ENC 0x002 /* 转换允许位*/#define ADC12TOVIE 0x004 /*转换时间溢出中断允许位*/#define ADC12OVIE 0x008 /*溢出中断允许位*/#define ADC12ON 0x010 /*ADC12内核控制位*/#define REFON 0x020 /*参考电压控制位*/#define REF2_5V 0x040 /*内部参考电压的电压值选择位 '0'为1.5V; '1'为2.5V*/ #define MSH 0x080 /*多次采样/转换位*/#define MSC 0x080 /*多次采样/转换位*//*SHT0 采样保持定时器0 控制ADC12的结果存贮器MEM0~MEM7的采样周期*/#define SHT0_0 0*0x100 /*采样周期=TADC12CLK*4 */#define SHT0_1 1*0x100 /*采样周期=TADC12CLK*8 */#define SHT0_2 2*0x100 /*采样周期=TADC12CLK*16 */#define SHT0_3 3*0x100 /*采样周期=TADC12CLK*32 */#define SHT0_4 4*0x100 /*采样周期=TADC12CLK*64 */#define SHT0_5 5*0x100 /*采样周期=TADC12CLK*96 */#define SHT0_6 6*0x100 /*采样周期=TADC12CLK*128 */#define SHT0_7 7*0x100 /*采样周期=TADC12CLK*192 */#define SHT0_8 8*0x100 /*采样周期=TADC12CLK*256 */#define SHT0_9 9*0x100 /*采样周期=TADC12CLK*384 */#define SHT0_10 10*0x100 /*采样周期=TADC12CLK*512 */#define SHT0_11 11*0x100 /*采样周期=TADC12CLK*768 */#define SHT0_12 12*0x100 /*采样周期=TADC12CLK*1024 */#define SHT0_13 13*0x100 /*采样周期=TADC12CLK*1024 */ #define SHT0_14 14*0x100 /*采样周期=TADC12CLK*1024*/ #define SHT0_15 15*0x100 /*采样周期=TADC12CLK*1024 */ /*SHT1 采样保持定时器1 控制ADC12的结果存贮器MEM8~MEM15的采样周期*/#define SHT1_0 0*0x100 /*采样周期=TADC12CLK*4 */#define SHT1_1 1*0x100 /*采样周期=TADC12CLK*8 */#define SHT1_2 2*0x100 /*采样周期=TADC12CLK*16 */#define SHT1_3 3*0x100 /*采样周期=TADC12CLK*32 */#define SHT1_4 4*0x100 /*采样周期=TADC12CLK*64 */#define SHT1_5 5*0x100 /*采样周期=TADC12CLK*96 */#define SHT1_6 6*0x100 /*采样周期=TADC12CLK*128 */ #define SHT1_7 7*0x100 /*采样周期=TADC12CLK*192 */ #define SHT1_8 8*0x100 /*采样周期=TADC12CLK*256 */ #define SHT1_9 9*0x100 /*采样周期=TADC12CLK*384 */ #define SHT1_10 10*0x100 /*采样周期=TADC12CLK*512 */ #define SHT1_11 11*0x100 /*采样周期=TADC12CLK*768 */ #define SHT1_12 12*0x100 /*采样周期=TADC12CLK*1024 */ #define SHT1_13 13*0x100 /*采样周期=TADC12CLK*1024 */ #define SHT1_14 14*0x100 /*采样周期=TADC12CLK*1024 */ #define SHT1_15 15*0x100 /*采样周期=TADC12CLK*1024 *//* ADC12CTL1 内8位控制寄存器位*/#define ADC12BUSY 0x0001 /*ADC12忙标志位*/#define CONSEQ_0 0*2 /*单通道单次转换*/#define CONSEQ_1 1*2 /*序列通道单次转换*/#define CONSEQ_2 2*2 /*单通道多次转换*/#define CONSEQ_3 3*2 /*序列通道多次转换*/#define ADC12SSEL_0 0*8 /*ADC12内部时钟源*/#define ADC12SSEL_1 1*8 /*ACLK*/#define ADC12SSEL_2 2*8 /*MCLK*/#define ADC12SSEL_3 3*8 /*SCLK*/#define ADC12DIV_0 0*0x20 /*1分频*/#define ADC12DIV_1 1*0x20 /*2分频*/#define ADC12DIV_2 2*0x20 /*3分频*/#define ADC12DIV_3 3*0x20 /*4分频*/#define ADC12DIV_4 4*0x20 /*5分频*/#define ADC12DIV_5 5*0x20 /*6分频*/#define ADC12DIV_6 6*0x20 /*7分频*/#define ADC12DIV_7 7*0x20 /*8分频*/#define ISSH 0x0100 /*采样输入信号反向与否控制位*/#define SHP 0x0200 /*采样信号(SAMPCON)选择控制位*/#define SHS_0 0*0x400 /*采样信号输入源选择控制位 ADC12SC*/#define SHS_1 1*0x400 /*采样信号输入源选择控制位 TIMER_A.OUT1*/ #define SHS_2 2*0x400 /*采样信号输入源选择控制位 TIMER_B.OUT0*/ #define SHS_3 3*0x400 /*采样信号输入源选择控制位 TIMER_B.OUT1*/ /*转换存贮器地址定义位*/#define CSTARTADD_0 0*0x1000 /*选择MEM0首地址*/#define CSTARTADD_1 1*0x1000 /*选择MEM1首地址*/#define CSTARTADD_2 2*0x1000 /*选择MEM2首地址*/#define CSTARTADD_3 3*0x1000 /*选择MEM3首地址*/#define CSTARTADD_4 4*0x1000 /*选择MEM4首地址*/#define CSTARTADD_5 5*0x1000 /*选择MEM5首地址*/#define CSTARTADD_6 6*0x1000 /*选择MEM6首地址*/#define CSTARTADD_7 7*0x1000 /*选择MEM7首地址*/#define CSTARTADD_8 8*0x1000 /*选择MEM8首地址*/#define CSTARTADD_9 9*0x1000 /*选择MEM9首地址*/#define CSTARTADD_10 10*0x1000 /*选择MEM10首地址*/#define CSTARTADD_11 11*0x1000 /*选择MEM11首地址*/#define CSTARTADD_12 12*0x1000 /*选择MEM12首地址*/#define CSTARTADD_13 13*0x1000 /*选择MEM13首地址*/#define CSTARTADD_14 14*0x1000 /*选择MEM14首地址*/#define CSTARTADD_15 15*0x1000 /*选择MEM15首地址*//* ADC12MCTLx */#define INCH_0 0 /*选择模拟量通道0 A0 */#define INCH_1 1 /*选择模拟量通道0 A1*/#define INCH_2 2 /*选择模拟量通道0 A2*/#define INCH_3 3 /*选择模拟量通道0 A3*/#define INCH_4 4 /*选择模拟量通道0 A4*/#define INCH_5 5 /*选择模拟量通道0 A5*/#define INCH_6 6 /*选择模拟量通道0 A6*/#define INCH_7 7 /*选择模拟量通道0 A7*/#define INCH_8 8 /*VEREF+*/#define INCH_9 9 /*VEREF-*/#define INCH_10 10 /*片内温度传感器的输出*/#define INCH_11 11 /*(AVCC-AVSS)/2*/#define INCH_12 12 /*(AVCC-AVSS)/2*/#define INCH_13 13 /*(AVCC-AVSS)/2*/#define INCH_14 14 /*(AVCC-AVSS)/2*/#define INCH_15 15 /*(AVCC-AVSS)/2*//*参考电压源选择位*/#define SREF_0 0*0x10 /*VR+ = AVCC; VR- = AVSS*/#define SREF_1 1*0x10 /*VR+ = VREF+; VR- = AVSS*/ #define SREF_2 2*0x10 /*VR+ = VEREF+; VR- = AVSS*/ #define SREF_3 3*0x10 /*VR+ = VEREF+; VR- = AVSS*/ #define SREF_4 4*0x10 /*VR+ = AVCC; VR- = VREF-*/ #define SREF_5 5*0x10 /*VR+ = VREF+; VR- = VREF-*/ #define SREF_6 6*0x10 /*VR+ = VEREF+; VR- = VREF-*/ #define SREF_7 7*0x10 /*VR+ = VEREF+; VR- = VREF-*/#define EOS 0x80 /*序列结束选择位*/MSP430寄存器中文注释----串口寄存器/************************************************************* USART 串口寄存器"UCTL","UTCTL","URCTL"定义的各个位可串口1 串口2公用************************************************************//* UCTL 串口控制寄存器*/#define PENA 0x80 /*校验允许位*/#define PEV 0x40 /*偶校验为0时为奇校验*/#define SPB 0x20 /*停止位为2 为0时停止位为1*/#define CHAR 0x10 /*数据位为8位为0时数据位为7位*/#define LISTEN 0x08 /*自环模式(发数据同时在把发的数据接收回来)*/#define SYNC 0x04 /*同步模式为0异步模式*/#define MM 0x02 /*为1时地址位多机协议(异步) 主机模式(同步);为0时线路空闲多机协议(异步) 从机模式(同步)*/#define SWRST 0x01 /*控制位*//* UTCTL 串口发送控制寄存器*/#define CKPH 0x80 /*时钟相位控制位(只同步方式用)为1时时钟UCLK延时半个周期*/#define CKPL 0x40 /*时钟极性控制位为1时异步与UCLK相反;同步下降延有效*/#define SSEL1 0x20 /*时钟源选择位:与SSEL0组合为0,1,2,3四种方式*/#define SSEL0 0x10 /*"0"选择外部时钟,"1"选择辅助时钟,"2","3"选择系统子时钟 */#define URXSE 0x08 /*接收触发延控制位(只在异步方式下用)*/#define TXWAKE 0x04 /*多处理器通信传送控制位(只在异步方式下用)*/#define STC 0x02 /*外部引脚STE选择位为0时为4线模式为1时为3线模式*/ #define TXEPT 0x01 /*发送器空标志*//* URCTL 串口接收控制寄存器同步模式下只用两位:FE和OE*/#define FE 0x80 /*帧错标志*/#define PE 0x40 /*校验错标志位*/#define OE 0x20 /*溢出标志位*/#define BRK 0x10 /*打断检测位*/#define URXEIE 0x08 /*接收出错中断允许位*/#define URXWIE 0x04 /*接收唤醒中断允许位*/#define RXWAKE 0x02 /*接收唤醒检测位*/#define RXERR 0x01 /*接收错误标志位*//************************************************************* USART 0 串口0寄存器定义************************************************************/#define U0CTL_ 0x0070 /* UART 0 Control */sfrb U0CTL = U0CTL_;#define U0TCTL_ 0x0071 /* UART 0 Transmit Control */ sfrb U0TCTL = U0TCTL_;#define U0RCTL_ 0x0072 /* UART 0 Receive Control */ sfrb U0RCTL = U0RCTL_;#define U0MCTL_ 0x0073 /* UART 0 Modulation Control */ sfrb U0MCTL = U0MCTL_;#define U0BR0_ 0x0074 /* UART 0 Baud Rate 0 */sfrb U0BR0 = U0BR0_;#define U0BR1_ 0x0075 /* UART 0 Baud Rate 1 */sfrb U0BR1 = U0BR1_;#define U0RXBUF_ 0x0076 /* UART 0 Receive Buffer */ const sfrb U0RXBUF = U0RXBUF_;#define U0TXBUF_ 0x0077 /* UART 0 Transmit Buffer */ sfrb U0TXBUF = U0TXBUF_;/* Alternate register names */#define UCTL0_ 0x0070 /* UART 0 Control */sfrb UCTL0 = UCTL0_;#define UTCTL0_ 0x0071 /* UART 0 Transmit Control */ sfrb UTCTL0 = UTCTL0_;#define URCTL0_ 0x0072 /* UART 0 Receive Control */ sfrb URCTL0 = URCTL0_;#define UMCTL0_ 0x0073 /* UART 0 Modulation Control */ sfrb UMCTL0 = UMCTL0_;#define UBR00_ 0x0074 /* UART 0 Baud Rate 0 */sfrb UBR00 = UBR00_;#define UBR10_ 0x0075 /* UART 0 Baud Rate 1 */sfrb UBR10 = UBR10_;#define RXBUF0_ 0x0076 /* UART 0 Receive Buffer */ const sfrb RXBUF0 = RXBUF0_;#define TXBUF0_ 0x0077 /* UART 0 Transmit Buffer */ sfrb TXBUF0 = TXBUF0_;#define UCTL_0_ 0x0070 /* UART 0 Control */sfrb UCTL_0 = UCTL_0_;#define UTCTL_0_ 0x0071 /* UART 0 Transmit Control */ sfrb UTCTL_0 = UTCTL_0_;#define URCTL_0_ 0x0072 /* UART 0 Receive Control */ sfrb URCTL_0 = URCTL_0_;#define UMCTL_0_ 0x0073 /* UART 0 Modulation Control */ sfrb UMCTL_0 = UMCTL_0_;#define UBR0_0_ 0x0074 /* UART 0 Baud Rate 0 */sfrb UBR0_0 = UBR0_0_;#define UBR1_0_ 0x0075 /* UART 0 Baud Rate 1 */sfrb UBR1_0 = UBR1_0_;#define RXBUF_0_ 0x0076 /* UART 0 Receive Buffer */ const sfrb RXBUF_0 = RXBUF_0_;#define TXBUF_0_ 0x0077 /* UART 0 Transmit Buffer *//************************************************************* USART 1 串口1寄存器定义************************************************************/#define U1CTL_ 0x0078 /* UART 1 Control */sfrb U1CTL = U1CTL_;#define U1TCTL_ 0x0079 /* UART 1 Transmit Control */ sfrb U1TCTL = U1TCTL_;#define U1RCTL_ 0x007A /* UART 1 Receive Control */ sfrb U1RCTL = U1RCTL_;#define U1MCTL_ 0x007B /* UART 1 Modulation Control */ sfrb U1MCTL = U1MCTL_;#define U1BR0_ 0x007C /* UART 1 Baud Rate 0 */sfrb U1BR0 = U1BR0_;#define U1BR1_ 0x007D /* UART 1 Baud Rate 1 */sfrb U1BR1 = U1BR1_;#define U1RXBUF_ 0x007E /* UART 1 Receive Buffer */ const sfrb U1RXBUF = U1RXBUF_;#define U1TXBUF_ 0x007F /* UART 1 Transmit Buffer */ sfrb U1TXBUF = U1TXBUF_;#define UCTL1_ 0x0078 /* UART 1 Control */sfrb UCTL1 = UCTL1_;#define UTCTL1_ 0x0079 /* UART 1 Transmit Control */ sfrb UTCTL1 = UTCTL1_;#define URCTL1_ 0x007A /* UART 1 Receive Control */ sfrb URCTL1 = URCTL1_;#define UMCTL1_ 0x007B /* UART 1 Modulation Control */ sfrb UMCTL1 = UMCTL1_;#define UBR01_ 0x007C /* UART 1 Baud Rate 0 */#define UBR11_ 0x007D /* UART 1 Baud Rate 1 */sfrb UBR11 = UBR11_;#define RXBUF1_ 0x007E /* UART 1 Receive Buffer */ const sfrb RXBUF1 = RXBUF1_;#define TXBUF1_ 0x007F /* UART 1 Transmit Buffer */ sfrb TXBUF1 = TXBUF1_;#define UCTL_1_ 0x0078 /* UART 1 Control */sfrb UCTL_1 = UCTL_1_;#define UTCTL_1_ 0x0079 /* UART 1 Transmit Control */ sfrb UTCTL_1 = UTCTL_1_;#define URCTL_1_ 0x007A /* UART 1 Receive Control */ sfrb URCTL_1 = URCTL_1_;#define UMCTL_1_ 0x007B /* UART 1 Modulation Control */ sfrb UMCTL_1 = UMCTL_1_;#define UBR0_1_ 0x007C /* UART 1 Baud Rate 0 */sfrb UBR0_1 = UBR0_1_;#define UBR1_1_ 0x007D /* UART 1 Baud Rate 1 */sfrb UBR1_1 = UBR1_1_;#define RXBUF_1_ 0x007E /* UART 1 Receive Buffer */ const sfrb RXBUF_1 = RXBUF_1_;#define TXBUF_1_ 0x007F /* UART 1 Transmit Buffer */ sfrb TXBUF_1 = TXBUF_1_;MSP430寄存器中文注释---P1/2口（带中断功能）/************************************************************* DIGITAL I/O Port1/2 寄存器定义有中断功能************************************************************/#define P1IN_ 0x0020 /* P1 输入寄存器 */const sfrb P1IN = P1IN_;#define P1OUT_ 0x0021 /* P1 输出寄存器 */sfrb P1OUT = P1OUT_;#define P1DIR_ 0x0022 /* P1 方向选择寄存器 */sfrb P1DIR = P1DIR_;#define P1IFG_ 0x0023 /* P1 中断标志寄存器*/sfrb P1IFG = P1IFG_;#define P1IES_ 0x0024 /* P1 中断边沿选择寄存器*/ sfrb P1IES = P1IES_;#define P1IE_ 0x0025 /* P1 中断使能寄存器 */sfrb P1IE = P1IE_;#define P1SEL_ 0x0026 /* P1 功能选择寄存器*/sfrb P1SEL = P1SEL_;#define P2IN_ 0x0028 /* P2 输入寄存器 */const sfrb P2IN = P2IN_;#define P2OUT_ 0x0029 /* P2 输出寄存器 */sfrb P2OUT = P2OUT_;#define P2DIR_ 0x002A /* P2 方向选择寄存器 */ sfrb P2DIR = P2DIR_;#define P2IFG_ 0x002B /* P2 中断标志寄存器 */sfrb P2IFG = P2IFG_;#define P2IES_ 0x002C /* P2 中断边沿选择寄存器 */ sfrb P2IES = P2IES_;#define P2IE_ 0x002D /* P2 中断使能寄存器 */sfrb P2IE = P2IE_;#define P2SEL_ 0x002E /* P2 功能选择寄存器 */sfrb P2SEL = P2SEL_;MSP430寄存器中文注释---P3/4口（无中断功能）/************************************************************ * DIGITAL I/O Port3/4寄存器定义无中断功能************************************************************/#define P3IN_ 0x0018 /* P3 输入寄存器 */const sfrb P3IN = P3IN_;#define P3OUT_ 0x0019 /* P3 输出寄存器 */sfrb P3OUT = P3OUT_;#define P3DIR_ 0x001A /* P3 方向选择寄存器 */sfrb P3DIR = P3DIR_;#define P3SEL_ 0x001B /* P3 功能选择寄存器*/sfrb P3SEL = P3SEL_;#define P4IN_ 0x001C /* P4 输入寄存器 */const sfrb P4IN = P4IN_;#define P4OUT_ 0x001D /* P4 输出寄存器 */sfrb P4OUT = P4OUT_;#define P4DIR_ 0x001E /* P4 方向选择寄存器 */sfrb P4DIR = P4DIR_;#define P4SEL_ 0x001F /* P4 功能选择寄存器 */sfrb P4SEL = P4SEL_;/************************************************************ * DIGITAL I/O Port5/6 I/O口寄存器定义PORT5和6 无中断功能************************************************************/#define P5IN_ 0x0030 /* P5 输入寄存器 */const sfrb P5IN = P5IN_;#define P5OUT_ 0x0031 /* P5 输出寄存器*/sfrb P5OUT = P5OUT_;#define P5DIR_ 0x0032 /* P5 方向选择寄存器*/sfrb P5DIR = P5DIR_;#define P5SEL_ 0x0033 /* P5 功能选择寄存器*/sfrb P5SEL = P5SEL_;#define P6IN_ 0x0034 /* P6 输入寄存器 */const sfrb P6IN = P6IN_;#define P6OUT_ 0x0035 /* P6 输出寄存器*/sfrb P6OUT = P6OUT_;#define P6DIR_ 0x0036 /* P6 方向选择寄存器*/sfrb P6DIR = P6DIR_;#define P6SEL_ 0x0037 /* P6 功能选择寄存器*/sfrb P6SEL = P6SEL_;MSP430寄存器中文注释--- 硬件乘法器/************************************************************ 硬件乘法器的寄存器定义************************************************************/#define MPY_ 0x0130 /* 无符号乘法 */sfrw MPY = MPY_;#define MPYS_ 0x0132 /* 有符号乘法*/sfrw MPYS = MPYS_;#define MAC_ 0x0134 /* 无符号乘加 */sfrw MAC = MAC_;#define MACS_ 0x0136 /* 有符号乘加 */sfrw MACS = MACS_;#define OP2_ 0x0138 /* 第二乘数 */sfrw OP2 = OP2_;#define RESLO_ 0x013A /* 低6位结果寄存器 */sfrw RESLO = RESLO_;#define RESHI_ 0x013C /* 高6位结果寄存器 */sfrw RESHI = RESHI_;#define SUMEXT_ 0x013E /*结果扩展寄存器 */const sfrw SUMEXT = SUMEXT_;MSP430寄存器中文注释---看门狗和定时器/************************************************************* 看门狗定时器的寄存器定义************************************************************/#define WDTCTL_ 0x0120sfrw WDTCTL = WDTCTL_;#define WDTIS0 0x0001 /*选择WDTCNT的四个输出端之一*/#define WDTIS1 0x0002 /*选择WDTCNT的四个输出端之一*/#define WDTSSEL 0x0004 /*选择WDTCNT的时钟源*/#define WDTCNTCL 0x0008 /*清除WDTCNT端: 为1时从0开始计数*/#define WDTTMSEL 0x0010 /*选择模式 0: 看门狗模式; 1: 定时器模式*/#define WDTNMI 0x0020 /*选择NMI/RST 引脚功能 0:为 RST; 1:为NMI*/#define WDTNMIES 0x0040 /*WDTNMI=1时.选择触发延 0:为上升延 1:为下降延*/ #define WDTHOLD 0x0080 /*停止看门狗定时器工作 0:启动;1:停止*/#define WDTPW 0x5A00 /* 写密码:高八位*//* SMCLK= 1MHz定时器模式 */#define WDT_MDLY_32 WDTPW+WDTTMSEL+WDTCNTCL /* TSMCLK*2POWER15=32ms 复位状态 */#define WDT_MDLY_8 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS0 /* TSMCLK*2POWER13=8.192ms " */#define WDT_MDLY_0_5 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1 /* TSMCLK*2POWER9=0.512ms " */#define WDT_MDLY_0_064 WDTPW+WDTTMSEL+WDTCNTCL+WDTIS1+WDTIS0 /* TSMCLK*2POWER6=0.512ms " *//* ACLK=32.768KHz 定时器模式*/#define WDT_ADLY_1000 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL /* TACLK*2POWER15=1000ms " */#define WDT_ADLY_250 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS0 /* TACLK*2POWER13=250ms " */#define WDT_ADLY_16 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1 /*TACLK*2POWER9=16ms " */#define WDT_ADLY_1_9 WDTPW+WDTTMSEL+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 /* TACLK*2POWER6=1.9ms " *//* SMCLK=1MHz看门狗模式 */#define WDT_MRST_32 WDTPW+WDTCNTCL /* TSMCLK*2POWER15=32ms 复位状态 */#define WDT_MRST_8 WDTPW+WDTCNTCL+WDTIS0 /* TSMCLK*2POWER13=8.192ms " */#define WDT_MRST_0_5 WDTPW+WDTCNTCL+WDTIS1 /* TSMCLK*2POWER9=0.512ms " */#define WDT_MRST_0_064 WDTPW+WDTCNTCL+WDTIS1+WDTIS0 /* TSMCLK*2POWER6=0.512ms " *//* ACLK=32KHz看门狗模式 */#define WDT_ARST_1000 WDTPW+WDTCNTCL+WDTSSEL /* TACLK*2POWER15=1000ms " */#define WDT_ARST_250 WDTPW+WDTCNTCL+WDTSSEL+WDTIS0 /* TACLK*2POWER13=250ms " */#define WDT_ARST_16 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1 /* TACLK*2POWER9=16ms " */#define WDT_ARST_1_9 WDTPW+WDTCNTCL+WDTSSEL+WDTIS1+WDTIS0 /* TACLK*2POWER6=1.9ms " */MSP430寄存器中文注释---A/D采样寄存器定义/************************************************************* ADC12 A/D采样寄存器定义************************************************************//*ADC12转换控制类寄存器*/#define ADC12CTL0_ 0x0;' /* ADC12 Control 0 */sfrw ADC12CTL0 = ADC12CTL0_;#define ADC12CTL1_ 0x01A2 /* ADC12 Control 1 */sfrw ADC12CTL1 = ADC12CTL1_;/*ADC12中断控制类寄存器*/#define ADC12IFG_ 0x01A4 /* ADC12 Interrupt Flag */sfrw ADC12IFG = ADC12IFG_;#define ADC12IE_ 0x01A6 /* ADC12 Interrupt Enable */sfrw ADC12IE = ADC12IE_;#define ADC12IV_ 0x01A8 /* ADC12 Interrupt Vector Word */sfrw ADC12IV = ADC12IV_;/*ADC12存贮器类寄存器*/#define ADC12MEM_ 0x0140 /* ADC12 Conversion Memory */#ifndef __IAR_SYSTEMS_ICC#define ADC12MEM ADC12MEM_ /* ADC12 Conversion Memory (for assembler) */ #else#define ADC12MEM ((int*) ADC12MEM_) /* ADC12 Conversion Memory (for C) */ #endif#define ADC12MEM0_ ADC12MEM_ /* ADC12 Conversion Memory 0 */sfrw ADC12MEM0 = ADC12MEM0_;#define ADC12MEM1_ 0x0142 /* ADC12 Conversion Memory 1 */sfrw ADC12MEM1 = ADC12MEM1_;#define ADC12MEM2_ 0x0144 /* ADC12 Conversion Memory 2 */sfrw ADC12MEM2 = ADC12MEM2_;#define ADC12MEM3_ 0x0146 /* ADC12 Conversion Memory 3 */sfrw ADC12MEM3 = ADC12MEM3_;#define ADC12MEM4_ 0x0148 /* ADC12 Conversion Memory 4 */sfrw ADC12MEM4 = ADC12MEM4_;#define ADC12MEM5_ 0x014A /* ADC12 Conversion Memory 5 */sfrw ADC12MEM5 = ADC12MEM5_;#define ADC12MEM6_ 0x014C /* ADC12 Conversion Memory 6 */sfrw ADC12MEM6 = ADC12MEM6_;#define ADC12MEM7_ 0x014E /* ADC12 Conversion Memory 7 */sfrw ADC12MEM7 = ADC12MEM7_;#define ADC12MEM8_ 0x0150 /* ADC12 Conversion Memory 8 */sfrw ADC12MEM8 = ADC12MEM8_;#define ADC12MEM9_ 0x0152 /* ADC12 Conversion Memory 9 */sfrw ADC12MEM9 = ADC12MEM9_;#define ADC12MEM10_ 0x0154 /* ADC12 Conversion Memory 10 */sfrw ADC12MEM10 = ADC12MEM10_;#define ADC12MEM11_ 0x0156 /* ADC12 Conversion Memory 11 */sfrw ADC12MEM11 = ADC12MEM11_;#define ADC12MEM12_ 0x0158 /* ADC12 Conversion Memory 12 */sfrw ADC12MEM12 = ADC12MEM12_;#define ADC12MEM13_ 0x015A /* ADC12 Conversion Memory 13 */sfrw ADC12MEM13 = ADC12MEM13_;#define ADC12MEM14_ 0x015C /* ADC12 Conversion Memory 14 */sfrw ADC12MEM14 = ADC12MEM14_;#define ADC12MEM15_ 0x015E /* ADC12 Conversion Memory 15 */sfrw ADC12MEM15 = ADC12MEM15_;/*ADC12存贮控制类寄存器*/#define ADC12MCTL_ 0x0080 /* ADC12 Memory Control */#ifndef __IAR_SYSTEMS_ICC#define ADC12MCTL ADC12MCTL_ /* ADC12 Memory Control (for assembler) */#else#define ADC12MCTL ((char*) ADC12MCTL_) /* ADC12 Memory Control (for C) */ #endif#define ADC12MCTL0_ ADC12MCTL_ /* ADC12 Memory Control 0 */sfrb ADC12MCTL0 = ADC12MCTL0_;#define ADC12MCTL1_ 0x0081 /* ADC12 Memory Control 1 */sfrb ADC12MCTL1 = ADC12MCTL1_;#define ADC12MCTL2_ 0x0082 /* ADC12 Memory Control 2 */sfrb ADC12MCTL2 = ADC12MCTL2_;#define ADC12MCTL3_ 0x0083 /* ADC12 Memory Control 3 */sfrb ADC12MCTL3 = ADC12MCTL3_;#define ADC12MCTL4_ 0x0084 /* ADC12 Memory Control 4 */sfrb ADC12MCTL4 = ADC12MCTL4_;#define ADC12MCTL5_ 0x0085 /* ADC12 Memory Control 5 */sfrb ADC12MCTL5 = ADC12MCTL5_;#define ADC12MCTL6_ 0x0086 /* ADC12 Memory Control 6 */sfrb ADC12MCTL6 = ADC12MCTL6_;#define ADC12MCTL7_ 0x0087 /* ADC12 Memory Control 7 */sfrb ADC12MCTL7 = ADC12MCTL7_;#define ADC12MCTL8_ 0x0088 /* ADC12 Memory Control 8 */sfrb ADC12MCTL8 = ADC12MCTL8_;#define ADC12MCTL9_ 0x0089 /* ADC12 Memory Control 9 */sfrb ADC12MCTL9 = ADC12MCTL9_;#define ADC12MCTL10_ 0x008A /* ADC12 Memory Control 10 */sfrb ADC12MCTL10 = ADC12MCTL10_;#define ADC12MCTL11_ 0x008B /* ADC12 Memory Control 11 */sfrb ADC12MCTL11 = ADC12MCTL11_;#define ADC12MCTL12_ 0x008C /* ADC12 Memory Control 12 */sfrb ADC12MCTL12 = ADC12MCTL12_;#define ADC12MCTL13_ 0x008D /* ADC12 Memory Control 13 */sfrb ADC12MCTL13 = ADC12MCTL13_;#define ADC12MCTL14_ 0x008E /* ADC12 Memory Control 14 */sfrb ADC12MCTL14 = ADC12MCTL14_;#define ADC12MCTL15_ 0x008F /* ADC12 Memory Control 15 */sfrb ADC12MCTL15 = ADC12MCTL15_;/* ADC12CTL0 内8位控制寄存器位*/#define ADC12SC 0x001 /*采样/转换控制位*/#define ENC 0x002 /* 转换允许位*/#define ADC12TOVIE 0x004 /*转换时间溢出中断允许位*/#define ADC12OVIE 0x008 /*溢出中断允许位*/#define ADC12ON 0x010 /*ADC12内核控制位*/#define REFON 0x020 /*参考电压控制位*/#define REF2_5V 0x040 /*内部参考电压的电压值选择位 '0'为1.5V; '1'为2.5V*/ #define MSH 0x080 /*多次采样/转换位*/#define MSC 0x080 /*多次采样/转换位*//*SHT0 采样保持定时器0 控制ADC12的结果存贮器MEM0~MEM7的采样周期*/。

OPT3001 MSP430G2553完整程序

if(ManufacturerIDNum==0x5449&&DeviceIDNum==0x3001) //如果读出来的ID都正确表示初始化成功
{
return 0;
}
else//否则初始化不成功
{
return 1;
}
}
//OPT3001寄存器配置
//12-15位RN[0,3]:0x1100,设置为Full-Scale Mode
OPT3001IIC_Init();//OPT3001端口初始化
OPT3001Config(); //配置OPT3001并且唤醒OPT3001
delay();
ManufacturerIDNum=GetOPT3001ManufacturerID();
delay();
DeviceIDNum=GetOPT3001DeviceID();
write1();
stop();//停止信号
}
//*********************************************************
//读出BMP085内部数据,连续两个
//*********************************************************
}
BCSCTL1 = CALBC1_1MHZ; // Set DCO
DCOCTL = CALDCO_1MHZ;
}
void Opt3001WriteRegister(unsigned char registerName, unsigned int value)
{
start(); //起始信号
write1byte(0x88); //发送设备地址+写信号

MSP430G2553_PWM

/************************************************************** 名称：PWM输出* 硬件描述：MSP430G2553 P1.2 P1.6 P2.1 P2.2 P2.4 P2.5* 功能：初始化定时器，输出PWM波* 入口参数：周期Cyc，占空比Occupancy* 出口参数：无* 时间：2014年7月27日* 作者：Jelly-Li* 说明：* Timer_A0_1_init(int Cyc,int Occupancy); P1.2 P1.6* Timer_A1_1_init(int Cyc,int Occupancy); P2.1 P2.2* Timer_A1_2_init(int Cyc,int Occupancy); P2.4 P2.5* 注意：* 使用的那几个IO口* 输出几个信号* 范例：* Timer_A0_1_init(500,100); 20% P1.2 P1.6* Timer_A1_1_init(300,150); 50% P2.1 P2.2* Timer_A1_2_init(8000,200); 2.5% P2.4 P2.5*************************************************************/#include <msp430g2553.h>/************************************************************** 名称：void Timer_A0_1_init(int Cyc,int Occupancy) TA0.1输出PWM* 硬件描述：MSP430G2553 P1.2 P1.6* 功能：输出PWM* 入口参数：周期Cyc，占空比Occupancy* 出口参数：无* 时间：2014年7月27日* 作者：Jelly-Li* 说明：* Timer_A0_1_init(int Cyc,int Occupancy); P1.2 P1.6* 使用P1.2口和P1.6口输出，可以同时也可以只输出一个* 注意：* 要输出几个信号，修改程序* 范例：* Timer_A0_1_init(500,100); 20% P1.2 P1.6*************************************************************/void Timer_A0_1_init(int Cyc,int Occupancy) //TA0.1输出PWM{P1SEL |= BIT2 + BIT6; //P1.2 和P1.6同时输出一样的PWM,可以只用其中一个输出P1DIR |= BIT2 + BIT6;CCR0 = Cyc; //设置周期（频率）CCR1 = Occupancy; //占空比CCR1/CCR0CCTL1 = OUTMOD_7; //输出模式为复位/置位TACTL |= TASSEL_1 + MC_1; //选择时钟,增计数}/************************************************************** 名称：void Timer_A1_1_init(int Cyc,int Occupancy) //TA1.1输出PWM* 硬件描述：MSP430G2553 P2.1 P2.2* 功能：* 入口参数：Cyc* 出口参数：Occupancy* 时间：2014年7月27日* 作者：Jelly-Li* 说明：* Timer_A1_1_init(int Cyc,int Occupancy); P2.1 P2.2* P2.1 P2.2输出TA1.1 OUT1 可以输出两个或任意一个* 注意：* 要输出几个信号，修改程序* 范例：* Timer_A1_1_init(300,150); 50% P2.1 P2.2*************************************************************/void Timer_A1_1_init(int Cyc,int Occupancy) //TA1.1输出PWM{P2SEL |= BIT1 + BIT2; //P2.1 和P2.2同时输出一样的PWMP2DIR |= BIT1 + BIT2;TA1CCR0 = Cyc; //时钟频率TA1CCR1 = Occupancy; //占空比CCR1/CCR0，注意CCR1要写成TA1CCR1 TA1.1由P2.1 P2.2输出TA1CCTL1 = OUTMOD_7; //输出模式为复位/置位，注意CCTL1要写为TA1CCTL1TA1CTL |= TASSEL_1 + MC_1; //时钟,增计数}/************************************************************** 名称：void Timer_A1_2_init(int Cyc,int Occupancy)* 硬件描述：MSP430G2553 P2.4 P2.5* 功能：* 入口参数：Cyc* 出口参数：Occupancy* 时间：2014年7月27日* 作者：Jelly-Li* 说明：* Timer_A1_2_init(int Cyc,int Occupancy); P2.4 P2.5* P2.4 P2.5输出TA1.2 OUT2 可以任意输出一个或者两个，但必须是这两个端口* 注意：* 要输出几个信号，修改程序* 范例：* Timer_A1_2_init(8000,200); 2.5% P2.4 P2.5*************************************************************/void Timer_A1_2_init(int Cyc,int Occupancy) //TA1.2输出PWM{//端口初始化P2SEL |= BIT4 + BIT5; //P2.4 和P2.5同时输出一样的PWMP2DIR |= BIT4 + BIT5;//TA1CCR0 = Cyc; //设置周期，当T1.1不用时，要设置，当T1.1使用时不设置，与T1.1周期一致TA1CCR2 = Occupancy; //占空比CCR2/CCR0，注意CCR2要写成TA1CCR2 TA1.2由P2.4 P2.5输出TA1CCTL2 = OUTMOD_7; //输出模式为复位/置位，注意CCTL2要写为TA1CCTL2//TA1CTL |= TASSEL_1 + MC_1; //时钟,增计数当T1.1不用时，要设置，当T1.1使用时不设置，与T1.1周期一致}。

MSP430G2553寄存器资料讲解

MSP430G2553学习笔记常用赋值运算符：清除：&=~ ，置位：|= ，测试：&= ，取反：^= ，看门狗模块：WDT（看门狗）WDTCTL 看门狗定时器控制寄存器15--8 7 6 5 4 3 2 1 0口令HOLD NMIES NMI TMSEL CNTCL SSEL IS1 IS0IS1，IS0 选择看门狗定时器的定时输出，T是WDTCNT的输入时钟源周期0 T x 2(15)1 T x 2(13)2 T x 2(9)3 T x 2(6)SSEL 选择WDTCNT的时钟源0 SMCLK1 ACLKIS0、IS1、SSEL可确定WDT定时时间，WDT只能定时8种和时钟源相关的时间WDT可选的定时时间(晶体为32768HZ，SMCLK=1MHZ)SSEL IS1 IS0 定时时间/ms0 1 1 0.056 Tsmclk x 2(6)0 1 0 0.5 Tsmclk x 2(9)1 1 1 1.9 Taclk x 2(6)0 0 1 8 Tsmclk x 2(13)1 1 0 16 Taclk x 2(9)0 0 0 32 Tsmclk x 2(15)(PUC复位后的值)1 0 1 250 Taclk x 2(13)1 0 0 1000 Taclk x 2(15)CNTCL当该位为1时，清除WDTCNTTMSEL 工作模式选择0 看门狗模式1 定时器模式NMI 选择RST/NMI引脚功能，在PUC后被复位0 RST/NMI引脚为复位端1 RST/NMI引脚为边沿触发的非屏蔽中断输入NMIES 选择中断的边沿触发方式0 上升沿触发NMI中断1 下降沿触发NMI中断HOLD 停止看门狗定时器工作，降低功耗0 WDT功能激活1 时钟禁止输入，计数停止WDT（看门狗）配置语句WDTCTL=WDTPW+WDTHOLD；//将WDTPW+WDTHOLD赋值给WDTCTL，关闭看门狗定时器控制寄存器（Stop watchdogtimer）IE1 |= WDTIE；//使能WDT中断WDTCTL = WDT_ADL Y_1000；//WDT 1 s / 4间隔计时器WDTCTL = WDTPW + WDTHOLD + WDTNMI + WDTNMIES；//WDTCTL 由高8位口令和低8位控制命令组成，要写入操作WDT的控制命令，出于安全原因必须先正确写入高字节看门狗口令。

MSP430G2553_官方例程(加注释版)

__bis_SR_register(LPM0_bits + GIE); // LPM0 with interrupts enabled
// oF = ((A10/1024)*1500mV)-923mV)*1/1.97mV = A10*761/1024 - 468
temp = ADC10MEM;
IntDegF = ((temp - 630) * 761) / 1024;
//BCSCTL1 = CALBC1_16MHZ;
//DCOCTL = CALBC1_16MHZ;
P1DIR |= 0x31; // P1.0,5 and P1.4 outputs
P1SEL |= 0x11; // P1.0,4 ACLK/VLO, SMCLK/DCO output
//SMCLK Sub-System Main Clk，ACLK和SMCLK可以通过复用引脚输出，MCLK不能直接输出体现, MCLK可以配置为VLO或者DCO
P1OUT = 0;// green LED off
_delay_cycles(5000);
}
}
2.
//******************************************************************************
// LaunchPad Lab3 - Software Port Interrupt Service
P1IFG &= ~BIT3; // P1.3 IFG cleared
P1IE |= BIT3; // P1.3 interrupt enabled
_BIS_SR(LPM4_bits + GIE); // Enter LPM4 w/interrupt

mini12864的MSP430G2553驱动程序

else
ret_data=ret_data+0;
// P2DIR|=BIT1;
ROMSCK_1;
}
return(ret_data);
}
/*从相关地址（addrHigh：地址高字节,addrMid：地址中字节,addrLow：地址低字节）中连续读出DataLen个字节的数据到 pBuff的地址*/
LCDSID_1;
else
LCDSID_0;
LCDSCLK_1;
data1=data1<<=1;
}
}
/*写数据到LCD模块*/
void transfer_data_lcd(int data1)
{
char i;
LCDRS_1;
for(i=0;i<8;i++)
#define ROMCS_0 P2OUT&=~BIT3
/*写指令到LCD模块*/
void transfer_command_lcd(int data1)
{
char i;
LCDRS_0;
for(i=0;i<8;i++)
{
LCDSCLK_0;
if(data1&0x80)
#define LCDCS_0 P1OUT&=~BIT4
#define ROMIN_1 P2OUT|=BIT0 /*字库IC接口定义:Rom_IN就是字库IC的SI*/
#define ROMIN_0 P2OUT&=~BIT0
#define ROMOUT_1 P2OUT|=BIT1 /*字库IC接口定义:Rom_OUT就是字库IC的SO*/

Msp430g2553头文件

Msp430g2553定义部分/＊*＊****＊＊****＊****＊***＊**＊*＊＊**＊＊*＊＊＊*＊＊*＊＊＊*＊*＊*＊＊＊*＊＊*＊**＊＊＊＊*＊＊＊＊** Standard register and bit definitions for the Texas Instruments标准寄存器和位于德克萨斯工具定义* MSP430 microcontroller.*MSP430系列单片机。

* This file supports assembler and C development for＊ MSP430G2553 devices。

*本文件支持的汇编和C开发 * msp430g2553设备。

＊ Texas Instruments， Version 1.0*德克萨斯仪器，1版* Rev。

1.0， Setup＊**＊**＊＊*＊****＊******＊**＊*＊＊*＊＊**＊*＊＊＊＊＊＊＊＊**＊＊***＊*＊＊**＊＊＊＊*＊＊＊＊****/#ifndef __MSP430G2553#define __MSP430G2553#define __MSP430_HEADER_VERSION__ 1062#ifdef __cplusplusextern”C” ｛＃endif/*———-——----———--—-———-----—---—--—--—--——-————-----—---———-—---——--—-—--——-—-*//* PERIPHERAL FILE MAP *//＊—-----—-—-—-—-—--—--—---——--——--————--------——-—-—-——-----————-——----—-—-——-*//＊ External references resolved by a device-specific linker command file ＊//*外部引用通过特定装置的连接命令文件＊/＃define SFR_8BIT(address) extern volatile unsigned char address＃define SFR_16BIT（address) extern volatile unsigned int address/＊＊＊*＊***＊＊＊****＊＊＊*＊*＊＊＊＊＊**＊＊***＊**＊＊*＊*＊＊*＊＊**＊*＊**＊＊＊*＊＊＊* STANDARD BITS**＊**＊＊＊**＊***＊＊＊＊*＊**＊＊**＊＊＊＊＊**＊*****＊*＊*＊＊***＊＊**＊＊*＊*＊*＊/＃define BIT0 (0x0001)＃define BIT1 (0x0002）＃define BIT2 (0x0004)＃define BIT3 (0x0008)＃define BIT4 (0x0010)#define BIT5 （0x0020)＃define BIT6 （0x0040)＃define BIT7 （0x0080)#define BIT8 (0x0100)#define BIT9 (0x0200)＃define BITA (0x0400)#define BITB （0x0800)#define BITC (0x1000）＃define BITD (0x2000)#define BITE （0x4000)#define BITF （0x8000）/*＊*＊＊＊＊＊＊**＊**＊*＊*＊＊**＊＊＊＊*****＊***＊*＊＊*＊＊*＊**＊＊**＊＊*＊*＊*＊＊* * STATUS REGISTER BITS状态寄存器*＊*＊*＊*＊***＊＊***＊＊＊*＊*＊＊＊＊＊＊***＊*＊**＊****＊＊＊＊*＊＊**＊＊＊**＊*＊＊*/＃define C （0x0001）#define Z （0x0002)＃define N (0x0004）＃define V (0x0100)＃define GIE （0x0008）#define CPUOFF (0x0010)＃define OSCOFF （0x0020)#define SCG0 (0x0040）＃define SCG1 （0x0080)/＊ Low Power Modes coded with Bits 4-7 in SR */低功耗模式编码与SR 4-7位#ifdef __ASM_HEADER__ /* Begin ＃defines for assembler开始＃defines（定义）汇编*/#define LPM0 （CPUOFF）#define LPM1 (SCG0+CPUOFF)#define LPM2 （SCG1+CPUOFF)＃define LPM3 (SCG1+SCG0+CPUOFF）＃define LPM4 （SCG1+SCG0+OSCOFF+CPUOFF）/＊ End ＃defines for assembler ＊/＃else /* Begin #defines for C ＊/＃define LPM0_bits （CPUOFF）＃define LPM1_bits （SCG0+CPUOFF）＃define LPM2_bits (SCG1+CPUOFF)＃define LPM3_bits (SCG1+SCG0+CPUOFF)#define LPM4_bits （SCG1+SCG0+OSCOFF+CPUOFF）#include”in430.h”＃define LPM0 _bis_SR_register(LPM0_bits) /＊ Enter Low Power Mode 0 */#define LPM0_EXIT _bic_SR_register_on_exit（LPM0_bits） /＊ Exit Low Power Mode 0 ＊/#define LPM1 _bis_SR_register（LPM1_bits) /* Enter Low Power Mode 1 */＃define LPM1_EXIT _bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 ＊/＃define LPM2 _bis_SR_register（LPM2_bits) /* Enter Low Power Mode 2 */#define LPM2_EXIT _bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 ＊/#define LPM3 _bis_SR_register(LPM3_bits） /＊ Enter Low Power Mode 3 */＃define LPM3_EXIT _bic_SR_register_on_exit（LPM3_bits) /* Exit Low Power Mode 3 */＃define LPM4 _bis_SR_register（LPM4_bits） /＊ Enter Low Power Mode 4 */＃define LPM4_EXIT _bic_SR_register_on_exit(LPM4_bits） /* Exit Low Power Mode 4 */＃endif /＊ End #defines for C *//*＊**＊***＊＊＊＊＊＊*＊＊＊＊**＊＊****＊*＊＊＊＊*＊***＊*＊＊*＊***＊*＊*＊＊＊＊＊＊＊＊* * PERIPHERAL FILE MAP*＊***＊*****＊**＊***＊***＊＊＊＊*＊*＊＊*＊*＊***＊＊＊＊＊**＊**＊＊＊＊＊＊＊*＊＊＊＊//＊＊**＊＊＊＊＊***＊*＊＊*＊**＊***＊***＊＊*＊＊＊＊****＊＊＊*****＊＊＊＊**＊＊***＊＊＊ SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS***＊＊＊*＊*＊＊＊*＊＊＊＊****＊*＊**＊＊*＊***＊*＊＊*＊**＊*＊＊*＊**＊＊****＊＊＊*＊/SFR_8BIT（IE1）; /* Interrupt Enable 1 ＊/#define WDTIE (0x01) /＊ Watchdog Interrupt Enable ＊/＃define OFIE （0x02） /* Osc。

msp430g2553驱动dht11温湿度传感器

////////////////////main.c///////BY Wangzengri NKU#include "msp430g2553.h"#include"12864.h"const unsigned char tishi_W[]={"温度："};const unsigned char tishi_Wd[]={"°"};const unsigned char tishi_S[]={"湿度："};const unsigned char tishi_Sd[]={"%"};const unsigned char tishi_dot[]={".00"};#define CPU (1000000)#define delay_us(x) (__delay_cycles((double)x*CPU/1000000.0))#define delay_ms(x) (__delay_cycles((double)x*CPU/1000.0))#define HIGH P2OUT|= BIT1;#define LOW P2OUT &=~BIT1;unsigned char temph,templ,humdh,humdl,check,cal;void show_Wendu();void show_Shidu();void show_tishi();/*void DelayNus(unsigned int n) //延时Nus{unsigned int i;for(i = n;i > 0;i--)_NOP();}*/char receive(void) //接受函数{unsigned char num=0,tem,cnt; //临时变量用于存储接受数据for(cnt=0;cnt<8;cnt++){tem=0;while(!(P2IN&BIT1)); //等待14us的低电平结束delay_us(30);if((P2IN&BIT1)) /////////长于30us定义为1{tem=1;while((P2IN&BIT1)); //等待一位的采集结束}num<<=1;num|=tem;}return num;}void receive_init(){P2DIR|=BIT1;LOW;delay_ms(20);HIGH;delay_us(30); //20--40P2DIR &=~BIT1;if(!(P2IN&BIT1)); //从机发出响应信号{while(!(P2IN&BIT1));//等待响应响应结束while((P2IN&BIT1));//开始采集humdh=receive();humdl=receive();temph=receive();templ=receive();check=receive();}}void main( void ){WDTCTL=WDTPW+WDTHOLD;DCOCTL = CALDCO_1MHZ;Ini_Lcd();show_tishi();while(1){receive_init();cal=humdh+humdl+temph+templ;if(cal==check){show_Wendu();show_Shidu();}}}void show_tishi(){Disp_HZ(0x80,tishi_W,3);Disp_HZ(0x86,tishi_Wd,1);Disp_HZ(0x88,tishi_S,3);Disp_HZ(0x8e,tishi_Sd,1);}void show_Wendu(){Disp_SZ(0x83,temph);Disp_HZ(0x84,tishi_dot,2);//Disp_SZ(0x84,templ);}void show_Shidu(){Disp_SZ(0x8b,humdh);Disp_HZ(0x8c,tishi_dot,2);//Disp_SZ(0x8c,humdl);}//12864.c#include <msp430g2553.h>typedef unsigned int uint;typedef unsigned char uchar;#define BIT(x) (1 << (x))const uchar numtable[]={"0123456789"};void Send(uchar type,uchar transdata);/**********液晶控制IO的宏定义*************/ #define cyCS 0 //P1.0，片选信号#define cySID 1 //P1.1，串行数据#define cyCLK 2 //P1.2，同步时钟#define cyPORT P1OUT#define cyDDR P1DIR/******************************************* 函数名称：delay_Nus功能：延时N个us的时间参数：n--延时长度返回值：无********************************************/ void delay_Nus(uint n){uchar i;for(i = n;i > 0;i--)_NOP();}/******************************************* 函数名称：delay_1ms功能：延时约1ms的时间参数：无返回值：无********************************************/void delay_1ms(void){uchar i;for(i = 150;i > 0;i--) _NOP();}/*******************************************函数名称：delay_Nms功能：延时N个ms的时间参数：无返回值：无********************************************/void delay_Nms(uint n){uint i = 0;for(i = n;i > 0;i--)delay_1ms();}/*******************************************函数名称：Ini_Lcd功能：初始化液晶模块参数：无返回值：无********************************************/void Ini_Lcd(void){cyDDR |= BIT(cyCLK) + BIT(cySID) + BIT(cyCS); //相应的位端口设置为输出delay_Nms(100); //延时等待液晶完成复位Send(0,0x30); /*功能设置:一次送8位数据,基本指令集*/delay_Nus(72);Send(0,0x02); /*DDRAM地址归位*/delay_Nus(72);Send(0,0x0c); /*显示设定:开显示,不显示光标,不做当前显示位反白闪动*/delay_Nus(72);Send(0,0x01); /*清屏，将DDRAM的位址计数器调整为“00H”*/delay_Nus(72);Send(0,0x06); /*功能设置，点设定:显示字符/光标从左到右移位,DDRAM地址加1*/ delay_Nus(72);}/*******************************************函数名称：Send功能：MCU向液晶模块发送1一个字节的数据参数：type--数据类型，0--控制命令，1--显示数据transdata--发送的数据返回值：无********************************************/void Send(uchar type,uchar transdata){uchar firstbyte = 0xf8;uchar temp;uchar i,j = 3;if(type) firstbyte |= 0x02;cyPORT |= BIT(cyCS);cyPORT &= ~BIT(cyCLK);while(j > 0){if(j == 3) temp = firstbyte;else if(j == 2) temp = transdata&0xf0;else temp = (transdata << 4) & 0xf0;for(i = 8;i > 0;i--){if(temp & 0x80) cyPORT |= BIT(cySID);else cyPORT &= ~BIT(cySID);cyPORT |= BIT(cyCLK);temp <<= 1;cyPORT &= ~BIT(cyCLK);}//三个字节之间一定要有足够的延时，否则易出现时序问题if(j == 3) delay_Nus(600);else delay_Nus(200);j--;}cyPORT &= ~BIT(cySID);cyPORT &= ~BIT(cyCS);}/*******************************************函数名称：Clear_GDRAM功能：清除液晶GDRAM内部的随机数据参数：无返回值：无void Clear_GDRAM(void){uchar i,j,k;Send(0,0x34); //打开扩展指令集i = 0x80;for(j = 0;j < 32;j++){Send(0,i++);Send(0,0x80);for(k = 0;k < 16;k++){Send(1,0x00);}}i = 0x80;for(j = 0;j < 32;j++){Send(0,i++);Send(0,0x88);for(k = 0;k < 16;k++){Send(1,0x00);}}Send(0,0x30); //回到基本指令集}/******************************************* 函数名称：Disp_HZ功能：显示汉字程序参数：addr--显示位置的首地址pt--指向显示数据的指针num--显示数据的个数返回值：无********************************************/ void Disp_HZ(uchar addr,const uchar * pt,uchar num) {uchar i;Send(0,addr);for(i = 0;i < (num*2);i++)Send(1,*(pt++));}函数名称：Draw_PM功能：在整个屏幕上画一个图片参数：ptr--指向保存图片位置的指针返回值：无********************************************/ void Draw_PM(const uchar *ptr){uchar i,j,k;Send(0,0x34); //打开扩展指令集i = 0x80;for(j = 0;j < 32;j++){Send(0,i++);Send(0,0x80);for(k = 0;k < 16;k++){Send(1,*ptr++);}}i = 0x80;for(j = 0;j < 32;j++){Send(0,i++);Send(0,0x88);for(k = 0;k < 16;k++){Send(1,*ptr++);}}Send(0,0x36); //打开绘图显示Send(0,0x30); //回到基本指令集}/*******************************************函数名称：Draw_TX功能：在液晶上描绘一个16*16的图形参数：Y addr--Y地址，Xaddr--X地址dp--指向保存图形数据的指针返回值：无********************************************/ void Draw_TX(uchar Y addr,uchar Xaddr,const uchar * dp) {uchar j;uchar k = 0;Send(0,0x34); //使用扩展指令集，关闭绘图显示for(j = 0;j < 16;j++){Send(0,Y addr++); //Y地址Send(0,Xaddr); //X地址Send(1,dp[k++]); //送两个字节的显示数据Send(1,dp[k++]);}Send(0,0x36); //打开绘图显示Send(0,0x30); //回到基本指令集模式}/*******************************************函数名称：Disp_SZ功能：显示一个两位数字参数：addr--显示地址数字--显示的数字返回值：无********************************************/void Disp_SZ(uchar addr,uchar shuzi){uchar tmp0,tmp1;tmp0 = shuzi / 10;tmp1 = shuzi % 10;Send(0,addr);Send(1,numtable[tmp0]);Send(1,numtable[tmp1]);}//12864.hvoid Send(unsigned char type,unsigned char transdata);void Ini_Lcd(void);void Clear_GDRAM(void);void Disp_HZ(unsigned char addr,const unsigned char * pt,unsigned char num); void Draw_PM(const unsigned char *ptr);void Draw_TX(unsigned char Y addr,unsigned char Xaddr,const unsigned char * dp) ; void Disp_SZ(unsigned char addr,unsigned char shuzi);void delay_Nus(unsigned int n);void delay_Nms(unsigned int n);void delay_1ms(void);。

基于MSP430G2553的函数信号发生器

#include <msp430g2553.h>#include "lcd1602_4.h"#define LDAC_LOW P2OUT &= ~BIT1; //p2.1作为#define LDAC_HIGH P2OUT |= BIT1;#define LOAD_HIGH P1OUT |= BIT0;#define LOAD_LOW P1OUT &= ~BIT0;unsigned char TLVBUF[]={0,0};void TxSPI1(unsigned char c);void TxSPInbytes(unsigned char *p,unsigned char cnt);void TxTLV5620(unsigned char ch,unsigned char data);char xianshi[4]= " ",pinlv[7] = "hello!";unsigned long int p2Keytime1=0, p2Keytime2=0, k,i;unsigned long f_out=1;int a=100, b=99, freq2=123, freq1=123, WaveSelect=0;char *p1,*p2,*pa;int flag = 1,k1,k2,k3,k4;char saw[50]={0x00,0x05,0x0a,0x0f,0x14,0x19,0x1e,0x23,0x28,0x2d,0x32,0x37,0x3c,0x041,0x46,0x4b,0x50,0x55,0x5a,0x5f,0x64,0x69,0x61,0x73,0x78,0x7d,0x82,0x87,0x8c,0x91,0x96,0x9b, 0xa0,0xa5,0xaa,0xaf,0xb4,0xb9,0xbe,0xc3,0xc8,0xcd,0xd2,0xd7,0xdc,0xe1,0xe6,0xeb,0xf0,0xf5};char squ[50]={0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x0 0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00};char tri[50]={0x00,0x0a,0x14,0x1e,0x28,0x32,0x3c,0x46,0x50,0x5a,0x64,0x61,0x78,0x82,0x8c,0x96,0xa0,0xaa,0xb4,0xbe,0xc8,0xd2,0xdc,0xe6,0xf0,0xe6,0xdc,0xd2,0xc8,0xbe,0xb4,0xa0,0xaa,0x96,0x8c,0x82,0x78,0x61,0x64,0x5a, 0x50,0x46,0x3c,0x32,0x28,0x1e,0x14,0x0a};char sin[50]={0x64,0x5a,0x4e,0x44,0x3b,0x30,0x28,0x21,0x19,0x15,0x11,0x0e,0x0d,0x0c,0x0e,0x11,0x15,0x19,0x21,0x28,0x30,0x3b,0x44,0x4e,0x5a,0x64,0x6e,0x79,0x84,0x8e,0x97,0xa0,0xa7,0xae,0xb3,0xb7,0xba,0xbb,0xba,0xb7,0xb3,0xae,0xa7,0xa0,0x97,0x8e,0x84,0x79,0x6e,0x64};void main(void){WDTCTL = WDTPW + WDTHOLD; // Stop WDTdo{BCSCTL1 |=CALBC1_16MHZ; //Configure DCO: 设置范围可以改变相应的频率DCOCTL |=CALDCO_16MHZ; //Configure DCO:设置频率16MHZBCSCTL3 |=XT2S_2; //Configure XT2:选择2-16MHZBCSCTL3 |=LFXT1S_2; //Configure LFXT1:选择VLO 超低频IFG1 &= ~OFIFG; //清除振荡错误标志for(i = 0; i < 1000; i++)_NOP(); //延时等待}while ((IFG1 & OFIFG) != 0); //如果标志为1继续循环等待IFG1 &= ~OFIFG; // Clear OSCFault flag//BCSCTL3 |=LFXT1S_2;//ACLK=VLOBCSCTL2 |=SELM_1+DIVM_0;//MCLK=DCO 不分频BCSCTL2 &=~SELS; //SELS=1是前提，使SMCLK=DC0BCSCTL2 |=DIVS_0; //DIVS=1是前提，使SMCLK=8M 2分频//按键中断配置P1DIR |= BIT0+BIT5; // P1.0 output// P1.5 outputP1DIR&=~(BIT6+BIT7);P1IES|=BIT6+BIT7;P1IE|=BIT6+BIT7;P2DIR&=~(BIT2+BIT3);//P2.3 P2.->INPUT//P2SEL&=~(BIT6+BIT7);//关闭第二功能P2IES|=BIT2+BIT3;//下降沿触发P2IE|=BIT2+BIT3;//开中断//SPI信号输出端口设置P1OUT = 0x00; // P1 setup for LED & reset outputP1DIR |= BIT0 + BIT5;P1SEL = BIT1 + BIT2 + BIT4;P1SEL2 = BIT1 + BIT2 + BIT4;//SPI配置UCA0CTL1|=UCSWRST;UCA0CTL0 |= UCCKPL + UCMSB + UCMST + UCSYNC; // 3-pin, 8-bit SPI master UCCKPL为时钟极性控制位// 置位SSEL0与SSEL1时钟的类型，11则为SMCLK；CKPL为时钟极性控制位，0时UCLKI信号// 与UCLK信号极性相同，1时UCLKI信号与UCLK信号极性相反。

msp430g2553nrf24l01（msp430g2553nrf24l01）

msp430g2553 nrf24l01（msp430g2553 nrf24l01）#包括“io430。

”#包括“API。

”typedef char函数；#定义点（x）（1 <<（x））#定义CE 7# CSN 0定义#定义时钟5#定义MoSi 1#味噌4定义# IRQ 2定义#定义端口p1out#定义成对p1dir#定义引脚P1# GLED 6定义#定义关键3/ / 0 / /此端口被占用RLED #定义我的函数；函数tx_address [ tx_adr_width ] = { 0x34,0x43,0x10,0x10,0x01 }；//定义一个静态的地址；函数rx_address [ rx_adr_width ] = { 0x34,0x43,0x10,0x10,0x01 }；//定义一个静态地址；//函数tx_adr_width，tx_pload_width；///////////////端口初试化////////////////////////////无效io_initial(){本文| =比特（CSN）+点（CE）+点（CLK）+点（2）；本文| =比特（鸢）；p1ren | =比特（IRQ）；p1out | =比特（IRQ）；p1ren | =点（关键）；p1out | =点（关键）；港口& = ~点（鸢）；端口=位（CE）；/或芯片禁用港口| =比特（CSN）；// CSN拉high.disable操作端口=位（CLK）；/时钟是低的}/ /*********************************************************** *******************************/ /延时函数/ /*********************************************************** *******************************无效delay_us（unsigned int n）{为（n；0；n）；}//////////////////初始化时钟虚空（void）FaultRoutine而（1）；//异常挂起}configclocks虚空（void）{如果（calbc1_1mhz = = 0xff | | caldco_1mhz = = 0xff）faultroutine()；//如果校准数据擦除/ /运行faultroutine()bcsctl1 = calbc1_1mhz；//设置范围dcoctl = caldco_1mhz；//设置DCO步+调制bcsctl3 | = lfxt1s_2；// LFXT1 = VLOifg1 & = ~ ofifg；//清OSCFault旗bcsctl2 = 0；// MCLK SMCLK DCO = =}////////////// LED开启或关闭//////////////无效gled_off(){港口& = ~点（鸢）；}无效gled_on(){港口| =比特（鸢）；}无效gled_ray(){港口^ =比特（鸢）；}///////////////得到IRQ //////////////////////// get_key函数（void）{返回（引脚（位（键）））；/////////////////////////读写操作/////////////////////////////////////spi_rw函数（函数的字节）{bit_ctr函数；端口=（位（CLK））；对于（bit_ctr = 0；bit_ctr＜8；bit_ctr + +）/输出8位{如果（字节和0x80）港口| =点（2）；其他的{港口& = ~（比特（MOSI））；//输出“字节”，MSB 2}字节（byte << 1）；/ /移一点到最高位..港口| =比特（CLK）；//设置时钟高..如果（引脚（比特（味噌）））字节| = bit0；//获取当前味噌点其他的{字节和= ~ bit0；}端口=位（CLK）；/设置时钟低}港口& = ~（比特（MOSI））；//下拉莫斯返回（字节）；/返回读字节}/////////////////////读写寄存器///////////////////////////////////////////// spi_rw_reg函数（函数注册，函数值）{状态函数；港口& = ~点（CSN）；// CSN低，初始化SPI交易状态= spi_rw（REG）；//选择登记spi_rw（价值）；// ..写它的价值..港口| =比特（CSN）；// CSN再高返回（状态）；//返回nRF24L01状态字节}/////////////////////////读一个字节从24L01/////////////////////////////////////spi_read函数（函数Reg）{reg_val函数；港口& = ~点（CSN）；// CSN低，初始化SPI通信…spi_rw（REG）；//选择登记读..reg_val = spi_rw（0）；// ..然后读registervalue 港口| =比特（CSN）；// CSN高，终止的SPI通信返回（reg_val）；//返回登记的价值}/////////////////////////读取RX的载荷，RX / Tx地址//////////////////////////spi_read_buf函数（函数的函数的函数注册，* pbuf，字节）{函数的状态，byte_ctr；港口& = ~点（CSN）；//设置CSN低，初始化SPI传输状态= spi_rw（REG）；//选择登记写和读状态字节对于（byte_ctr = 0；byte_ctr <字节；byte_ctr + +）byte_ctr pbuf [ ] = spi_rw（0）；/ / perform spi _ rw read bytes from nrf24l01port | = bits (csn); / / seen csn high againreturn (status); / / return nrf24l01 status byte}/ / / / / / / / / / / / / / / / / / / / / / / / / write tx payload, rx / tx address / / / / / / / / / / / / / / / / / / / / / / // / / / / / / / / /uchar spi _ write _ buf (uchar reg, uchar * pbuf, uchar bytes) {uchar status byte _ ctr;port & = ~ bits (csn); / / seen csn low practice spi tranactionstatus = spi _ rw (reg); / / select register to write to and read status bytefor (byte _ ctr = 0; byte _ ctr < bytes; byte _ ctr + +) / / then write all bytes in buffer (* pbuf)spi _ rw (* pbuf + +);port | = bits (csn); / / seen csn high againreturn (status); / / return nrf24l01 status byte}/ / * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * */ / nrf24l01初始化/ / * * * * * * * * * * * * * * * * * * * * * * * * * * * * ** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * /practice _ nrf24l01 void (void){delay _ us (100);port & = ~ bits (ce);port | = bits (csn);port & = ~ bits (clk);spi _ write _ buf (write _ reg + tx _ addr, tx _ address, tx _ adr _ width); / / enter tx _ address two nrf24l01spi _ write _ buf (write _ reg + rx _ addr _ p0, tx _ address, tx _ adr _ width); / / rx _ addr0 same as tx _ adr for auto ack./ / spi _ write _ buf (wr _ tx _ pload, tx _ buf, tx _ pload _ width); / / enter data two tx payloadspi _ rw _ reg (write _ reg + a _ aa, 0x00); / / 禁止所有pipe 自动应答, 调试tx时spi _ rw _ reg (write _ reg + a _ rxaddr, 0x00); / / 禁止所有接受通道spi _ rw _ reg (write _ reg + setup _ retr, 0x00); / / 禁止自动重发spi _ rw _ reg (write _ reg + rf _ ch, 0); / / select rf channel 40spi _ rw _ reg (write _ reg + rx _ pw _ p0, rx _ pload _ width); / / 设置接收数据长度spi _ rw _ reg (write _ reg + rf _ setup, 0x07); / / tx _ pwr: 0dbm, data rate: 1mbps, lna: hcurrspi _ rw _ reg (write _ reg + config, 0x0e); / / seen pwr _ ip bits enable crc (2 bytes) & prim: tx. max _ rt & tx _ ds enabled...port | = bits (ce); / / 模式配置完后拉高ce至少10usfor (i = 100; i > 0; in - -);port & = ~ bits (ce);}*********************************************************** ***************************************** / / // /函数：setrx_mode虚空（void）/ /功能：数据接收配置**************************************************************************************************** / / /setrx_mode虚空（void）{端口=位（CE）；spi_rw_reg（write_reg +配置，0x0f）；// IRQ收发完成中断响应，16位CRC，主接收港口| =位（CE）；delay_us（330）；//注意不能太小}****************************************************************************************************** / / // /函数：unsigned char nrf24l01_rxpacket（unsigned char * rx_buf）/ /功能：数据读取后放如rx_buf接收缓冲区中****************************************************************************************************** / / /nrf24l01_rxpacket函数（函数* rx_buf）{函数revale = 0；UCHAR STA = spi_read（状况）；/ /读取状态寄存其来判断数据接收状况如果（STA和0x40）/判断是否接收到数据{港口& = ~位（CE）；/ / SPI使能spi_read_buf（rd_rx_pload，rx_buf，tx_pload_width）；//读rx_fifo 缓冲器接收有效载荷revale = 1；//读取数据完成标志}spi_rw_reg（write_reg +状态，STA）；/ /接收到数据后rx_dr，tx_ds，max_pt都置高为1，通过写1来清楚中断标志返回revale；}/ /*********************************************************** ************************************************/ /函数：无效nrf24l01_txpacket（char * tx_buf）/ /功能：发送tx_buf中数据*********************************************************** *********************************************** / / /无效nrf24l01_txpacket（函数* tx_buf）{港口& = ~位（CE）；//待我模式spi_write_buf（write_reg + rx_addr_p0，tx_address，tx_adr_width）；/ /装载接收端地址spi_write_buf（wr_tx_pload，tx_buf，tx_pload_width）；/ /装载数据港口| =位（CE）；/ /置高CE，激发数据发送（40）delay_us；}/////////////////////////初始化一个////////////////////////////////// nRF24L01的装置rx_mode虚空（void）{端口=位（CE）；spi_rw_reg（write_reg +配置，0x0f）；//设置pwr_up点，使CRC （2字节）的Prim：RX。

1、下载文档前请自行甄别文档内容的完整性，平台不提供额外的编辑、内容补充、找答案等附加服务。
2、"仅部分预览"的文档,不可在线预览部分如存在完整性等问题,可反馈申请退款(可完整预览的文档不适用该条件!)。
3、如文档侵犯您的权益，请联系客服反馈,我们会尽快为您处理(人工客服工作时间：9:00-18:30)。

/* ============================================================================ *//* Copyright (c) 2014, Texas Instruments Incorporated */ /* All rights reserved. *//* *//* Redistribution and use in source and binary forms, with or without */ /* modification, are permitted provided that the following conditions */ /* are met: *//* *//* * Redistributions of source code must retain the above copyright */ /* notice, this list of conditions and the following disclaimer. */ /* *//* * Redistributions in binary form must reproduce the above copyright */ /* notice, this list of conditions and the following disclaimer in the */ /* documentation and/or other materials provided with the distribution. */ /* *//* * Neither the name of Texas Instruments Incorporated nor the names of */ /* its contributors may be used to endorse or promote products derived */ /* from this software without specific prior written permission. */ /* *//* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" *//* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */ /* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */ /* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */ /* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */ /* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */ /* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *//* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */ /* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */ /* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */ /* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ /* ============================================================================ *//********************************************************************** Standard register and bit definitions for the Texas Instruments* MSP430 microcontroller.** This file supports assembler and C development for* MSP430G2553 devices.** Texas Instruments, Version 1.1** Rev. 1.0, Setup* Rev. 1.1, added additional Cal Data Labels*********************************************************************/#ifndef __MSP430G2553#define __MSP430G2553#define __MSP430_HEADER_VERSION__ 1127#ifdef __cplusplusextern"C" {#endif/*----------------------------------------------------------------------------*//* PERIPHERAL FILE MAP *//*----------------------------------------------------------------------------*//* External references resolved by a device-specific linker command file */#define SFR_8BIT(address) externvolatileunsignedchar address#define SFR_16BIT(address) externvolatileunsignedint address#define SFR_32BIT(address) externvolatileunsignedlong address/************************************************************* STANDARD BITS************************************************************/#define BIT0 (0x0001)#define BIT1 (0x0002)#define BIT2 (0x0004)#define BIT3 (0x0008)#define BIT4 (0x0010)#define BIT5 (0x0020)#define BIT6 (0x0040)#define BIT7 (0x0080)#define BIT8 (0x0100)#define BIT9 (0x0200)#define BITA (0x0400)#define BITB (0x0800)#define BITC (0x1000)#define BITD (0x2000)#define BITE (0x4000)#define BITF (0x8000)/************************************************************* STATUS REGISTER BITS************************************************************/#define C (0x0001)#define Z (0x0002)#define N (0x0004)#define V (0x0100)#define GIE (0x0008)#define CPUOFF (0x0010)#define OSCOFF (0x0020)#define SCG0 (0x0040)#define SCG1 (0x0080)/* Low Power Modes coded with Bits 4-7 in SR */#ifdef __ASM_HEADER__ /* Begin #defines for assembler */#define LPM0 (CPUOFF)#define LPM1 (SCG0+CPUOFF)#define LPM2 (SCG1+CPUOFF)#define LPM3 (SCG1+SCG0+CPUOFF)#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)/* End #defines for assembler */#else/* Begin #defines for C */#define LPM0_bits (CPUOFF)#define LPM1_bits (SCG0+CPUOFF)#define LPM2_bits (SCG1+CPUOFF)#define LPM3_bits (SCG1+SCG0+CPUOFF)#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)#include"in430.h"#include<intrinsics.h>#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */#endif/* End #defines for C *//************************************************************* PERIPHERAL FILE MAP************************************************************//************************************************************* SPECIAL FUNCTION REGISTER ADDRESSES + CONTROL BITS************************************************************/SFR_8BIT(IE1); /* Interrupt Enable 1 */#define WDTIE (0x01) /* Watchdog Interrupt Enable */#define OFIE (0x02) /* Osc. Fault Interrupt Enable */ #define NMIIE (0x10) /* NMI Interrupt Enable */#define ACCVIE (0x20) /* Flash Access Violation Interrupt Enable */SFR_8BIT(IFG1); /* Interrupt Flag 1 */#define WDTIFG (0x01) /* Watchdog Interrupt Flag */#define OFIFG (0x02) /* Osc. Fault Interrupt Flag */#define PORIFG (0x04) /* Power On Interrupt Flag */#define RSTIFG (0x08) /* Reset Interrupt Flag */#define NMIIFG (0x10) /* NMI Interrupt Flag */SFR_8BIT(IE2); /* Interrupt Enable 2 */#define UC0IE IE2#define UCA0RXIE (0x01)#define UCA0TXIE (0x02)#define UCB0RXIE (0x04)#define UCB0TXIE (0x08)SFR_8BIT(IFG2); /* Interrupt Flag 2 */#define UC0IFG IFG2#define UCA0RXIFG (0x01)#define UCA0TXIFG (0x02)#define UCB0RXIFG (0x04)#define UCB0TXIFG (0x08)/************************************************************* ADC10************************************************************/#define__MSP430_HAS_ADC10__ /* Definition to show that Module is available */SFR_8BIT(ADC10DTC0); /* ADC10 Data Transfer Control 0 */ SFR_8BIT(ADC10DTC1); /* ADC10 Data Transfer Control 1 */ SFR_8BIT(ADC10AE0); /* ADC10 Analog Enable 0 */SFR_16BIT(ADC10CTL0); /* ADC10 Control 0 */SFR_16BIT(ADC10CTL1); /* ADC10 Control 1 */SFR_16BIT(ADC10MEM); /* ADC10 Memory */SFR_16BIT(ADC10SA); /* ADC10 Data Transfer Start Address *//* ADC10CTL0 */#define ADC10SC (0x001) /* ADC10 Start Conversion */#define ENC (0x002) /* ADC10 Enable Conversion */#define ADC10IFG (0x004) /* ADC10 Interrupt Flag */#define ADC10IE (0x008) /* ADC10 Interrupt Enalbe */#define ADC10ON (0x010) /* ADC10 On/Enable */#define REFON (0x020) /* ADC10 Reference on */#define REF2_5V (0x040) /* ADC10 Ref 0:1.5V / 1:2.5V */#define MSC (0x080) /* ADC10 Multiple SampleConversion */ #define REFBURST (0x100) /* ADC10 Reference Burst Mode */#define REFOUT (0x200) /* ADC10 Enalbe output of Ref. */#define ADC10SR (0x400) /* ADC10 Sampling Rate 0:200ksps / 1:50ksps */#define ADC10SHT0 (0x800) /* ADC10 Sample Hold Select Bit: 0 */ #define ADC10SHT1 (0x1000) /* ADC10 Sample Hold Select Bit: 1 */ #define SREF0 (0x2000) /* ADC10 Reference Select Bit: 0 */ #define SREF1 (0x4000) /* ADC10 Reference Select Bit: 1 */ #define SREF2 (0x8000) /* ADC10 Reference Select Bit: 2 */ #define ADC10SHT_0 (0*0x800u) /* 4 x ADC10CLKs */#define ADC10SHT_1 (1*0x800u) /* 8 x ADC10CLKs */#define ADC10SHT_2 (2*0x800u) /* 16 x ADC10CLKs */#define ADC10SHT_3 (3*0x800u) /* 64 x ADC10CLKs */#define SREF_0 (0*0x2000u) /* VR+ = AVCC and VR- = AVSS */#define SREF_1 (1*0x2000u) /* VR+ = VREF+ and VR- = AVSS */#define SREF_2 (2*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */#define SREF_3 (3*0x2000u) /* VR+ = VEREF+ and VR- = AVSS */#define SREF_4 (4*0x2000u) /* VR+ = AVCC and VR- = VREF-/VEREF- */#define SREF_5 (5*0x2000u) /* VR+ = VREF+ and VR- = VREF-/VEREF- */#define SREF_6 (6*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- */#define SREF_7 (7*0x2000u) /* VR+ = VEREF+ and VR- = VREF-/VEREF- *//* ADC10CTL1 */#define ADC10BUSY (0x0001) /* ADC10 BUSY */#define CONSEQ0 (0x0002) /* ADC10 Conversion Sequence Select 0 */#define CONSEQ1 (0x0004) /* ADC10 Conversion Sequence Select 1 */#define ADC10SSEL0 (0x0008) /* ADC10 Clock Source Select Bit: 0 */#define ADC10SSEL1 (0x0010) /* ADC10 Clock Source Select Bit: 1 */#define ADC10DIV0 (0x0020) /* ADC10 Clock Divider Select Bit: 0 */#define ADC10DIV1 (0x0040) /* ADC10 Clock Divider Select Bit: 1 */#define ADC10DIV2 (0x0080) /* ADC10 Clock Divider Select Bit: 2 */#define ISSH (0x0100) /* ADC10 Invert Sample Hold Signal */ #define ADC10DF (0x0200) /* ADC10 Data Format 0:binary 1:2's complement */#define SHS0 (0x0400) /* ADC10 Sample/Hold Source Bit: 0 */ #define SHS1 (0x0800) /* ADC10 Sample/Hold Source Bit: 1 */ #define INCH0 (0x1000) /* ADC10 Input Channel Select Bit: 0 */#define INCH1 (0x2000) /* ADC10 Input Channel Select Bit: 1 */#define INCH2 (0x4000) /* ADC10 Input Channel Select Bit: 2 */#define INCH3 (0x8000) /* ADC10 Input Channel Select Bit: 3 */#define CONSEQ_0 (0*2u) /* Single channel single conversion */#define CONSEQ_1 (1*2u) /* Sequence of channels */#define CONSEQ_2 (2*2u) /* Repeat single channel */#define CONSEQ_3 (3*2u) /* Repeat sequence of channels */#define ADC10SSEL_0 (0*8u) /* ADC10OSC */#define ADC10SSEL_1 (1*8u) /* ACLK */#define ADC10SSEL_2 (2*8u) /* MCLK */#define ADC10SSEL_3 (3*8u) /* SMCLK */#define ADC10DIV_0 (0*0x20u) /* ADC10 Clock Divider Select 0 */ #define ADC10DIV_1 (1*0x20u) /* ADC10 Clock Divider Select 1 */ #define ADC10DIV_2 (2*0x20u) /* ADC10 Clock Divider Select 2 */ #define ADC10DIV_3 (3*0x20u) /* ADC10 Clock Divider Select 3 */ #define ADC10DIV_4 (4*0x20u) /* ADC10 Clock Divider Select 4 */ #define ADC10DIV_5 (5*0x20u) /* ADC10 Clock Divider Select 5 */ #define ADC10DIV_6 (6*0x20u) /* ADC10 Clock Divider Select 6 */ #define ADC10DIV_7 (7*0x20u) /* ADC10 Clock Divider Select 7 */ #define SHS_0 (0*0x400u) /* ADC10SC */#define SHS_1 (1*0x400u) /* TA3 OUT1 */#define SHS_2 (2*0x400u) /* TA3 OUT0 */#define SHS_3 (3*0x400u) /* TA3 OUT2 */#define INCH_0 (0*0x1000u) /* Selects Channel 0 */#define INCH_1 (1*0x1000u) /* Selects Channel 1 */#define INCH_2 (2*0x1000u) /* Selects Channel 2 */#define INCH_3 (3*0x1000u) /* Selects Channel 3 */#define INCH_4 (4*0x1000u) /* Selects Channel 4 */#define INCH_5 (5*0x1000u) /* Selects Channel 5 */#define INCH_6 (6*0x1000u) /* Selects Channel 6 */#define INCH_7 (7*0x1000u) /* Selects Channel 7 */#define INCH_8 (8*0x1000u) /* Selects Channel 8 */#define INCH_9 (9*0x1000u) /* Selects Channel 9 */#define INCH_10 (10*0x1000u) /* Selects Channel 10 */#define INCH_11 (11*0x1000u) /* Selects Channel 11 */#define INCH_12 (12*0x1000u) /* Selects Channel 12 */#define INCH_13 (13*0x1000u) /* Selects Channel 13 */#define INCH_14 (14*0x1000u) /* Selects Channel 14 */#define INCH_15 (15*0x1000u) /* Selects Channel 15 *//* ADC10DTC0 */#define ADC10FETCH (0x001) /* This bit should normally be reset */#define ADC10B1 (0x002) /* ADC10 block one */#define ADC10CT (0x004) /* ADC10 continuous transfer */#define ADC10TB (0x008) /* ADC10 two-block mode */#define ADC10DISABLE (0x000) /* ADC10DTC1 *//************************************************************* Basic Clock Module************************************************************/#define__MSP430_HAS_BC2__ /* Definition to show that Module is available */SFR_8BIT(DCOCTL); /* DCO Clock Frequency Control */ SFR_8BIT(BCSCTL1); /* Basic Clock System Control 1 */ SFR_8BIT(BCSCTL2); /* Basic Clock System Control 2 */ SFR_8BIT(BCSCTL3); /* Basic Clock System Control 3 */ #define MOD0 (0x01) /* Modulation Bit 0 */#define MOD1 (0x02) /* Modulation Bit 1 */#define MOD3 (0x08) /* Modulation Bit 3 */#define MOD4 (0x10) /* Modulation Bit 4 */#define DCO0 (0x20) /* DCO Select Bit 0 */#define DCO1 (0x40) /* DCO Select Bit 1 */#define DCO2 (0x80) /* DCO Select Bit 2 */#define RSEL0 (0x01) /* Range Select Bit 0 */#define RSEL1 (0x02) /* Range Select Bit 1 */#define RSEL2 (0x04) /* Range Select Bit 2 */#define RSEL3 (0x08) /* Range Select Bit 3 */#define DIVA0 (0x10) /* ACLK Divider 0 */#define DIVA1 (0x20) /* ACLK Divider 1 */#define XTS (0x40) /* LFXTCLK 0:Low Freq. / 1: High Freq. */#define XT2OFF (0x80) /* Enable XT2CLK */#define DIVA_0 (0x00) /* ACLK Divider 0: /1 */#define DIVA_1 (0x10) /* ACLK Divider 1: /2 */#define DIVA_2 (0x20) /* ACLK Divider 2: /4 */#define DIVA_3 (0x30) /* ACLK Divider 3: /8 */#define DIVS0 (0x02) /* SMCLK Divider 0 */#define DIVS1 (0x04) /* SMCLK Divider 1 */#define SELS (0x08) /* SMCLK Source Select 0:DCOCLK / 1:XT2CLK/LFXTCLK */#define DIVM0 (0x10) /* MCLK Divider 0 */#define DIVM1 (0x20) /* MCLK Divider 1 */#define SELM0 (0x40) /* MCLK Source Select 0 */#define SELM1 (0x80) /* MCLK Source Select 1 */#define DIVS_0 (0x00) /* SMCLK Divider 0: /1 */#define DIVS_1 (0x02) /* SMCLK Divider 1: /2 */#define DIVS_2 (0x04) /* SMCLK Divider 2: /4 */#define DIVS_3 (0x06) /* SMCLK Divider 3: /8 */#define DIVM_0 (0x00) /* MCLK Divider 0: /1 */#define DIVM_1 (0x10) /* MCLK Divider 1: /2 */#define DIVM_2 (0x20) /* MCLK Divider 2: /4 */#define DIVM_3 (0x30) /* MCLK Divider 3: /8 */#define SELM_0 (0x00) /* MCLK Source Select 0: DCOCLK */ #define SELM_1 (0x40) /* MCLK Source Select 1: DCOCLK */ #define SELM_2 (0x80) /* MCLK Source Select 2:XT2CLK/LFXTCLK */#define SELM_3 (0xC0) /* MCLK Source Select 3: LFXTCLK */ #define LFXT1OF (0x01) /* Low/high Frequency Oscillator Fault Flag */#define XT2OF (0x02) /* High frequency oscillator 2 fault flag */#define XCAP0 (0x04) /* XIN/XOUT Cap 0 */#define XCAP1 (0x08) /* XIN/XOUT Cap 1 */#define LFXT1S0 (0x10) /* Mode 0 for LFXT1 (XTS = 0) */#define LFXT1S1 (0x20) /* Mode 1 for LFXT1 (XTS = 0) */#define XT2S1 (0x80) /* Mode 1 for XT2 */#define XCAP_0 (0x00) /* XIN/XOUT Cap : 0 pF */#define XCAP_1 (0x04) /* XIN/XOUT Cap : 6 pF */#define XCAP_2 (0x08) /* XIN/XOUT Cap : 10 pF */#define XCAP_3 (0x0C) /* XIN/XOUT Cap : 12.5 pF */#define LFXT1S_0 (0x00) /* Mode 0 for LFXT1 : Normal operation */#define LFXT1S_1 (0x10) /* Mode 1 for LFXT1 : Reserved */#define LFXT1S_2 (0x20) /* Mode 2 for LFXT1 : VLO */#define LFXT1S_3 (0x30) /* Mode 3 for LFXT1 : Digital input signal */#define XT2S_0 (0x00) /* Mode 0 for XT2 : 0.4 - 1 MHz */ #define XT2S_1 (0x40) /* Mode 1 for XT2 : 1 - 4 MHz */#define XT2S_2 (0x80) /* Mode 2 for XT2 : 2 - 16 MHz */#define XT2S_3 (0xC0) /* Mode 3 for XT2 : Digital input signal *//************************************************************* Comparator A************************************************************/#define__MSP430_HAS_CAPLUS__ /* Definition to show that Module is available */SFR_8BIT(CACTL1); /* Comparator A Control 1 */SFR_8BIT(CACTL2); /* Comparator A Control 2 */SFR_8BIT(CAPD); /* Comparator A Port Disable */#define CAIFG (0x01) /* Comp. A Interrupt Flag */#define CAIE (0x02) /* Comp. A Interrupt Enable */#define CAIES (0x04) /* Comp. A Int. Edge Select: 0:rising / 1:falling */#define CAON (0x08) /* Comp. A enable */#define CAREF0 (0x10) /* Comp. A Internal Reference Select 0 */#define CAREF1 (0x20) /* Comp. A Internal Reference Select 1 */#define CARSEL (0x40) /* Comp. A Internal Reference Enable */#define CAEX (0x80) /* Comp. A Exchange Inputs */#define CAREF_0 (0x00) /* Comp. A Int. Ref. Select 0 : Off */#define CAREF_1 (0x10) /* Comp. A Int. Ref. Select 1 :0.25*Vcc */#define CAREF_2 (0x20) /* Comp. A Int. Ref. Select 2 : 0.5*Vcc */#define CAREF_3 (0x30) /* Comp. A Int. Ref. Select 3 : Vt*/ #define CAOUT (0x01) /* Comp. A Output */#define CAF (0x02) /* Comp. A Enable Output Filter */ #define P2CA0 (0x04) /* Comp. A +Terminal Multiplexer */#define P2CA1 (0x08) /* Comp. A -Terminal Multiplexer */ #define P2CA2 (0x10) /* Comp. A -Terminal Multiplexer */ #define P2CA3 (0x20) /* Comp. A -Terminal Multiplexer */ #define P2CA4 (0x40) /* Comp. A +Terminal Multiplexer */ #define CASHORT (0x80) /* Comp. A Short + and - Terminals */ #define CAPD0 (0x01) /* Comp. A Disable Input Buffer of Port Register .0 */#define CAPD1 (0x02) /* Comp. A Disable Input Buffer of Port Register .1 */#define CAPD2 (0x04) /* Comp. A Disable Input Buffer of Port Register .2 */#define CAPD3 (0x08) /* Comp. A Disable Input Buffer of Port Register .3 */#define CAPD4 (0x10) /* Comp. A Disable Input Buffer of Port Register .4 */#define CAPD5 (0x20) /* Comp. A Disable Input Buffer of Port Register .5 */#define CAPD6 (0x40) /* Comp. A Disable Input Buffer of Port Register .6 */#define CAPD7 (0x80) /* Comp. A Disable Input Buffer of Port Register .7 *//************************************************************** Flash Memory*************************************************************/#define__MSP430_HAS_FLASH2__ /* Definition to show that Module is available */SFR_16BIT(FCTL1); /* FLASH Control 1 */SFR_16BIT(FCTL2); /* FLASH Control 2 */SFR_16BIT(FCTL3); /* FLASH Control 3 */#define FRKEY (0x9600) /* Flash key returned by read */#define FWKEY (0xA500) /* Flash key for write */#define FXKEY (0x3300) /* for use with XOR instruction */ #define ERASE (0x0002) /* Enable bit for Flash segment erase */#define MERAS (0x0004) /* Enable bit for Flash mass erase */ #define WRT (0x0040) /* Enable bit for Flash write */#define BLKWRT (0x0080) /* Enable bit for Flash segment write */#define SEGWRT (0x0080) /* old definition *//* Enable bit for Flash segment write */#define FN0 (0x0001) /* Divide Flash clock by 1 to 64 using FN0 to FN5 according to: */#define FN1 (0x0002) /* 32*FN5 + 16*FN4 + 8*FN3 + 4*FN2 + 2*FN1 + FN0 + 1 */#ifndef FN2#define FN2 (0x0004)#endif#ifndef FN3#define FN3 (0x0008)#endif#ifndef FN4#define FN4 (0x0010)#endif#define FN5 (0x0020)#define FSSEL0 (0x0040) /* Flash clock select 0 *//* to distinguish from USART SSELx */#define FSSEL1 (0x0080) /* Flash clock select 1 */#define FSSEL_0 (0x0000) /* Flash clock select: 0 - ACLK */ #define FSSEL_1 (0x0040) /* Flash clock select: 1 - MCLK */ #define FSSEL_2 (0x0080) /* Flash clock select: 2 - SMCLK */ #define FSSEL_3 (0x00C0) /* Flash clock select: 3 - SMCLK */ #define BUSY (0x0001) /* Flash busy: 1 */#define KEYV (0x0002) /* Flash Key violation flag */#define ACCVIFG (0x0004) /* Flash Access violation flag */#define WAIT (0x0008) /* Wait flag for segment write */#define LOCK (0x0010) /* Lock bit: 1 - Flash is locked (read only) */#define EMEX (0x0020) /* Flash Emergency Exit */#define LOCKA (0x0040) /* Segment A Lock bit: read = 1 - Segment is locked (read only) */#define FAIL (0x0080) /* Last Program or Erase failed */ /************************************************************* DIGITAL I/O Port1/2 Pull up / Pull down Resistors************************************************************/#define__MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */#define__MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */SFR_8BIT(P1IN); /* Port 1 Input */SFR_8BIT(P1OUT); /* Port 1 Output */SFR_8BIT(P1DIR); /* Port 1 Direction */SFR_8BIT(P1IFG); /* Port 1 Interrupt Flag */SFR_8BIT(P1IES); /* Port 1 Interrupt Edge Select */ SFR_8BIT(P1IE); /* Port 1 Interrupt Enable */SFR_8BIT(P1SEL); /* Port 1 Selection */SFR_8BIT(P1SEL2); /* Port 1 Selection 2 */SFR_8BIT(P1REN); /* Port 1 Resistor Enable */SFR_8BIT(P2IN); /* Port 2 Input */SFR_8BIT(P2OUT); /* Port 2 Output */SFR_8BIT(P2DIR); /* Port 2 Direction */SFR_8BIT(P2IFG); /* Port 2 Interrupt Flag */SFR_8BIT(P2IES); /* Port 2 Interrupt Edge Select */ SFR_8BIT(P2IE); /* Port 2 Interrupt Enable */SFR_8BIT(P2SEL); /* Port 2 Selection */SFR_8BIT(P2SEL2); /* Port 2 Selection 2 */SFR_8BIT(P2REN); /* Port 2 Resistor Enable *//************************************************************* DIGITAL I/O Port3 Pull up / Pull down Resistors************************************************************/#define__MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */SFR_8BIT(P3IN); /* Port 3 Input */SFR_8BIT(P3OUT); /* Port 3 Output */SFR_8BIT(P3DIR); /* Port 3 Direction */SFR_8BIT(P3SEL); /* Port 3 Selection */SFR_8BIT(P3SEL2); /* Port 3 Selection 2 */SFR_8BIT(P3REN); /* Port 3 Resistor Enable *//************************************************************* Timer0_A3************************************************************/#define__MSP430_HAS_TA3__ /* Definition to show that Module is available */SFR_16BIT(TA0IV); /* Timer0_A3 Interrupt Vector Word */ SFR_16BIT(TA0CTL); /* Timer0_A3 Control */SFR_16BIT(TA0CCTL0); /* Timer0_A3 Capture/Compare Control 0 */SFR_16BIT(TA0CCTL1); /* Timer0_A3 Capture/Compare Control 1 */SFR_16BIT(TA0CCTL2); /* Timer0_A3 Capture/Compare Control 2 */SFR_16BIT(TA0R); /* Timer0_A3 Counter Register */ SFR_16BIT(TA0CCR0); /* Timer0_A3 Capture/Compare 0 */ SFR_16BIT(TA0CCR1); /* Timer0_A3 Capture/Compare 1 */ SFR_16BIT(TA0CCR2); /* Timer0_A3 Capture/Compare 2 *//* Alternate register names */#define TAIV TA0IV /* Timer A Interrupt Vector Word */ #define TACTL TA0CTL /* Timer A Control */#define TACCTL0 TA0CCTL0 /* Timer A Capture/Compare Control 0 */#define TACCTL1 TA0CCTL1 /* Timer A Capture/Compare Control 1 */#define TACCTL2 TA0CCTL2 /* Timer A Capture/Compare Control 2 */#define TAR TA0R /* Timer A Counter Register */#define TACCR0 TA0CCR0 /* Timer A Capture/Compare 0 */#define TACCR1 TA0CCR1 /* Timer A Capture/Compare 1 */#define TACCR2 TA0CCR2 /* Timer A Capture/Compare 2 */#define TAIV_ TA0IV_ /* Timer A Interrupt Vector Word */ #define TACTL_ TA0CTL_ /* Timer A Control */#define TACCTL0_ TA0CCTL0_ /* Timer A Capture/Compare Control 0 */#define TACCTL1_ TA0CCTL1_ /* Timer A Capture/Compare Control 1 */#define TACCTL2_ TA0CCTL2_ /* Timer A Capture/Compare Control 2 */#define TAR_ TA0R_ /* Timer A Counter Register */#define TACCR0_ TA0CCR0_ /* Timer A Capture/Compare 0 */#define TACCR1_ TA0CCR1_ /* Timer A Capture/Compare 1 */#define TACCR2_ TA0CCR2_ /* Timer A Capture/Compare 2 *//* Alternate register names 2 */#define CCTL0 TACCTL0 /* Timer A Capture/Compare Control 0 */#define CCTL1 TACCTL1 /* Timer A Capture/Compare Control 1 */#define CCTL2 TACCTL2 /* Timer A Capture/Compare Control 2 */#define CCR0 TACCR0 /* Timer A Capture/Compare 0 */#define CCR1 TACCR1 /* Timer A Capture/Compare 1 */#define CCR2 TACCR2 /* Timer A Capture/Compare 2 */#define CCTL0_ TACCTL0_ /* Timer A Capture/Compare Control 0 */#define CCTL1_ TACCTL1_ /* Timer A Capture/Compare Control 1 */#define CCTL2_ TACCTL2_ /* Timer A Capture/Compare Control 2 */#define CCR0_ TACCR0_ /* Timer A Capture/Compare 0 */#define CCR1_ TACCR1_ /* Timer A Capture/Compare 1 */#define CCR2_ TACCR2_ /* Timer A Capture/Compare 2 */#define TASSEL1 (0x0200) /* Timer A clock source select 1 */ #define TASSEL0 (0x0100) /* Timer A clock source select 0 */ #define ID1 (0x0080) /* Timer A clock input divider 1 */ #define ID0 (0x0040) /* Timer A clock input divider 0 */ #define MC1 (0x0020) /* Timer A mode control 1 */#define MC0 (0x0010) /* Timer A mode control 0 */#define TACLR (0x0004) /* Timer A counter clear */#define TAIE (0x0002) /* Timer A counter interrupt enable */#define TAIFG (0x0001) /* Timer A counter interrupt flag */ #define MC_0 (0*0x10u) /* Timer A mode control: 0 - Stop */ #define MC_1 (1*0x10u) /* Timer A mode control: 1 - Up to CCR0 */#define MC_2 (2*0x10u) /* Timer A mode control: 2 - Continous up */#define MC_3 (3*0x10u) /* Timer A mode control: 3 - Up/Down */#define ID_0 (0*0x40u) /* Timer A input divider: 0 - /1 */ #define ID_1 (1*0x40u) /* Timer A input divider: 1 - /2 */ #define ID_2 (2*0x40u) /* Timer A input divider: 2 - /4 */ #define ID_3 (3*0x40u) /* Timer A input divider: 3 - /8 */ #define TASSEL_0 (0*0x100u) /* Timer A clock source select: 0 - TACLK */#define TASSEL_1 (1*0x100u) /* Timer A clock source select: 1 - ACLK */#define TASSEL_2 (2*0x100u) /* Timer A clock source select: 2 - SMCLK */#define TASSEL_3 (3*0x100u) /* Timer A clock source select: 3 - INCLK */#define CM1 (0x8000) /* Capture mode 1 */#define CM0 (0x4000) /* Capture mode 0 */#define CCIS1 (0x2000) /* Capture input select 1 */#define CCIS0 (0x1000) /* Capture input select 0 */#define SCS (0x0800) /* Capture sychronize */#define SCCI (0x0400) /* Latched capture signal (read) */ #define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */#define OUTMOD2 (0x0080) /* Output mode 2 */#define OUTMOD1 (0x0040) /* Output mode 1 */#define OUTMOD0 (0x0020) /* Output mode 0 */#define CCIE (0x0010) /* Capture/compare interrupt enable */#define CCI (0x0008) /* Capture input signal (read) */#define OUT (0x0004) /* PWM Output signal if output mode 0 */#define COV (0x0002) /* Capture/compare overflow flag */ #define CCIFG (0x0001) /* Capture/compare interrupt flag */ #define OUTMOD_0 (0*0x20u) /* PWM output mode: 0 - output only */#define OUTMOD_1 (1*0x20u) /* PWM output mode: 1 - set */#define OUTMOD_2 (2*0x20u) /* PWM output mode: 2 - PWMtoggle/reset */#define OUTMOD_3 (3*0x20u) /* PWM output mode: 3 - PWM set/reset */#define OUTMOD_4 (4*0x20u) /* PWM output mode: 4 - toggle */#define OUTMOD_5 (5*0x20u) /* PWM output mode: 5 - Reset */#define OUTMOD_6 (6*0x20u) /* PWM output mode: 6 - PWM toggle/set */#define OUTMOD_7 (7*0x20u) /* PWM output mode: 7 - PWM reset/set */#define CCIS_0 (0*0x1000u) /* Capture input select: 0 - CCIxA */ #define CCIS_1 (1*0x1000u) /* Capture input select: 1 - CCIxB */ #define CCIS_2 (2*0x1000u) /* Capture input select: 2 - GND */ #define CCIS_3 (3*0x1000u) /* Capture input select: 3 - Vcc */ #define CM_0 (0*0x4000u) /* Capture mode: 0 - disabled */#define CM_1 (1*0x4000u) /* Capture mode: 1 - pos. edge */#define CM_2 (2*0x4000u) /* Capture mode: 1 - neg. edge */#define CM_3 (3*0x4000u) /* Capture mode: 1 - both edges */ /* T0_A3IV Definitions */#define TA0IV_NONE (0x0000) /* No Interrupt pending */#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */#define TA0IV_6 (0x0006) /* Reserved */#define TA0IV_8 (0x0008) /* Reserved */#define TA0IV_TAIFG (0x000A) /* TA0IFG *//************************************************************* Timer1_A3************************************************************/#define__MSP430_HAS_T1A3__ /* Definition to show that Module is available */SFR_16BIT(TA1IV); /* Timer1_A3 Interrupt Vector Word */ SFR_16BIT(TA1CTL); /* Timer1_A3 Control */SFR_16BIT(TA1CCTL0); /* Timer1_A3 Capture/Compare Control。