MEMORY存储芯片MT41J512M4JE-15E A中文规格书

Registers
16.4.1.7Source C Index/Destination C Index Parameter(SRC_DST_CIDX)
The source C index/destination C index parameter(SRC_DST_CIDX)specifies the value(2s complement) used for source address modification between each array in the3rd dimension and the value
(2s complement)used for destination address modification between each array in the3rd dimension.The SRC_DST_CIDX is shown in Figure16-41and described in Table16-21.
Figure16-41.Source C Index/Destination C Index Parameter(SRC_DST_CIDX) 3116
DSTCIDX
R/W-x
150
SRCCIDX
R/W-x
LEGEND:R/W=Read/Write;-n=value after reset;-x=value is indeterminate after reset
Table16-21.Source C Index/Destination C Index Parameter(SRC_DST_CIDX)Field Descriptions Bit Field Value Description
31-16DSTCIDX0-FFFFh Destination C index.Signed value specifying the byte address offset between frames within a
block(3rd dimension).Valid values range from–32768and32767.
15-0SRCCIDX0-FFFFh Source C index.Signed value specifying the byte address offset between frames within a block
(3rd dimension).Valid values range from–32768and32767.
16.4.1.8C Count Parameter(CCNT)
The C count parameter(CCNT)specifies the number of frames in a block.The CCNT is shown in
Figure16-42and described in Table16-22.
Figure16-42.C Count Parameter(CCNT)
3116
Reserved
R/W-x
150
CCNT
R/W-x
LEGEND:R/W=Read/Write;-n=value after reset;-x=value is indeterminate after reset
Table16-22.C Count Parameter(CCNT)Field Descriptions Bit Field Value Description
31-16Reserved0Reserved
15-0CCNT0-FFFFh C counter.Unsigned value specifying the number of frames in a block,where a frame is BCNT
arrays of ACNT bytes.Valid values range from1to65535.
Registers 16.4.2.2Error Registers
The EDMA3CC contains a set of registers that provide information on missed DMA and/or QDMA events, and instances when event queue thresholds are exceeded.If any of the bits in these registers is set,it results in the EDMA3CC generating an error interrupt.
16.4.2.2.1Event Missed Registers(EMR)
For a particular DMA channel,if a second event is received prior to the first event getting cleared/serviced, the bit corresponding to that channel is set/asserted in the event missed register(EMR).All trigger types are treated individually,that is,manual triggered(ESR),chain triggered(CER),and event triggered(ER) are all treated separately.The EMR bit for a channel is also set if an event on that channel encounters a NULL entry(or a NULL TR is serviced).If any EMR bit is set(and all errors,including bits in other error registers(QEMR,CCERR)were previously cleared),the EDMA3CC generates an error interrupt.See
Section16.2.9.4for details on EDMA3CC error interrupt generation.
The EMR is shown in Figure16-48and described in Table16-30.
Figure16-48.Event Missed Register(EMR)
31302928272625242322212019181716 E31E30E29E28E27E26E25E24E23E22E21E20E19E18E17E16 R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0 1514131211109876543210 E15E14E13E12E11E10E9E8E7E6E5E4E3E2E1E0 R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0R-0 LEGEND:R=Read only;-n=value after reset
Table16-30.Event Missed Register(EMR)Field Descriptions Bit Field Value Description
31-0E n Channel0-31event missed.E n is cleared by writing a1to the corresponding bit in the event missed clear
register(EMCR).
0No missed event.
1Missed event occurred.。