PWM信号发生器(verilog)

module pwmgen(clk,rst,ce,addr,write,wrdata,read,bytesel,rddata,pwm);
input clk,rst,ce;
input [1:0]addr;
input write,read;
input[31:0]wrdata;
output[31:0]rddata;
input[31:0]bytesel;
output pwm;
reg[31:0]clk_div_reg,duty_cycle_reg;
reg control_reg;
reg clk_div_reg_sel,duty_cycle_reg_sel,control_reg_sel;
reg[31:0]pwm_cnt,rddata;
reg pwm;
wire pwm_ena;
//地址译码
always@(addr)
begin
clk_div_reg_sel<=0;duty_cycle_reg_sel<=0;control_reg_sel<=0;
case(addr)
2'b00:clk_div_reg_sel<=1;
2'b01:duty_cycle_reg_sel<=1;
2'b10:control_reg_sel<=1;
default:
begin
clk_div_reg_sel<=0;
duty_cycle_reg_sel<=0;
control_reg_sel<=0;
end
endcase
end
//时钟寄存器
always@(posedge clk or negedge rst)
begin
if(rst==1'b0)
clk_div_reg=0;
else
begin
if(write & ce & clk_div_reg_sel)
begin
if(bytesel[0])
clk_div_reg[7:0]=wrdata[7:0];
if(bytesel[1])
clk_div_reg[15:8]=wrdata[15:8];
if(bytesel[2])
clk_div_reg[23:16]=wrdata[23:16];
if(bytesel[3])
clk_div_reg[31:24]=wrdata[31:24];
end
end
end
//周期占空比寄存器
always@(posedge clk or negedge rst)
begin
if(rst==1'b0)
duty_cycle_reg=0;
else
begin
if(write&ce&duty_cycle_reg_sel)
begin
if(bytesel[0])
duty_cycle_reg[7:0]=wrdata[7:0];
if(bytesel[1])
duty_cycle_reg[15:8]=wrdata[15:8];
if(bytesel[2])
duty_cycle_reg[23:16]=wrdata[23:16];
if(bytesel[3])
duty_cycle_reg[31:24]=wrdata[31:24];
end
end
end
//控制寄存器
always@(posedge clk or negedge rst)
begin
if(rst==1'b0)
control_reg=0;
else
begin
if(write & ce & control_reg_sel)
begin
if(bytesel[0])control_reg=wrdata[0];
end
end
end
//读寄存器
always@(addr or read or clk_div_reg or duty_cycle_reg or control_reg or ce)
begin
if(read & ce)
case(addr)
2'b00:rddata<=clk_div_reg;
2'b01:rddata<=duty_cycle_reg;
2'b10:rddata<=control_reg;
default:rddata=32'h8888;
endcase
end
assign pwm_en=control_reg;
//计数控制电路
always@(posedge clk or negedge rst)
begin
if(rst==1'b0)
pwm_cnt=0;
else
begin
if(pwm_en)
begin
if(pwm_cnt>=clk_div_reg)
pwm_cnt<=0;
else
pwm_cnt<=pwm_cnt+1;
end
else
pwm_cnt<=0;
end
end
//输出控制寄存器
always@(posedge clk or negedge rst)
begin
if(rst==1'b0);
else
begin
if(pwm_en)
begin
if(pwm_cnt<=duty_cycle_reg)
pwm<=1'b1;
else
pwm<=1'b0;
end
else
pwm<=1'b0;
end
end
endmodule