IS62WV51216

IS62WV51216ALL IS62WV51216BLLISSI®Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.512K x 16 LOW VOLTAGE,ULTRA LOW POWER CMOS STATIC RAMFEATURES•High-speed access time: 45ns, 55ns •CMOS low power operation – 36 mW (typical) operating – 12 µW (typical) CMOS standby •TTL compatible interface levels •Single power supply– 1.65V--2.2V V DD (62WV51216ALL)– 2.5V--3.6V V DD (62WV51216BLL)•Fully static operation: no clock or refresh required •Three state outputs•Data control for upper and lower bytes •Industrial temperature available •Lead-free availableDESCRIPTIONThe ISSI IS62WV51216ALL/ IS62WV51216BLL are high-speed, 8M bit static RAMs organized as 512K words by 16bits. It is fabricated using ISSI 's high-performance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields high-performance and low power consumption devices.When CS1 is HIGH (deselected) or when CS2 is LOW (deselected) or when CS1 is LOW, CS2 is HIGH and both LB and UB are HIGH, the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels.Easy memory expansion is provided by using Chip Enable and Output Enable inputs. The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB)access.The IS62WV51216ALL and IS62WV51216BLL are packaged in the JEDEC standard 48-pin mini BGA (7.2mm x 8.7mm)and 44-Pin TSOP (TYPE II).FUNCTIONAL BLOCK DIAGRAMFEBRUARY 2005IS62WV51216ALL, IS62WV51216BLL ISSI®PIN CONFIGURATIONS48-Pin mini BGA (7.2mm x 8.7mm)PIN DESCRIPTIONSA0-A18Address InputsI/O0-I/O15Data Inputs/OutputsCS1, CS2Chip Enable InputOE Output Enable InputWE Write Enable InputLB Lower-byte Control (I/O0-I/O7) UB Upper-byte Control (I/O8-I/O15) NC No ConnectionV DD PowerGND Ground1 2 3 4 5 6A B C D E F G HLB OE A0A1A2CS2I/O8UB A3A4CS1I/O0I/O9I/O10A5A6I/O1I/O2 GND I/O11A17A7I/O3V DD` V DD I/O12GND A16I/O4GND I/O14I/O13A14A15I/O5I/O6 I/O15NC A12A13WE I/O7A18A8A9A10A11NC1234567891011121314151617181920212244434241403938373635343332313029282726252423A4 A3 A2 A1 A0 CS1 I/O0 I/O1 I/O2 I/O3 V DD GND I/O4 I/O5 I/O6 I/O7 WE A16 A15 A14 A13 A12A5A6A7 OE UB LB I/O15 I/O14 I/O13 I/O12 GND V DD I/O11 I/O10 I/O9 I/O8 A18 A8A9A10 A11 A1744-Pin TSOP (Type II)2Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.BIS62WV51216ALL, IS62WV51216BLL ISSI®TRUTH TABLEI/O PINMode WE CS1CS2OE LB UB I/O0-I/O7I/O8-I/O15V DD Current Not Selected X H X X X X High-Z High-Z I SB1, I SB2X X L X X X High-Z High-Z I SB1, I SB2X X X X H H High-Z High-Z I SB1, I SB2 Output Disabled H L H H L X High-Z High-Z I CCH L H H X L High-Z High-Z I CCRead H L H L L H D OUT High-Z I CCH L H L H L High-Z D OUTH L H L L L D OUT D OUTWrite L L H X L H D IN High-Z I CCL L H X H L High-Z D INL L H X L L D IN D INOPERATING RANGE (V DD)Range Ambient Temperature IS62WV51216ALL (70ns)IS62WV51216BLL (55ns, 70ns)IS62WV51216BLL (45ns) Commercial0°C to +70°C 1.65V - 2.2V 2.5V - 3.6V 3.0 - 3.6VIndustrial–40°C to +85°C 1.65V - 2.2V 2.5V - 3.6VIS62WV51216ALL, IS62WV51216BLL ISSI®ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameter Value UnitV TERM Terminal Voltage with Respect to GND–0.2 to V DD+0.3VT BIAS Temperature Under Bias–40 to +85°CV DD V DD Related to GND–0.2 to +3.8VT STG Storage Temperature–65 to +150°CP T Power Dissipation 1.0WNote:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to thedevice. This is a stress rating only and functional operation of the device at these or any other conditions abovethose indicated in the operational sections of this specification is not implied. Exposure to absolute maximumrating conditions for extended periods may affect reliability.DC ELECTRICAL CHARACTERISTICS(Over Operating Range)Symbol Parameter Test Conditions V DD Min.Max.Unit V OH Output HIGH Voltage I OH = -0.1 mA 1.65-2.2V 1.4—VI OH = -1 mA 2.5-3.6V 2.2—VV OL Output LOW Voltage I OL = 0.1 mA 1.65-2.2V—0.2VI OL = 2.1 mA 2.5-3.6V—0.4VV IH Input HIGH Voltage 1.65-2.2V 1.4V DD + 0.2V2.5-3.6V 2.2V DD + 0.3VV IL(1)Input LOW Voltage 1.65-2.2V–0.20.4V2.5-3.6V–0.20.6VI LI Input Leakage GND ≤ V IN≤ V DD–11µAI LO Output Leakage GND ≤ V OUT≤ V DD, Outputs Disabled–11µA Notes:1.V IL (min.) = –1.0V for pulse width less than 10 ns.4Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.BIS62WV51216ALL, IS62WV51216BLL ISSI®CAPACITANCE(1)Symbol Parameter Conditions Max.UnitC IN Input Capacitance V IN = 0V8pFC OUT Input/Output Capacitance V OUT = 0V10pFNote:1.Tested initially and after any design or process changes that may affect these parameters.AC TEST CONDITIONSParameter62WV51216ALL62WV51216BLL(Unit)(Unit)Input Pulse Level0.4V to V DD-0.20.4V to V DD-0.3VInput Rise and Fall Times 5 ns5nsInput and Output Timing V REF V REFand Reference LevelOutput Load See Figures 1 and 2See Figures 1 and 262WV51216ALL62WV51216BLL(1.65V - 2.2V)(2.5V - 3.6V)R1(Ω)30701029R2(Ω)31501728V REF0.9V 1.5VV TM 1.8V 2.8VAC TEST LOADSFigure 1IS62WV51216ALL, IS62WV51216BLL ISSI®IS62WV51216ALL, POWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)Symbol Parameter Test Conditions Max.Unit70I C C V DD D ynamic O perating V DD=M ax.,Com.20m ASupply C urrent I OUT = 0 mA, f = f MAX Ind.25I CC1Operating S upply V DD = Max., CS1 = 0.2V Com.4m ACurrent WE = V DD – 0.2V Ind.4CS2 = V DD – 0.2V, f = 1MHZI SB1TTL Standby Current V DD=M ax.,Com.0.3m A(TTL Inputs)V IN = V IH or V IL Ind.0.3CS1 = V IH , CS2 = V IL,f = 1 MH ZORULB Control V DD = Max., V IN = V IH or V ILCS1 = V IL, f = 0, UB = V IH, LB = V IHI SB2CMOS S tandby V DD=M ax.,Com.15µACurrent (CMOS Inputs)CS1≥V DD – 0.2V,Ind.21CS2 ≤ 0.2V,typ.(1)3V IN≥V DD – 0.2V, orV IN≤0.2V, f = 0ORULB Control V DD = Max., CS1 = V IL, CS2=V IHV IN≥ V DD – 0.2V, or V IN≤ 0.2V, f = 0;UB / LB = V DD – 0.2VNote:.1. Typical values are measured at V DD = 1.8V, T A = 25o C and not 100% tested.6Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.BIS62WV51216ALL, IS62WV51216BLL ISSI®IS62WV51216BLL, POWER SUPPLY CHARACTERISTICS(1)(Over Operating Range)Symbol Parameter Test Conditions Max.Max.Max.Unit455570I C C V DD D ynamic O perating V DD=M ax.,Com.353025m ASupply C urrent I OUT = 0 mA, f = f MAX Ind.403530I CC1Operating S upply V DD = Max., CS1 = 0.2V Com.555m ACurrent WE = V DD – 0.2V Ind.555CS2 = V DD – 0.2V, f = 1MHZI SB1TTL Standby Current V DD=M ax.,Com.0.30.30.3m A(TTL Inputs)V IN = V IH or V IL Ind.0.30.30.3CS1 = V IH , CS2 = V IL,f = 1 MH ZORULB Control V DD = Max., V IN = V IH or V ILCS1 = V IL, f = 0, UB = V IH, LB = V IHI SB2CMOS S tandby V DD=M ax.,Com.202020µACurrent (CMOS Inputs)CS1≥V DD – 0.2V,Ind.252525CS2 ≤ 0.2V,typ. (2)444V IN≥V DD – 0.2V, orV IN≤0.2V, f = 0ORULB Control V DD = Max., CS1 = V IL, CS2=V IHV IN≥ V DD – 0.2V, or V IN≤ 0.2V, f = 0;UB / LB = V DD – 0.2VNote:1.At f = f MAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.2. Typical values are measured at V DD =3.0V, T A = 25o C and not 100% tested.IS62WV51216ALL, IS62WV51216BLL ISSI®READ CYCLE SWITCHING CHARACTERISTICS(1)(Over Operating Range)45 ns55 ns70 nsSymbol Parameter Min.Max.Min.Max.Min.Max.Unit t RC Read Cycle Time45—55—70—ns t AA Address Access Time—45—55—70ns t OHA Output Hold Time10—10—10—ns t ACS1/t ACS2CS1/CS2 Access Time—45—55—70ns t DOE OE Access Time—20—25—35ns t HZOE(2)OE to High-Z Output—15—20—25ns t LZOE(2)OE to Low-Z Output5—5—5—ns t HZCS1/t HZCS2(2)CS1/CS2 to High-Z Output015020025ns t LZCS1/t LZCS2(2)CS1/CS2 to Low-Z Output10—10—10—ns t BA LB, UB Access Time—45—55—70ns t HZB LB, UB to High-Z Output015020025ns t LZB LB, UB to Low-Z Output0—0—0—ns Notes:1.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 toV DD-0.2V/0.4V to V DD-0.3V and output loading specified in Figure 1.2.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.AC WAVEFORMSREAD CYCLE NO. 1(1,2) (Address Controlled) (CS1 = OE = V IL,CS2 = WE = V IH, UB or LB = V IL)8Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.BIS62WV51216ALL, IS62WV51216BLL ISSI®AC WAVEFORMSREAD CYCLE NO. 2(1,3)(CS1,CS2, OE, AND UB/LB Controlled)1.WE is HIGH for a Read Cycle.2.The device is continuously selected. OE, CS1, UB, or LB = V IL. CS2=WE=V IH.3.Address is valid prior to or coincident with CS1 LOW transition.IS62WV51216ALL, IS62WV51216BLL ISSI®WRITE CYCLE SWITCHING CHARACTERISTICS(1,2) (Over Operating Range)45ns55 ns70 nsSymbol Parameter Min.Max. Min.Max. Min.Max.Unit t WC Write Cycle Time 45— 55— 70—ns t SCS1/t SCS2CS1/CS2 to Write End 35— 45— 60—ns t AW Address Setup Time to Write End 35— 45— 60—ns t HA Address Hold from Write End 0— 0— 0—ns t SA Address Setup Time 0— 0— 0—ns t PWB LB, UB Valid to End of Write 35— 45— 60—ns t PWE(4)WE Pulse Width 35— 40— 50—ns t SD Data Setup to Write End 20— 25— 30—ns t HD Data Hold from Write End 0— 0— 0—ns t HZWE(3)WE LOW to High-Z Output —20 —20 —30ns t LZWE(3)WE HIGH to Low-Z Output 5— 5— 5—ns Notes:1.Test conditions assume signal transition times of 5 ns or less, timing reference levels of 0.9V/1.5V, input pulse levels of 0.4 toV DD-0.2V/0.4V to V DD-0.3V and output loading specified in Figure 1.2.The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and UB or LB, and WE LOW. All signals must be in valid states to initiate a Write, butany one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write.3.Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.4. t PWE> t HZWE + t SD when OE is LOW.AC WAVEFORMSWRITE CYCLE NO. 1(1,2)(CS1 Controlled, OE = HIGH or LOW)1.WRITE is an internally generated signal asserted during an overlap of the LOW states on the CS1 , CS2 and WE inputs and atleast one of the LB and UB inputs being in the LOW state.2.WRITE = (CS1) [ (LB) = (UB) ] (WE).10Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.BIS62WV51216ALL, IS62WV51216BLL ISSI®WRITE CYCLE NO. 2 (WE Controlled: OE is HIGH During Write Cycle)WRITE CYCLE NO. 3 (WE Controlled: OE is LOW During Write Cycle)Integrated Silicon Solution, Inc. — — 1-800-379-477411 Rev.B02/24/05IS62WV51216ALL, IS62WV51216BLL ISSI®WRITE CYCLE NO. 4 (UB/LB Controlled)12Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.B02/24/05IS62WV51216ALL, IS62WV51216BLL ISSI®DATA RETENTION SWITCHING CHARACTERISTICSSymbol Parameter Test Condition Min.Max.UnitV DR V DD for Data Retention See Data Retention Waveform 1.2 3.6VI DR Data Retention Current V DD = 1.2V, CS1≥ V DD – 0.2V—20µAt SDR Data Retention Setup Time See Data Retention Waveform0—nst RDR Recovery Time See Data Retention Waveform t RC—nsDATA RETENTION WAVEFORM (CS1 Controlled)DATA RETENTION WAVEFORM (CS2 Controlled)Integrated Silicon Solution, Inc. — — 1-800-379-477413 Rev.B02/24/05IS62WV51216ALL, IS62WV51216BLL ISSI®ORDERING INFORMATIONIS62WV51216ALL (1.65V - 2.2V)Industrial Range: –40°C to +85°CSpeed (ns)Order Part No.Package70IS62WV51216ALL-70TI TSOP-IIIS62WV51216ALL-70BI mini BGA (7.2mm x 8.7mm)IS62WV51216ALL-70XI DIEORDERING INFORMATIONIS62WV51216BLL (2.5V - 3.6V)Commercial Range: 0°C to +70°CSpeed (ns)Order Part No.Package45IS62WV51216BLL-45B mini BGA (7.2mm x 8.7mm) Industrial Range: –40°C to +85°CSpeed (ns)Order Part No.Package55IS62WV51216BLL-55TI TSOP-IIIS62WV51216BLL-55TLI TSOP-II, Lead-freeIS62WV51216BLL-55BI mini BGA (7.2mm x 8.7mm)IS62WV51216BLL-55BLI mini BGA (7.2mm x 8.7mm), Lead-free 70IS62WV51216BLL-70XI DIE14Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.B02/24/05Integrated Silicon Solution, Inc. — — 1-800-379-477415Rev.B 02/24/05IS62WV51216ALL, IS62WV51216BLL ISSI®Mini Ball Grid ArrayPackage Code: B (48-pin)Notes:1. Controlling dimensions are in millimeters.T op View Bottom ViewmBGA - 7.2mm x 8.7mmMILLIMETERSINCHES Sym.Min.Typ.Max.Min.Typ.Max.N0.Leads 48A —— 1.20— —0.047A10 .24—0.300.009 —0.012A20.60——0.024——D 8.608.708.800.3390.3430.346D1 5.25BSC 0.207BSC E 7.107.207.300.2800.2830.287E1 3.75BSC 0.148BSC e 0.75BSC 0.030BSC b0.300.350.400.0120.0140.016PACKAGING INFORMATIONISSI®Integrated Silicon Solution, Inc. — — 1-800-379-4774Rev.F 06/18/03Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.Plastic TSOPPackage Code: T (Type II)。