IS41LV16100-60T中文资料

IS41C16100IS41LV16100ISSI®Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any timewithout notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.FEATURES•TTL compatible inputs and outputs; tristate I/O •Refresh Interval:—Auto refresh Mode : 1,024 cycles /16 ms—RAS -Only, CAS -before-RAS (CBR), and Hidden —Self refresh Mode - 1,024 cycles / 128ms •JEDEC standard pinout •Single power supply:—5V ± 10% (IS41C16100)—3.3V ± 10% (IS41LV16100)•Byte Write and Byte Read operation via two CAS •Industrail Temperature Range -40o C to 85o CDESCRIPTIONThe ISSI IS41C16100 and IS41LV16100 are 1,048,576 x 16-bit high-performance CMOS Dynamic Random Access Memories.These devices offer an accelerated cycle access called EDO Page Mode. EDO Page Mode allows 1,024 random accesses within a single row with access cycle time as short as 20 ns per 16-bit word.The Byte Write control, of upper and lower byte, makes the IS41C16100 ideal for use in 16-bit and 32-bit wide data bus systems.These f eatures m ake t he I S41C16100and I S41LV16100 i deally s uited for high-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications.The IS41C16100 and IS41LV16100 are packaged in a 42-pin 400-mil SOJ and 400-mil 50- (44-) pin TSOP (Type II). The lead-free 400-mil 50- (44-) option is available too.1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODEKEY TIMING PARAMETERSParameter-50-60Unit Max. RAS Access Time (t RAC )5060ns Max. CAS Access Time (t CAC )1315ns Max. Column Address Access Time (t AA )2530ns Min. EDO Page Mode Cycle Time (t PC )2025ns Min. Read/Write Cycle Time (t RC )84104nsPIN CONFIGURATIONS50(44)-Pin TSOP (Type II)42-Pin SOJPIN DESCRIPTIONSA0-A9Address Inputs I/O0-15Data Inputs/Outputs WE Write Enable OE Output Enable RAS Row Address StrobeUCAS Upper Column Address Strobe LCAS Lower Column Address Strobe Vcc Power GND Ground NCNo ConnectionApril 2003元器件交易网IS41C16100IS41LV161002Integrated Silicon Solution, Inc. — — 1-800-379-4774R e v.I ISSI®FUNCTIONAL BLOCK DIAGRAM元器件交易网元器件交易网IS41C16100IS41LV16100ISSI®TRUTH TABLEFunction RAS LCAS UCAS WE OE Address t R/t C I/OStandby H H H X X X High-ZRead: Word L L L H L ROW/COL D OUTRead: Lower Byte L L H H L ROW/COL Lower Byte, D OUTUpper Byte, High-Z Read: Upper Byte L H L H L ROW/COL Lower Byte, High-ZUpper Byte, D OUT Write: Word (Early Write)L L L L X ROW/COL D INWrite: Lower Byte (Early Write)L L H L X ROW/COL Lower Byte, D INUpper Byte, High-Z Write: Upper Byte (Early Write)L H L L X ROW/COL Lower Byte, High-ZUpper Byte, D IN Read-Write(1,2)L L L H→L L→H ROW/COL D OUT, D INEDO Page-Mode Read(2)1st Cycle:L H→L H→L H L ROW/COL D OUT2nd Cycle:L H→L H→L H L NA/COL D OUTAny Cycle:L L→H L→H H L NA/NA D OUT EDO Page-Mode Write(1)1st Cycle:L H→L H→L L X ROW/COL D IN2nd Cycle:L H→L H→L L X NA/COL D IN EDO Page-Mode(1,2)1st Cycle:L H→L H→L H→L L→H ROW/COL D OUT, D INRead-Write2nd Cycle:L H→L H→L H→L L→H NA/COL D OUT, D INHidden Refresh Read(2)L→H→L L L H L ROW/COL D OUTWrite(1,3)L→H→L L L L X ROW/COL D OUT RAS-Only Refresh L H H X X ROW/NA High-ZCBR Refresh(4)H→L L L X X X High-ZNotes:1.These WRITE cycles may also be BYTE WRITE cycles (either LCAS or UCAS active).2.These READ cycles may also be BYTE READ cycles (either LCAS or UCAS active).3.EARLY WRITE only.4.At least one of the two CAS signals must be active (LCAS or UCAS).IS41C16100IS41LV161004Integrated Silicon Solution, Inc. — — 1-800-379-4774R e v.I ISSI®Functional DescriptionThe IS41C16100 and IS41LV16100 is a CMOS DRAM optimized for high-speed bandwidth, low power applications.During READ or WRITE cycles, each bit is uniquely addressed through the 16 address bits. These are entered ten bits (A0-A9) at time. The row address is latched by the Row Address Strobe (RAS ). The column address is latched by the Column Address Strobe (CAS ). RAS is used to latch the first nine bits and CAS is used to latch the latter nine bits.The IS41C16100 and IS41LV16100 has two CAS con-trols, LCAS and UCAS . The LCAS and UCAS inputs internally generates a CAS signal functioning in an identical manner to the single CAS input on the other 1M x 16 DRAMs. The key differ-ence is that each CAS controls its corresponding I/O tristate logic (in conjunction with OE and WE and RAS ). LCAS controls I/O0 through I/O7 and UCAS controls I/O8 through I/O15.The IS41C16100 and IS41LV16100 CAS function is determined by the first CAS (LCAS or UCAS ) transitioning LOW and the last transitioning back HIGH. The two CAS controls give the IS41C16100 and IS41LV16100 both BYTE READ and BYTE WRITE cycle capabilities.Memory CycleA memory cycle is initiated by bring RAS LOW and it is terminated by returning both RAS and CAS HIGH. To ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum t RAS time has expired. A new cycle must not be initiated until the minimum precharge time t RP , t CP has elapsed.Read CycleA read cycle is initiated by the falling edge of CAS or OE ,whichever occurs last, while holding WE HIGH. The column address must be held for a minimum time specified by t AR .Data Out becomes valid only when t RAC , t AA , t CAC and t OEA are all satisfied. As a result, the access time is dependent on the timing relationships between these parameters.Write CycleA write cycle is initiated by the falling edge of CAS and WE ,whichever occurs last. The input data must be valid at or before the falling edge of CAS or WE , whichever occurs first.Auto Refresh CycleTo retain data, 1,024 refresh cycles are required in each 16 ms period. There are two ways to refresh the memory.1.By clocking each of the 1,024 row addresses (A0 through A9)with RAS at least once every 128 ms. Any read, write, read-modify-write or RAS -only cycle refreshes the addressed ing a CAS -before-RAS refresh cycle. CAS -before-RAS refresh is activated by the falling edge of RAS ,while holding CAS LOW. In CAS -before-RAS refresh cycle, an internal 9-bit counter provides the row ad-dresses and the external address inputs are ignored.CAS -before-RAS is a refresh-only mode and no data access or device selection is allowed. Thus, the output remains in the High-Z state during the cycle.Self Refresh CycleThe Self Refresh allows the user a dynamic refresh, data retention mode at the extended refresh period of 128 ms.i.e., 125 µs per row when using distributed CBR refreshes.The feature also allows the user the choice of a fully static, low power data retention mode. The optional Self Refresh feature is initiated by performing a CBR Refresh cycle and holding RAS LOW for the specified t RAS .The Self Refresh mode is terminated by driving RAS HIGH for a minimum time of t RP . This delay allows for the completion of any internal refresh cycles that may be in process at the time of the RAS LOW-to-HIGH transition.If the DRAM controller uses a distributed refresh sequence,a burst refresh is not required upon exiting Self Refresh.However, if the DRAM controller utilizes a RAS -only or burst refresh sequence, all 1,024 rows must be refreshed within the average internal refresh rate, prior to the resumption of normal operation.Extended Data Out Page ModeEDO page mode operation permits all 1,024 columns within a selected row to be randomly accessed at a high data rate.In EDO page mode read cycle, the data-out is held to the next CAS cycle’s falling edge, instead of the rising edge.For this reason, the valid data output time in EDO page mode is extended compared with the fast page mode. In the fast page mode, the valid data output time becomes shorter as the CAS cycle time becomes shorter. There-fore, in EDO page mode, the timing margin in read cycle is larger than that of the fast page mode even if the CAS cycle time becomes shorter.In EDO page mode, due to the extended data function, the CAS cycle time can be shorter than in the fast page mode if the timing margin is the same.The EDO page mode allows both read and write opera-tions during one RAS cycle, but the performance is equivalent to that of the fast page mode in that case.Power-OnAfter application of the V CC supply, an initial pause of 200 µs is required followed by a minimum of eight initialization cycles (any combination of cycles contain-ing a RAS signal).During power-on, it is recommended that RAS track with V CC or be held at a valid V IH to avoid current surges.元器件交易网元器件交易网IS41C16100IS41LV16100ISSI®ABSOLUTE MAXIMUM RATINGS(1)Symbol Parameters Rating UnitV T Voltage on Any Pin Relative to GND5V–1.0 to +7.0V3.3V–0.5 to +4.6V CC Supply Voltage5V–1.0 to +7.0V3.3V–0.5 to +4.6I OUT Output Current50mAP D Power Dissipation1WT A Commercial Operation Temperature0 to +70°CIndustrial Operationg Temperature-40 to +85°CT STG Storage Temperature–55 to +125°CNote:1.Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanentdamage to the device. This is a stress rating only and functional operation of the device at theseor any other conditions above those indicated in the operational sections of this specification is notimplied. Exposure to absolute maximum rating conditions for extended periods may affectreliability.RECOMMENDED OPERATING CONDITIONS (Voltages are referenced to GND.)Symbol Parameter Min.Typ.Max.UnitV CC Supply Voltage5V 4.5 5.0 5.5V3.3V 3.0 3.3 3.6V IH Input High Voltage5V 2.4—V CC + 1.0V3.3V 2.0—V CC + 0.3V IL Input Low Voltage5V–1.0—0.8V3.3V–0.3—0.8T A Commercial Ambient Temperature0—70°CIndustrial Ambient Temperature–40—85°CCAPACITANCE(1,2)Symbol Parameter Max.UnitC IN1Input Capacitance: A0-A95pFC IN2Input Capacitance: RAS, UCAS, LCAS, WE, OE7pFC IO Data Input/Output Capacitance: I/O0-I/O157pFNotes:1.Tested initially and after any design or process changes that may affect these parameters.2.Test conditions: T A = 25°C, f = 1 MHz.IS41C16100IS41LV161006Integrated Silicon Solution, Inc. — — 1-800-379-4774R e v.I ISSI®ELECTRICAL CHARACTERISTICS (1)(Recommended Operating Conditions unless otherwise noted.)Symbol ParameterTest ConditionSpeedMin.Max.UnitI IL Input Leakage Current Any input 0V ≤ V IN ≤ Vcc–55µA Other inputs not under test = 0V I IO Output Leakage Current Output is disabled (Hi-Z)–55µA 0V ≤ V OUT ≤ Vcc V OH Output High Voltage Level I OH = –5.0 mA (5V) 2.4—V I OH = –2.0 mA (3.3V)V OL Output Low Voltage Level I OL = 4.2 mA (5V)—0.4V I OL = 2.0 mA (3.3V)I CC 1Standby Current: TTLRAS , LCAS , UCAS ≥ V IH Commerical5V —3mA3.3V—3Industrial 5V—4mA 3.3V—4I CC 2Standby Current: CMOS RAS , LCAS , UCAS ≥ V CC – 0.2V 5V —2mA 3.3V —2I CC 3Operating Current:RAS , LCAS , UCAS ,-50—160mARandom Read/Write (2,3,4)Address Cycling, t RC = t RC (min.)-60—145Average Power Supply Current I CC 4Operating Current:RAS = V IL , LCAS , UCAS ,-50—90mAEDO Page Mode (2,3,4)Cycling t PC = t PC (min.)-60—80Average Power Supply Current I CC 5Refresh Current:RAS Cycling, LCAS , UCAS ≥ V IH -50—160mARAS -Only (2,3)t RC = t RC (min.)-60—145Average Power Supply Current I CC 6Refresh Current:RAS , LCAS , UCAS Cycling -50—160mACBR (2,3,5)t RC = t RC (min.)-60—145Average Power Supply CurrentNotes:1.An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS -Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the t REF refresh requirement is exceeded.2.Dependent on cycle rates.3.Specified values are obtained with minimum cycle time and the output open.4.Column-address is changed once each EDO page cycle.5.Enables on-chip refresh and address counters.元器件交易网元器件交易网IS41C16100IS41LV16100ISSI®AC CHARACTERISTICS(1,2,3,4,5,6)(Recommended Operating Conditions unless otherwise noted.)-50-60Symbol Parameter Min.Max.Min.Max.Unitst RC Random READ or WRITE Cycle Time84—104—nst RAC Access Time from RAS(6, 7)—50—60nst CAC Access Time from CAS(6, 8, 15)—13—15nst AA Access Time from Column-Address(6)—25—30nst RAS RAS Pulse Width5010K6010K nst RP RAS Precharge Time30—40—nst CAS CAS Pulse Width(26)810K1010K nst CP CAS Precharge Time(9, 25)9—9—nst CSH CAS Hold Time (21)38—40—nst RCD RAS to CAS Delay Time(10, 20)12371445nst ASR Row-Address Setup Time0—0—nst RAH Row-Address Hold Time8—10—nst ASC Column-Address Setup Time(20)0—0—nst CAH Column-Address Hold Time(20)8—10—nst AR Column-Address Hold Time30—40—ns (referenced to RAS)t RAD RAS to Column-Address Delay Time(11)10251230nst RAL Column-Address to RAS Lead Time25—30—nst RPC RAS to CAS Precharge Time5—5—nst RSH RAS Hold Time(27)8—10—nst RHCP RAS Hold Time from CAS Precharge37—37—nst CLZ CAS to Output in Low-Z(15, 29)0—0—nst CRP CAS to RAS Precharge Time(21)5—5—nst OD Output Disable Time(19, 28, 29)315315nst OE Output Enable Time(15, 16)—13—15nst OED Output Enable Data Delay (Write)20—20—nst OEHC OE HIGH Hold Time from CAS HIGH5—5—nst OEP OE HIGH Pulse Width10—10—nst OES OE LOW to CAS HIGH Setup Time5—5—nst RCS Read Command Setup Time(17, 20)0—0—nst RRH Read Command Hold Time0—0—ns (referenced to RAS)(12)t RCH Read Command Hold Time0—0—ns (referenced to CAS)(12, 17, 21)t WCH Write Command Hold Time(17, 27)8—10—nst WCR Write Command Hold Time40—50—ns (referenced to RAS)(17)IS41C16100IS41LV161008Integrated Silicon Solution, Inc. — — 1-800-379-4774R e v.I ISSI®AC CHARACTERISTICS (Continued)(1,2,3,4,5,6)(Recommended Operating Conditions unless otherwise noted.)-50-60Symbol ParameterMin.Max.Min.Max.Units t WP Write Command Pulse Width (17)8—10—ns t WPZ WE Pulse Widths to Disable Outputs 10—10—ns t RWL Write Command to RAS Lead Time (17)13—15—ns t CWL Write Command to CAS Lead Time (17, 21)8—10—ns t WCS Write Command Setup Time (14, 17, 20)0—0—ns t DHR Data-in Hold Time (referenced to RAS )39—39—ns t ACH Column-Address Setup Time to CAS 15—15—ns Precharge during WRITE Cycle t OEH OE Hold Time from WE during 8—10—ns READ-MODIFY-WRITE cycle (18)t DS Data-In Setup Time (15, 22)0—0—ns t DH Data-In Hold Time (15, 22)8—10—ns t RWC READ-MODIFY-WRITE Cycle Time 108—133—ns t RWD RAS to WE Delay Time during 64—77—ns READ-MODIFY-WRITE Cycle (14)t CWD CAS to WE Delay Time (14, 20)26—32—ns t AWD Column-Address to WE Delay Time (14)39—47—ns t PC EDO Page Mode READ or WRITE 20—25—ns Cycle Time (24)t RASP RAS Pulse Width in EDO Page Mode 50100K 60100K ns t CPA Access Time from CAS Precharge (15)—30—35ns t PRWC EDO Page Mode READ-WRITE 56—68—ns Cycle Time (24)t COH Data Output Hold after CAS LOW 5—5—ns t OFF Output Buffer Turn-Off Delay from 1.612 1.615ns CAS or RAS (13,15,19, 29)t WHZ Output Disable Delay from WE 310310ns t CLCH Last CAS going LOW to First CAS 10—10—ns returning HIGH (23)t CSR CAS Setup Time (CBR REFRESH)(30, 20)5—5—ns t CHR CAS Hold Time (CBR REFRESH)(30, 21)8—10—ns t ORD OE Setup Time prior to RAS during 0—0—ns HIDDEN REFRESH Cyclet REF Auto Refresh Period (1,024 Cycles)—16—16ms t REF Self Refresh Period (1,024 Cycles)—128—128ms t TTransition Time (Rise or Fall)(2, 3)150150ns元器件交易网IS41C16100IS41LV16100ISSI®Notes:1.An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycle (RAS -Only or CBR) before proper device operation is assured. The eight RAS cycles wake-up should be repeated any time the t REF refresh requirement is exceeded.2.V IH (MIN) and V IL (MAX) are reference levels for measuring timing of input signals. Transition times, are measured between V IH and V IL (or between V IL and V IH ) and assume to be 1 ns for all inputs.3.In addition to meeting the transition rate specification, all input signals must transit between V IH and V IL (or between V IL and V IH ) in a monotonic manner.4.If CAS and RAS = V IH , data output is High-Z.5.If CAS = V IL , data output may contain data from the last valid READ cycle.6.Measured with a load equivalent to one TTL gate and 50 pF.7.Assumes that t RCD - t RCD (MAX). If t RCD is greater than the maximum recommended value shown in this table, t RAC will increase by the amount that t RCD exceeds the value shown.8.Assumes that t RCD • t RCD (MAX).9.If CAS is LOW at the falling edge of RAS , data out will be maintained from the previous cycle. To initiate a new cycle and clear the data output buffer, CAS and RAS must be pulsed for t CP .10.Operation with the t RCD (MAX) limit ensures that t RAC (MAX) can be met. t RCD (MAX) is specified as a reference point only; if t RCD isgreater than the specified t RCD (MAX) limit, access time is controlled exclusively by t CAC .11.Operation within the t RAD (MAX) limit ensures that t RCD (MAX) can be met. t RAD (MAX) is specified as a reference point only; if t RAD isgreater than the specified t RAD (MAX) limit, access time is controlled exclusively by t AA .12.Either t RCH or t RRH must be satisfied for a READ cycle.13.t OFF (MAX) defines the time at which the output achieves the open circuit condition; it is not a reference to V OH or V OL .14.t WCS , t RWD , t AWD and t CWD are restrictive operating parameters in LATE WRITE and READ-MODIFY-WRITE cycle only. If t WCS • t WCS(MIN), the cycle is an EARLY WRITE cycle and the data output will remain open circuit throughout the entire cycle. If t RWD • t RWD (MIN),t AWD • t AWD (MIN) and t CWD • t CWD (MIN), the cycle is a READ-WRITE cycle and the data output will contain data read from the selected cell. If neither of the above conditions is met, the state of I/O (at access time and until CAS and RAS or OE go back to V IH ) is indeterminate. OE held HIGH and WE taken LOW after CAS goes LOW result in a LATE WRITE (OE -controlled) cycle.15.Output parameter (I/O) is referenced to corresponding CAS input, I/O0-I/O7 by LCAS and I/O8-I/O15 by UCAS .16.During a READ cycle, if OE is LOW then taken HIGH before CAS goes HIGH, I/O goes open. If OE is tied permanently LOW, a LATEWRITE or READ-MODIFY-WRITE is not possible.17.Write command is defined as WE going low.TE WRITE and READ-MODIFY-WRITE cycles must have both t OD and t OEH met (OE HIGH during WRITE cycle) in order to ensurethat the output buffers will be open during the WRITE cycle. The I/Os will provide the previously written data if CAS remains LOW and OE is taken back to LOW after t OEH is met.19.The I/Os are in open during READ cycles once t OD or t OFF occur.20.The first χCAS edge to transition LOW.21.The last χCAS edge to transition HIGH.22.These parameters are referenced to CAS leading edge in EARLY WRITE cycles and WE leading edge in LATE WRITE or READ-MODIFY-WRITE cycles.st falling χCAS edge to first rising χCAS edge.st rising χCAS edge to next cycle’s last rising χCAS st rising χCAS edge to first falling χCAS edge.26.Each χCAS must meet minimum pulse st χCAS to go LOW.28.I/Os controlled, regardless UCAS and LCAS .29.The 3 ns minimum is a parameter guaranteed by design.30.Enables on-chip refresh and address counters.AC TEST CONDITIONSOutput load:Two TTL Loads and 50 pF (Vcc = 5.0V ±10%)One TTL Load and 50 pF (Vcc = 3.3V ±10%)Input timing reference levels:V IH = 2.4V, V IL = 0.8V (Vcc = 5.0V ±10%);V IH = 2.0V, V IL = 0.8V (Vcc = 3.3V ±10%)Output timing reference levels:V OH = 2.0V, V OL = 0.8V (Vcc = 5V ±10%, 3.3V ±10%)元器件交易网IS41C16100IS41LV1610010Integrated Silicon Solution, Inc. — — 1-800-379-4774R e v.I ISSI®READ CYCLENote:1.t OFF is referenced from rising edge of RAS or CAS , whichever occurs last.元器件交易网EARLY WRITE CYCLE (OE = DON'T CARE)READ WRITE CYCLE (LATE WRITE and READ-MODIFY-WRITE Cycles)12Integrated Silicon Solution, Inc. — — 1-800-379-4774R e v.IEDO-PAGE-MODE READ CYCLENote:1.t PC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Bothmeasurements must meet the t PC specifications.EDO-PAGE-MODE EARLY-WRITE CYCLE14Integrated Silicon Solution, Inc. — — 1-800-379-4774R e v.IEDO-PAGE-MODE READ-WRITE CYCLE (LATE WRITE and READ-MODIFY WRITE Cycles)Note:1.t PC can be measured from falling edge of CAS to falling edge of CAS, or from rising edge of CAS to rising edge of CAS. Bothmeasurements must meet the t PC specifications.EDO-PAGE-MODE READ-EARLY-WRITE CYCLE (Psuedo READ-MODIFY WRITE)16Integrated Silicon Solution, Inc. — — 1-800-379-4774R e v.IAC WAVEFORMSREAD CYCLE (With WE-Controlled Disable)RAS-ONLY REFRESH CYCLE (OE, WE = DON'T CARE)CBR REFRESH CYCLE (Addresses; WE, OE = DON'T CARE)HIDDEN REFRESH CYCLE(1)(WE = HIGH; OE = LOW)Notes:1.A Hidden Refresh may also be performed after a Write Cycle. In this case, WE = LOW and OE = HIGH.2.t OFF is referenced from rising edge of RAS or CAS, whichever occurs last.18Integrated Silicon Solution, Inc. — — 1-800-379-4774R e v.IORDERING INFORMATION : 5V Commercial Range: 0°C to 70°CSpeed (ns)Order Part No.Package50IS41C16100-50K400-mil SOJIS41C16100-50T400-mil TSOP (Type II) 60IS41C16100-60K400-mil SOJIS41C16100-60T400-mil TSOP (Type II)Industrial Range: -40°C to 85°CSpeed (ns)Order Part No.Package50IS41C16100-50KI400-mil SOJIS41C16100-50TI400-mil TSOP (Type II) 60IS41C16100-60KI400-mil SOJIS41C16100-60TI400-mil TSOP (Type II)ORDERING INFORMATION : 3.3VCommercial Range: 0°C to 70°CSpeed (ns)Order Part No.P a c k a g e50IS41LV16100-50K400-mil SOJIS41LV16100-50T400-mil TSOP (Type II)IS41LV16100-50TL400-mil TSOP (Type II), Lead-free60IS41LV16100-60K400-mil SOJIS41LV16100-60T400-mil TSOP (Type II)IS41LV16100-60TL400-mil TSOP (Type II), Lead-freeIndustrial Range: -40°C to 85°CSpeed (ns)Order Part No.P a c k a g e50IS41LV16100-50KI400-mil SOJIS41LV16100-50TI400-mil TSOP (Type II)IS41LV16100-50TLI400-mil TSOP (Type II), Lead-free60IS41LV16100-60KI400-mil SOJIS41LV16100-60TI400-mil TSOP (Type II)IS41LV16100-60TLI400-mil TSOP (Type II), Lead-free20Integrated Silicon Solution, Inc. — — 1-800-379-4774R e v.I。