IS43R32800B-6BL-TR;IS43R32800B-5BL-TR;IS43R32800B-6BL;IS43R32800B-5BL;中文规格书,Datasheet资料

Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-est version of this device specification before relying on any published information and before placing orders for products.IS43R32800B8Mx32256Mb DDR Synchronous DRAMPRELIMINARY INFORMATIONMAY 2008DESCRIPTION:IS43R32800B is a 4-bank x 2,097,152-word x32bit Double Data Rate Synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobe, and output data and data strobe are referenced on both edges of CLK. TheIS43R32800B achieves very high speed clock rate up to 200 MHz. It is packaged in 144-ball FBGA.FEATURESV • dd /V ddq =2.5V+0.2V (-5, -6, -75)Double data rate architecture; two data transfers • per clock cycleBidirectional, data strobe (DQS) is transmitted/ • received with dataDifferential clock input (CLK and /CLK)• DLL aligns DQ and DQS transitions with CLK • transitions edges of DQSCommands entered on each positive CLK edge;• Data and data mask referenced to both edges of • DQS4 bank operation controlled by BA0, BA1 (Bank • Address)/CAS latency –2.0/2.5/3.0 (programmable)• Burst length - 2/4/8 (programmable)• Burst type - Sequential/ Interleave (program-• mable)Auto precharge / All bank precharge controlled • by A84096 refresh cycles/ 64ms (4 banks concurrent • refresh)Auto refresh and Self refresh• Row address A0-11/ Column address A0-7, A9-• SSTL_2 InterfacePackage 144-ball FBGA• Available in Industrial T emperature • Temperature Range:• Commercial (0o C to +70o C) Industrial (-40o C to +85o C)ADDRESS TABLEParameter 8M x 32Configuration 2M x 32 x 4 banks Bank Address Pins BA0, BA1Autoprecharge Pins A8/AP Row Addresses A0 – A11Column Addresses A0 – A7, A9Refresh Count4096 / 64msKEY TIMING PARAMETERSParameter -5 -6 -75 UnitClk Cycle Time CAS Latency = 3 5 6 7.5 ns CAS Latency = 2.5 5 6 7.5 ns CAS Latency = 2 7.5 7.5 7.5 ns Clk Frequency CAS Latency = 3 200 167 143 MHz CAS Latency = 2.5 200 167 143 MHz CAS Latency = 2 143 143 143 MHz Access Time from ClockCAS Latency = 3 +0.70 +0.70 +0.70 ns CAS Latency = 2.5 +0.70 +0.70 +0.70 ns CAS Latency = 2+0.75 +0.75 +0.70 nsIS43R32800BFUNCTIONAL BLOCK DIAGRAMIS43R32800BCLK, /CLK : Ma ster Cl ock CKE : Clock En able /CS : Ch ip Select/RAS : Row Address Strobe /CAS : Column A ddress Strobe /WE : Write Enab le A0-11: Address InputBA 0,1: Ba nk A ddress Input V DD: Power Supply V DDQ : Power Supply for Output Vs s : GroundVssQ : Ground for Output DQ 0-31: Data I/O DM 0-3: Write MaskVREFCK EA8/APA7A6A4A3A1A0BA 0NC/CSMNC /CLK CL K NC A5A9A11A2BA 1NC NC /R AS L NC NC VD D VSS NC VD D VD D A10VSS VD D /WE /CAS K DQ 8DQ 9VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ 23DQ 22J DQ 10DQ 11VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ 20DQ 21H DQS1DM1NC VSSQ VSS VSS VSS VSS VSSQ NC DM2DQS2G DQ 12DQ 13VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ 18DQ 19F DQ 14DQ 15VDDQ VSSQ VSS VSS VSS VSS VSSQ VDDQ DQ 16DQ 17E DQ 24VDDQ VD D VSS VSSQ VSS VSS VSSQ VSS VD D VDDQ DQ 7D DQ 25DQ 26VSSQ VSSQ VSSQ VD D VD D VSSQ VSSQ VSSQ DQ 5DQ 6C DQ 27VDDQ NC VDDQ DQ 30VDDQ VDDQ DQ 1VDDQ NC VDDQ DQ 4B DQS3DM3VSSQ DQ 28DQ 29DQ 31DQ 0DQ 2DQ 3VSSQ DM0DQS0A 121110987654321DQ S0-3: Data StrobeV REF: Reference VoltagePIN CONFIGURATIONPackage Code: B 144-ball FBGA (Top View) (12.00mm x 12.00mm Body, 0.8mm Ball PitchPIN DESCRIPTIONSIS43R32800BCL K,/CLK Inpu tCl ock:CL K a nd/CLK are d ifferential clock inputs.A ll address andcont rol inpu t signals are sampled on the crossing o f the po sitive ed ge of CL K a nd ne gative edgeof /CLK .Outpu t (read)data is referenced to the crossings of CL K a nd/CLK (bot h directions of crossing).CK E I np utCl ock E nable:CK E controls internal clock.W he n CKE is low,inte rnal clock for the following cycle is ceased .C KE is also used to select auto/self refresh.Af te r self refresh mo de is starte d,CK E becomes asynchrono us input.Self refresh is maintained as long as CK E i s low./CS I np ut Chip Select:W he n /CS is high,any command means No Operation./RAS ,/CAS,/WEI np utComb ination o f /RA S,/CAS ,/WE de fine s basic comma nds.A0-11Inp utA0-11spe cify the Row /Colum n Add ress in conjunction with BA0,1.T he Row Address is spe cified by A0-11.The Colum n Add ress is specified by A0-7,A 9.A8is also used toindicate precharge option.Whe n A8ishigh at a read /write command,an auto p recharge is pe rforme d.When A8is high at a precharge command,all banks are p recharge d.BA 0,1Inpu t DQ0-31Inpu t /OutputDQS0-3V DD ,Vs s Power Supp ly Power Supp ly for theme mo ry array andpe ripheral circuitry.V DDQ ,Vss QPower Supp lyV DDQ and Vss Q are suppl i ed to the Outp ut Buffers only.Bank Address:BA 0,1spe cifies one of four banks to which a comma ndis appl i ed.BA 0,1must b e set with ACT,PR E,READ,WR IT E comma nds.Data Input /Output :Data b usData Strobe :Outputwith read data,inputwith write data.E dg e-aligne d with read data,cente red in write ed to captu re write d ata.DQS 0for DQ0-DQ7,DQS 1for DQ8-DQ15,DQS2for DQ16-DQ23,DQS3for DQ24-DQ31.SYMBOLTYPEDESCRIPTIONDM0-3Inpu tInpu t Data Mask:DM is an inputmask signal for write data.I np ut data is masked when DM is samp led HIG H along with that inpu t data during a WR IT E access.DM is samp led o n bot h e dge s of DQS.Al though DM pins are inp ut only,the DM loading matches the DQ andDQS loading.DM 0for DQ0-DQ7,DM1for DQ8-DQ15,DM 2for DQ16-DQ23,DM 3for DQ24-DQ31.Inpu t /Outp utVrefInputSST L_2reference voltage .PIN FUNCTIONSIS43R32800BISSI's 256-Mbit DDR SDRA M provides basic function s, bank (row) activate, burst read / write, bank (row)precharge ,and auto /self refresh.E ach com mand is defined b y con trol signals of /RA S,/CAS and /WE at CLK rising ed ge.I n addition to 3signals,/CS ,C KE and A8are usedas chip select,refresh op tion ,and prechargeoption ,respect ively.To know th e d etailed d efinition of com mands,please see the comm andtruthtable./CS ChipSelect :L =select,H=deselect /RAS Comma nd /CAS Comma nd /WE Comma ndCK E Refresh Option @refresh commandA8Precharg e Opt ion @precharg e o r read/write commandCL K define ba sic commands/CLK Activate (ACT)[/RA S =L,/CAS =/WE =H]AC T com mand activates a row in an idle b ank indicated by BA.Read (R EAD)[/RAS =H,/CA S =L,/WE =H]RE AD comm and starts burst read fromth e active b ank indicated by BA.First outp ut data appear s after /CAS latency.When A8=H at this comm and,th e b ank is deactivated after the burst read (auto -precharge READ A)Write (WRITE)[/RA S =H,/CAS =/WE =L ]WR IT E comma nd starts burst write to th e active b ank indicated by BA.T otal data length to be written is set b y burst length .W hen A8=H at this comma nd,the bank is de activated after th e b urst write (auto-prechar ge,WRITEA )Precharge (PRE )[/RAS =L ,/CA S =H,/WE =L]PR E comma nd de activates the active b ank indicated by BA.T his com mand also terminates burst read /write operation.When A8=H at this comm and,all banks are deactivated (prechar ge all,PREA ).Auto-Ref resh (REFA )[/RAS =/CA S =L,/WE =CK E =H]RE FA comm and starts auto-refresh cycle.R efresh addr ess including bank addr ess are generated internally.A fter this comma nd,the banks are precharged automatically.FUNCTIONAL DESCRIPTIONIS43R32800BH=High Leve l,L=Low Lev el,V=Valid,X=Don't Ca re ,n=CLK cycle n umbe r NOTE:1.Applies o nly to rea d bursts with autoprech arge disa bled;this comma nd is unde fi ne d (and s hould not be us ed)forread bursts with au toprec ha rge e nabled,and for write bursts .2.BA0-BA1selec t eithe r the Baseor the Extende d Mode Register (BA0=0,BA1=0selec ts Mode Register;BA0=1,BA1=0selec ts Extended Mode Register;other combinations of BA0-BA1are rese rved;A0-A11provide the op-code to be written to the selected Mode Register.COMMAND MNEMONIC CKEn-1CKE n /CS /RAS /CAS /WE BA0,1A8/AP A0-7,A9-11Dese lect DE SEL H X H X X X X X X No Oper atio n NOP H X L H H H X X X Row Addres s Entry &Bank Activate ACT H H L L H H V V V Single Ba nk Precha rge PRE H H L L H L V L X Prech argeAll Ban ks PR EA H H L L H L H X Co lumn Addres s E ntry&Write WRITEHHLHLLVLVCo lumn Addres s E ntry&Write with Auto-Pre charge WRITEA H H L H L L V H V Co lumn Addres s E ntry&Rea d READHHLHLHVLVCo lumn Addres s E ntry &Rea d with Auto-Prech argeRE ADA H H L H L H V H V Auto-Ref re sh REFA H H L L L H X X X Self-Refre shEntry REFS H L L L L H X X X Self-Refre shExit REFSX L H H X X X X X X L H L H H H X X X Burst Terminate TE RM H H L H H L X X X ModeRe gisterSetMRSHHLLLLLLVX note12COMMAND TRUTH TABLEIS43R32800BFUNCTIONAL TRUTH TABLEIS43R32800BFUNCTION AL TRUTH TABLE (continued)IS43R32800BFUNCTION AL TRUTH TABLE (continued)IS43R32800BABBREVIATIONS :H=Hi gh Level,L=Low L evel,X =Don't CareBA =Bank A dd ress,R A=Row Address,CA =Column Add ress,NOP =No Ope rationNOTES :1.Al l ent ries assume that CK E was Hi gh du ring the p receding clock cycle and t he current clock cycle.2.ILLEGAL to bank in specified state ;function may be legal in t he bank indicated b y B A,de pe nding o n t he state o f that bank.3.Must satisfy bus contention,bus turn around ,write recovery requireme nts.4.NOP to bank precharging or in idle state.May prechargebank indicated b y B A.5.ILLEGAL if any bank is not idle.ILLEGA L =Device operation and /o r data-integrity are not guaranteed.FUNCTIONAL TRUTH TABLE (continued)分销商库存信息:ISSIIS43R32800B-6BL-TR IS43R32800B-5BL-TR IS43R32800B-6BL IS43R32800B-5BL。