Floating point arithmetic unit with size efficient
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专利名称：Floating point arithmetic unit with size
efficient pipelined multiply-add architecture 发明人：Tan V. Chu,Faraydon O. Karim,Christopher H.
Olson
申请号：US07/807697
申请日：19911216
公开号：US05241493A
公开日：
19930831
专利内容由知识产权出版社提供
摘要：An architecture and method relating to a floating point operation which performs the mathematical computation of A*B+C. The multiplication is accomplished in two or more stages, each stage involving corresponding sets of partial products and concurrently accomplished incremental summations. A pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand C at a stage preceding entry into a full adder. Thereby, a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit. Partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required. Pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation A*B+C while using a full adder of three-quarters normal size.
申请人：INTERNATIONAL BUSINESS MACHINES CORPORATION
代理人：Casimer K. Salys
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