LM2465TANOPB;中文规格书,Datasheet资料
LMP92001SQENOPB;LMP92001SQXNOPB;LMP92001EVALNOPB;中文规格书,Datasheet资料
LMP92001April 19, 2012 Analog System Monitor and Controller1.0 General DescriptionThe LMP92001 is a complete analog monitoring and control circuit which includes a sixteen channel 12-bit Analog to Dig-ital Converter (ADC), twelve 12-bit Digital to Analog Convert-ers (DACs), an internal reference, an internal temp sensor, an 8-bit GPIO port, and an I2C-compatible interface.The ADC can be used to monitor rail voltages, current sense amplifier outputs or sensors and includes a programmable window comparator function on six of its 16 channels to detect out-of range conditions.The DACs can be used to control PA bias points, actuators, potentiometers, etc. When required, the outputs can be in-stantaneously driven to either supply rail using the output switches and the asynchronous DAC control inputs.Both ADC and DACs can use either the internal 4.5V refer-ence or an external reference independently.The built-in temperature sensor is treated as the 17th analog sense input. In addition, the 8-bit G PIO port allows for the resources of the microcontroller to be further extended, pro-viding even more flexibility.The LMP92001 is available in a space saving 10mmx5.5mm LLP 54-pin package and is operational over the full − 40°C to 125°C temperature range.2.0 Features16 Analog Voltage Monitoring Channels■12-bit ADC with programmable input MUX■No Missing Codes■Total Unadjusted Error (TUE) ±0.1%■Single-Shot or Continuous Conversion Modes ■Programmable window comparator function■Interrupt signal generation for input out-of-bound condition 12 Programmable Analog Voltage Outputs■Twelve 12-bit DACs■Guaranteed Monotonic■Settling Time 8.5 µs■Simultaneous update of all channels to same value■Asynchronous output control forces rail voltage at output Voltage Reference■User-selectable source: External or Internal■Internal Reference 4.5V ±0.7%Analog Temperature Sensor■Readable via ADC channel 17■Temperature Error ±2°C8-bit GPIO Port■Each bit individually programmableI2C-Compatible Bus■Supports Standard and Fast Modes■Bus TIMEOUT function■Supports Block data transfersLLP-54 package (10 x 5.5 mm, 0.5 mm pitch)3.0 Applications■RF PA Bias Monitoring and Control■System Monitoring and Control■Industrial Monitoring and Control■Test Equipment and Instrumentation4.0 Block Diagram30132736 National Semiconductor® is a registered trademark of National Semiconductor Corporation.© 2012 Texas Instruments Incorporated301327 SNAS507B LMP92001 Analog System Monitor and Controller5.0 Typical Application30132706 2L M P 920016.0 OverviewThe LMP92001 has a flexible, feature-rich functionality which makes it ideally suited for many analog monitoring and control applications, for example base-station PA subsystems. This device provides the analog interface between a pro-grammable supervisor, such as a microcontroller, and an analog system whose behavior is to be monitored and con-trolled by the supervisor.To facilitate analog monitoring functionality, the device con-tains a single 12-bit ADC fronted by a 17-input multiplexor. The 16 MUX inputs are available to the user via pins IN[16:1]. The last remaining MUX channel is reserved for the internal analog temperature sensor.The analog control functionality is served by twelve 12-bit voltage output DACs. Besides producing voltage correspond-ing to the digital input code, the DACs can be forced by the user to either rail instantaneously.Additional digital monitoring and control can be realized via the General Purpose I/O port GPIO[7:0].Two more blocks are present for added functionality: a local temperature sensor (already mentioned above) and an inter-nal reference voltage generator.6.1 17-CHANNEL ANALOG SENSE WITH 12-BIT ADC The user can monitor up to 16 external voltages with the 12-bit ADC and its 17-channel input MUX. Typically these volt-ages will be generated by the analog sensors, instrumenta-tion amplifiers, current sense amplifiers, or simply resistive dividers if high potentials need to be measured. Channel 17 of the input MUX is reserved for the internal temperature sen-sor, and is not available as an external input to the device. User can program which MUX channels to enable, and whether to convert these channel inputs in sequence contin-uously, or in a single-shot mode. Upon completion all con-version results are stored in the internal data registers, and can be read back by the user via the I2C-compatible interface. Analog input channels 1-3 and 9-11 have a built-in digital window comparator function with user programmable thresh-olds. This function can be used to alert the supervisor micro-controller of an out-of-bound condition. The comparator function result is stored in the internal status register which is user accessible. It can also be used as the interrupt signal generator where the out of bound conditions will be reported via the INT[2:1] output pins.Sequencing of the analog sense system is governed by the internal controller. Once enabled the MUX, the ADC, the win-dow comparator and the interrupts perform their function without further user intervention.6.2 PROGRAMMABLE ANALOG CONTROL VOLTAGE OUTPUTSTwelve identical individually programmable 12-bit DAC blocks are available to generate analog voltages, which canbe used to control bias conditions of external circuits, positionof servos, etc.In case simultaneous update of all outputs to the same levelis needed, a single internal register is provided that effectssimultaneous update of all DAC data registers.A DAC, by definition, produces an output in the range of GNDto DREF. In some systems, however, it may be desirable forthe OUT pins to produce either GND or VDD, i.e., beyondDREF. This is made possible via the asynchronous DAC con-trol inputs C[4:1]. When activated, these inputs will force theOUT pins to either rail. The choice of rail is made in the inter-nal control register.6.3 INTERNAL ANALOG TEMPERATURE SENSORAn on-board analog temperature sensor is available to mon-itor the device’s own temperature. Once enabled, the analogtemperature sensor output is sampled via the MUX channel17, and its conversion result is stored in the internal registerfor user read back.6.4 INTERNAL VOLTAGE REFERENCE SOURCEAnother resource available to the user is the internal, tem-perature-compensated reference voltage source. By defaultboth ADC and DACs expect reference potentials to be sup-plied externally. The user can choose to enable the internalreference and use it with the ADC and/or the DACs.The internal reference source cannot drive an external load.6.5 8-BIT GENERAL PURPOSE I/OThe GPIO port can be used to expand the microcontroller ca-pabilities. This port is memory mapped to the internal register,which in turn is accessible via the I2C-compatible interface.Since each bit is individually programmable as an Input orOutput, the port is ideally suited for external switch control andstatus flag monitoring, without further burdening of microcon-troller I/O resources.6.6 I2C-COMPATIBLE INTERFACEThe microcontroller supervisor communicates withLMP92001 via a popular I2C-compatible 2–wire interface.This interface provides the user full access to all Data, Statusand Control registers of the device.There are 2 address setting pins, AS[1:0], that allow the de-vice to occupy any one of 9 possible Interface Addresses onthe bus.Block Access commands are provided to minimize the trans-fer overhead of larger data sets.LMP920017.0 Connection Diagram30132708LLP-54 (SQA54AB)Top View 4L M P 920018.0 Pin DescriptionsNamePinESD StructuresFunctionVDD 14, 50Supply railGND 4, 13, 41, 45Device GroundIN15Analog Voltage Sense InputsIN26IN37IN48IN59IN610IN711IN812IN940IN1039IN1138IN1237IN1336IN1435IN1534IN1633OUT152Analog Control Voltage OutputsOUT253OUT354OUT41OUT52OUT63OUT748OUT847OUT946OUT1044OUT1143OUT1242SCL 23I 2C-compatible clock input SDA24Bidirectional I 2C-compatible data lineAS[0:1]31:32I 2C-compatible Interface Addressselection inputs.LMP92001Name Pin ESD Structures FunctionC[1:4]27:30Asynchronous DAC output controldigital inputs GPIO[0:7]15:22Digital I/O. CMOS Input or Open-DrainOutput INT[1:2]25:26Interrupt outputs. Open-Drain, activeLOWAREF49ADC referenceDREF 51DAC reference9.0 Ordering InformationOrder Number NS Package NumberTransport Media LMP92001SQE SQA54AB 250 piece reel LMP92001SQXSQA54AB2000 piece reel 6L M P 92001LMP92001Table of Contents1.0 General Description (1)2.0 Features (1)3.0 Applications (1)4.0 Block Diagram (1)5.0 Typical Application (2)6.0 Overview (3)6.1 17-CHANNEL ANALOG SENSE WITH 12-BIT ADC (3)6.2 PROGRAMMABLE ANALOG CONTROL VOLTAGE OUTPUTS (3)6.3 INTERNAL ANALOG TEMPERATURE SENSOR (3)6.4 INTERNAL VOLTAGE REFERENCE SOURCE (3)6.5 8-BIT GENERAL PURPOSE I/O (3)6.6 I2C-COMPATIBLE INTERFACE (3)7.0 Connection Diagram (4)8.0 Pin Descriptions (5)9.0 Ordering Information (6)10.0 Absolute Maximum Ratings (9)11.0 Operating Conditions (Note 1, Note 2) (9)12.0 Electrical Characteristics (9)13.0 I2C Interface Timing Diagram (12)14.0 Typical Performance Characteristics (13)15.0 Register Set (16)15.1 REGISTER MAP (16)15.2 TEST AND INFO REGISTERS (17)15.2.1 Test Register: TEST[7:0], default = 0x00 (17)15.2.2 Company ID Register: ID[7:0], default = 0x01 (17)15.2.3 Device Version Register: VER[7:0], default = 0x10 (17)15.3 STATUS REGISTERS (18)15.3.1 General Status Register: SGEN[7:0], default = 0x40 (18)15.3.2 GPIO Status Register: SGPI[7:0], default = 0x** (18)15.3.3 High-Limit Status Register: SHIL[7:0], default = 0x00 (18)15.3.4 Low-Limit Status Register: SLOL[7:0], default = 0x00 (18)15.4 CONTROL REGISTERS (19)15.4.1 General Configuration Register: CGEN[7:0], default = 0x00 (19)15.4.2 DAC Configuration Register: CDAC[7:0], default 0x03 (19)15.4.3 GPIO Output Control Register: CGPO[7:0], default = 0xFF (19)15.4.4 INT1, INT2 High-Limit Control Register: CINH[7:0], default = 0x00 (19)15.4.5 INT1, INT2 Low-Limit Control Register: CINL[7:0], default = 0x00 (19)15.4.6 ADC Conversion Enable Register 1: CAD1[7:0], default = 0x00 (19)15.4.7 ADC Conversion Enable Register 2: CAD2[7:0], default = 0x00 (19)15.4.8 ADC Conversion Enable Register 3: CAD3[7:0], default = 0x00 (19)15.4.9 ADC One-Shot Conversion Trigger Register : CTRIG[7:0], default = 0x00 (20)15.4.10 Reference Mode Register: CREF[7:0], default = 0x07 (20)15.5 DATA REGISTERS (20)15.5.1 ADC Output Data Register: ADCx[15:0], default 0x0000 (20)15.5.2 ADC High-Limit Register: LIHx[15:0], default 0x0FFF (20)15.5.3 ADC Low-Limit Register: LILx[15:0], default 0x0000 (20)15.5.4 DAC Data Register: DACx[15:0], default 0x0000 (20)15.5.5 Write all DAC's Data Register: DALL[15:0], default 0x0000 (20)15.6 BLOCK COMMANDS (21)16.0 Application Information (22)16.1 ANALOG SENSE SUBSYSTEM (22)16.1.1 Sampling and Conversion (22)16.1.2 Sampling Transient (22)16.1.3 Channel Selection (22)16.1.4 Single-Shot and Continuous Sequencing (22)16.1.5 Reference (24)16.1.6 Window Comparator Function (24)16.1.7 Interrupt Subsystem (25)16.2 PROGRAMMABLE ANALOG OUTPUT SUBSYSTEM (25)16.2.1 DAC Core (25)16.2.2 Reference (26)16.2.3 Asynchronous Output Control (26)16.3 TEMPERATURE SENSOR (27)16.4 ADC/DAC VOLTAGE REFERENCE (27)16.5 GENERAL PURPOSE I/O ..................................................................................................... 2816.6 SERIAL INTERFACE (28)16.6.1 I 2C-Compatible Protocol .............................................................................................. 2916.6.2 Device Address .......................................................................................................... 3016.6.3 Block Access ............................................................................................................. 3116.6.4 I 2C-Compatible Bus Reset . (31)17.0 Application Circuit Example ........................................................................................................... 3218.0 Physical Dimensions .. (33) 8L M P 9200110.0 Absolute Maximum Ratings (Note 1, Note 2)If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.VDD Relative to GND−0.3V to 6.0V Voltage between any 2 pins(Note 3) 6.0V Current in or out of any pin (Note 3)5mACurrent through VDD or GND78 mA, TA = 125°C120 mA, TA= 105°C Junction Temperature+150°C Storage Temperature Range−65°C to +150°C ESD Susceptibility(Note 4)Human Body Model Machine Model Charged Device Model 2500V250V1250VFor Soldering specifications:See product folder at and/ms/MS-SOLDERING.pdf.11.0 Operating Conditions (Note 1, Note2)Operating Ambient Temperature−40°C to 125°CVDD Voltage Range 4.5V to 5.5VDAC Output Load C0pF to 1500pFθJA24°C/WθJC2°C/W12.0 Electrical CharacteristicsUnless otherwise noted, these specifications apply for VDD=4.75V to 5.5V, AREF=DREF=VDD, TA=25°C. Boldface limits are over the temperature range of −40°C ≤ T A≤ 125°C unless otherwise noted. DAC input code range 48 to 4047. DAC output C L = 200 pF unless otherwise noted.Symbol Parameter Conditions Min Typ Max UnitsDAC CHARACTERISTICSResolution1212BitsMonotonicity12BitsDNL Differential Non-Linearity R L = 100k−0.60.6LSB INL Integral Non-Linearity R L = 100k−88ZE Zero Error R L = 100k15mVZEDRIFT Zero Error Temperature Drift R L = 100k 2.0µV/°CFSE Full-Scale Error R L = 100k0−0.75%FS GE Gain Error R L = 100k0−1GEDRIFT Gain Error Temperature Drift R L = 100k11.0ppm/° CZCO Zero Code Output IOUT= 200 µA7mV IOUT= 1mA31FSO Full Scale Output at code 4095VDD = DREF = 5V, I OUT = 1mA 4.988 4.995VDD VI OS Output Short Circuit Current(Source) (Note 5)VDD = 5V, OUT = 0V,Input Code = FFFhCDAC.OFF=0C[4:1]=HIGH−60mAI OS Output Short Circuit Current(Sink) (Note 5)VDD = 5V, OUT = DREF,Input Code = 000hCDAC.OFF=0C[4:1]=HIGH70I O Continuous Output Current perChannel (to prevent damage)TA= 105° C10TA= 125° C 6.5C L Load Capacitance RL= 2k or ∞1500pFDC Output Impedance8ΩOUT[1:12] Output Voltage whenAsynchronous Output Control isactivatedRL= 100k, C[1:4] = GND,CDAC.OLVL = 14.992VDD VC[1:4] = GND, CDAC.OLVL = 0GND0.6mVLMP92001Symbol ParameterConditionsMin Typ Max UnitsADC CHARACTERISTICSResolution with No Missing Codes11 Bits−40°C ≤ T A ≤ 105°C12 TUE Total Unadjusted Error−0.1 0.1%DNL Differential Non-Linearity −40°C ≤ T A ≤ 105°C−0.99 1LSB −1.2 1INL Integral Non-Linearity ±0.6 OE Offset Error−2.3 2.3OEDRIFT Offset Error Temperature Drift 0.005 LSB/°C OEMTCH Offset Error Match −1.5 1.5LSB GE Gain Error−2 2GEDRIFT Gain Error Temperature Drift −0.002 LSB/°C GEMTCH Gain Error Match −1.5 1.5LSB SNR Signal-to-Noise Ratio72 dB PSRR Power Supply Rejection Ratio Offset Error change with VDD 77 dB Gain Error change with VDD73 V IN FS Input RangeAREF I INA Input Current In Hold or inactive±1µA C INAInput CapacitanceIn Track 33 pF In Hold or inactive3 pF REFERENCE CHARACTERISTICSAREF Reference Input Range CREF.AEXT = 1 2.7 VDD V DREF Reference Input Range CREF.DEXT = 1 2.5 VDD V DREF Reference Input Resistance 10 k Ω DREF Input Current DREF = 5V,CREF.DEXT = 1 660µA AREF Peak Current AREF = 5V CREF.DEXT = 12.3 mA AREF and DREF Reference Current in Powerdown1µA Internally Generated Reference Voltage4.47 4.5 4.53VAREF, DREF Output Impedance when Internal Reference Active CREF.AEXT = 0CREF.DEXT = 05ΩTEMPERATURE SENSORSensor Gain−13.45 mV/°CTemperature Error−25°C to +85°C −2 2°C−45°C to +125°C−2.5 2.5DIGITAL INPUT CHARACTERISTICS (AS1:AS0)V IH Input HIGH Voltage 0.90x VDD V V IM Input MID Voltage 0.43 x VDD0.57 x VDD V IL Input LOW Voltage 0.1 x VDDV I IND Digital Input Current ±0.005±1µA C IND Input Capacitance 4 pF DIGITAL INPUT CHARACTERISTICS (GPIO0:GPIO7, C1:C4)V IH Input HIGH Voltage 0.7 x VDDV V IL Input LOW Voltage 0.3 x VDDVHysteresis0.47V 10L M P 92001分销商库存信息:NATIONAL-SEMICONDUCTORLMP92001SQE/NOPB LMP92001SQX/NOPB LMP92001EVAL/NOPB。
LF356NNOPB,LF356M,LF356H,LF156H,LF256H,LF356MX, 规格书,Datasheet 资料
capability
Applications
n Precision high speed integrators n Fast D/A and A/D converters n High impedance buffers n Wideband, low noise, low drift amplifiers
LF155/LF156/LF256/LF257/LF355/LF356/LF357 JFET Input Operational Amplifiers
December 2001
LF155/LF156/LF256/LF257/LF355/LF356/LF357
JFET Input Operational Amplifiers
1.5
12 5 12
LF257/ LF357 (AV=5)
1.5
50 20 12
Units µs
V/µs MHz
Simplified Schematic
*3pF in LF357 series.
BI-FET™, BI-FET II™ are trademarks of National Semiconductor Corporation.
300˚C
300˚C
Dual-In-Line Package
Soldering (10 sec.)
260˚C
260˚C
260˚C
Small Outline Package
Vapor Phase (60 sec.)
LM2452TBNOPB;中文规格书,Datasheet资料
LM2452LM2452 220V Monolithic Triple Channel 17 MHz DC Coupled CRT DTV DriverLiterature Number: SNOSAN8E20144501 FIGURE 1. Top ViewOrder Number LM2452TBSee NS Package Number TB15A20144502 FIGURE 2. Simplified Schematic Diagram(One Channel)© 2011 Texas Instruments 201445 Version 6 Revision 2Print Date/Time: 2011/11/02 10:28:56 2452 220V Monolithic Triple Channel 17 MHz DC Coupled CRT DTV Driver2201445 Version 6 Revision 2Print Date/Time: 2011/11/02 10:28:56L522014450310 pF load includes parasitic capacitance.FIGURE 3. Test Circuit (One Channel)Figure 3 shows a typical test circuit for evaluation of the LM2452. This circuit is designed to allow testing of the LM2452 in a environment without the use of an expensive FET probe. The two 4990Ω resistors form a 400:1 divider with the 50Ωand the oscilloscope. A test point is included for easy use of an oscilloscope probe. The compensation capacitor is used to com-pensate the network to achieve flat frequency response.201445 Version 6 Revision 2Print Date/Time: 2011/11/02 10:28:56C 20144504FIGURE 4. V OUT vs V IN20144505FIGURE 5. LM2452 Pulse Response 20144506FIGURE 6. Bandwidth 20144507FIGURE 7. Speed vs Load Capacitance20144508FIGURE 8. Speed vs Offset20144509FIGURE 9. Speed vs Case Temperature4201445 Version 6 Revision 2Print Date/Time: 2011/11/02 10:28:56LC20144510 FIGURE 10. Power Dissipation vs Frequency20144511 FIGURE 11. Safe Operating Area20144512FIGURE 12. LM2452 Cathode Response 201445 Version 6 Revision 2Print Date/Time: 2011/11/02 10:28:5652201445 FIGURE 13. One Channel of the LM2452 with the Recommended Application CircuitEFFECT OF LOAD CAPACITANCEFigure 7 shows the effect of increased load capacitance the speed of the device. This demonstrates the importance knowing the load capacitance in the application. Increasi the load capacitance from 10 pF to 20 pF adds about 9 ns the rise and fall times. It is very important to keep the boa capacitance as low as possible to maximize the speed of t driver.EFFECT OF OFFSETFigure 8 shows the variation in rise and fall times when tblack level of the device is varied from 180V to 200VDC . Trise time increases only about 2ns as the offset is increas6201445 Version 6 Revision 2Print Date/Time: 2011/11/02 10:28:56L52 This example assumes a capacitive load of 10 pF and no re-sistive load. If the maximum ambient temperature is 50°C,then the heat sink thermal resistance can increase to 3.3°C/W. The designer should note that if the load capacitance is201445 Version 6 Revision 2Print Date/Time: 2011/11/02 10:28:568201445 Version 6 Revision 2Print Date/Time: 2011/11/02 10:28:56L 201445 Version 6 Revision 2Print Date/Time: 2011/11/02 10:28:5652分销商库存信息: NATIONAL-SEMICONDUCTOR LM2452TB/NOPB。
LMK00101SQXNOPB;LMK00101SQNOPB;LMK00101SQENOPB;LMK00101BEVALNOPB;中文规格书,Datasheet资料
LMK00101January 16, 2012Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input1.0 General DescriptionThe LMK00101 is a high performance, low noise LVCMOS fanout buffer which can distribute 10 ultra-low jitter clocks from a differential, single ended, or crystal input. The LMK00101 supports synchronous output enable for glitch free operation. The ultra low-skew, low-jitter, and high PSRR make this buffer ideally suited for various networking, tele-com, server and storage area networking, RRU LO reference distribution, medical and test equipment applications.The core voltage can be set to 2.5 or 3.3 V, while the output voltage can be set to 1.5, 1.8, 2.5 or 3.3 V. The LMK00101 can be easily configured through pin programming.2.0 Target Applications■LO Reference Distribution for RRU Applications■SONET, Ethernet, Fibre Channel Line Cards■Optical Transport Networks■GPON OLT/ONU■Server and Storage Area Networking■Medical Imaging■Portable Test and Measurement■High-end A/V 3.0 Features■10 LVCMOS/LVTTL Outputs, DC to 200 MHz ■Universal Input—LVPECL—LVDS—HCSL—SSTL—LVCMOS / LVTTL■Crystal Oscillator Interface—Crystal Input Frequency: 10 to 40 MHz■Output Skew: 6 ps■Additive Phase Jitter—30 fs at 156.25 MHz (12 kHz to 20 MHz)■Low Propagation Delay■Operates with 3.3 or 2.5 V Core Supply Voltage ■Adjustable Output Power Supply—1.5 V, 1.8 V, 2.5 V, and 3.3 V For Each Bank ■32 pin LLP Package 5.0 x 5.0 x 0.8 mm4.0 Functional Block Diagram30146901TRI-STATE® is a registered trademark of National Semiconductor Corporation.© 2012 Texas Instruments Incorporated301469 LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input5.0 Connection Diagram32-Pin LLP Package301469026.0 Pin DescriptionsPin #Pin Name Type DescriptionDAP DAP -The DAP should be grounded1CLKout0Output LVCMOS Output2, 6Vddo Power Power Supply for Bank A (CLKout0 to CLKout4) CLKout pins.19,23Vddo Power Power Supply for Bank B (CLKout5 to CLKout9) CLKout pins.3CLKout1Output LVCMOS Output 4,9,15,16,21,25,26,32GND GND Ground5CLKout2Output LVCMOS Output 7CLKout3Output LVCMOS Output 8CLKout4Output LVCMOS Output10Vdd Power Supply for operating core and input buffer 11OSCin Input Input for Crystal 12OSCout Output Output for Crystal 13CLKin0Input Input Pin14CLKin0*Input Optional complimentary input pin 17CLKout5Output LVCMOS Output 18CLKout6Output LVCMOS Output 20CLKout7Output LVCMOS Output 22CLKout8Output LVCMOS Output 24CLKout9Output LVCMOS Output27CLKin1*Input Optional Complimentary Input Pin 28CLKin1Input Input Pin29SEL1Input MSB for Input Clock Selection. This pin has an internal pull-down resistor.30SEL0Input LSB for Input Clock Selection. This pin has an internal pull-down resistor.31OEInputOutput Enable. This pin has an internal pull-down resistor. 2L M K 00101 U l t r a -l o w J i t t e r L V C M O S F a n o u t B u f f e r /L e v e l T r a n s l a t o r w i t h U n i v e r s a l I n p u t7.0 Absolute Maximum Ratings (Note 1, Note 2)If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.Parameter Symbol Ratings Units Core Supply Voltage Vdd-0.3 to 3.6VOutput Supply Voltage Vddo-0.3 to 3.6V Input Voltage V IN-0.3 to Vdd + 0.3V Storage Temperature Range T STG-65 to 150°CLead Temperature (solder 4 s)T L+260°C Junction Temperature T J+125°C8.0 Recommended Operating ConditionsParameter Symbol Min Typ Max Units Ambient Temperature T A-402585°CCore Supply Voltage Vdd 2.375 3.3 3.45V Output Supply Voltage (Note 3)Vddo 1.425 3.3Vdd VNote 1:"Absolute Maximum Ratings" indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.Note 2:This device is a high performance integrated circuit with ESD handling precautions. Handling of this device should only be done at ESD protected work stations. The device is rated to a HBM-ESD of > 2.5 kV, a MM-ESD of > 250 V, and a CDM-ESD of > 1 kV.Note 3:Vddo should be less than or equal to Vdd(Vddo≤ Vdd)9.0 Package Thermal Resistance32-Lead LLPPackage Symbols Ratings UnitsThermal resistance from junction to ambienton 4-layer Jedec board (Note 4)θJA50° C/WThermal resistance from junction to case(Note 5)θJC (DAP)20° C/WNote 4:Specification assumes 5 thermal vias connect to die attach pad to the embedded copper plane on the 4-layer Jedec board. These vias play a key role in improving the thermal performance of the LLP. For best thermal dissipation it is recommended that the maximum number of vias be used on the board layout.Note 5:Case is defined as the DAP (die attach pad).LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input10.0 Electrical Characteristics(2.375 V ≤ Vdd ≤ 3.45 V, 1.425 ≤ Vddo ≤ Vdd, -40 °C ≤ T A ≤ 85 °C, Differential inputs. Typical values represent most likely parametric norms at Vdd = Vddo = 3.3 V, T A = 25 °C, at the Recommended Operation Conditions at the time of product charac-terization and are not guaranteed). Test conditions are: F test = 100 MHz, Load = 5 pF in parallel with 50 Ω unless otherwise stated.SymbolParameterTest ConditionsMinTypMaxUnitsTotal Device CharacteristicsVddCore Supply Voltage2.3752.5 or3.33.45VVddo Output Supply Voltage 1.425 1.5,1.8,2.5, or3.3Vdd VI VddCore CurrentNo CLKin1625mAV ddo = 3.3 V, F test = 100 MHz 24 V ddo = 2.5 V, F test = 100 MHz 20 I Vddo[n]Current for Each OutputV ddo = 2.5 V,OE = High, F test = 100 MHz5 mAV ddo = 3.3 V,OE = High, F test = 100 MHz7 OE = Low 0.1 I Vdd + I VddoTotal Device Current with Loads onall outputsOE = High @ 100 MHz95 mAOE = Low16Power Supply Ripple Rejection (PSRR)PSRRRipple Induced Phase Spur Level100 kHz, 100 mVpp Ripple Injected on V dd , V ddo = 2.5 V-44dBcOutputs (Note 6)Skew Output Skew Measured between outputs,referenced to CLKout06 ps f CLKoutOutput Frequency(Note 7)DC 200MHzt Rise Rise/Fall Time V dd = 3.3 V, V ddo = 1.8 V, C L = 10 pF500 psV dd = 2.5 V, V ddo = 2.5 V, C L = 10 pF 300 V dd = 3.3 V, V ddo = 3.3 V, C L = 10 pF200 V CLKout Low Output Low Voltage 0.1V V CLKout High Output High Voltage Vddo-0.1 R CLKoutOutput Resistance50 ohm t jRMS Additive Jitterf CLKout = 156.25 MHz,CMOS input slew rate ≥ 2 V/ns C L = 5 pF, BW = 12 kHz to 20 MHz30fs 4L M K 00101 U l t r a -l o w J i t t e r L V C M O S F a n o u t B u f f e r /L e v e l T r a n s l a t o r w i t h U n i v e r s a l I n p u tSymbol Parameter Test ConditionsMin Typ Max UnitsDigital Inputs (OE, SEL0, SEL1)V Low Input Low Voltage Vdd = 2.5 V 0.4VV High Input High Voltage Vdd = 2.5 V 1.3 Vdd = 3.3 V1.6 I IH High Level Input Current 50uAI IL Low Level Input Current -5 5CLKin0/0* and CLKin1/1* Input Clock Specifications, (Note 9, Note 10)I IH High Level Input Current V CLKin = Vdd 20uA I IL Low Level Input Current(Note 8)V CLKin = 0 V-20 uA V IH Input High Voltage Vdd VV ILInput Low VoltageGND V CMDifferential InputCommon Mode Input Voltage(Note 12)V ID = 150 mV0.5 Vdd-1.2VV ID = 350 mV 0.5 Vdd-1.1V ID = 800 mV0.5 Vdd-0.9V ID Differential Input Voltage Swing CLKin driven differentially 0.15 1.5V OSCin/OSCout Pinsf OSCinInput Frequency (Note 7)Single-Ended Input, OSCout floatingDC200MHzf XTALCrystal Frequency Input Range Fundamental Mode Crystal ESR < 200 Ω ( f Xtal ≤ 30 MHz )ESR < 120 Ω ( f Xtal > 30 MHz )(Note 11, Note 7)10 40MHzC OSCinShunt Capacitance1 pFNote 6:AC Parameters for CMOS are dependent upon output capacitive loading Note 7:Guaranteed by characterization.Note 8:V IL should not go below -0.3 volts.Note 9:See Section 12.1 Differential Voltage Measurement Terminology for definition of V ID and V OD .Note 10:Refer to application note AN-912 Common Data Transmission Parameters and their Definitions for more information.Note 11:The ESR requirements stated are what is necessary in order to ensure that the Oscillator circuitry has no start up issues. However, lower ESR values for the crystal might be necessary in order to stay below the maximum power dissipation requirements for that crystal.Note 12:When using differential signals with V CM outside of the acceptable range for the specified V ID , the clock must be AC coupled.LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input30146942Iddo per Output vs Frequency50100150200250051015C U R R E N T (m A )FREQUENCY (MHz)Cload = 10 pFVddo = 1.5 V Vddo = 1.8 V Vddo = 2.5 V Vddo = 3.3 V 30146976Note 13:Test conditions: LVCMOS Input, slew rate ≥ 2 V/ns, C L = 5 pF in parallel with 50 6L M K 00101 U l t r a -l o w J i t t e r L V C M O S F a n o u t B u f f e r /L e v e l T r a n s l a t o r w i t h U n i v e r s a l I n p u t12.0 Measurement Definitions12.1 Differential Voltage Measurement TerminologyThe differential voltage of a differential signal can be de-scribed by two different definitions causing confusion when reading datasheets or communicating with other engineers. This section will address the measurement and description of a differential signal so that the reader will be able to under-stand and discern between the two different definitions when used.The first definition used to describe a differential signal is the absolute value of the voltage potential between the inverting and non-inverting signal. The symbol for this first measure-ment is typically VID or VODdepending on if an input or outputvoltage is being described.The second definition used to describe a differential signal is to measure the potential of the non-inverting signal with re-spect to the inverting signal. The symbol for this second measurement is VSSand is a calculated parameter. Nowherein the IC does this signal exist with respect to ground, it onlyexists in reference to its differential pair. VSScan be measured directly by oscilloscopes with floating references, otherwisethis value can be calculated as twice the value of VODas de-scribed in the first sectionFigure 1 illustrates the two different definitions side-by-side for inputs and Figure 2 illustrates the two different definitionsside-by-side for outputs. The VIDand VODdefinitions showVAand VBDC levels that the non-inverting and inverting sig-nals toggle between with respect to ground. VSSinput and output definitions show that if the inverting signal is consid-ered the voltage potential reference, the non-inverting signal voltage potential is now increasing and decreasing above and below the non-inverting reference. Thus the peak-to-peak voltage of the differential signal can be measured.VIDand VODare often defined in volts (V) and VSSis oftendefined as volts peak-to-peak (VPP).30146912FIGURE 1. Two Different Definitions for Differential Input Signals30146913FIGURE 2. Two Different Definitions for Differential Output Signals LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input13.0 Functional DescriptionThe LMK00101 is a 10 output LVCMOS clock fanout buffer with low additive jitter that can operate up to 200 MHz. It fea-tures a 3:1 input multiplexer with a crystal oscillator input,single supply or dual supply (lower power) operation, and pin-programmable device configuration. The device is offered in a 32-pin LLP package.13.1 V dd and V ddo Power Supplies (Note 14, Note 15)Separate core and output supplies allow the output buffers to operate at the same supply as the Vdd core supply (3.3 V or 2.5 V) or from a lower supply voltage (3.3 V, 2.5 V, 1.8 V, or 1.5 V). Compared to single-supply operation, dual supply op-eration enables lower power consumption and output-level compatibility.Bank A (CLKout0 to CLKout4) and Bank B (CLKout5 to CLK-out9) may also be operated at different V ddo voltages, provid-ed neither V ddo voltage exceeds V dd .Note 14:Care should be taken to ensure the V ddo voltage does not exceed the Vdd voltage to prevent turning-on the internal ESD protection circuitry.Note 15:DO NOT DISCONNECT OR GROUND ANY OF THE V ddo PINS as the V ddo pins are internally connected within an output bank.13.2 CLOCK INPUTSThe LMK00101 has three different inputs, CLKin0/CLKin0*,CLKin1/CLKin1*, and OSCin that can be driven in different manners that are described in the following sections.13.2.1 SELECTION OF CLOCK INPUTClock input selection is controlled using the SEL0 and SEL1pins as shown in Table 1. Refer to Section 14.1 Driving the Clock Inputs for clock input requirements. When CLKin0 or CLKin1 is selected, the crystal circuit is powered down. When OSCin is selected, the crystal oscillator will start-up and its clock will be distributed to all outputs. Refer to Section 14.2Crystal Interface for more information. Alternatively, OSCin may be driven by a single ended clock, up to 200 MHz, instead of a crystal.TABLE 1. Input SelectionSEL1SEL0Input 00CLKin0, CLKin0*01CLKin1, CLKin1*1XOSCin (Crystal Mode)13.2.1.1 CLKin/CLKin* PinsThe LMK00101 has two differential inputs (CLKin0/CLKin0*and CLKin1/CLKin1*) that can be driven single-ended or dif-ferentially. They can accept AC or DC coupled 3.3V/2.5V LVPECL, LVDS, or other differential and singled ended sig-nals that meet the input requirements under the “CLKin0/0*and CLKin1/1* Input Clock Specifications” portion of the Sec-tion 10.0 El ectrical Characteristics and (Note 12). Refer to Section 14.1 Driving the Clock Inputs for more details on driv-ing the LMK00101 inputs.In the event that a Crystal mode is not selected and the CLKin pins do not have an AC signal applied to them, Table 2 fol-lowing will be the state of the outputs.TABLE 2. CLKinX Input vs. Output States CLKinX CLKinX*Output State Open Open Logic Low Logic Low Logic Low Logic Low Logic High Logic Low Logic High Logic LowLogic HighLogic Low13.3 CLOCK OUTPUTSThe LMK00101 has 10 LVCMOS outputs.13.3.1 Output Enable PinWhen the output enable pin is held High, the outputs are en-abled. When it is held Low, the outputs are held in a Low state as shown in Table 3.TABLE 3. Output Enable Pin StatesOE Outputs Low Disabled (Hi-Z)HighEnabledThe OE pin is synchronized to the input clock to ensure that there are no runt pulses. When OE is changed from Low to High, the outputs will initially have an impedance of about 400 Ω to ground until the second falling edge of the input clock. Starting with the second falling edge of the input clock,the outputs will buffer the input. If the OE pin is taken from Low to High when there is no input clock present, the outputs will either go High or Low and stay a that state; they will not oscillate. When the OE pin is taken from High to Low the out-puts will become Low after the second falling edge of the clock input and then will go to a Disabled (Hi-Z) state starting after the next rising edge.13.3.2 Using Less than Ten OutputsAlthough the LMK00101 has 10 outputs, not all applications will require all of these. In this case, the unused outputs should be left floating with a minimum copper length (Note 16) to minimize capacitance. In this way, this output will con-sume minimal output current because it has no load.Note 16:For best soldering practices, the minimum trace length should extend to include the pin solder mask. This way during reflow, the solder has the same copper area as connected pins. This allows for good, uniform fillet solder joints helping to keep the IC level during reflow. 8L M K 00101 U l t r a -l o w J i t t e r L V C M O S F a n o u t B u f f e r /L e v e l T r a n s l a t o r w i t h U n i v e r s a l I n p u t14.0 Application Information14.1 Driving the Clock InputsThe LMK00101 has two differential inputs (CLKin0/CLKin0*and CLKin1/CLKin1*) that can accept AC or DC coupled 3.3V/2.5V LVPECL, LVDS, and other differential and single ended signals that meet the input requirements specified in Sec-tion 10.0 Electrical Characteristics . The device can accept a wide range of signals due to its wide input common mode voltage range (V CM ) and input voltage swing (V ID )/dynamic range. AC coupling may also be employed to shift the input signal to within the V CM range.To achieve the best possible phase noise and jitter perfor-mance, it is mandatory for the input to have a high slew rate of 2 V/ns (differential) or higher. Driving the input with a lower slew rate will degrade the noise floor and jitter. For this rea-son, a differential input signal is recommended over single-ended because it typically provides higher slew rate and common-mode noise rejection.While it is recommended to drive CLKin0 and CLKin1 with a differential signal input, it is possible to drive them with a sin-gle ended clock. The single-ended input slew rate should be as high as possible to minimize performance degradation.The CLKinX input has an internal bias voltage of about 1.4 V,so the input can be AC coupled as shown in Figure 3, Figure 4, or Figure 5 depending upon the application.30146938FIGURE 3. Single-Ended LVCMOS Input, AC Coupling,Near and Far End Termination30146943FIGURE 4. Single-Ended LVCMOS Input, AC Coupling,Near End Termination30146944FIGURE 5. Single-Ended LVCMOS Input, AC Coupling,Far End Termination A single ended clock may also be DC coupled to CLKinX as shown in Figure 6. If the DC coupled input swing has a com-mon mode level near the devices internal bias of 1.4 V, then only a 0.1 µF bypass cap is required on CLKinX*. Otherwise,if the input swing is not optimally centered near the internal bias voltage, then CLKinX* should be externally biased to the midpoint voltage of the input swing. This can be achieved us-ing external biasing resistors, R B1 and R B2, or another low-noise voltage reference. The external bias voltage should be within the specified input common voltage (VCM) range. This will ensure the input swing crosses the threshold voltage at a point where the input slew rate is the highest.30146939FIGURE 6. Single-Ended LVCMOS Input, DC Couplingwith Common Mode Biasing If the crystal oscillator circuit is not used, it is possible to drive the OSCin input with an single-ended external clock as shown in Figure 7. Configurations similar to Figure 4 or Figure 5 could also be used as long as the OSCout pin is left floating. The input clock should be AC coupled to the OSCin pin, which has an internally generated input bias voltage, and the OSCout pin should be left floating. While OSCin provides an alterna-tive input to multiplex an external clock, it is recommended to use either differential input (CLKinX) since it offers higher op-erating frequency, better common mode, improved power supply noise rejection, and greater performance over supply voltage and temperature variations.LMK00101 Ultra-low Jitter LVCMOS Fanout Buffer/Level Translator with Universal Input30146903FIGURE 7. Driving OSCin with a Single-Ended ExternalClock 14.2 Crystal InterfaceThe LMK00101 has an integrated crystal oscillator circuit that supports a fundamental mode, AT-cut crystal. The crystal in-terface is shown in Figure 8.30146904FIGURE 8. Crystal InterfaceThe load capacitance (C L ) is specific to the crystal, but usually on the order of 18 to 20 pF. While C L is specified for the crys-tal, the OSCin input capacitance (C IN = 1 pF typical) of the device and PCB stray capacitance (C STRAY ~ 1 to 3 pF) can affect the discrete load capacitor values, C 1 and C 2. For the parallel resonant circuit, the discrete capacitor values can be calculated as follows:C L = (C 1 * C 2) / (C 1 + C 2) + C IN + C STRAY(1)Typically, C 1 = C 2 for optimum symmetry, so Equation 1 can be rewritten in terms of C 1only:C L = C 12 / (2 * C 1 ) + C IN + C STRAY(2)Finally, solve for C 1:C 1 = (C L - C IN - C STRAY ) * 2(3)Section 10.0 Electrical Characteristics provides crystal inter-face specifications with conditions that ensure start-up of the crystal, but it does not specify crystal power dissipation. The designer will need to ensure the crystal power dissipation does not exceed the maximum drive level specified by the crystal manufacturer. Overdriving the crystal can cause pre-mature aging, frequency shift, and eventual failure. Drive level should be held at a sufficient level necessary to start-up and maintain steady-state operation.The power dissipated in the crystal, P XTAL , can be computed by:P XTAL = I RMS 2 * R ESR * (1 + C 0 / C L )2(4)Where:•I RMS is the RMS current through the crystal.•R ESR is the maximum equivalent series resistance specified for the crystal.•C L is the load capacitance specified for the crystal.•C 0 is the minimum shunt capacitance specified for the crystal.I RMS can be measured using a current probe (e.g. Tektronix CT-6 or equivalent) placed on the leg of the crystal connected to OSCout with the oscillation circuit active.As shown in Figure 8, an external resistor, R LIM , can be used to limit the crystal drive level if necessary. If the power dissi-pated in the selected crystal is higher than the drive level specified for the crystal with R LIM shorted, then a larger resis-tor value is mandatory to avoid overdriving the crystal. How-ever, if the power dissipated in the crystal is less than the drive level with R LIM shorted, then a zero value for R LIM can be used.As a starting point, a suggested value for R LIM is 1.5 k Ω14.3 Power Supply Ripple RejectionIn practical system applications, power supply noise (ripple)can be generated from switching power supplies, digital ASICs or FPGAs, etc. While power supply bypassing will help filter out some of this noise, it is important to understand the effect of power supply ripple on the device performance.When a single-tone sinusoidal signal is applied to the power supply of a clock distribution device, such as LMK00101, it can produce narrow-band phase modulation as well as am-plitude modulation on the clock output (carrier). In the single-side band phase noise spectrum, the ripple-induced phase modulation appears as a phase spur level relative to the car-rier (measured in dBc).For the LMK00101, power supply ripple rejection (PSRR),was measured as the single-sideband phase spur level (in dBc) modulated onto the clock output when a ripple signal was injected onto the V ddo supply. The PSRR test setup is shown in Figure 9.30146940FIGURE 9. PSRR Test SetupA signal generator was used to inject a sinusoidal signal onto the V ddo supply of the DUT board, and the peak-to-peak ripple amplitude was measured at the V ddo pins of the device. A lim-iting amplifier was used to remove amplitude modulation on the differential output clock and convert it to a single-ended signal for the phase noise analyzer. The phase spur level measurements were taken for clock frequencies of 100 MHz under the following power supply ripple conditions:•Ripple amplitude: 100 mVpp on V ddo = 2.5 V •Ripple frequency: 100 kHzAssuming no amplitude modulation effects and small index modulation, the peak-to-peak deterministic jitter (DJ) can be calculated using the measured single-sideband phase spur level (PSRR) as follows:10L M K 00101 U l t r a -l o w J i t t e r L V C M O S F a n o u t B u f f e r /L e v e l T r a n s l a t o r w i t h U n i v e r s a l I n p u t分销商库存信息:NATIONAL-SEMICONDUCTORLMK00101SQX/NOPB LMK00101SQ/NOPB LMK00101SQE/NOPB LMK00101BEVAL/NOPB。
LM224中文资料_数据手册_参数
Parameter Supply Voltage
Input Voltage
Differential Input Voltage - (*)
Power Dissipation
N Suffix D Suffix
Output Short-circuit Duration - (note 1)
Supply Voltage Rejection (VCCT+am=b5=V+t2o53o0CV)
Ratio
(RS
≤
10kΩ)
Tmin. ≤ Tamb ≤ Tmax.
Supply Current, all Amp, no load
Tamb = +25oC
VCC = +5V
VCC = +30V
Tmin. ≤ Tamb ≤ Tmax.
(VCCTa=mb+5=V+,2R5LoC= 2kΩ)
Tmin. ≤ Tamb ≤ Tmax.
RL = 2kΩ RL = 10kΩ
Low Level Tamb =
Output +25oC
Voltage
(RL
=
10kΩ)
Tmin. ≤ Tamb ≤ Tmax.
Slew Rate VCC = 15V, VI = 0.5 to 3V, RL = 2kΩ, CL = 100pF, unity gain)
Input Offset Current Drift
Channel Separation (note 5) 1kHz ≤ f ≤ 20kHz
MHz
1.3 %
0.015
nV
40
LC245A中文资料
GQN OR ZQN PACKAGE (TOP VIEW)
1234
A B C D E
TERMINAL ASSIGNMENTS
1
2
3
4
A
A1
DIR
VCC
OE
B
A3
B2
A2
B1
C
A5
A4
B4
B3
D
A7
B6
A6
B5
E
GND
A8
B8
B7
FUNCTION TABLE
INPUTS
OE DIR
L
L
L
H
H
X
OPERATION
QFN – RGY
Reel of 1000
SN74LVC245ARGYR
SOIC – DW
Tube of 25 Reel of 2000
SN74LVC245ADW SN74LVC245ADWR
SOP – NS
Reel of 2000
SN74LVC245ANSR
SSOP – DB
Reel of 2000
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DIR 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 GND 10
LMX2354TMNOPB;LMX2354SLBXNOPB;LMX2354TMXNOPB;中文规格书,Datasheet资料
LMX2354LMX2354 PLLatinum Fractional N RF/ Integer N IF Dual Low Power Frequency Synthesizer LMX2354 2.5 GHz/550 MHzLiterature Number: SNAS118BLMX2354PLLatinum Fractional N RF/Integer N IF Dual Low Power Frequency Synthesizer LMX23542.5GHz/550MHzGeneral DescriptionThe LMX2354is part of a family of monolithic integrated fractional N/Integer N frequency synthesizers designed to be used in a local oscillator subsystem for a radio transceiver.It is fabricated using National’s 0.5µABiC V silicon BiCMOS process.The LMX2354contains quadruple modulus pres-calers along with modulo 15or 16fractional compensation circuitry in the RF divider.The LMX2354provides a continu-ous divide ratio of 80to 32767in 16/17/20/21(1.2GHz–2.5GHz)fractional mode and 40to 16383in 8/9/12/13(550MHz–1.2GHz)fractional mode.The IF cir-cuitry for the LMX2354contains an 8/9prescaler,and is fully ing a fractional N phase locked loop tech-nique,the LMX2354can generate very stable low noise control signals for UHF and VHF voltage controlled oscilla-tors (VCOs).For the RF PLL,a highly flexible 16level programmable charge pump supplies output current magnitudes from 100µA to 1.6mA.Two uncommitted CMOS outputs can be used to provide external control signals,or configured to FastLock mode.Serial data is transferred into the LMX2354via a three wire interface (Data,LE,Clock).Supply voltage can range from 2.7V to 5.5V.The LMX2354family features very low current consumption;typically LMX2354(2.5GHz)—7.0mA.The LMX2354are available in a 24-pin TSSOP surface mount plastic package and 24-pin CSP .Featuresn Pin compatible/functional equivalent to the LMX2350n Enhanced Low Noise Fractional Engine n 2.7V to 5.5V operation n Low current consumptionLMX2354:I CC =7mA typical at 3Vn Programmable or logical power down mode:I CC =5µA typical at 3Vn Modulo 15or 16fractional RF N divider supports ratios of 1,2,3,4,5,8,15,or 16nProgrammable charge pump current levels RF 100µA to 1.6mA in 100µA steps IF 100µA or 800µAn Digital filtered lock detectnAvailable in 24-pin TSSOP and 24-pin CSPApplicationsn Portable wireless communications (PCS/PCN,cordless)n Dual mode cellular telephone systems n Zero blind slot TDMA systemsn Spread spectrum communication systems (CDMA)nCable TV Tuners (CATV)Functional Block Diagram20004801©2001National Semiconductor Corporation 20004802Order Number LMX2354TM or LMX2355TMSee NS Package Number MTC2420004822Order Number LMX2354SLB or LMX2355SLBSee NS Package Number SLBL 2Pin No.for TSSOP Package Pin No.forCSPPackagePinName I/O Description124OUT0O Programmable CMOS output.Level of the output is controlled by IF_N[17]bit. 21V CCRF—RF PLL power supply voltage input.Must be equal to Vcc IF.May range from2.7V to5.5V.Bypass capacitors should be placed as close as possible to thispin and be connected directly to the ground plane.32V PRF —Power supply for RF charge pump.Must be≥V CCRFand V CCIF.43CP oRFO RF charge pump output.Connected to a loop filter for driving the control inputof an external VCO.54GND—Ground for RF PLL digital circuitry.65fin RF I RF prescaler input.Small signal input from the VCO.76fin RF I RF prescaler complimentary input.A bypass capacitor should be placed asclose as possible to this pin and be connected directly to the ground plane.87GND—Ground for RF PLL analog circuitry.98OSC RF I Dual mode oscillator output or RF R counter input.Has a V CC/2input thresholdwhen configured as an input and can be driven from an external CMOS or TTLlogic gate.109OSC IF I Oscillator input which can be configured to drive both the IF and RF R counterinputs or only the IF R counter depending on the state of the OSCprogramming bit.(See functional description1.1and programming description3.1.)1110Fo/LD O Multiplexed output of N or R divider and RF/IF lock detect.CMOS output.(Seeprogramming description3.1.5.)1211RF_EN I RF PLL Enable.Powers down RF N and R counters,prescaler,andTRI-STATE®charge pump output when LOW.Bringing RF_EN high powers upRF PLL depending on the state of RF_CTL_WORD.(See functional description1.9.)1312IF_EN I IF PLL Enable.Powers down IF N and R counters,prescaler,and TRI-STATEcharge pump output when LOW.Bringing IF_EN high powers up IF PLLdepending on the state of IF_CTL_WORD.(See functional description1.9.) 1413CLOCK I High impedance CMOS Clock input.Data for the various counters is clockedinto the24-bit shift register on the rising edge.1514DATA I Binary serial data input.Data entered MSB first.The last two bits are thecontrol bits.High impedance CMOS input.1615LE I Load Enable high impedance CMOS input.Data stored in the shift registers isloaded into one of the4internal latches when LE goes HIGH.(See functionaldescription1.7.)1716GND—Ground for IF analog circuitry.1817fin IF I IF prescaler complimentary input.A bypass capacitor should be placed asclose as possible to this pin and be connected directly to the ground plane. 1918fin IF I IF prescaler input.Small signal input from the VCO.2019GND—Ground for IF digital circuitry.2120CPo IF O IF charge pump output.For connection to a loop filter for driving the input of anexternal VCO.2221V PIF—Power supply for IF charge pump.Must be≥V CCRF and V CCIF.2322V CCIF —IF power supply voltage input.Must be equal to V CCRF.Input may range from2.7V to5.5V.Bypass capacitors should be placed as close as possible to thispin and be connected directly to the ground plane.2423OUT1O Programmable CMOS output.Level of the output is controlled by IF_N[18]bit.3Parameter SymbolValueU Min Typ MaxPower Supply Voltage V CCRF−0.3 6.5V CCIF−0.3 6.5Vp RF−0.3 6.5Vp IF−0.3 6.5 Voltage on any pin with GND=0V Vi−0.3V CC+0.3 Storage Temperature Range Ts−65+150 Lead Temperature(Solder4sec.)T L+260 Recommended Operating ConditionsParameter SymbolValueUn Min Typ MaxPower Supply Voltage V CCRF2.7 5.5V CCIF V CCRFV CCRFV pRF V CC 5.5V pIF V CC 5.5Operating Temperature T A−40+85˚Note1:“Absolute Maximum Ratings”indicate limits beyond which damage to the device may occur.Operating Ratings indicate conditions for which the intended to be functional,but do not guarantee specific performance limits.For guaranteed specifications and test conditions,see the Electrical Characteris guaranteed specifications apply only for the test conditions listed.Note2:This Device is a high performance RF integrated circuit with an ESD rating<2kV and is ESD sensitive.Handling and assembly of this device sho be done at ESD-free workstations.Electrical Characteristics(Vcc RF =V ccIF=V PRF=V PIF=3.0V;−40˚C<T A<+85˚C except as specified)All min/max specifications are guaranteed by design,or test,or statistical methods.Symbol Parameter ConditionsValueMin Typ MaxGENERALI CC Power Supply Current RF and IF 6.08.5IF Only 1.1 2.0 I CC-PWDN Power Down Current RF_EN=IF_EN=LOW2050 f in RF RF Operating Frequency0.5 2.5 f in IF IF Operating Frequency10550 f OSC Oscillator Frequency No load on OSC RF250 fφPhase Detector Frequency RF and IF10 Pf in RF RF Input Sensitivity V CC=3.0V−150V CC=5.0V−100 Pf in IF IF Input Sensitivity 2.7V≤V CC≤5.5V−100 V OSC Oscillator Sensitivity OSC IF,OSC RF0.5V CC CHARGE PUMPICPo-source RF RF Charge Pump OutputCurrent(see ProgrammingDescription3.2.2)VCPo Vp/2,RF_CP_WORD=0000−100ICPo-sink RF VCPo=Vp/2,RF_CP_WORD=0000100 ICPo-source RF VCPo=Vp/2,RF_CP_WORD=1111−1.6ICPo-sink RF VCPo=Vp/2,RF_CP_WORD=11111.6L4Symbol Parameter ConditionsValueUnits Min Typ MaxICPo-source IF IF Charge Pump OutputCurrent(see ProgrammingDescription3.1.4)VCPo=Vp/2,CP_GAIN_8=0−100µAICPo-sink IF VCPo=Vp/2,CP_GAIN_8=0100µA ICPo-source IF VCPo=Vp/2,CP_GAIN_8=1−800µA ICPo-sink IF VCPo=Vp/2,CP_GAIN_8=1800µAICPo-Tri Charge Pump TRI-STATECurrent 0.5≤VCPo≤Vp−0.5−40˚C<T A<+85˚C−2.5 2.5nARF ICPo-sink vs.ICPo-source RF CP Sink vs.SourceMismatchVCPo=Vp/2T A=25˚CRF ICPo=900µA−1.6mA3.510%ICPo vs.VCPo CP Current vs.VoltageVariation 0.5≤VCPo≤Vp−0.5T A=25˚C RF ICPo510%ICPo vs.T CP Current vsTemperature VCPo=Vp/2−40˚C<T A<+85˚C RF ICPo8%V CP Charge Pump OutputVoltage(RF only)2.7V≤V CC≤3.3V,DoublerEnabled2*V CC−0.5VDIGITAL INTERFACE(DATA,CLK,LE,EN,FoLD)V IH High-level Input Voltage(Note3)0.8V CC V V IL Low-level Input Voltage(Note3)0.2V CC V I IL Low-level Input Current V IL=0,V CC=5.5V,(Note3)−1.0 1.0µA I IH High-level Input Current V IH=V CC=5.5V,(Note3)−1.0 1.0µA I IH Oscillator Input Current V IH=V CC=5.5V100µA I IL Oscillator Input Current V IL=0,V CC=5.5V−100µA V OH High-level Output Voltage I OH=−500µA V CC−0.4V V OL High-level Output Voltage I OL=500µA0.4V MICROWIRE TIMINGt CS Data to Clock Setup Time See Data Input Timing50ns t CH Data to Clock Hold Time See Data Input Timing10ns t CWH Clock Pulse Width High See Data Input Timing50ns t CWL Clock Pulse Width Low See Data Input Timing50nst ES Clock to Load Enable SetUp Time See Data Input Timing50nst EW Load Enable Pulse Width See Data Input Timing50nsNote3:except f IN,OSC IF and OSC RF520004823 I1=CP sink current at V Do=Vp−∆VI2=CP sink current at V Do=Vp/2I3=CP sink current at V Do=∆VI4=CP source current at V Do=Vp−∆VI5=CP source current at V Do=Vp/2I6=CP source current at V Do=∆V∆V=Voltage offset from positive and negative rails.Dependent on VCO tuning range relative to V CC and ground.Typical values are between0.5V and Note4:I Do vs V Do=Charge Pump Output Current magnitude variation vs Voltage=[1⁄2*{||1|−||3|}]/[1⁄2*{||1|+||3|}]*100%and[1⁄2*{||4|−||6|}]/[1⁄2 ||6|}]*100%Note5:I Do-sink vs I Do-source=Charge Pump Output Current Sink vs Source Mismatch=[||2|−||5|]/[1⁄2*{||2|+||5|}]*100%Note6:I Do vs T A=Charge Pump Output Current magnitude variation vs Temperature=[||2@temp|−||2@25˚C|]/||2@25˚C|*100%and[||5@temp 25˚C|]/||5@25˚C|*100%620004824Note:N =10,000R =50P =16Note:Sensitivity limit is reached when the error of the divided RF output,F o LD,is ≥1Hz.Typical Performance CharacteristicsI CC vs V CC LMX2354I CPO TRI-STATE vsCP O Voltage2000482520004827Charge Pump Current vs CP O Voltage RF_CP_WORD =0000and 0111IF CP_GAIN_8=0and 1Charge Pump Current vs CP O Voltage RF_CP_WORD =0011and 111120004828200048297Sink vs Source Mismatch(See (Note 6)under Charge Pump CurrentSpecification Definitions)RF Input ImpedanceV CC =2.7V to 5.5V,f IN =550MHz to 2.5GHz (f IN Capacitor =100pF)20004830IF Input ImpedanceV CC =2.7V to 5.5V,f IN =50MHz to 550MHz (f IN Capacitor =100pF)LMX2354RF Sensitivity vs Frequency20004832200L 8IF Input Sensitivity vs Frequency Oscillator Input Sensitivity vs Frequency20004836200048359分销商库存信息:NATIONAL-SEMICONDUCTORLMX2354TM/NOPB LMX2354SLBX/NOPB LMX2354TMX/NOPB。
LM3551SDNOPB;LM3552SDNOPB;LM3551SDXNOPB;LM3552SDXNOPB;中文规格书,Datasheet资料
Electrical Characteristics (Note 2, Note 9)
Limits in standard typeface are for TJ = +25° C. Limits in boldface type apply over the full operating junction temperature range
Typical Application Circuits
© 2011 National Semiconductor Corporation 201512
/
20151205
LM3551/L
Connection Diagram
14 Pin Dual LLP Package
VIN pin: Voltage to GND SW pin: Voltage to GND FB pin: Voltage to GND VC pin: Voltage to GND SD,T/F pins: Voltage to GND FET-T, FET-F: Voltage to GND Continuous Power Dissipation (Note 3) Junction Temperature (TJ-MAX ) Storage Temperature Range Maximum Lead Temperature (Soldering) ESD Rating(Note 5) Human Body Model
7.5V 21V
LMZ10501SEXNOPB;LMZ10501SENOPB;LMZ10501SEENOPB;LMZ10501EVALNOPB;中文规格书,Datasheet资料
LMZ10501 1A SIMPLE SWITCHER® Nano Module with 5.5V Maximum Input Voltage
Literature Number: SNVS677B
/
SIMPLE SWITCHER® Nano Module with 5.5V Maximum Input Voltage
Key Features
■ Integrated inductor ■ Miniature form factor (3.0 mm x 2.5 mm x 1.2 mm) ■ 8-pin LLP footprint ■ -40°C to 125°C junction temperature range ■ Adjustable output voltage ■ 2.0MHz fixed PWM switching frequency ■ Integrated compensation ■ Soft start function ■ Current limit protection ■ Thermal shutdown protection ■ Input voltage UVLO for power-up, power-down, and
Supplied As 250 units, Tape-and-Reel 1000 units, Tape-and-Reel 3000 units, Tape-and-Reel
Note: The actual physical placement of the package marking will vary from part to part. The package marking “X” designates the date code. “V” is a NSC inter code for die traceability. Both will vary in production. “S” designates device type as switcher and “SP” identifies the device (part number).
LMX2310USLDXNOPB;LMX2311USLDXNOPB;LMX2312USLDXNOPB;LMX2313USLDXNOPB;中文规格书,Datasheet资料
LMX2310U/LMX2311U/LMX2312U/LMX2313U PLLatinum Ultra Low Power Frequency Synthesizerfor RF Personal Communications LMX2310U - 2.5 GHz, LMX2311U 2.0 GHz,LMX2312U - 1.2 GHz, LMX2313U - 600 MHz
14 15
GND CE
— Digital ground. I High impedance CMOS Chip Enable input. Provides logical power-down control of the device. Pull-up to VµC if unused. The Chip Enable is internally referenced to VµC.
Features
■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■
RF operation up to 2.5 GHz 2.7V to 5.5V operation Ultra Low Current Consumption Low prescaler values LMX2310/1/2U 32/33 or 16/17 LMX2313U 16/17 or 8/9 Excellent Phase Noise Internal balanced, low leakage charge pump Selectable Charge Pump Current Levels Selectable Fastlock mode with Time-Out Counter Low Voltage MICROWIRE interface (1.72V to VCC) Digital and Analog Lock Detect Small 20-pad Thin Chip Scale Package
LM5060Q1MMNOPB;LM5060MMXNOPB;LM5060MMNOPB;LM5060Q1MMXNOPB;中文规格书,Datasheet资料
Features
■ Available in Automotive grade / AEC Q-100 ■ Wide operating input voltage range: +5.5V to +65V ■ Less than 15 µA quiescent current in disabled mode ■ Controlled output rise time for safe connection of
capacitor close to this pin is recommended to suppress noise.
Over-Voltage
An external resistor divider from the system input voltage sets the Over-Voltage turn-off threshold. The GATE pin is pulled low when OVP exceeds the typical 2.0V threshold, but the
The operating voltage range is 5.5V to 65V. The internal power-on-reset (POR) circuit typically 2 VIN Supply Voltage Input switches to the active state when the VIN pin is greater than 5.1V. A small ceramic bypass
The LM5060 high-side protection controller provides intelligent control of a high-side N-Channel MOSFET during normal on/off transitions and fault conditions. In-rush current is controlled by the nearly constant rise time of the output voltage. A power good output indicates when the output voltage reaches the input voltage and the MOSFET is fully on. Input UnderVoltage Lock-Out, with hysteresis, is provided as well as programmable input Over-Voltage Protection. An enable input provides remote On / Off control. The programmable Under-Voltage Lock-Out input can be used as second enable input for safety redundancy. A single capacitor programs the initial start-up VGS fault detection delay time, the transition VDS fault detection delay time, and the continuous Over-Current VDS fault detection delay time. When a detected fault condition persists longer than the allowed fault delay time, the MOSFET is latched off until either the Enable input or the Under-Voltage Lock-Out input is toggled low and then high.
LMV324中文资料
1 2 3 4
+
8 7
+
+Vs Out2 -In2 +In2
Out1 -In1 +In1 -Vs
1 2 3 4
+
8 7
+
+Vs Out2 -In2 +In2
6 5
6 5
LMV324
TSSOP-14 SOIC-14
Out1 -In1 +In1 +Vs +In2 -In2 Out2
1 2 3 4 5 6 7
DATA SHEET LMV321/LMV358/LMV324
Pin Assignments
LMV321
SOT23-5 SC70-5
+In -Vs -In
1
+
5
+Vs
+In -Vs
1+5 Nhomakorabea+Vs
2 3
–
2 3
–
4
Out
-In
4
Out
LMV358
SOIC-8 MSOP-8
Out1 -In1 +In1 -Vs
Vo = 1Vpp >50kHz 100kHz 100kHz
DC
50
120
LO HI
0 50
1.3
RL = 10kΩ to Vs/2; LO1 RL = 10kΩ to Vs/2; HI1
0.1
2.6
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are determined from tested parameters. Notes: 1. Guaranteed by testing or statistical analysis at +25°C. 2. +IN and -IN are gates to CMOS transistors with typical input bias current of <1nA. CMOS leakage is too small to practically measure.
74HC245中文资料,74HC245N规格书,74HC245D技术文档,DATASHEET,NXP代理商
Table 1: Quick reference data GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns.
Symbol Parameter
Conditions
Min Typ Max Unit
Type 74HC245
tPHL, tPLH propagation delay An to Bn or Bn to An
7#43;125 °C DIP20
plastic dual in-line package; 20 leads (300 mil)
SOT146-1
74HCT245D
−40 °C to +125 °C SO20
plastic small outline package; 20 leads; body width 7.5 mm
6. Pinning information
6.1 Pinning
1 DIR 20 VCC
DIR 1 A0 2 A1 3 A2 4 A3 5 A4 6 A5 7 A6 8 A7 9 GND 10
20 VCC 19 OE 18 B0 17 B1 16 B2 245 15 B3 14 B4 13 B5 12 B6 11 B7
SOT163-1
74HCT245PW
−40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; SOT360-1 body width 4.4 mm
74HCT245DB
−40 °C to +125 °C SSOP20
74HC245DB
−40 °C to +125 °C SSOP20
APT24F50B;中文规格书,Datasheet资料
25 TJ = -55°C
TJ = 25°C 20
TJ = 125°C
15
10
5
0
0
5
10
15
20
25
ID, DRAIN CURRENT (A) Figure 5, Gain vs Drain Current
4 Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS. 5 Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any value of
VGS = 0V, VDS = 0V to 333V
Qg Qgs Qgd td(on)
tr td(off)
tf
Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Current Rise Time Turn-Off Delay Time Current Fall Time
nC ns
Source-Drain Diode Characteristics
Symbol Parameter
Test Conditions
Min Typ Max Unit
IS ISM VSD trr Qrr Irrm
dv/dt
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) 1 Diode Forward Voltage Reverse Recovery Time
24LC65SM;24C65SM;24LC65-ISM;24LC65-IP;24C65P;中文规格书,Datasheet资料
24AA65/24LC65/24C65 Device Selection TableFeatures:•Voltage Operating Range: 1.8V to 6.0V-Peak write current 3 mA at 6.0V-Maximum read current 150 μA at 6.0V-Standby current 1 μA, typical•Industry Standard Two-Wire Bus Protocol I2C™ Compatible•8-Byte Page, or Byte modes Available• 2 ms Typical Write Cycle Time, Byte or Page •64-Byte Input Cache for Fast Write Loads•Up to 8 devices may be connected to the same bus for up to 512K bits total memory•Including 100 kHz (1.8V ≤ Vcc < 4.5V) and 400 kHz (4.5V ≤ V CC≤ 6.0V) Compatibility •Programmable Block Security Options •Programmable Endurance Options•Schmitt Trigger, Filtered Inputs for Noise Suppression•Output Slope Control to Eliminate Ground Bounce •Self-Timed Erase and Write Cycles•Power-on/off Data Protection Circuitry •Endurance:-10,000,000 E/W cycles for a High EnduranceBlock-1,000,000 E/W cycles for a StandardEndurance Block•Electrostatic Discharge Protection > 4000V •Data Retention > 200 years•8-pin PDIP/SOIJ Packages• Temperature Ranges•Pb-Free and RoHS Compliant Description:The Microchip Technology Inc. 24AA65/24LC65/ 24C65 (24XX65)* is a “smart” 8K x 8 Serial Electrically Erasable PROM. This device has been developed for advanced, low-power applications such as personal communications, and provides the systems designer with flexibility through the use of many new user-pro-grammable features. The 24XX65 offers a relocatable 4K bit block of ultra-high-endurance memory for data that changes frequently. The remainder of the array, or 60K bits, is rated at 1,000,000 erase/write (E/W) cycles ensured. The 24XX65 features an input cache for fast write loads with a capacity of eight pages, or 64 bytes. This device also features programmable security options for E/W protection of critical data and/or code of up to fifteen 4K blocks. Functional address lines allow the connection of up to eight 24XX65’s on the same bus for up to 512K bits contiguous EEPROM memory. Advanced CMOS technology makes this device ideal for low-power nonvolatile code and data applications. The 24XX65 is available in the standard 8-pin plastic DIP and 8-pin surface mount SOIJ package.Package TypesPart Number V CC Range Page Size Temp. Ranges Packages 24AA65 1.8-6.0V64 Bytes C P, SM 24LC65 2.5-6.0V64 Bytes C, I P, SM 24C65 4.5-6.0V64 Bytes C, I, E P, SM-Industrial (I)-40°C to+85°C -Automotive (E)-40°C to+125°C24XX65A0A1A2V SS12348765V CCNCSCLSDA24XX65A0A1A2V SS12348765V CCNCSCLSDA PDIPSOIJ64K I2C™ Smart Serial™ EEPROM*24XX65 is used in this document as a generic partnumber for the 24AA65/24LC65/24C65 devices.© 2008 Microchip Technology Inc.DS21073K-page 124AA65/24LC65/24C65DS21073K-page 2© 2008 Microchip Technology Inc.Block DiagramPin Function TableHV GeneratorEEPROM Array Page LatchesYDECXDECSense Amp.R/W ControlMemory Control LogicI/O Control Logic SDA SCL V CC V SSI/OA2A1A0CacheName FunctionA0, A1, A2User Configurable Chip Selects V SS GroundSDA Serial Address/Data/I/O SCL Serial ClockV CC +1.8V to 6.0V Power Supply NCNo Internal Connection© 2008 Microchip Technology Inc.DS21073K-page 324AA65/24LC65/24C651.0ELECTRICAL CHARACTERISTICSAbsolute Maximum Ratings (†)V CC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. V SS ..........................................................................................................-0.6V to V CC +1.0V Storage temperature...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥ 4 kV TABLE 1-1:DC CHARACTERISTICSFIGURE 1-1:BUS TIMING START/STOP† NOTICE : Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability.DC CHARACTERISTICSV CC = +1.8V to +6.0VCommercial (C):T A =0°C to +70°C Industrial (I):T A =-40°C to +85°C Automotive (E):T A =-40°C to +125°C ParameterSym Min Max Units ConditionsA0, A1, A2, SCL and SDA pins:High-level input voltage Low-level input voltageHysteresis of Schmitt Trigger inputs Low-level output voltage V IHV IL V HYS V OL .7 V CC —.05 V CC——.3 V CC —.40V V V V (Note 1)I OL = 3.0 mA Input leakage current I LI —±1μA V IN = .1V to V CC Output leakage current I LO—±1μA V OUT = .1V to V CC Pin capacitance (all inputs/outputs)C IN , C OUT —10pF V CC = 5.0V (Note 1)T A = 25°C, F CLK = 1 MHz Operating current I CC Write I CC Read ——3150mA μA V CC = 6.0V, SCL = 400 kHz V CC = 6.0V, SCL = 400 kHz Standby current I CCS—5μAV CC = 5.0V, SCL = SDA = V CC A0, A1, A2 = V SSNote 1:This parameter is periodically sampled and not 100% tested.T SU :STAT HD :STAV HYST SU :STOStart StopSCLSDA24AA65/24LC65/24C65DS21073K-page 4© 2008 Microchip Technology Inc.TABLE 1-2:AC CHARACTERISTICSParameterSymbolV CC = 1.8V-6.0V STD. Mode V CC = 4.5-6.0V FAST Mode UnitsRemarksMinMax Min Max Clock frequencyF CLK —100—400kHz Clock high time T HIGH 4000—600—ns Clock low timeT LOW 4700—1300—ns SDA and SCL rise time T R —1000—300ns (Note 1)SDA and SCL fall time T F—300—300ns (Note 1)Start condition setup time T HD :STA 4000—600—ns After this period the first clock pulse is generated Start condition setup time T SU :STA 4700—600—ns Only relevant forrepeated Start conditionData input hold time T HD :DAT 0—0—ns Data input setup time T SU :DAT 250—100—ns Stop condition setup time T SU :STO 4000—600—ns Output valid from clock T AA —3500—900ns (Note 2)Bus free timeT BUF4700—1300—ns Time the bus must be free before a new transmission can start Output fall time from V IH min to V IL max T OF —25020 + 0.1C B250ns (Note 1), C B ≤ 100 pFInput filter spike suppression (SDA and SCL pins)T SP50—50—ns (Note 3)Write cycle time T WR—5—5ms/page (Note 4)EnduranceHigh Endurance Block Rest of Array 10M 1M ——10M 1M ——cycles 25°C, (Note 5)Note 1:Not 100 percent tested. C B = total capacitance of one bus line in pF.2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3:The combined T SP and V HYS specifications are due to new Schmitt Trigger inputs which provide improvednoise and spike suppression. This eliminates the need for a Ti specification for standard operation.4:The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the writecache for total time.5:This parameter is not tested but ensured by characterization. For endurance estimates in a specificapplication, please consult the Total Endurance™ Model which can be downloaded at .© 2008 Microchip Technology Inc.DS21073K-page 524AA65/24LC65/24C652.0FUNCTIONAL DESCRIPTIONThe 24XX65 supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus must be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XX65 works as slave.Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.3.0BUS CHARACTERISTICSThe following bus protocol has been defined:•Data transfer may be initiated only when the bus is not busy.•During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition.Accordingly, the following bus conditions have been defined (Figure 3-1).3.1Bus not Busy (A)Both data and clock lines remain high.3.2Start Data Transfer (B)A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.3.3Stop Data Transfer (C)A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition.3.4Data Valid (D)The state of the data line represents valid data when,after a Start condition, the data line is stable for the duration of the high period of the clock signal.The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device.3.5AcknowledgeEach receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit.A device that acknowledges must pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by NOT generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX65) must leave the data line high to enable the master to generate the Stop condition.Note:The 24XX65 does not generate any Acknowledge bits if an internal program-ming cycle is in progress.24AA65/24LC65/24C65DS21073K-page 6© 2008 Microchip Technology Inc.3.6Device AddressingA control byte is the first byte received following the Start condition from the master device. The control byte consists of a four-bit control code, for the 24XX65 this is set as ‘1010’ binary for read and write operations.The next three bits of the control byte are the device select bits (A2, A1, A0). They are used by the master device to select which of the eight devices are to be accessed. These bits are in effect the three Most Significant bits of the word address. The last bit of the control byte defines the operation to be performed.When set to a one a read operation is selected, when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 4-1). Because only A12..A0 are used, the upper three address bits must be zeros. The Most Significant bit of the Most Significant Byte is transferred first. Following the Start condition, the 24XX65monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a ‘1010’code and appropriate device select bits, the slave device (24XX65) outputs an Acknowledge signal on the SDA line. Depending upon the state of the R/W bit, the 24XX65 will select a read or write operation. FIGURE 3-2:CONTROL BYTE4.0WRITE OPERATION4.1Byte WriteFollowing the Start condition from the master, the con-trol code (four bits), the device select (three bits), and by the master transmitter. This indicates to the addressed slave receiver (24XX65) that a byte with a word address will follow after it has generated an Acknowledge bit during the ninth clock cycle. There-fore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the Address Pointer of the 24XX65. The next byte is the Least Significant Address Byte. After receiving another Acknowledge signal from the 24XX65, the master device will transmit the data word to be written into the addressed memory location. The 24XX65acknowledges again and the master generates a Stop condition. This initiates the internal write cycle, and during this time the 24XX65 will not generate Acknowledge signals (Figure 4-1).4.2Page WriteThe write control byte, word address and the first data byte are transmitted to the 24XX65 in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to eight pages of eight data bytes each (64 bytes total), which are temporarily stored in the on-chip page cache of the 24XX65. They will be written from the cache into the EEPROM array after the master has transmitted a Stop condition. After the receipt of each word, the six lower order Address Pointer bits are internally incremented by one. The higher order seven bits of the word address remain constant. If the master should transmit more than eight bytes prior to generating the Stop condition (writing across a page boundary), the address counter (lower three bits) will roll over and the pointer will be incremented to point to the next line in the cache. This can continue to occur up to eight times or until the cache is full, at which time a Stop condition should be generated by the master. If a Stop condition is not received, the cache pointer will roll over to the first line (byte 0) of the cache, and any further data received will overwrite previously captured data. The Stop condition can be sent at any time during the transfer. As with the byte write operation, once the Stop condition is received an internal write cycle will begin. The 64-byte cache will continue to capture data until a Stop condition occurs or the operation is aborted (Figure 4-2).Operation Control Code Device Select R/W Read 1010Device Address 1Write1010Device Address© 2008 Microchip Technology Inc.DS21073K-page 724AA65/24LC65/24C65FIGURE 4-1:BYTE WRITEFIGURE 4-2:PAGE WRITE (FOR CACHE WRITE, SEE FIGURE 8-2)FIGURE 4-3:CURRENT ADDRESS READ000Bus Activity Master SDA Line Bus ActivityS T A R T Control ByteWord Address (1)Word Address (0)DataA C KA C K A C KA C KS T O P SP Bus MasterSDA Line Bus Control Byte Word Address (1)S T O P S T A R TA C K0A C K A C K Activity Activity :A C K A C KData n Data n + 700Word Address (0)PS SPBus Activity Master SDA Line Bus ActivityS T A R T S T O P Control ByteData nA C KN OA C K24AA65/24LC65/24C65DS21073K-page 8© 2008 Microchip Technology Inc.FIGURE 4-4:RANDOM READFIGURE 4-5:SEQUENTIAL READSDA Line Bus Control ByteWord Address (1)S T O P S T A R TA C K A C K A C K ActivityA C KN O Data n000Word Address (0)S T A R T Control ByteA C KPSSPBus Activity Master SDA Line Bus ActivityS T O P Control ByteA C KN OA C KData n Data n + 1Data n + 2Data n + XA C KA C KA C K24AA65/24LC65/24C655.0READ OPERATIONRead operations are initiated in the same way as writeslave address is set to one. There are three basic types of read operations: current address read, random read and sequential read.5.1Current Address ReadThe 24XX65 contains an address counter that main-tains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24XX65 issues an acknowledge and transmits the eight-bit data word. The master will not acknowledge the transfer but does generate a Stop condition and the 24XX65 discontinues transmission (Figure4-3).5.2Random ReadRandom read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24XX65 as part of a write operation (R/W bit set to ‘0’). After the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then the master issues The 24XX65 will then issue an acknowledge and transmit the eight-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition which causes the 24XX65 to discontinue transmission (Figure4-4).5.3Sequential ReadSequential reads are initiated in the same way as a random read except that after the 24XX65 transmits the first data byte, the master issues an acknowledge as opposed to the Stop condition used in a random read. This acknowledge directs the 24XX65 to transmit the next sequentially addressed 8-bit word (Figure4-5). Following the final byte transmitted to the master, the master will NOT generate an acknowledge, but will generate a Stop condition.To provide sequential reads the 24XX65 contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation.5.4Contiguous Addressing AcrossMultiple DevicesThe device select bits A2, A1, A0 can be used to expand the contiguous address space for up to 512K bits by adding up to eight 24XX65's on the same bus. In this case, software can use A0 of the control byte as address bit A13, A1 as address bit A14 and A2 as address bit A15.5.5Noise ProtectionThe SCL and SDA inputs have filter circuits which suppress noise spikes to assure proper device operation even on a noisy bus. All I/O lines incorporate Schmitt Triggers for 400 kHz (Fast mode) compatibility.5.6High Endurance BlockThe location of the high endurance block within the memory map is programmed by setting the leading bit 7 (S/HE) of the configuration byte to ‘0’. The upper bits of the address loaded in this command will determine which 4K block within the memory map will be set to high endurance. This block will be capable of 10,000,000 erase/write cycles typical (Figure8-1). The high endurance block will retain its value as the high endurance block even if it resides within the security block range. The high endurance setting always takes precedence to the security setting. Note:The high endurance block cannot be changed after the security option has beenset with a length greater than zero. If theH.E. block is not programmed by the user,the default location is the highest block ofmemory which starts at location 0x1E00and ends at 0x1FFF.© 2008 Microchip Technology Inc.DS21073K-page 924AA65/24LC65/24C65DS21073K-page 10© 2008 Microchip Technology Inc.5.7Security OptionsThe 24XX65 has a sophisticated mechanism for write protecting portions of the array. This write-protect function is programmable and allows the user to protect 0-15 contiguous 4K blocks. The user sets the security option by sending to the device the starting block number for the protected region and the number of blocks to be protected. All parts will come from the factory in the default configuration with the starting block number set to 15 and the number of protected blocks set to zero. THE SECURITY OPTION CAN BE SET ONLY ONCE WITH A LENGTH GREATER THAN ZERO.To invoke the security option, a Write command is sent to the device with the leading bit (bit 7) of the first address byte set to a ‘1’ (Figure 8-1). Bits 1-4 of the first address byte define the starting block number for the protected region.For example, if the starting block number is to be set to 5, the first address byte would be 1XX0101X . Bits 0, 5and 6 of the first address byte are disregarded by the device and can be either high or low. The device will acknowledge after the first address byte. A byte of “don’t care” bits is then sent by the master, with the device acknowledging afterwards. The third byte sent to the device has bit 7 (S/HE) set high and bit 6 (R) set low. Bits 4 and 5 are “don’t cares” and bits 0-3 define the number of blocks to be write-protected. For exam-ple, if three blocks are to be protected, the third byte would be 10XX0011. After the third byte is sent to the device, it will acknowledge and a Stop bit is then sent by the master to complete the command.If one of the security blocks coincides with the high endurance block, the high endurance setting will take precedence. Also, if the range of the security blocks encompass the high endurance block when the secu-rity option is set, the security block range will be set accordingly, but the high endurance block will continue to retain the high endurance setting. As a result, the memory blocks preceding the high endurance block will be set as secure sections.During a normal write sequence, if an attempt is made to write to a protected address, no data will be written and the device will not report an error or abort the command. If a Write command is attempted across a secure boundary, unprotected addresses will be written and protected addresses will not.5.8Security Configuration ReadThe status of the secure portion of memory can be read by using the same technique as programming this option except the read bit (bit 6) of the configuration byte is set to a one. After the configuration byte is sent,the device will acknowledge and then send two bytes of data to the master just as in a normal read sequence.The master must acknowledge the first byte and notacknowledge the second, and then send a Stop bit to end the sequence. The upper four bits of both of these bytes will always be read as ‘1’s. The lower four bits of the first byte contains the starting secure block. The lower four bits of the second byte contains the number of secure blocks. The default starting secure block is fifteen and the default number of secure blocks is zero (Figure 8-1).6.0ACKNOWLEDGE POLLINGSince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a Write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned.If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 6-1 for flow diagram.FIGURE 6-1:ACKNOWLEDGE POLLING FLOWSendWrite CommandSend Stop Condition to Initiate Write CycleSend StartSend Control Byte with R/W = 0Did Device Acknowledge (ACK = 0)?Next OperationNOYES分销商库存信息:MICROCHIP24LC65/SM24C65/SM24LC65-I/SM 24LC65-I/P24C65/P24C65-I/SM 24LC65/P24C65-I/P24AA65/SM 24AA65T/SM24C65T-I/SM24C65T/SM 24LC65T-I/SM24LC65T/SM24AA65/P。
LMK04808BISQENOPB;LMK04806BISQENOPB;LMK04803BISQENOPB;LMK04808BISQNOPB;中文规格书,Datasheet资料
LMK04800 FamilyMarch 29, 2012 Low-Noise Clock Jitter Cleaner with Dual Loop PLLs1.0 General DescriptionThe LMK04800 family is the industry's highest performance clock conditioner with superior clock jitter cleaning, genera-tion, and distribution with advanced features to meet next generation system requirements. The dual loop PLLat-inum™ architecture enables 111 fs rms jitter (12 kHz to 20 MHz) using a low noise VCXO module or sub-200 fs rms jitter (12 kHz to 20 MHz) using a low cost external crystal and var-actor diode.The dual loop architecture consists of two high-performance phase-locked loops (PLL), a low-noise crystal oscillator cir-cuit, and a high-performance voltage controlled oscillator (VCO). The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock gen-eration. PLL1 can be configured to either work with an exter-nal VCXO module or the integrated crystal oscillator with an external tunable crystal and varactor diode. When used with a very narrow loop bandwidth, PLL1 uses the superior close-in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2 where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimized to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.Device VCO FrequencyLMK04803B1840 to 2030 MHzLMK04805B2148 to 2370 MHzLMK04806B2370 to 2600 MHzLMK04808B2750 to 3072 MHz 2.0 Features■Ultra-Low RMS Jitter Performance—111 fs RMS jitter (12 kHz to 20 MHz)—123 fs RMS jitter (100 Hz to 20 MHz)■Dual Loop PLLatinum PLL Architecture—PLL1■Integrated Low-Noise Crystal Oscillator Circuit■Holdover mode when input clocks are lost—Automatic or manual triggering/recovery —PLL2■Normalized [1 Hz] PLL noise floor of -227 dBc/Hz■Phase detector rate up to 155 MHz■OSCin frequency-doubler■Integrated Low-Noise VCO■ 2 redundant input clocks with LOS—Automatic and manual switch-over modes■50% duty cycle output divides, 1 to 1045 (even and odd)■LVPECL, LVDS, or LVCMOS programmable outputs■Precision digital delay, fixed or dynamically adjustable ■25 ps step analog delay control.■14 differential outputs. Up to 26 single ended.—Up to 6 VCXO/Crystal buffered outputs■Clock rates of up to 1536 MHz■0-delay mode■Three default clock outputs at power up■Multi-mode: Dual PLL, single PLL, and clock distribution ■Industrial Temperature Range: -40 to 85 °C■ 3.15 V to 3.45 V operation■Package: 64-pin LLP (9.0 x 9.0 x 0.8 mm)3.0 Target Applications■Data Converter Clocking / Wireless Infrastructure■Networking, SONET/SDH, DSLAM■Medical / Video / Military / Aerospace■Test and Measurement30102340PLLatinum™ is a trademark of National Semiconductor Corporation.TRI-STATE® is a registered trademark of National Semiconductor Corporation.© 2012 Texas Instruments Incorporated301023 SNAS489I LMK04800 Family Low-Noise Clock Jitter Cleaner with Dual Loop PLLs4.0 Device Configuration Information NSIDReference Inputs Dedicated Buffered/Divided OSCin Clock Programmable LVDS/LVPECL/LVCMOS Outputs (Note 1)VCO LMK04803BISQ22121840 to 2030 MHz LMK04805BISQ22122148 to 2370 MHz LMK04806BISQ22122370 to 2600 MHz LMK04808BISQ 22122750 to 3072 MHz Note 1:Up to 4 of these outputs are also able to be driven by the OSCin clock.5.0 Functional Block Diagrams and Operating ModesThe LMK048xx is a flexible device that can be configured for many different use cases. The following simplified block diagrams help show the user the different use cases of the device.5.1 Dual PLLFigure 1 illustrates the typical use case of the LMK048xx in dual loop mode. In dual loop mode the reference to PLL1 is either CLKin0 or CLKin1. An external VCXO or tunable crystal will be used to provide feedback for the first PLL and a reference to the second PLL. This first PLL cleans the jitter with the VCXO or low cost tunable crystal by using a narrow loop bandwidth. The VCXO or tunable crystal output may be buffered through the two OSCout ports and optionally on up to 4 of the CLKouts. The VCXO or tunable crystal is used as the reference to PLL2 and may be doubled using the frequency doubler. The internal VCO drives up to six divide/delay blocks which drive 12 clock outputs.Holdover functionality is optionally available when the input reference clock is lost. Holdover works by fixing the tuning voltage of PLL1 to the VCXO or tunable crystal.It is also possible to use an external VCO in place of PLL2's internal VCO.30102308FIGURE 1. Simplified Functional Block Diagram for Dual Loop Mode 2L M K 04800 F a m i l y5.2 0-Delay Dual PLLFigure 2 illustrates the use case of 0-delay dual loop mode. This configuration is very similar to Section 5.1 Dual PLL except that the feedback to the first PLL is driven by a clock output. This causes the clock outputs to have deterministic phase with the clock input. Since all the clock outputs can be synchronized together, all the clock outputs can be in phase with the clock input signal. The feedback to PLL1 can be connected internally as shown, or externally using FBCLKin (CLKin1) as an input port.It is also possible to use an external VCO in place of PLL2's internal VCO.30102309 FIGURE 2. Simplified Functional Block Diagram for 0-delay Dual Loop Mode5.3 Single PLLFigure 3 illustrates the use case of single PLL mode. In single PLL mode only PLL2 is used and PLL1 is powered down. OSCin is used as the reference input. The internal VCO drives up to 6 divide/delay blocks which drive 12 clock outputs. The reference at OSCin can be used to drive up to 2 OSCout ports. OSCin can also optionally drive up to 4 of the clock outputs.It is also possible to use an external VCO in place of PLL2's internal VCO.30102310FIGURE 3. Simplified Functional Block Diagram for Single Loop Mode LMK04800 Family5.4 0-delay Single PLL Figure 4 illustrates the use case of 0-delay single PLL mode. This configuration is very similar to Section 5.3 Single PLL except that the feedback to PLL2 comes from a clock output. This causes the clock outputs to be in phase with the reference input. Since all the clock outputs can be synchronized together, all the clock outputs can be in phase with the clock input signal. The feedback to PLL2 can be performed internally as shown, or externally using FBCLKin (CLKin1) as an input port.It is also possible to use an external VCO in place of PLL2's internal VCO.30102311FIGURE 4. Simplified Functional Block Diagram for 0-delay Single Loop Mode5.5 Clock DistributionFigure 5 illustrates the LMK04800 used for clock distribution. CLKin1 is used to drive up to 6 divide/delay blocks which drive 12outputs. OSCin can be used to drive up to 2 OSCout ports. OSCin can also optionally drive up to 4 of the clock outputs.30102312FIGURE 5. Simplified Functional Block Diagram for Mode Clock Distribution 4L M K 04800 F a m i l y5.6 Detailed LMK0480x Block DiagramFigure 6 illustrates the complete LMK0480x block diagram for the LMK0480x family.30102301FIGURE 6. Detailed LMK0480x Block Diagram LMK04800 FamilyTable of Contents 1.0 General Description ......................................................................................................................... 12.0 Features ........................................................................................................................................ 13.0 Target Applications .......................................................................................................................... 14.0 Device Configuration Information ....................................................................................................... 25.0 Functional Block Diagrams and Operating Modes ................................................................................ 25.1 Dual PLL (2)5.2 0-Delay Dual PLL (3)5.3 Single PLL (3)5.4 0-delay Single PLL (4)5.5 Clock Distribution (4)5.6 Detailed LMK0480x Block Diagram (5)6.0 Connection Diagram ...................................................................................................................... 107.0 Pin Descriptions (Note 2). (11)8.0 Absolute Maximum Ratings (13)9.0 Package Thermal Resistance (13)10.0 Recommended Operating Conditions (13)11.0 Electrical Characteristics (14)12.0 Serial MICROWIRE Timing Diagram (22)12.1 ADVANCED MICROWIRE TIMING DIAGRAMS (22)12.1.1 3 Extra Clocks or Double Program (22)12.1.2 Three Extra Clocks with LEuWire High (23)12.1.3 Readback (23)13.0 Measurement Definitions (24)13.1 CHARGE PUMP CURRENT SPECIFICATION DEFINITIONS (24)13.1.1 Charge Pump Output Current Magnitude Variation Vs. Charge Pump Output Voltage (24)13.1.2 Charge Pump Sink Current Vs. Charge Pump Output Source Current Mismatch (24)13.1.3 Charge Pump Output Current Magnitude Variation Vs. Temperature ................................. 2413.2 DIFFERENTIAL VOLTAGE MEASUREMENT TERMINOLOGY (Note 28) (25)14.0 Typical Performance Characteristics (26)14.2 CLOCK OUTPUT AC CHARACTERISTICS (26)15.0 Features (27)15.1 SYSTEM ARCHITECTURE (27)15.2 PLL1 REDUNDANT REFERENCE INPUTS (CLKin0/CLKin0* and CLKin1/CLKin1*) (27)15.3 PLL1 TUNABLE CRYSTAL SUPPORT (27)15.4 VCXO/CRYSTAL BUFFERED OUTPUTS (27)15.5 FREQUENCY HOLDOVER (27)15.6 INTEGRATED LOOP FILTER POLES (27)15.7 INTERNAL VCO (27)15.8 EXTERNAL VCO MODE (28)15.9 CLOCK DISTRIBUTION (28)15.9.1 CLKout DIVIDER (28)15.9.2 CLKout DELAY (28)15.9.3 PROGRAMMABLE OUTPUT TYPE (28)15.9.4 CLOCK OUTPUT SYNCHRONIZATION (28)15.10 0-DELAY (28)15.11 DEFAULT STARTUP CLOCKS (28)15.12 STATUS PINS (28)15.13 REGISTER READBACK (28)16.0 Functional Description (29)16.1 FUNCTIONAL OVERVIEW (29)16.2 MODE SELECTION (29)16.3 INPUTS / OUTPUTS (29)16.3.1 PLL1 Reference Inputs (CLKin0 and CLKin1) (29)16.3.2 PLL2 OSCin / OSCin* Port (29)16.3.3 CRYSTAL OSCILLATOR (29)16.4 INPUT CLOCK SWITCHING (30)16.4.1 Input Clock Switching - Manual Mode (30)16.4.2 Input Clock Switching - Pin Select Mode (30)16.4.3 Input Clock Switching - Automatic Mode (30)16.4.4 Input Clock Switching - Automatic Mode with Pin Select (31)16.5 HOLDOVER MODE (31)16.5.1 Holdover Frequency Accuracy and DAC Performance (32)16.5.2 Holdover Mode - Automatic Exit of Holdover (32)16.6 PLLs ................................................................................................................................... 6L M K 04800 F a m i l yLMK04800 Family16.6.1 PLL1 (32)16.6.2 PLL2 (32)16.6.2.1 PLL2 FREQUENCY DOUBLER (32)16.6.3 DIGITAL LOCK DETECT (33)16.7 STATUS PINS (33)16.7.1 Logic Low (33)16.7.2 Digital Lock Detect (33)16.7.3 Holdover Status (33)16.7.4 DAC (33)16.7.5 PLL Divider Outputs (33)16.7.6 CLKinX_LOS (33)16.7.7 CLKinX Selected (33)16.7.8 MICROWIRE Readback (33)16.8 VCO (33)16.9 CLOCK DISTRIBUTION (34)16.9.1 Fixed Digital Delay (34)16.9.1.1 FIXED DIGITAL DELAY - EXAMPLE (34)16.9.2 Clock Output Synchronization (SYNC) (34)16.9.2.1 DYNAMICALLY PROGRAMMING DIGITAL DELAY (36)16.9.2.1.1 Absolute Dynamic Digital Delay (38)16.9.2.1.1.1 ABSOLUTE DYNAMIC DIGITAL DELAY - EXAMPLE (38)16.9.2.1.2 Relative Dynamic Digital Delay (40)16.9.2.1.2.1 RELATIVE DYNAMIC DIGITAL DELAY - EXAMPLE (40)16.9.3 0-Delay Mode (42)17.0 General Programming Information (43)17.1 SPECIAL PROGRAMMING CASE FOR R0 to R5 for CLKoutX_Y_DIV & CLKoutX_Y_DDLY (43)17.1.1 Example (43)17.2 RECOMMENDED PROGRAMMING SEQUENCE (43)17.2.1 Overview (43)17.3 READBACK (44)17.3.1 Readback - Example (44)17.4 REGISTER MAP AND READBACK REGISTER MAP (44)17.5 DEFAULT DEVICE REGISTER SETTINGS AFTER POWER ON RESET (49)17.6 REGISTER R0 TO R5 (53)17.6.1 CLKoutX_Y_PD, Powerdown CLKoutX_Y Output Path (53)17.6.2 CLKoutX_Y_OSCin_Sel, Clock group source (53)17.6.3 CLKoutY_ADLY_SEL[29], CLKoutX_ADLY_SEL[28], Select Analog Delay (53)17.6.4 CLKoutX_Y_DDLY, Clock Channel Digital Delay (53)17.6.5 RESET (53)17.6.6 POWERDOWN (54)17.6.7 CLKoutX_Y_HS, Digital Delay Half Shift (54)17.6.8 CLKoutX_Y_DIV, Clock Output Divide (54)17.7 REGISTERS R6 TO R8 (54)17.7.1 CLKoutX_TYPE (54)17.7.2 CLKoutX_Y_ADLY (55)17.8 REGISTER R10 (56)17.8.1 OSCout1_LVPECL_AMP, LVPECL Output Amplitude Control (56)17.8.2 OSCout0_TYPE (56)17.8.3 EN_OSCoutX, OSCout Output Enable (56)17.8.4 OSCoutX_MUX, Clock Output Mux (56)17.8.5 PD_OSCin, OSCin Powerdown Control (56)17.8.6 OSCout_DIV, Oscillator Output Divide (57)17.8.7 VCO_MUX (57)17.8.8 EN_FEEDBACK_MUX (57)17.8.9 VCO_DIV, VCO Divider (57)17.8.10 FEEDBACK_MUX (57)17.9 REGISTER R11 (58)17.9.1 MODE: Device Mode (58)17.9.2 EN_SYNC, Enable Synchronization (58)17.9.3 NO_SYNC_CLKoutX_Y (58)17.9.4 SYNC_MUX (58)17.9.5 SYNC_QUAL (59)17.9.6 SYNC_POL_INV (59)17.9.7 SYNC_EN_AUTO (59)17.9.8 SYNC_TYPE (59)17.9.9 EN_PLL2_XTAL (59)17.10 REGISTER R12................................................................................................................. 6017.10.1 LD_MUX .................................................................................................................. 6017.10.2 LD_TYPE ................................................................................................................ 6017.10.3 SYNC_PLLX_DLD .................................................................................................... 6017.10.4 EN_TRACK ............................................................................................................. 6017.10.5 HOLDOVER_MODE ................................................................................................. 6017.11 REGISTER R13................................................................................................................. 6117.11.1 HOLDOVER_MUX . (61)17.11.2 HOLDOVER_TYPE (61)17.11.3 Status_CLKin1_MUX (61)17.11.4 Status_CLKin0_TYPE (61)17.11.5 DISABLE_DLD1_DET (61)17.11.6 Status_CLKin0_MUX (61)17.11.7 CLKin_SELECT_MODE (62)17.11.8 CLKin_Sel_INV (62)17.11.9 EN_CLKinX (62)17.12 REGISTER 14 (63)17.12.1 LOS_TIMEOUT (63)17.12.2 EN_LOS (63)17.12.3 Status_CLKin1_TYPE (63)17.12.4 CLKinX_BUF_TYPE, PLL1 CLKinX/CLKinX* Buffer Type (63)17.12.5 DAC_HIGH_TRIP (63)17.12.6 DAC_LOW_TRIP (63)17.12.7 EN_VTUNE_RAIL_DET (63)17.13 REGISTER 15 (64)17.13.1 MAN_DAC (64)17.13.2 EN_MAN_DAC (64)17.13.3 HOLDOVER_DLD_CNT (64)17.13.4 FORCE_HOLDOVER (64)17.14 REGISTER 16 (64)17.14.1 XTAL_LVL (64)17.15 REGISTER 23 (64)17.15.1 DAC_CNT (64)17.16 REGISTER 24 (64)17.16.1 PLL2_C4_LF, PLL2 Integrated Loop Filter Component (64)17.16.2 PLL2_C3_LF, PLL2 Integrated Loop Filter Component (65)17.16.3 PLL2_R4_LF, PLL2 Integrated Loop Filter Component (65)17.16.4 PLL2_R3_LF, PLL2 Integrated Loop Filter Component (65)17.16.5 PLL1_N_DLY (65)17.16.6 PLL1_R_DLY (65)17.16.7 PLL1_WND_SIZE (65)17.17 REGISTER 25 (66)17.17.1 DAC_CLK_DIV (66)17.17.2 PLL1_DLD_CNT (66)17.18 REGISTER 26 (66)17.18.1 PLL2_WND_SIZE (66)17.18.2 EN_PLL2_REF_2X, PLL2 Reference Frequency Doubler (66)17.18.3 PLL2_CP_POL, PLL2 Charge Pump Polarity (66)17.18.4 PLL2_CP_GAIN, PLL2 Charge Pump Current (66)17.18.5 PLL2_DLD_CNT (66)17.18.6 PLL2_CP_TRI, PLL2 Charge Pump TRI-STATE (66)17.19 REGISTER 27 (67)17.19.1 PLL1_CP_POL, PLL1 Charge Pump Polarity (67)17.19.2 PLL1_CP_GAIN, PLL1 Charge Pump Current (67)17.19.3 CLKinX_PreR_DIV (67)17.19.4 PLL1_R, PLL1 R Divider (67)17.19.5 PLL1_CP_TRI, PLL1 Charge Pump TRI-STATE (67)17.20 REGISTER 28 (68)17.20.1 PLL2_R, PLL2 R Divider (68)17.20.2 PLL1_N, PLL1 N Divider (68)17.21 REGISTER 29 (68)17.21.1 OSCin_FREQ, PLL2 Oscillator Input Frequency Register (68)17.21.2 PLL2_FAST_PDF, High PLL2 Phase Detector Frequency (68)17.21.3 PLL2_N_CAL, PLL2 N Calibration Divider (68)17.22 REGISTER 30 (69)17.22.1 PLL2_P, PLL2 N Prescaler Divider (69) 8L M K 04800 F a m i l yLMK04800 Family17.22.2 PLL2_N, PLL2 N Divider (69)17.23 REGISTER 31 (69)17.23.1 READBACK_LE (69)17.23.2 READBACK_ADDR (69)17.23.3 uWire_LOCK (69)18.0 Application Information (70)18.1 FREQUENCY PLANNING WITH THE LMK04800 FAMILY (Note 36) (70)18.2 PLL PROGRAMMING (71)18.2.1 Example PLL2 N Divider Programming (71)18.3 LOOP FILTER (72)18.3.1 PLL1 (72)18.3.2 PLL2 (72)18.4 SYSTEM LEVEL DIAGRAM (73)18.5 PIN CONNECTION RECOMMENDATIONS (75)18.5.1 Vcc Pins and Decoupling (75)18.5.1.1 Vcc2, Vcc3, Vcc10, Vcc11, Vcc12, Vcc13 (CLKout Vccs) (75)18.5.1.2 Vcc1 (VCO), Vcc4 (Digital), and Vcc9 (PLL2) (75)18.5.1.3 Vcc6 (PLL1 Charge Pump) and Vcc8 (PLL2 Charge Pump) (75)18.5.1.4 Vcc5 (CLKin & OSCout1), Vcc7 (OSCin & OSCout0) (75)18.5.2 LVPECL Outputs (75)18.5.3 Unused Clock Outputs (75)18.5.4 Unused Clock Inputs (75)18.5.5 LDO Bypass (75)18.6 DIGITAL LOCK DETECT FREQUENCY ACCURACY (76)18.6.1 Minimum Lock Time Calculation Example (76)18.7 CALCULATING DYNAMIC DIGITAL DELAY VALUES FOR ANY DIVIDE (77)18.7.1 Example (77)18.8 OPTIONAL CRYSTAL OSCILLATOR IMPLEMENTATION (OSCin/OSCin*) (79)18.9 DRIVING CLKin AND OSCin INPUTS (82)18.9.1 Driving CLKin Pins with a Differential Source (82)18.9.2 Driving CLKin Pins with a Single-Ended Source (82)18.10 TERMINATION AND USE OF CLOCK OUTPUT (DRIVERS) (83)18.10.1 Termination for DC Coupled Differential Operation (83)18.10.2 Termination for AC Coupled Differential Operation (83)18.10.3 Termination for Single-Ended Operation (84)18.11 POWER SUPPLY (85)18.11.1 Current Consumption / Power Dissipation Calculations (85)18.12 THERMAL MANAGEMENT (87)19.0 Physical Dimensions (88)20.0 Ordering Information (88)6.0 Connection Diagram 64-Pin LLP Package30102302 10L M K 04800 F a m i l y分销商库存信息:NATIONAL-SEMICONDUCTORLMK04808BISQE/NOPB LMK04806BISQE/NOPB LMK04803BISQE/NOPB LMK04805BISQE/NOPB LMK04808BISQ/NOPB LMK04808BISQX/NOPB LMK04803BISQ/NOPB LMK04803BISQX/NOPB LMK04805BISQ/NOPB LMK04805BISQX/NOPB LMK04806BISQ/NOPB LMK04806BISQX/NOPB。
LM2642MTCNOPB;LM2642MTCXNOPB;中文规格书,Datasheet资料
LM2642LM2642 Two-Phase Synchronous Step-Down Switching ControllerLiterature Number: SNVS203HLM2642Two-Phase Synchronous Step-Down Switching ControllerGeneral DescriptionThe LM2642consists of two current mode synchronous buck regulator controllers with a switching frequency of 300kHz.The two switching regulator controllers operate 180˚out of phase.This feature reduces the input ripple RMS current,thereby significantly reducing the required input capacitance.The two switching regulator outputs can also be paralleled to operate as a dual-phase single output regulator.The output of each channel can be independently adjusted from 1.3to V IN •maximum duty cycle.An internal 5V rail is also available externally for driving bootstrap circuitry.Current-mode feedback control assures excellent line and load regulation and a wide loop bandwidth for excellent response to fast load transients.Current is sensed across either the Vds of the top FET or across an external current-sense resistor connected in series with the drain of the top FET.Current limit is independently adjustable for each chan-nel.The LM2642features analog soft-start circuitry that is inde-pendent of the output load and output capacitance.This makes the soft-start behavior more predictable and control-lable than traditional soft-start circuits.A PGOOD1pin is provided to monitor the dc output of channel 1.Over-voltage protection is available for both out-puts.A UV-Delay pin is also available to allow delayed shut off time for the IC during an output under-voltage event.Featuresn Two synchronous buck regulators n 180˚out of phase operation n 4.5V to 30V input rangen Power good function monitors Ch.1n 37µA Shutdown currentn 0.04%(typical)line and load regulation errorn Current mode control with or without a sense resistor n Independent enable/soft-start pins allow simple sequential startup configuration.n Configurable for single output parallel operation.(See Figure 2).n Adjustable cycle-by-cycle current limit n Input under-voltage lockoutn Output over-voltage latch protectionn Output under-voltage protection with delay n Thermal shutdownn Self discharge of output capacitors when the regulator is OFFnTSSOP packageApplicationsn Embedded computer systems n High end gaming systems n Set-top boxes nWebPADBlock Diagram20046201©2006National Semiconductor Corporation TOP VIEW20046202 28-Lead TSSOP(MTC) Order NUmber LM2642MTC See NS Package Number MTC28Pin DescriptionsKS1(Pin1):The positive(+)Kelvin sense for the internalcurrent sense amplifier of e a separate trace toconnect this pin to the current sense point.It should beconnected to VIN as close as possible to the node of thecurrent sense resistor.When no current-sense resistor isused,connect as close as possible to the drain node of theupper MOSFET.ILIM1(Pin2):Current limit threshold setting for Channel1.Itsinks a constant current of10µA,which is converted to avoltage across a resistor connected from this pin to VIN.Thevoltage across the resistor is compared with either the VDSof the top MOSFET or the voltage across the external cur-rent sense resistor to determine if an over-current conditionhas occurred in Channel1.COMP1(Pin3):Compensation pin for Channel1.This is theoutput of the internal transconductance amplifier.The com-pensation network should be connected between this pinand the signal ground,SGND(Pin8).FB1(Pin4):Feedback input for channel 1.Connect toVOUT through a voltage divider to set the channel1outputvoltage.PGOOD1(Pin5):An open-drain power-good output forChannel1.It is’LOW’(low impedance to ground)wheneverthe output voltage of Channel1falls outside of a+15%to-9%window.PGOOD1stays latched in a’LOW’state duringOVP or UVP on either channel.It will recover to a’HIGH’state(high impedance to ground)after a Channel1outputunder-voltage event(<91%)when the output returns to within6%of its nominal value.See Operation Descriptionsfor details.UV_DELAY(Pin6):A capacitor from this pin to ground setsthe delay time for UVP.The capacitor is charged from a5µAcurrent source.When UV_DELAY charges to2.3V(typical),the system immediately latches off.Connecting this pin toground will disable the output under-voltage protection.VLIN5(Pin7):The output of an internal5V LDO re derived from VIN.It supplies the internal bias for the ch supplies the bootstrap circuitry for gate drive.Bypass t to signal ground with a minimum of4.7µF capacitor. SGND(Pin8):The ground connection for the signa circuitry.It should be connected to the ground rail system.ON/SS1(Pin9):Channel1enable pin.This pin is int pulled up to one diode drop above VLIN5.Pulling t below1.2V(open-collector type)turns off Channel1. ON/SS1and ON/SS2pins are pulled below1.2V,the chip goes into shut down mode.Adding a capacitor pin provides a soft-start feature that minimizes inrush c and output voltage overshoot.ON/SS2(Pin10):Channel2enable pin.See the desc for Pin9,ON/SS1.May be connected to ON/SS1for taneous startup or for parallel operation.FB2(Pin11):Feedback input for channel2.Conn VOUT through a voltage divider to set the Channel2 voltage.COMP2(Pin12):Compensation pin for Channel2. the output of the internal transconductance amplifie compensation network should be connected betwee pin and the signal ground SGND(Pin8).ILIM2(Pin13):Current limit threshold setting for Cha See ILIM1(Pin2).KS2(Pin14):The positive(+)Kelvin sense for the i current sense amplifier of Channel2.See KS1(Pin1 RSNS2(Pin15):The negative(-)Kelvin sense f internal current sense amplifier of Channel2.Conne pin to the low side of the current sense resistor that is between VIN and the drain of the top MOSFET.Wh Rds of the top MOSFET is used for current sensing,c this pin to the source of the top MOSFET.Always separate trace to form a Kelvin connection to this pin2is connected to the source of the top MOSFET of Channel2. It serves as the negative supply rail for the top-side gate driver,HDRV2.HDRV2(Pin17):Top-side gate-drive output for Channel2. HDRV is a floating drive output that rides on the correspond-ing switching-node voltage.CBOOT2(Pin18):Bootstrap capacitor connection.It serves as the positive supply rail for the Channel2top-side gate drive.Connect this pin to VDD2(Pin19)through a diode, and connect the low side of the bootstrap capacitor to SW2 (Pin16).VDD2(Pin19):The supply rail for the Channel2low-side gate drive.Connected to VLIN5(Pin7)through a 4.7Ωresistor and bypassed to power ground with a ceramic ca-pacitor of at least1µF.Tie this pin to VDD1(Pin24). LDRV2(Pin20):Low-side gate-drive output for Channel2. PGND(Pin21):The power ground connection for both channels.Connect to the ground rail of the system.connected to the same voltage rail as the top FET drain(orthe current sense resistor when used).LDRV1(Pin23):Low-side gate-drive output for Channel1.VDD1(Pin24):The supply rail for Channel1low-side gatedrive.Tie this pin to VDD2(Pin19).CBOOT1(Pin25)::Bootstrap capacitor connection.Itserves as the positive supply rail for Channel1top-side gatedrive.See CBOOT2(Pin18).HDRV1(Pin26):Top-side gate-drive output for Channel1.See HDRV2(Pin17).SW1(Pin27):Switch-node connection for Channel1.SeeSW2(Pin16).RSNS1(Pin28):The negative(-)Kelvin sense for theinternal current sense amplifier of Channel1.See RSNS2(Pin15). 3please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Voltages from the indicated pins to SGND/PGND:VIN,ILIM1,ILIM2,KS1,KS2−0.3V to32V SW1,SW2,RSNS1,RSNS2−0.3to(V IN+0.3)V FB1,FB2,VDD1,VDD2−0.3V to6VPGOOD,COMP1,COMP2,UV Delay −0.3V to(VLIN5+0.3)VON/SS1,ON/SS2(Note2)−0.3V to(VLIN5+0.6)V CBOOT1to SW1,CBOOT2to SW2−0.3V to7V LDRV1,LDRV2−0.3V to(VDD+0.3)V HDRV1to SW1,HDRV2to SW2−0.3V HDRV1to CBOOT1,HDRV2toCBOOT2+0.3VAmbient Storage TemperatureRange−65˚C to+ Soldering Dwell Time,Temperature(Note4)WaveInfraredVapor Phase4sec,10sec,75sec, ESD Rating(Note5)Operating Ratings(Note1)VIN(VLIN5tied to VIN) 4.5V to VIN(VIN and VLIN5separate) 5.5V t Junction Temperature−40˚C to+Electrical CharacteristicsUnless otherwise specified,V IN=15V,GND=PGND=0V,VLIN5=VDD1=VDD2.Limits appearing in boldface type over the specified operating junction temperature range,(-20˚C to+125˚C,if not otherwise specified).Specifications app in plain type are measured using low duty cycle pulse testing with T A=25˚C(Note6),(Note7).Min/Max limits are gua by design,test,or statistical analysis.Symbol Parameter Conditions Min Typ Max System∆V OUT/V OUT Load Regulation VIN=15V,V compx=0.5V to1.5V0.04∆V OUT/V OUT Line Regulation 5.5V≤VIN≤30V,V compx=1.25V0.04V FB1_FI2Feedback Voltage 5.5V≤VIN≤30V 1.215 1.238 1.2600˚C to125˚C 1.217 1.259-40˚C to125˚C 1.212 1.261I VIN Input Supply Current V ON_SSx>2V5.5V≤VIN≤30V 1.02.0Shutdown(Note8)V ON_SS1=V ON_SS2=0V 37110VLIN5VLIN5Output Voltage(Note9)IVLIN5=0to25mA,5.5V≤VIN≤30V4.7055.30 -40˚C to125˚C 4.68 5.30V CLos Current LimitComparator Offset(VILIMX−VRSNSX)±2±7.0I CL Current Limit SinkCurrent91011 -40˚C to125˚C8.6711I ss_SC1, I ss_SC2Soft-Start SourceCurrentV ON_ss1=V ON_ss2=1.5V(on)0.52 5.0I ss_SK1, I ss_SK2Soft-Start Sink Current V ON_ss1=V ON_ss2=2V2 5.210V ON_SS1, V ON_SS2Soft-Start On Threshold0.7 1.12 1.4V SSTO Soft-Start TimeoutThreshold (Note10)3.3I sc_uvdelay UV_DELAY SourceCurrent UV-DELAY=2V2594over the specified operating junction temperature range,(-20˚C to+125˚C,if not otherwise specified).Specifications appearing in plain type are measured using low duty cycle pulse testing with T A=25˚C(Note6),(Note7).Min/Max limits are guaranteed by design,test,or statistical analysis.Symbol Parameter Conditions Min Typ Max Units I sk_uvdelay UV_DELAY Sink Current UV-DELAY=0.4V0.20.48 1.2mA V UVDelay UV_DELAY ThresholdVoltage2.3VV UVP FB1,FB2,UnderVoltage Protection LatchThreshold As a percentage of nominal outputvoltage(falling edge)758086%Hysteresis4%V OVP V OUT OvervoltageShutdown LatchThreshold As a percentage measured at V FB1,V FB2107113122%V pwrbad Regulator WindowDetector Thresholds(PGOOD1from High toLow)As a percentage of output voltage86.590.394.5%V pwrgd Regulator WindowDetector Thresholds(PGOOD1from Low toHigh)91.59497.0%S wx_R SW1,SW2ON-Resistance V SW1=V SW2=2V420480535ΩGate DriveI CBOOT CBOOTx LeakageCurrent V CBOOT1=V CBOOT2=7V10nAI SC_DRV HDRVx and LDRVxSource Current V CBOOT1=V CBOOT2=5V,VSWx=0V,HDRVx=LDRVx=2.5V0.5AI sk_HDRV HDRVx Sink Current V CBOOTx=VDDx=5V,V SWx=0V,HDRVX=2.5V0.8AI sk_LDRV LDRVx Sink Current V CBOOTx=VDDx=5V,V SWx=0V,LDRVX=2.5V1.1AR HDRV HDRV1&2SourceOn-Resistance V CBOOT1=V CBOOT2=5V,V SW1=V SW2=0V3.1ΩHDRV1&2SinkOn-Resistance1.5ΩR LDRV LDRV1&2SourceOn-Resistance V CBOOT1=V CBOOT2=5V,V SW1=V SW2=0VV DD1=V DD1=5V3.1ΩLDRV1&2SinkOn-Resistance1.1ΩOscillatorF osc Oscillator Frequency260300340kHz-40˚C to125˚C257.5340Don_max Maximum On-Duty Cycle V FB1=V FB2=1V,Measured at pinsHDRV1and HDRV29698%-40˚C to125˚C95.64T on_min Minimum On-Time166nsSS OT_delta HDRV1and HDRV2Delta On Time ON/SS1=ON/SS2=2V20150nsError Amplifier5over the specified operating junction temperature range,(-20˚C to+125˚C,if not otherwise specified).Specifications app in plain type are measured using low duty cycle pulse testing with T A=25˚C(Note6),(Note7).Min/Max limits are gua by design,test,or statistical analysis.Symbol Parameter Conditions Min Typ MaxI FB1,I FB2Feedback Input BiasCurrent V FB1_FIX=1.5V,V FB2_FIX=1.5V65±200I comp1_SC, I comp2_SC COMP Output SourceCurrentV FB1_FIX=V FB2_FIX=1V,V COMP1=V COMP2=1V181130˚C to125˚C32-40˚C to125˚C6I comp1_SK, I comp2_SK COMP Output SinkCurrentV FB1_FIX=V FB2_FIX=1.5V andV COMP1=V COMP2=0.5V181080˚C to125˚C32-40˚C to125˚C6gm1,gm2Transconductance650GI SNS1, GI SNS2Current Sense Amplifier(1&2)GainV COMPx=1.25V4.25.27.5Voltage References and Linear Voltage RegulatorsUVLO VLIN5Under-voltageLockoutThreshold Rising ON/SS1,ON/SS2transitionfrom low to high 3.6 4.0 4.4Logic OutputsI OL PGOOD Low SinkCurrent V PGOOD=0.4V0.600.95I OH PGOOD High LeakageCurrent V PGOOD=5V5200Note1:Absolute maximum ratings indicate limits beyond which damage to the device may occur.Operating Range indicates conditions for which the d intended to be functional,but does not guarantee specfic performance limits.For guaranteed specifications and test conditions,see the Electrical Charac The guaranteed specifications apply only for the test conditions.Some performance characteristics may degrade when the device is not operated under t test conditions.Note2:ON/SS1and ON/SS2are internally pulled up to one diode drop above VLIN5.Do not apply an external pull-up voltage to these pins.It may cause to the IC.Note3:The maximum allowable power dissipation is calculated by using P DMAX=(T JMAX-T A)/θJA,where T JMAX is the maximum junction temperature, ambient temperature andθJA is the junction-to-ambient thermal resistance of the specified package.The1.1W rating results from using125˚C,25˚C,and9 for T JMAX,T A,andθJA respectively.AθJA of90.6˚C/W represents the worst-case condition of no heat sinking of the28-pin TSSOP.A thermal shutdown w if the temperature exceeds the maximum junction temperature of the device.Note4:For detailed information on soldering plastic small-outline packages,refer to the Packaging Databook available from National Semiconductor Cor Note5:For testing purposes,ESD was applied using the human-body model,a100pF capacitor discharged through a1.5kΩresistor.Note6:A typical is the center of characterization data measured with low duty cycle pulse tsting at T A=25˚C.Typicals are not guaranteed.Note7:All limits are guaranteed.All electrical characteristics having room-temperature limits are tested during production with T A=T J=25˚C.All hot and c are guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.Note8:Both switching controllers are off.The linear regulator VLIN5remains on.Note9:The output voltage at the VLIN5pin may be as high as5.9V in shutdown mode(ON/SS1=ON/SS2=0V).Note10:When SS1and SS2pins are charged above this voltage and either of the output voltages at Vout1or Vout2is still below the regulation limit,th voltage protection feature is initialized.620046203FIGURE1.Typical2Channel Application Circuit720046204FIGURE2.Typical Single Channel Application Circuit8B l o c k D i a g r a m200462059分销商库存信息:NATIONAL-SEMICONDUCTORLM2642MTC/NOPB LM2642MTCX/NOPB。
LM2412TNOPB;中文规格书,Datasheet资料
LM2412LM2412 Monolithic Triple 2.8 ns CRT DriverLiterature Number: SNOS511ALM2412Monolithic Triple 2.8ns CRT DriverGeneral DescriptionThe LM2412is an integrated high voltage CRT driver circuit designed for use in high resolution color monitor applica-tions.The IC contains three high input impedance,wide band amplifiers which directly drive the RGB cathodes of a CRT.Each channel has its gain internally set to −14and can drive CRT capacitive loads as well as resistive loads pre-sented by other applications,limited only by the package’s power dissipation.The LM2412is a low power alternative of the LM2402The IC is packaged in an industry standard 11lead TO-220molded plastic power package.See thermal considerations section for heat sinking requirements.Featuresn Rise/fall times typically 2.8ns with 8pF load at 40V PPn Lower power than LM2402with the same bandwidth n Well matched with LM2202video preamps n Output swing capability:50V PP for V CC =80V n 1V to 5V input rangenStable with 0-20pF capacitive loads and inductive peaking networksn Convenient TO-220staggered lead package style n Standard LM240X family pinout which is designed for easy PCB layoutApplicationsn CRT driver for color monitors with display resolutions up to 1600x 1200with 85Hz refresh rate n Pixel clock frequency up to 200MHzSchematic and Connection DiagramsDS101298-1FIGURE 1.Simplified Schematic Diagram(One Channel)DS101298-2Top ViewOrder Number LM2412T See NS package Number©2001National Semiconductor Corporation please contact the National Semiconductor Sales Office/ Distributors for availability and specifications.Supply Voltage,V CC+90V Bias Voltage,V BB+16V Input Voltage,V IN0V to6V Storage Temperature Range,T STG−65˚C to+150˚C Lead Temperature(Soldering,<10sec.)300˚CMachine ModelOperating Ranges(Note3)V CC+60V to V BB+8V to V IN+1V to V OUT(V CC=80V,V BB=12V)+15V to Case Temperature−20˚C to+1 Do not operate the part without a heat sink.Electrical Characteristics(See Figure2for Test Circuit)Unless otherwise noted:V CC=+80V,V BB=+12V,V IN=+3.3V DC,C L=8pF,T C=60˚C,no AC input.Symbol Parameter ConditionsLM2412Min Typ MaxI CC Supply Current Per Channel,No Output Load162126I BB Bias Current All Three Channels274257V OUT DC Output Voltage V IN=1.9V626568A V DC Voltage Gain−12−14−16∆A V Gain Matching(Note4) 1.0LE Linearity Error(Notes4,5) 3.5t r Rise Time(Notes6,7)10%to90%,40V PP Output(1MHz) 2.8 3.5t f Fall Time(Notes6,7)10%to90%,40V PP Output(1MHz) 2.8 3.5OS Overshoot40V PP Output(1MHz)5Note1:“Absolute Maximum Ratings”are those values beyond which the safety of the device cannot be guaranteed.They are not meant to imply that the should be operated at these limits.The table of“Electrical Characteristics”specifies conditions of device operation.Note2:All voltages are measured with respect to GND,unless otherwise specified.Note3:Operating ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.For guaranteed specificat test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.Some performance characteris change when the device is not operated under the listed test conditions.Note4:Calculated value from voltage gain test on each channel.Note5:Linearity error is the variation in DC gain from V IN=1.6V to V IN=5.0V.Note6:Input from signal generator:t r,t f<1ns.Note7:100%tested in production.These limits are not used to calculate outgoing quality levels.AC Test CircuitFigure2shows a typical test circuit for evaluation of the LM2412.This circuit is designed to allow testing of the LM2412in a50Ωenvironment without the use of an expen-sive FET probe.The combined resitors of4950Ωat the output form a200:1voltage divider when connected to a 50Ωload.The test board supplied by NSC also offers the option to test theLM2412with a FET probe.C L is the total capacitance at the LM2412output,including the boa pacitance.DS101298-3FIGURE2.Test Circuit(One Channel) 2DS101298-4 FIGURE3.V IN vs V OUTDS101298-6 FIGURE4.Speed vs Temp.DS101298-8 FIGURE5.Rise/Fall TimeDS101298-5FIGURE6.Power Dissipation vs FrequencyDS101298-7FIGURE7.Speed vs OffsetDS101298-9FIGURE8.Bandwidth 3driver suitable for very high resolution display applications, up to1600x1200at85Hz refresh rate.The LM2412 operates using80V and12V power supplies.The part is housed in the industry standard11-lead TO-220molded plastic power package.The simplified circuit diagram of one channel of the LM2412 is shown in Figure1.A PNP emitter follower,Q5,provides input buffering.This minimizes the current loading of the video pre-amp.R9is used to turn on Q5when there is no input.With Q5turned on,Q1will be almost completely off, minimizing the current flow through Q1and Q2.This will drive the output stage near the V CC rail,minimizing the power dissipation with no inputs.R6is a pull-up resistor for Q5and also limits the current flow through Q5.R3and R2 are used to set the current flow through Q1and Q2.The ratio of R1to R2is used to set the gain of the LM2412.R1,R2 and R3are all related when calculating the output voltage of the CRT driver.R b limits the current through the base of Q2. Q1and Q2are in a cascode configuration.Q1is a low voltage and very fast transistor.Q2is a higher voltage transistor.The cascode configuration gives the equivalent of a very fast and high voltage transistor.The two output tran-sistors,Q3and Q4,form a class B amplifier output stage.R4 and R5are used to limit the current through the output stage and set the output impedance of the LM2412.Q6,along with R7and R8set the bias current through Q3and Q4when there is no change in the signal level.This bias current minimizes the crossover distortion of the output stage.With this bias current the output stage now becomes a class AB amplifier with a crossover distortion much lower than a class B amplifier.Figure2shows a typical test circuit for evaluation of the LM2412.Due to the very wide bandwidth of the LM2412,it is highly recommended that the stand alone board suplied by NSC be used for the evaluation of the CRT driver’s perfor-mance.The50Ωresistor is used to duplicate the required series resistor in the actual application.This resistor would be part of the arc-over protection circuit.The input signal from the generator is AC coupled to the input of the CRT driver.Application HintsINTRODUCTIONNational Semiconductor(NSC)is committed to providing application information that assists our customers in obtain-ing the best performance possible from our products.The following information is provided in order to support this commitment.The reader should be aware that the optimiza-tion of performance was done using a specific printed circuit board designed at NSC.Variations in performance can be realized due to physical changes in the printed circuit board and the application.Therefore,the designer should know that component value changes may be required in order to optimize performance in a given application.The values shown in this document can be used as a starting point for evaluation purposes.When working with high bandwidth circuits,good layout practices are also critical to achieving maximum performance.power supply bypassing is critical for optimum perform Improper power supply bypassing can result in large shoot,ringing and oscillation.A0.1µF capacitor sho connected from the supply pin,V CC,to ground,as c the supply and ground pins as is practical.Addition 10µF to100µF electrolytic capacitor should be con from the supply pin to ground.The electrolytic ca should also be placed reasonably close to the LM supply and ground pins.A0.1µF capacitor should b nected from the bias pin,V BB,to ground,as close practical to the part.ARC PROTECTIONDuring normal CRT operation,internal arcing may occ ally occur.Spark gaps,in the range of200V,connecte the CRT cathodes to CRT ground will limit the ma voltage,but to a value that is much higher than allowa the LM2412.This fast,high voltage,high energy pul damage the LM2412output stage.The application shown in Figure9is designed to help clamp the volt the output of the LM2412to a safe level.The clamp should have a fast transient response,high peak c rating,low series impedance and low shunt capac FDH400or equivalent diodes are recommended.D1a should have short,low impedance connections to V C ground respectively.The cathode of D1should be l very close to a separately decoupled bypass capacito ground connection of the diode and the decoupling ca should be very close to the LM2412ground.This will cantly reduce the high frequency voltage transients th LM2412would be subjected to during an arc-over con Resistor R2limits the arc-over current that is seen diodes while R1limits the current into the LM2412as the voltage stress at the outputs of the device.R2sho a1⁄2W solid carbon type resistor.R1can be a1⁄4W m carbon film type resistor.Inductor L1is critical to redu initial high frequency voltage levels that the LM2412 be subjected to during an arc-over.Having large value tors for R1and R2would be desirable,but this has the of increasing rise and fall times.The inductor will n help protect the device but it will also help optimize ri fall times as well as minimize EMI.For proper arc prot it is important to not omit any of the arc protection c nents shown in Figure9.The values of L1and R1ma to be adjusted for a particular application.The recomm minimum value for R1is75Ω,with L1=.049µH. OPTIMIZING TRANSIENT RESPONSEReferring to Figure9,there are three components(R and L1)that can be adjusted to optimize the transi sponse of the application circuit.Increasing the valuesDS1 FIGURE9.One Channel of the LM2412with t Recommended Arc Protection Circuit.4shoot.Increasing the value of L1will speed up the circuit as well as increase overshoot.It is very important to use induc-tors with very high self-resonant frequencies,preferably above 300MHz.Air core inductors from ler Magnet-ics (part #75F518MPC)were used for optimizing the perfor-mance of the device in the NSC application board.The values shown in Figure 9can be used as a good starting point for the evaluation of the LM2412.Effect of Load CapacitanceThe output rise and fall times as well as overshoot will vary as the load capacitance varies.The values of the output circuit (R1,R2and L1in Figure 9)should be chosen based on the nominal load capacitance.Once this is done the performance of the design can be checked by varying the load based on what the expected variation will be during production.Effect of OffsetFigure 7shows the variation in rise and fall times when the output offset of the device is varied from 35to 55V DC .The rise and fall times show about the same overall variation.The slightly slower fall time is fastest near the center point of 45V,making this the optimum operating point.At the low and high output offset range,the characteristic of rise/fall time is slower due to the saturation of Q3and Q4.The recovery time of the output transistors takes longer coming out of saturation thus slows down the rise and fall times.THERMAL CONSIDERATIONSFigure 4shows the performance of the LM2412in the test circuit shown in Figure 2as a function of case temperature.Figure 4shows that both the rise and fall times of the LM2412become slightly longer as the case temperature increases from 40˚C to 125˚C.In addition to exceeding the safe operating temperature,the rise and fall times will typi-cally exceed 3nsec.Please note that the LM2412is never to be operated over a case temperature of 100˚C.In addition to exceeding the safe operating temperature,the rise and fall times will typically exceed 3nsec.Figure 6shows the total power dissipation of the LM2412vs.Frequency when all three channels of the device are driving an 8pF load.Typically the active time is about 72%of the total time for one frame.Worst case power dissipation is when a one on,one off pixel is displayed over the active time of the video input.This is the condition used to measure the total power disspation of the LM2412at different input fre-quencies.Figure 6gives all the information a monitor de-signer normally needs for worst case power dissipation.However,if the designer wants to calculate the power dissi-pation for an active time different from 72%,this can be done using the information in Figure 14.The recommended input black level voltage is 1.9V.From Figure 14,if a 1.9V input is used for the black level,then power dissipation during the inactive video time is 2.7W.This includes both the 80V and 12V supplies.If the monitor designer chooses to calculate the power dis-sipation for the LM2412using an active video time different from 72%,then he needs to use the following steps when using a 1.9V input black level:1.Multiply the black level power dissipation,2.7W,by 0.28,the result is 0.8W.clock.The power dissipation is 13.8W.3.Subtract the 0.8W from the power dissipation from Fig-ure 6.For 100MHz this would be 13.8–0.8=13.0W.4.Divide the result from step 3by 0.72.For 100MHz,the result is 18.1W.5.Multiply the result in 4by the new active time percent-age.6.Multiply 2.7W by the new inactive time.7.Add together the results of steps 5and 6.This is the expected power dissipation for the LM2412in the de-signer’s application.The LM2412case temperature must be maintained below 100˚C.If the maximum expected ambient temperature is 70˚C and the maximum power dissipation is 13.8W (from Figure 6.100MHz)then a maximum heat sink thermal resis-tance can be calculated:TYPICAL APPLICATIONA typical application of the LM2412is shown in Figure ed in conjunction with three LM2202s,a complete video channel from monitor input to CRT cathode can be achieved.Performance is excellent for resolutions up to 1600x 1200and pixel clock frequencies at 200MHz.Figure 10is the schematic for the NSC demonstration board that can be used to evaluate the LM2202/LM2412combination in a monitor.PC Board Layout ConsiderationsFor optimum performance,an adequate ground plane,iso-lation between channels,good supply bypassing and mini-mizing unwanted feedback are necessary.Also,the length of the signal traces from the preamplifier to the LM2412and from the LM2412to the CRT cathode should be as short as possible.The red video trace from the buffer transistor to the LM2412input is about the absolute maximum length one should consider on a PCB layout.If possible the traces should actually be shorter than the red video trace.The following references are recommended for video board de-signers:Ott,Henry W.,“Noise Reduction Techniques in Electronic Systems”,John Wiley &Sons,New York,1976.“Guide to CRT Video Design”,National Semiconductor Ap-plication Note 861.“Video Amplifier Design for Computer Monitors”,National Semiconductor Application Note 1013.Pease,Robert A.,“Troubleshooting Analog Circuits”,Butterworth-Heinemann,1991.Because of its high small signal bandwidth,the part may oscillate in a monitor if feedback occurs around the video channel through the chassis wiring.To prevent this,leads to the video amplifier input circuit should be shielded,and input circuit wiring should be spaced as far as possible from output circuit wiring.NSC Demonstration BoardFigures 11,12show routing and component placement on the NSC LM2202/2412demonstration board.The schematic of the board is shown in Figure 10.This board provides a5future layouts.Note the location of the following compo-nents:•C47-V CC bypass capacitor,located very close to pin6 and ground pins.(Figure12)•C49-V BB bypass capacitor,located close to pin10and ground.(Figure12)•C46and C77-V CC bypass capacitors,near LM2412and V CC clamp diodes.Very important for arc protection.(Figure11)The routing of the LM2412outputs to the CRT is very critical to achieving optimum performance.Figure13shows the routing and component placement from pin1to the blue cathode.Note that the components are placed so that they almost line up from the output pin of the LM2412to the blue cathode pin of the CRT connector.This is done to minimize D25,R58and D19are placed to keep the size of the nodes to a minimum(R58is located under D19).Thi mizes parasitic capacitance in the video path and al hances the effectiveness of the protection diodes.The in the video nodes to these components are shown white line.The anode of protection diode D25is con directly to the ground plane giving a short and direct the LM2412ground pins.The cathode of D24is con to V CC very close to decoupling capacitor C78(Figu which is connected to the same section of the ground as D25.The diode placement and routing is very imp for minimizing the voltage stress on the LM2412dur arc-over stly,notice that S3is placed very c the blue cathode and is tied directly to CRT ground.6D S 101298-12F IG U R E 10.D e m o B o a r d S c h e m a t i c7DS101FIGURE11.PCB Top Layer8DS101298-14 FIGURE12.PCB Bottom Layer9分销商库存信息: NATIONAL-SEMICONDUCTOR LM2412T/NOPB。
LM4755TSNOPB,LM4755TSXNOPB,LM4755TNOPB, 规格书,Datasheet 资料
LM4755LM4755 Stereo 11W Audio Power Amplifier with MuteLiterature Number: SNAS010D 芯天下--/May 14, 2008LM4755Stereo 11W Audio Power Amplifier with MuteGeneral DescriptionThe LM4755 is a stereo audio amplifier capable of delivering 11W per channel of continuous average output power to a 4Ω load or 7W per channel into 8Ω using a single 24V supply at 10% THD+N. The internal mute circuit and pre-set gain re-sistors provide for a very economical design solution.Output power specifications at both 20V and 24V supplies and low external component count offer high value to con-sumer electronic manufacturers for stereo TV and compact stereo applications. The LM4755 is specifically designed for single supply operation.Key Specifications■Output power at 10% THD with 1kHz into 4Ω atV CC = 24V: 11W (typ)■Output power at 10% THD with 1kHz into 8Ω at V CC = 24V: 7W (typ)■Closed loop gain: 34dB (typ)■P O at 10% THD+N @ 1kHz into 4Ω single-ended TO-263package at V CC =12V: 2.5W (typ)■P O at 10% THD+N @ 1kHz into 8Ω bridged TO-263package at V CC =12V: 5W (typ)Features■Drives 4Ω and 8Ω loads ■Integrated mute function ■Internal Gain Resistors■Minimal external components needed ■Single supply operation■Internal current limiting and thermal protection ■Compact 9-lead TO-220 package ■Wide supply range 9V - 40VApplications■Stereos TVs■Compact stereos■Mini component stereosTypical Application10005901FIGURE 1. Typical Audio Amplifier Application Circuit© 2008 National Semiconductor Corporation LM4755 Stereo 11W Audio Power Amplifier with MuteConnection DiagramsPlastic Package10005902Package DescriptionTop ViewOrder Number LM4755T Package Number TA09A10005936Top ViewOrder Number LM4755TS Package Number TS9A 2L M 4755Absolute Maximum Ratings (Note 2)If Military/Aerospace specified devices are required,please contact the National Semiconductor Sales Office/Distributors for availability and specifications.Supply Voltage 40V Input Voltage±0.7V Input Voltage at Output Pins (Note 8)GND -0.4V Output CurrentInternally LimitedPower Dissipation (Note 3)62.5W ESD Susceptibility (Note 4) 2 kV Junction Temperature150°CSoldering InformationT Package (10 seconds)250°CStorage Temperature −40°C to 150°COperating RatingsTemperature RangeT MIN ≤ T A ≤ T MAX −40°C ≤ T A ≤ +85°CSupply Voltage 9V to 32VθJC 2°C/W θJA76°C/WElectrical CharacteristicsThe following specifications apply to each channel with V CC = 24V, T A = 25°C unless otherwise specified.Symbol ParameterConditionsLM4755Units (Limits)Typical (Note 5)Limit I TOTALTotal Quiescent Power Supply CurrentMute Off1015mA(max)7mA(min)Mute On7mA P OOutput Power (Continuous Average per Channel)f = 1 kHz, THD+N = 10%, R L = 8Ω7 W f = 1 kHz, THD+N = 10%, R L = 4Ω1110W(min)V S = 20V, R L = 8Ω4 W V S = 20V, R L = 4Ω7 W f = 1 kHz, THD+N = 10%, R L = 4ΩV S = 12V, TO-263 Pkg.2.5W THD Total Harmonic Distortion f = 1 kHz, P O = 1 W/ch, R L = 8Ω0.08 %V OSW Output Swing P O = 10W, R L = 8Ω15V P O = 10W, R L = 4Ω14V X TALK Channel SeparationSee Apps. Circuit55dBf = 1 kHz, V O = 4 VrmsPSRR Power Supply Rejection Ratio See Apps. Circuit50dB f = 120 Hz, V O = 1 mVrms V ODV Differential DC Output Offset Voltage V IN = 0V 0.090.4V(max)SR Slew Rate2V/µs R IN Input Impedance 83k ΩPBW Power Bandwidth3 dB BW at P O = 2.5W, R L = 8Ω65kHz A VCL Closed Loop Gain (Internally Set)R L = 8Ω3433dB(min)35dB(max)εIN NoiseIHF-A Weighting Filter, R L = 8ΩOutput Referred 0.2mVrms I OOutput Short Circuit Limit V IN = 0.5V, R L = 2Ω2A(min)Mute Pin V IL Mute Low Input Voltage Not in Mute Mode 0.8V(max)V IH Mute High Input Voltage In Mute Mode 2.0 2.5V(min)A MMute AttenuationV MUTE = 5.0V80 dBLM4755Note 1:All voltages are measured with respect to the GND pin (5), unless otherwse specified.Note 2:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. Electrical Characteristics state DC and AC electrical specifications under particular test conditions which guarantee specific performance limits. This assumes that the device is within the Operating Ratings. Specifications are not guaranteed for parameters where no limit is given, however, the typical value is a good indication of device performance.Note 3:For operating at case temperatures above 25°C, the device must be derated based on a 150°C maximum junction temperature and a thermal resistance of θJC = 2°C/W (junction to case). Refer to the section Determining the Maximum Power Dissipation in the Application Information section for more information.Note 4:Human body model, 100 pF discharged through a 1.5 k Ω resistor.Note 5:Typicals are measured at 25°C and represent the parametric norm.Note 6:Limits are guaranteed that all parts are tested in production to meet the stated values.Note 7:The TO-263 Package is not recommended for V S > 16V due to impractical heatsinking limitations.Note 8:The outputs of the LM4755 cannot be driven externally in any mode with a voltage lower than -0.4V below GND or permanent damage to the LM4755will result. 4L M 4755Equivalent Schematic100059035LM4755Test Circuit10005904FIGURE 2. Test Circuit 6L M 4755System Application Circuit10005905FIGURE 3. Circuit for External Components DescriptionExternal Components DescriptionComponents Function Description1, 2CSProvides power supply filtering and bypassing.3, 4RSN Works with CSNto stabilize the output stage from high frequency oscillations.5, 6CSN Works with RSNto stabilize the output stage from high frequency oscillations.7CbProvides filtering for the internally generated half-supply bias generator.8, 9CiInput AC coupling capacitor which blocks DC voltage at the amplifier's input terminals. Also creates a high passfilter with fc=1/(2 • π • Rin • Cin).10, 11CoOutput AC coupling capacitor which blocks DC voltage at the amplifier's output terminal. Creates a high passfilter with fc=1/(2 • π • Rout • Cout).12, 13RiVoltage control - limits the voltage level allowed to the amplifier's input terminals.14Rm Works with Cmto provide mute function timing.15Cm Works with Rmto provide mute function timing.LM4755Typical Performance Characteristics(Note 5)THD+N vs Output Power10005912THD+N vs Output Power10005913THD+N vs Output Power 10005914THD+N vs Output Power10005906THD+N vs Output Power 10005907THD+N vs Output Power10005908 8L M 4755THD+N vs Output Power10005915THD+N vs Output Power10005916THD+N vs Output Power10005917THD+N vs Output Power10005909THD+N vs Output Power10005910THD+N vs Output Power10005911LM4755THD+N vs Output Power 10005938THD+N vs Output Power10005939THD+N vs Output Power 10005940THD+N vs Output Power10005941THD+N vs Output Power 10005942THD+N vs Output Power10005943L M 4755THD+N vs Output Power10005944THD+N vs Output Power10005945THD+N vs Output Power10005946THD+N vs Output Power10005947THD+N vs Output Power10005948THD+N vs Output Power10005949LM4755Output Power vs Supply Voltage 10005918Output Power vs Supply Voltage10005919Frequency Response 10005920THD+N vs Frequency10005921THD+N vs Frequency 10005922Frequency Response10005923L M 4755Channel Separation10005924PSRR vs Frequency10005925Supply Current vs Supply Voltage10005926Power Derating Curve10005927Power Dissipation vs Output Power10005928Power Dissipation vs Output Power10005929LM4755Power Dissipation vs Output Power 10005960Power Dissipation vs Output Power10005961Application InformationThe LM4755 contains circuitry to pull down the bias line in-ternally, effectively shutting down the input stage. An external R-C should be used to adjust the timing of the pull-down. If the bias line is pulled down too quickly, currents induced in the internal bias resistors will cause a momentary DC voltage to appear across the inputs of each amplifier's internal differ-ential pair, resulting in an output DC shift towards Vsupply.An R-C timing circuit should be used to limit the pull-down time such that output “pops” and signal feedthroughs will be minimized. The pull-down timing is a function of a number of factors, including the internal mute circuitry, the voltage used to activate the mute, the bias capacitor, the half-supply volt-age, and internal resistances used in the half-supply genera-tor. Table 1 shows a list of recommended values for the external R-C.TABLE 1. Recommended Values for Mute Circuit V MUTE V CC Rm Cm 5V 12V 18 k Ω10 µF 5V 15V 18 k Ω10 µF 5V 20V 12 k Ω10 µF 5V 24V 12 k Ω10 µF 5V 28V 8.2 k Ω10 µF 5V30V8.2 k Ω10 µFCAPACITOR SELECTION AND FREQUENCY RESPONSE With the LM4755, as in all single supply amplifiers, AC cou-pling capacitors are used to isolate the DC voltage present atthe inputs (pins 3, 7) and outputs (pins 1, 8). As mentioned earlier in the External Components section these capacitors create high-pass filters with their corresponding input/output impedances. The Typical Application Circuit shown in Fig-ure 1 shows input and output capacitors of 0.1 µF and 1,000µF respectively. At the input, with an 83 k Ω typical input re-sistance, the result is a high pass 3 dB point occurring at 19Hz. There is another high pass filter at 39.8 Hz created with the output load resistance of 4Ω. Careful selection of these components is necessary to ensure that the desired frequen-cy response is obtained. The Frequency Response curves in the Typical Performance Characteristics section show how different output coupling capacitors affect the low frequency roll-off.OPERATING IN BRIDGE-MODEThough designed for use as a single-ended amplifier, the LM4755 can be used to drive a load differentially (bridge-mode). Due to the low pin count of the package, only the non-inverting inputs are available. An inverted signal must be provided to one of the inputs. This can easily be done with the use of an inexpensive op-amp configured as a standard in-verting amplifier. An LF353 is a good low-cost choice. Care must be taken, however, for a bridge-mode amplifier must theoretically dissipate four times the power of a single-ended type. The load seen by each amplifier is effectively half that of the actual load being used, thus an amplifier designed to drive a 4Ω load in single-ended mode should drive an 8Ω load when operating in bridge-mode.L M 475510005930 FIGURE 4. Bridge-Mode Application1000593110005937FIGURE 5. THD+N vs POUT for Bridge-Mode ApplicationLM4755PREVENTING OSCILLATIONSWith the integration of the feedback and bias resistors on-chip, the LM4755 fits into a very compact package. However,due to the close proximity of the non-inverting input pins to the corresponding output pins, the inputs should be AC ter-minated at all times. If the inputs are left floating, the amplifier will have a positive feedback path through high impedance coupling, resulting in a high frequency oscillation. In most ap-plications, this termination is typically provided by the previ-ous stage's source impedance. If the application will require an external signal, the inputs should be terminated to ground with a resistance of 50 k Ω or less on the AC side of the input coupling capacitors.UNDERVOLTAGE SHUTDOWNIf the power supply voltage drops below the minimum oper-ating supply voltage, the internal under-voltage detection cir-cuitry pulls down the half-supply bias line, shutting down the preamp section of the LM4755. Due to the wide operating supply range of the LM4755, the threshold is set to just under 9V. There may be certain applications where a higher thresh-old voltage is desired. One example is a design requiring a high operating supply voltage, with large supply and bias ca-pacitors, and there is little or no other circuitry connected to the main power supply rail. In this circuit, when the power is disconnected, the supply and bias capacitors will discharge at a slower rate, possibly resulting in audible output distortion as the decaying voltage begins to clip the output signal. An external circuit may be used to sense for the desired thresh-old, and pull the bias line (pin 6) to ground to disable the input preamp. Figure 6 shows an example of such a circuit. When the voltage across the zener diode drops below its threshold,current flow into the base of Q1 is interrupted. Q2 then turns on, discharging the bias capacitor. This discharge rate is gov-erned by several factors, including the bias capacitor value,the bias voltage, and the resistor at the emitter of Q2. An equation for approximating the value of the emitter discharge resistor, R, is given below:R = (0.7v) / (Cb • (V CC /2) / 0.1s)Note that this is only a linearized approximation based on a discharge time of 0.1s. The circuit should be evaluated and adjusted for each application.As mentioned earlier in the Built-in M ute Circuit section,when using an external circuit to pull down the bias line, the rate of discharge will have an effect on the turn-off induced distortions. Please refer to the Built-in Mute Circuit section for more information.10005932FIGURE 6. External Undervoltage Pull-DownTHERMAL CONSIDERATIONS Heat SinkingProper heatsinking is necessary to ensure that the amplifier will function correctly under all operating conditions. A heatsink that is too small will cause the die to heat excessively and will result in a degraded output signal as the thermal pro-tection circuitry begins to operate.The choice of a heatsink for a given application is dictated by several factors: the maximum power the IC needs to dissi-pate, the worst-case ambient temperature of the circuit, the junction-to-case thermal resistance, and the maximum junc-tion temperature of the IC. The heat flow approximation equa-tion used in determining the correct heatsink maximum thermal resistance is given below:T J –T A = P DMAX • (θJC + θCS + θSA )where:P DMAX = maximum power dissipation of the IC T J (°C) = junction temperature of the IC T A (°C) = ambient temperatureθJC (°C/W) = junction-to-case thermal resistance of the IC θCS (°C/W) = case-to-heatsink thermal resistance (typically 0.2 to 0.5 °C/W)θSA (°C/W) = thermal resistance of heatsinkWhen determining the proper heatsink, the above equation should be re-written as:θSA ≤ [(T J –T A ) / P DMAX ] - θJC –θCSTO-263 HEATSINKINGSurface mount applications will be limited by the thermal dis-sipation properties of printed circuit board area. The TO-263package is not recommended for surface mount applications with V S > 16V due to limited printed circuit board area. There are TO-263 package enhancements, such as clip-on heatsinks and heatsinks with adhesives, that can be used to improve performance.Standard FR-4 single-sided copper clad will have an approx-imate Thermal resistance (θSA ) ranging from:1.5 × 1.5 in. sq.20–27°C/W (T A =28°C, Sine wave testing, 1 oz. Copper)2 × 2 in. sq.16–23°C/WL M 4755The above values for θSA vary widely due to dimensional pro-portions (i.e. variations in width and length will vary θSA). For audio applications, where peak power levels are short in duration, this part will perform satisfactory with less heatsink-ing/copper clad area. As with any high power design proper bench testing should be undertaken to assure the design can dissipate the required power. Proper bench testing requires attention to worst case ambient temperature and air flow. At high power dissipation levels the part will show a tendency to increase saturation voltages, thus limiting the undistorted power levels.DETERMINING MAXIMUM POWER DISSIPATIONFor a single-ended class AB power amplifier, the theoretical maximum power dissipation point is a function of the supplyvoltage, VS , and the load resistance, RLand is given by thefollowing equation: (single channel)P DMAX (W) = [VS2 / (2 • π2 • R L)]The above equation is for a single channel class-AB power amplifier. For dual amplifiers such as the LM4755, the equa-tion for calculating the total maximum power dissipated is: (dual channel)P DMAX (W) = 2 • [VS2 / (2 • π2 • R L)]orVS2 / (π2 • R L) (Bridged Outputs)P DMAX (W) = 4[VS2 / (2π2 • R L)]HEATSINK DESIGN EXAMPLEDetermine the system parameters:VS= 24V Operating Supply VoltageRL= 4ΩMinimum Load ImpedanceTA= 55°C Worst Case Ambient Temperature Device parameters from the datasheet:TJ= 150°C Maximum Junction TemperatureθJC = 2°C/W Junction-to-Case Thermal Resistance Calculations:2 • PDMAX = 2 • [VS2 / 2 • π2 • R L)] = (24V)2 / (2 • π2 • 4Ω) =14.6WθSA≤ [(T J-T A) / P DMAX] - θJC–θCS = [ (150°C - 55°C) / 14.6W] - 2°C/W–0.2°C/W = 4.3°C/WConclusion: Choose a heatsink with θSA≤ 4.3°C/W.TO-263 HEATSINK DESIGN EXAMPLESExample 1:(Stereo Single-Ended Output)Given:TA=30°CTJ=150°CRL=4ΩVS=12VθJC=2°C/WP DMAX from PDvs POGraph:PDMAX≈ 3.7WCalculating PDMAX:PDMAX= VCC2/(π2R L) = (12V)2/π2(4Ω)) = 3.65WCalculating Heatsink Thermal Resistance:θSA < T J − T A / P DMAX − θJC − θCSθSA < 120°C/3.7W − 2.0°C/W − 0.2°C/W = 30.2°C/WTherefore the recommendation is to use 1.5 × 1.5 square inchof single-sided copper clad.Example 2:(Stereo Single-Ended Output)Given:TA=50°CTJ=150°CRL=4ΩVS=12VθJC=2°C/WPDMAXfrom PDvs POGraph:PDMAX≈ 3.7WCalculating PDMAX:PDMAX= VCC2/(π2R L)= (12V) 2/(π2(4Ω)) = 3.65WCalculating Heatsink Thermal Resistance:θSA < [(T J − T A) / P DMAX] − θJC − θCSθSA < 100°C/3.7W − 2.0°C/W − 0.2°C/W = 24.8°C/WTherefore the recommendation is to use 2.0 × 2.0 square inchof single-sided copper clad.Example 3:(Bridged Output)Given:TA=50°CTJ=150°CRL=8ΩVS=12VθJC=2°C/WCalculating PDMAX:PDMAX= 4[VCC2/(2π2R L)] = 4(12V)2/(2π2(8Ω)) = 3.65WCalculating Heatsink Thermal Resistance:θSA < [(T J − T A) / P DMAX] − θJC − θCSθSA < 100°C / 3.7W − 2.0°C/W − 0.2°C/W = 24.8°C/WTherefore the recommendation is to use 2.0 × 2.0 square inchof single-sided copper clad.LAYOUT AND GROUND RETURNSProper PC board layout is essential for good circuit perfor-mance. When laying out a PC board for an audio poweramplifier, particular attention must be paid to the routing of theoutput signal ground returns relative to the input signal andbias capacitor grounds. To prevent any ground loops, theground returns for the output signals should be routed sepa-rately and brought together at the supply ground. The inputsignal grounds and the bias capacitor ground line should alsobe routed separately. The 0.1 µF high frequency supply by-pass capacitor should be placed as close as possible to theIC.LM4755PC BOARD LAYOUT-COMPOSITE10005933L M 4755PC BOARD LAYOUT-SILK SCREEN10005934LM4755PC BOARD LAYOUT-SOLDER SIDE10005935 20L M 4755Physical Dimensions inches (millimeters) unless otherwise notedOrder Number LM4755TNS Package Number TA9A LM4755Order Number LM4755TS NS Package Number TS9A 22L M 4755LM4755 NotesNotesL M 4755 S t e r e o 11W A u d i o P o w e r A m p l i f i e r w i t h M u t eFor more National Semiconductor product information and proven design tools, visit the following Web sites at:ProductsDesign SupportAmplifiers /amplifiers WEBENCH /webench Audio/audio Analog University /AU Clock Conditioners /timing App Notes /appnotes Data Converters /adc Distributors /contacts Displays /displays Green Compliance /quality/green Ethernet /ethernet Packaging/packaging Interface /interface Quality and Reliability /quality LVDS/lvds Reference Designs /refdesigns Power Management /power Feedback /feedback Switching Regulators /switchers LDOs /ldo LED Lighting /led PowerWise/powerwise Serial Digital Interface (SDI)/sdiTemperature Sensors /tempsensors Wireless (PLL/VCO)/wirelessTHE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION (“NATIONAL”) PRODUCTS. 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LM5114BMFNOPB;LM5114BMFXNOPB;中文规格书,Datasheet资料
N_OUT
Sink-current output
Connect to the gate of the MOSFET with a short, low inductance path. A gate resistor can be used to adjust the turn-off speed.
Conditions
Min Typ Max Units
POWER SUPPLY
VDD UVLO
VDD Operating Voltage VDD Undervoltage Lockout
VDD Rising
4.0
12.6
V
3.25 3.6 4.00
V
VDD Undervoltage Lockout Hysteresis
Typical Applications
● Boost converters ● Flyback and forward converters ● Secondary synchronous FETs drive in isolated topologies ● Motor control
Block Diagram
3
/
LM5114
Absolute Maximum Ratings (Note 1)
VDD to VSS IN, INB to VSS N_OUT to VSS P_OUT to VSS Junction Temperature Storage Temperature Range ESD Rating HBM
0.4
V
VDD Undervoltage lockout to Output delay time
VDD Rising
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LM2465LM2465 Monolithic Triple 5.5 ns High Gain CRT DriverLiterature Number: SNOS967LM2465Monolithic Triple 5.5ns High Gain CRT DriverGeneral DescriptionThe LM2465is an integrated high voltage CRT driver circuit designed for use in color monitor applications.The IC contains three high input impedance,wide band amplifiers which directly drive the RGB cathodes of a CRT.Each channel has its gain internally set to −20and can drive CRT capacitive loads as well as resistive loads present in other applications,limited only by the package’s power dissipation.The IC is packaged in an industry standard 9-lead TO-220molded plastic package.Featuresn Higher gain to match LM126X CMOS preamplifiers n 0V to 3.75V input rangen Stable with 0–20pF capacitive loads and inductive peaking networksn Same pinout as LM2467/8/9,maintaining the standard LM243X Family pinout for easy PCB layoutn Convenient TO-220staggered lead package styleApplicationsn Up to 1280x 1024at 75Hzn Pixel clock frequencies up to 135MHz n Monitors using video blankingSchematic and Connection DiagramsDS200190-1FIGURE 1.Simplified Schematic Diagram(One Channel)DS200190-2Note:Tab is at GNDTop ViewOrder Number LM2465TA©2001National Semiconductor Corporation please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage(V CC)+90V Bias Voltage(V BB)+16V Input Voltage(V IN)0V to4.5V Storage Temperature Range(T STG)−65˚C to+150˚C Lead Temperature(Soldering,<10sec.)300˚C ESD Tolerance,Human Body Model2kV Operating Ranges(Note2)V CC+60V to V BB+8V to V IN+0V to V OUT+15V to Case Temperature−20˚C to+ Do not operate the part without a heat sink.Electrical Characteristics(See Figure2for Test Circuit)Unless otherwise noted:V CC=+80V,V BB=+12V,C L=8pF,T C=50˚C DC Tests:V IN=2.25VDCAC Tests:Output=40V PP(25V-65V)at1MHzSymbol Parameter ConditionsLM2465Min Typical MaxI CC Supply Current All Three Channels,No Input Signal,No Output Load3644I BB Bias Current All Three Channels2024V OUT DC Output Voltage No AC Input Signal,V IN=1.25V626568A V DC Voltage Gain No AC Input Signal−18−20−22∆A V Gain Matching(Note4),No AC Input Signal 1.0LE Linearity Error(Notes4,5),No AC Input Signal5t R Rise Time(Note6),10%to90% 5.5t F Fall Time(Note6),90%to10% 6.0OS Overshoot(Note6)3Note1:Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.Note2:Operating ratings indicate conditions for which the device is functional,but do not guarantee specific performance limits.For guaranteed specificat test conditions,see the Electrical Characteristics.The guaranteed specifications apply only for the test conditions listed.Some performance characteris change when the device is not operated under the listed test conditions.Note3:All voltages are measured with respect to GND,unless otherwise specified.Note4:Calculated value from Voltage Gain test on each channel.Note5:Linearity Error is the variation in dc gain from V IN=1.0V to V IN=3.5V.Note6:Input from signal generator:t r,t f<1ns.2Figure 2shows a typical test circuit for evaluation of the LM2465.This circuit is designed to allow testing of the LM2465in a 50Ωenvironment without the use of an expensive FET probe.The two 2490Ωresistors form a 200:1divider with the 50Ωresistor and the oscilloscope.A test point is included for easy use of an oscilloscope probe.The compensation capacitor is used to compensate the stray capacitance of the two 2490Ωresistors to achieve flat frequency response.DS200190-3Note:8pF load includes parasitic capacitance.FIGURE 2.Test Circuit (One Channel)3DS200190-4FIGURE 3.V OUT vs V INDS200190-5FIGURE 4.Speed vs TemperatureDS200190-6FIGURE 5.LM2465Pulse ResponseDS200190-7FIGURE 6.Power Dissipation vs FrequencyDS200190-8FIGURE 7.Speed vs OffsetDS200190-9FIGURE 8.Speed vs Load Capacitance 4driver suitable for high resolution display applications.The LM2465operates with80V and12V power supplies.The part is housed in the industry standard9-lead TO-220 molded plastic power package.The circuit diagram of the LM2465is shown in Figure1.The PNP emitter follower,Q5,provides input buffering.Q1and Q2form a fixed gain cascode amplifier with resistors R1and R2setting the gain at−20.Emitter followers Q3and Q4 isolate the high output impedance of the amplifier, decreasing the sensitivity of the device to changes in load capacitance.Q6provides biasing to the output emitter follower stage to reduce crossover distortion at low signal levels.Figure2shows a typical test circuit for evaluation of the LM2465.This circuit is designed to allow testing of the LM2465in a50Ωenvironment without the use of an expensive FET probe.In this test circuit,two low inductance resistors in series totaling4.95kΩform a200:1wideband, low capacitance probe when connected to a50Ωcoaxial cable and a50Ωload(such as a50Ωoscilloscope input). The input signal from the generator is ac coupled to the base of Q5.Application HintsINTRODUCTIONNational Semiconductor(NSC)is committed to provide application information that assists our customers in obtaining the best performance possible from our products. The following information is provided in order to support this commitment.The reader should be aware that the optimization of performance was done using a specific printed circuit board designed at NSC.Variations in performance can be realized due to physical changes in the printed circuit board and the application.Therefore,the designer should know that component value changes may be required in order to optimize performance in a given application.The values shown in this document can be used as a starting point for evaluation purposes.When working with high bandwidth circuits,good layout practices are also critical to achieving maximum performance.IMPORTANT INFORMATIONThe LM2465performance is targeted for the17“and low end 19“monitor market with resolutions up to1280X1024and a 75Hz refresh rate.It is designed to be a replacement for discrete CRT drivers.The application circuits shown in this document to optimize performance and to protect against damage from CRT arcover are designed specifically for the LM2465.If another member of the LM246X family is used, please refer to its datasheet.POWER SUPPLY BYPASSSince the LM2465is a wide bandwidth amplifier,proper power supply bypassing is critical for optimum performance. Improper power supply bypassing can result in large overshoot,ringing or oscillation.A0.1µF capacitor should be connected from the supply pin,V CC and V BB,to ground,as close to the LM2465as is practical.Additionally,a47µF or larger electrolytic capacitor should be connected from both supply pins to ground reasonably close to the LM2465.occasionally occur.Spark gaps,in the range of200V,connected from the CRT cathodes to CRT ground will limitthe maximum voltage,but to a value that is much higher thanallowable on the LM2465.This fast,high voltage,highenergy pulse can damage the LM2465output stage.Theapplication circuit shown in Figure9is designed to helpclamp the voltage at the output of the LM2465to a safe level.The clamp diodes,D1and D2,should have a fast transientresponse,high peak current rating,low series impedanceand low shunt capacitance.FDH400or equivalent diodesare recommended.Do not use1N4148diodes for the clampdiodes.D1and D2should have short,low impedanceconnections to V CC and ground respectively.The cathode ofD1should be located very close to a separately decoupledbypass capacitor(C3in Figure9).The ground connection ofD2and the decoupling capacitor should be very close to theLM2465ground.This will significantly reduce the highfrequency voltage transients that the LM2465would besubjected to during an arcover condition.Resistor R2limitsthe arcover current that is seen by the diodes while R1limitsthe current into the LM2465as well as the voltage stress atthe outputs of the device.R2should be a1⁄2W solid carbontype resistor.R1can be a1⁄4W metal or carbon film typeresistor.Having large value resistors for R1and R2would bedesirable,but this has the effect of increasing rise and falltimes.Inductor L1is critical to reduce the initial highfrequency voltage levels that the LM2465would besubjected to.The inductor will not only help protect thedevice but it will also help optimize rise and fall times as wellas minimize EMI.For proper arc protection,it is important tonot omit any of the arc protection components shown inFigure9. 5OPTIMIZING TRANSIENT RESPONSEReferring to Figure 9,there are three components (R1,R2and L1)that can be adjusted to optimize the transient response of the application circuit.Increasing the values of R1and R2will slow the circuit down while decreasing overshoot.Increasing the value of L1will speed up the circuit as well as increase overshoot.It is very important to use inductors with very high self-resonant frequencies,preferably above 300MHz.Ferrite core inductors from ler Magnetics (part #78FR--k)were used for optimizing the performance of the device in the NSC application board.The values shown in Figure 9can be used as a good starting point for the evaluation of the ing a variable resistor for R1will simplify finding the value needed for optimum performance in a given application.Once the optimum value is determined,the variable resistors can be replaced with fixed values.EFFECT OF LOAD CAPACITANCEFigure 8shows the effect of increased load capacitance on the speed of the device.This demonstrates the importance of knowing the load capacitance in the application.The rise time increased about 0.12nsec for an increase of 1pF in the load capacitance.The fall time increased about 0.10nsec for a 1pF increase in the load capacitance.EFFECT OF OFFSETFigure 7shows the variation in rise and fall times when the output offset of the device is varied from 40to 50V DC .The rise time increases less than 0.20nsec from its fastest point near 45V.The fall time becomes faster as the offset voltage increases,but the 45V offset is only 0.1nsec slower than the fastest fall time.THERMAL CONSIDERATIONSFigure 4shows the performance of the LM2465in the test circuit shown in Figure 2as a function of case temperature.The figure shows that the rise time of the LM2465increases by approximately 13%as the case temperature increases from 30˚C to 95˚C.This corresponds to a speed degradation of 2%for every 10˚C rise in case temperature.The fall time degrades around 0.3%for every 10˚C rise in case temperature.Figure 6shows the maximum power dissipation of the LM2465vs.Frequency when all three channels of the device are driving an 8pF load with a 40V p-p alternating one pixel on,one pixel off signal.The graph assumes a 72%active time (device operating at the specified frequency)which is typical in a monitor application.The other 28%of the timethe device is assumed to be sitting at the black level (this case).This graph gives the designer the infor needed to determine the heat sink requirement application.The designer should note that if the capacitance is increased,the AC component of th power dissipation will also increase.The LM2465case temperature must be maintained 100˚C.If the maximum expected ambient tempera 70˚C and the maximum power dissipation is 7.6W Figure 6,75MHz bandwidth)then a maximum hea thermal resistance can be calculated:This example assumes a capacitive load of 8pF a resistive load.TYPICAL APPLICATIONA typical application of the LM2465is shown in Fig and Figure ed in conjunction with an LM1267LM2479/2480bias clamp,a complete video channe monitor input to CRT cathode can be achieved.Perfor is ideal for 1280x 1024resolution displays with pixe frequencies up to 135MHz.Figure 10and Figure 11a schematic for the NSC demonstration board that c used to evaluate the LM1267/2465/2480combinatio monitor.PC BOARD LAYOUT CONSIDERATIONSFor optimum performance,an adequate ground isolation between channels,good supply bypassin minimizing unwanted feedback are necessary.Als length of the signal traces from the preamplifier LM2465and from the LM2465to the CRT cathode sho as short as possible.The following reference recommended:Ott,Henry W.,“Noise Reduction Techniques in Ele Systems”,John Wiley &Sons,New York,1976.“Video Amplifier Design for Computer Monitors”,N Semiconductor Application Note 1013.Pease,Robert A.,“Troubleshooting Analog Ci Butterworth-Heinemann,1991.Because of its high small signal bandwidth,the pa oscillate in a monitor if feedback occurs around the channel through the chassis wiring.To prevent this,le the video amplifier input circuit should be shielded,an circuit wiring should be spaced as far as possible from circuit wiring.DS200190-10FIGURE 9.One Channel of the LM2465with the Recommended Arc Protection Circuit6Figure12shows the routing and component placement onthe NSC LM126X/246X/LM2479/80demonstration board.The schematic of the board is shown in Figure10and Figure11.This board provides a good example of a layout that canbe used as a guide for future layouts.Note the location of thefollowing components:•C16,C19—V CC bypass capacitor,located very close topin4and ground pins•C17,C20—V BB bypass capacitors,located close to pin8and ground•C46,C47,C48—V CC bypass capacitors,near LM2465and V CC clamp diodes.Very important for arc protection.The routing of the LM2465outputs to the CRT is very criticalto achieving optimum performance.Figure13shows therouting and component placement from pin3of the LM2465to the blue cathode.Note that the components are placed sothat they almost line up from the output pin of the LM2465tothe blue cathode pin of the CRT connector.This is done tominimize the length of the video path between these twocomponents.Note also that D8,D9,R24and D6are placedto minimize the size of the video nodes that they areattached to.This minimizes parasitic capacitance in thevideo path and also enhances the effectiveness of theprotection diodes.The anode of protection diode D8isconnected directly to a section of the the ground plane thathas a short and direct path to the LM2465ground pins.Thecathode of D9is connected to V CC very close to decouplingcapacitor C48(see Figure13)which is connected to thesame section of the ground plane as D8.The diodeplacement and routing is very important for minimizing thevoltage stress on the LM2465during an arcover event.Lastly,notice that S3is placed very close to the blue cathodeand is tied directly to CRT ground.7D S 200190-11F IG U R E 10.L M 126X /L M 246X D e m o n s t r a t i o n B o a r d S c h e m a t i c8D S 200190-15F IG U R E 11.L M 126X /L M 246X D e m o n s t r a t i o n B o a r d S c h e m a t i c (c o n t i n u e d )9分销商库存信息: NATIONAL-SEMICONDUCTOR LM2465TA/NOPB。