微控制器MSP430G2221IPW14R MSP430G2221

MSP430G2x31
MSP430G2x21
SLAS694I–FEBRUARY2010–REVISED DECEMBER2011
MIXED SIGNAL MICROCONTROLLER
FEATURES
•Low Supply-Voltage Range:1.8V to3.6V•16-Bit Timer_A With Two Capture/Compare
Registers
•Ultra-Low Power Consumption
•Universal Serial Interface(USI)Supporting SPI –Active Mode:220µA at1MHz,2.2V
and I2C(See Table1)
–Standby Mode:0.5µA
•Brownout Detector
–Off Mode(RAM Retention):0.1µA
•10-Bit200-ksps A/D Converter With Internal •Five Power-Saving Modes
Reference,Sample-and-Hold,and Autoscan •Ultra-Fast Wake-Up From Standby Mode in(See Table1)
Less Than1µs
•Serial Onboard Programming,
•16-Bit RISC Architecture,62.5-ns Instruction No External Programming Voltage Needed, Cycle Time Programmable Code Protection by Security •Basic Clock Module Configurations Fuse
–Internal Frequencies up to16MHz With•On-Chip Emulation Logic With Spy-Bi-Wire One Calibrated Frequency Interface
–Internal Very Low Power Low-Frequency•For Family Members Details,See Table1 (LF)Oscillator•Available in14-Pin Plastic Small-Outline Thin –32-kHz Crystal Package(TSSOP)(PW),14-Pin Plastic Dual –External Digital Clock Source Inline Package(PDIP)(N),and16-Pin QFN
Package(RSA)
•For Complete Module Descriptions,See the
MSP430x2xx Family User’s Guide(SLAU144)
DESCRIPTION
The Texas Instruments MSP430family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications.The architecture,combined with five low-power modes,is optimized to achieve extended battery life in portable measurement applications.The device features a powerful16-bit RISC CPU,16-bit registers,and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator(DCO)allows wake-up from low-power modes to active mode in less than1µs. The MSP430G2x21/G2x31series is an ultra-low-power mixed signal microcontroller with a built-in16-bit timer and ten I/O pins.The MSP430G2x31family members have a10-bit A/D converter and built-in communication capability using synchronous protocols(SPI or I2C).For configuration details,see Table1.
Typical applications include low-cost sensor systems that capture analog signals,convert them to digital values, and then process the data for display or for transmission to a host system.
Please be aware that an important notice concerning availability,standard warranty,and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.Copyright©2010–2011,Texas Instruments Incorporated Products conform to specifications per the terms of the Texas
Instruments standard warranty.Production processing does not
necessarily include testing of all parameters.
MSP430G2x31
MSP430G2x21
SLAS694I–FEBRUARY2010–REVISED
Table1.Available Options(1)
Flash RAM ADC10Package Device BSL EEM Timer_A USI Clock I/O
(KB)(B)Channel Type(2) MSP430G2231IRSA1616-QFN MSP430G2231IPW14-121281x TA218LF,DCO,VLO1014-TSSOP MSP430G2231IN1414-PDIP MSP430G2221IRSA1616-QFN MSP430G2221IPW14-121281x TA21-LF,DCO,VLO1014-TSSOP MSP430G2221IN1414-PDIP MSP430G2131IRSA1616-QFN MSP430G2131IPW14-111281x TA218LF,DCO,VLO1014-TSSOP MSP430G2131IN1414-PDIP MSP430G2121IRSA1616-QFN MSP430G2121IPW14-111281x TA21-LF,DCO,VLO1014-TSSOP MSP430G2121IN1414-PDIP (1)For the most current package and ordering information,see the Package Option Addendum at the end of this document,or see the TI
web site at .
(2)Package drawings,thermal data,and symbolization are available at /packaging.
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DVCC
P1.6/TA0.1/SDO/SCL/TDI/TCLK
P1.7/SDI/SDA/TDO/TDI
RST/NMI/SBWTDIO TEST/SBWTCK XOUT/P2.7
XIN/P2.6/TA0.1DVSS
P1.0/TA0CLK/ACLK
P1.1/TA0.0P1.2/TA0.1
P1.3
P1.4/SMCLK/TCK P1.5/TA0.0/SCLK/TMS
P 1.4/S M C L K /T C K
P 1.5/T A 0.0/S C L K /T M S
P 1.6/T A 0.1/S D O /S C L /T D I /T C L K
P 1.7/S D I /S D A /T D O /T D I
D V S S
D V S S
D V C C
D V C C
P1.0/TA0CLK/ACLK
P1.1/TA0.0P1.2/TA0.1
P1.3
XIN/P2.6/TA0.1XOUT/P2.7TEST/SBWTCK RST/NMI/SBWTDIO
MSP430G2x31MSP430G2x21
SLAS694I –FEBRUARY 2010–REVISED DECEMBER 2011
Device Pinout,MSP430G2x21
N OR PW PACKAGE
(TOP VIEW)
NOTE:See port schematics in Application Information for detailed I/O information.
RSA PACKAGE (TOP VIEW)
NOTE:See port schematics in Application Information for detailed I/O information.
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DVCC
P1.6/TA0.1/A6/SDO/SCL/TDI/TCLK
P1.7/A7/SDI/SDA/TDO/TDI
RST/NMI/SBWTDIO
TEST/SBWTCK XOUT/P2.7XIN/P2.6/TA0.1DVSS
P1.0/TA0CLK/ACLK/A0
P1.1/TA0.0/A1P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREF-P1.4/SMCLK/A4/VREF+/VEREF+/TCK
P1.5/TA0.0/A5/SCLK/TMS
P 1.4/S M C L K /A 4/V R E F +/V E R E F +/T C P 1.5/T A 0.0/S C L K /A 5/T M S
P 1.6/T A 0.1/S D O /S C L /T D I /T C L K
P 1.7/S D I /S D A /T D O /T D D V S S
D V S S
D V C C
D V C C
P1.1/TA0.0/A1P1.2/TA0.1/A2
P1.3/ADC10CLK/A3/VREF-/VEREF-
MSP430G2x31MSP430G2x21
SLAS694I –FEBRUARY 2010–REVISED DECEMBER 2011
Device Pinout,MSP430G2x31
N OR PW PACKAGE
(TOP VIEW)
NOTE:See port schematics in Application Information for detailed I/O information.
RSA PACKAGE (TOP VIEW)
NOTE:See port schematics in Application Information for detailed I/O information.
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Copyright ©2010–2011,Texas Instruments Incorporated
DVCC
DVSS
P1.x XIN XOUT
P2.x
DVCC
DVSS
P1.x XIN XOUT
P2.x
MSP430G2x31MSP430G2x21
SLAS694I –FEBRUARY 2010–REVISED DECEMBER 2011
Functional Block Diagram,MSP430G2x21
Functional Block Diagram,MSP430G2x31
Copyright ©2010–2011,Texas Instruments Incorporated Submit Documentation Feedback 5
MSP430G2x31
MSP430G2x21
SLAS694I–FEBRUARY2010–REVISED
Table2.Terminal Functions
TERMINAL
NO.I/O DESCRIPTION
NAME
N,PW RSA
P1.0/General-purpose digital I/O pin
TA0CLK/Timer0_A,clock signal TACLK input
21I/O
ACLK/ACLK signal output
A0ADC10analog input A0(1)
P1.1/General-purpose digital I/O pin
TA0.0/32I/O Timer0_A,capture:CCI0A input,compare:Out0output
A1ADC10analog input A1(1)
P1.2/General-purpose digital I/O pin
TA0.1/43I/O Timer0_A,capture:CCI1A input,compare:Out1output
A2ADC10analog input A2(1)
P1.3/General-purpose digital I/O pin
ADC10CLK/ADC10,conversion clock output(1)
54I/O
A3/ADC10analog input A3(1)
VREF-/VEREF ADC10negative reference voltage(1)
P1.4/General-purpose digital I/O pin
SMCLK/SMCLK signal output
A4/65I/O ADC10analog input A4(1)
VREF+/VEREF+/ADC10positive reference voltage(1)
TCK JTAG test clock,input terminal for device programming and test
P1.5/General-purpose digital I/O pin
TA0.0/Timer0_A,compare:Out0output
A5/76I/O ADC10analog input A5(1)
SCLK/USI:clock input in I2C mode;clock input/output in SPI mode
TMS JTAG test mode select,input terminal for device programming and test
P1.6/General-purpose digital I/O pin
TA0.1/Timer0_A,capture:CCI1A input,compare:Out1output
A6/ADC10analog input A6(1)
87I/O
SDO/USI:Data output in SPI mode
SCL/USI:I2C clock in I2C mode
TDI/TCLK JTAG test data input or test clock input during programming and test
P1.7/General-purpose digital I/O pin
A7/ADC10analog input A7(1)
SDI/98I/O USI:Data input in SPI mode
SDA/USI:I2C data in I2C mode
TDO/TDI(2)JTAG test data output terminal or test data input during programming and test
XIN/Input terminal of crystal oscillator
P2.6/1312I/O General-purpose digital I/O pin
TA0.1Timer0_A,compare:Out1output
XOUT/Output terminal of crystal oscillator(3)
1211I/O
P2.7General-purpose digital I/O pin
RST/Reset
NMI/109I Nonmaskable interrupt input
SBWTDIO Spy-Bi-Wire test data input/output during programming and test
TEST/Selects test mode for JTAG pins on Port1.The device protection fuse is connected to TEST.
1110I
SBWTCK Spy-Bi-Wire test clock input during programming and test
DVCC115,16NA Supply voltage
DVSS1413,14NA Ground reference
QFN Pad-Pad NA QFN package pad connection to V SS recommended.
(1)MSP430G2x31only
(2)TDO or TDI is selected via JTAG instruction.
(3)If XOUT/P2.7is used as an input,excess current will flow until P2SEL.7is cleared.This is due to the oscillator output driver connection
to this pad after reset.
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Program Counter PC/R0Stack Pointer SP/R1Status Register SR/CG1/R2Constant Generator CG2/R3General-Purpose Register R4General-Purpose Register R5General-Purpose Register R6General-Purpose Register R7General-Purpose Register R8General-Purpose Register R9General-Purpose Register R10General-Purpose Register R11General-Purpose Register R12General-Purpose Register R13General-Purpose Register
R15
General-Purpose Register R14MSP430G2x31MSP430G2x21
SLAS694I –FEBRUARY 2010–REVISED DECEMBER 2011
SHORT-FORM DESCRIPTION
CPU
The MSP430CPU has a 16-bit RISC architecture that is highly transparent to the application.All operations,other than program-flow instructions,are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16registers that provide reduced instruction execution time.The register-to-register operation execution time is one cycle of the CPU clock.
Four of the registers,R0to R3,are dedicated as program counter,stack pointer,status register,and constant generator,respectively.The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data,address,and control buses,and can be handled with all instructions.
The instruction set consists of the original 51instructions with three formats and seven address modes and additional instructions for the expanded address range.Each instruction can operate on word and byte data.
Instruction Set
The instruction set consists of 51instructions with three formats and seven address modes.Each instruction can operate on word and byte data.Table 3shows examples of the three types of instruction formats;Table 4shows the address modes.
Table 3.Instruction Word Formats
INSTRUCTION FORMAT SYNTAX OPERATION Dual operands,source-destination ADD R4,R5R4+R5--->R5Single operands,destination only CALL R8PC -->(TOS),R8-->PC Relative jump,un/conditional
JNE
Jump-on-equal bit =0
Table 4.Address Mode Descriptions (1)
ADDRESS MODE
S D SYNTAX EXAMPLE OPERATION Register ✓✓MOV Rs,Rd MOV R10,R11R10---->R11Indexed
✓✓MOV X(Rn),Y(Rm)MOV 2(R5),6(R6)
M(2+R5)---->M(6+R6)Symbolic (PC relative)
✓✓MOV EDE,TONI M(EDE)---->M(TONI)Absolute ✓✓
MOV &MEM,&TCDAT M(MEM)---->M(TCDAT)Indirect
✓MOV @Rn,Y(Rm)MOV @R10,Tab(R6)M(R10)---->M(Tab+R6)
M(R10)---->R11Indirect autoincrement
✓MOV @Rn+,Rm MOV @R10+,R11R10+2---->R10Immediate
✓
MOV #X,TONI
MOV #45,TONI #45---->M(TONI)
(1)
S =source,D =destination
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MSP430G2x31
MSP430G2x21
SLAS694I–FEBRUARY2010–REVISED Operating Modes
The MSP430has one active mode and five software selectable low-power modes of operation.An interrupt event can wake up the device from any of the low-power modes,service the request,and restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
•Active mode(AM)
–All clocks are active
•Low-power mode0(LPM0)
–CPU is disabled
–ACLK and SMCLK remain active,MCLK is disabled
•Low-power mode1(LPM1)
–CPU is disabled
–ACLK and SMCLK remain active,MCLK is disabled
–DCO's dc generator is disabled if DCO not used in active mode
•Low-power mode2(LPM2)
–CPU is disabled
–MCLK and SMCLK are disabled
–DCO's dc generator remains enabled
–ACLK remains active
•Low-power mode3(LPM3)
–CPU is disabled
–MCLK and SMCLK are disabled
–DCO's dc generator is disabled
–ACLK remains active
•Low-power mode4(LPM4)
–CPU is disabled
–ACLK is disabled
–MCLK and SMCLK are disabled
–DCO's dc generator is disabled
–Crystal oscillator is stopped
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MSP430G2x31
MSP430G2x21 SLAS694I–FEBRUARY2010–REVISED DECEMBER2011 Interrupt Vector Addresses
The interrupt vectors and the power-up starting address are located in the address range0FFFFh to0FFC0h. The vector contains the16-bit address of the appropriate interrupt handler instruction sequence.
If the reset vector(located at address0FFFEh)contains0FFFFh(for example,flash is not programmed)the CPU goes into LPM4immediately after power-up.
Table5.Interrupt Sources,Flags,and Vectors
SYSTEM WORD INTERRUPT SOURCE INTERRUPT FLAG PRIORITY
INTERRUPT ADDRESS
Power-Up PORIFG
External Reset RSTIFG
Watchdog Timer+WDTIFG Reset0FFFEh31,highest
Flash key violation KEYV(2)
PC out-of-range(1)
NMI NMIIFG(non)-maskable
Oscillator fault OFIFG(non)-maskable0FFFCh30 Flash memory access violation ACCVIFG(2)(3)(non)-maskable
0FFFAh29
0FFF8h28
0FFF6h27 Watchdog Timer+WDTIFG maskable0FFF4h26 Timer_A2TACCR0CCIFG(4)maskable0FFF2h25
Timer_A2TACCR1CCIFG,TAIFG(2)(4)maskable0FFF0h24
0FFEEh23
0FFECh22 ADC10(5)ADC10IFG(4)(5)maskable0FFEAh21 USI USIIFG,USISTTIFG(2)(4)maskable0FFE8h20 I/O Port P2(two flags)P2IFG.6to P2IFG.7(2)(4)maskable0FFE6h19
I/O Port P1(eight flags)P1IFG.0to P1IFG.7(2)(4)maskable0FFE4h18
0FFE2h17
0FFE0h16
See(6)0FFDEh to
15to0,lowest
0FFC0h
(1)A reset is generated if the CPU tries to fetch instructions from within the module register memory address range(0h to01FFh)or from
within unused address ranges.
(2)Multiple source flags
(3)(non)-maskable:the individual interrupt-enable bit can disable an interrupt event,but the general interrupt enable cannot.
(4)Interrupt flags are located in the module.
(5)MSP430G2x31only
(6)The interrupt vectors at addresses0FFDEh to0FFC0h are not used in this device and can be used for regular program code if
necessary.
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MSP430G2x31
MSP430G2x21
SLAS694I–FEBRUARY2010–REVISED Special Function Registers(SFRs)
Most interrupt and module enable bits are collected into the lowest address space.Special function register bits not allocated to a functional purpose are not physically present in the device.Simple software access is provided with this arrangement.
Legend rw:Bit can be read and written.
rw-0,1:Bit can be read and written.It is reset or set by PUC.
rw-(0,1):Bit can be read and written.It is reset or set by POR.
SFR bit is not present in device.
Table6.Interrupt Enable Register1and2
Address76543210 00h ACCVIE NMIIE OFIE WDTIE
rw-0rw-0rw-0rw-0 WDTIE Watchdog Timer interrupt enable.Inactive if watchdog mode is selected.Active if Watchdog Timer is configured in interval timer mode.
OFIE Oscillator fault interrupt enable
NMIIE(Non)maskable interrupt enable
ACCVIE Flash access violation interrupt enable
Address76543210 01h
Table7.Interrupt Flag Register1and2
Address76543210 02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG
rw-0rw-(0)rw-(1)rw-1rw-(0) WDTIFG Set on watchdog timer overflow(in watchdog mode)or security key violation.
Reset on V CC power-on or a reset condition at the pin in reset mode.
OFIFG Flag set on oscillator fault.
PORIFG Power-On Reset interrupt flag.Set on V CC power-up.
RSTIFG External reset interrupt flag.Set on a reset condition at pin in reset mode.Reset on V CC power-up.
NMIIFG Set via pin
Address76543210 03h
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Memory Organization
Table8.Memory Organization
MSP430G2021MSP430G2121MSP430G2221
MSP430G2031MSP430G2131MSP430G2231 Memory Size512B1kB2kB
Main:interrupt vector Flash0xFFFF to0xFFC00xFFFF to0xFFC00xFFFF to0xFFC0 Main:code memory Flash0xFFFF to0xFE000xFFFF to0xFC000xFFFF to0xF800 Information memory Size256Byte256Byte256Byte
Flash010FFh to01000h010FFh to01000h010FFh to01000h
RAM Size128B128B128B
027Fh to0200h027Fh to0200h027Fh to0200h Peripherals16-bit01FFh to0100h01FFh to0100h01FFh to0100h
8-bit0FFh to010h0FFh to010h0FFh to010h
8-bit SFR0Fh to00h0Fh to00h0Fh to00h
Flash Memory
The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU.The CPU can perform single-byte and single-word writes to the flash memory.Features of the flash memory include:
•Flash memory has n segments of main memory and four segments of information memory(A to D)of 64bytes each.Each segment in main memory is512bytes in size.
•Segments0to n may be erased in one step,or each segment may be individually erased.
•Segments A to D can be erased individually or as a group with segments0to n.Segments A to D are also called information memory.
•Segment A contains calibration data.After reset segment A is protected against programming and erasing.It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required.
Peripherals are connected to the CPU through data,address,and control buses and can be handled using all instructions.For complete module descriptions,see the MSP430x2xx Family User's Guide(SLAU144). Oscillator and System Clock
The clock system is supported by the basic clock module that includes support for a32768-Hz watch crystal oscillator,an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator(DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption.The internal DCO provides a fast turn-on clock source and stabilizes in less than1µs.The basic clock module provides the following clock signals:
•Auxiliary clock(ACLK),sourced either from a32768-Hz watch crystal or the internal LF oscillator.
•Main clock(MCLK),the system clock used by the CPU.
•Sub-Main clock(SMCLK),the sub-system clock used by the peripheral modules.
Table9.DCO Calibration Data
(Provided From Factory In Flash Information Memory Segment A)
CALIBRATION
DCO FREQUENCY SIZE ADDRESS
REGISTER
CALBC1_1MHZ byte010FFh
1MHz
CALDCO_1MHZ byte010FEh
Brownout
The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off.
Digital I/O
There is one8-bit I/O port implemented—port P1—and two bits of I/O port P2:
•All individual I/O bits are independently programmable.
•Any combination of input,output,and interrupt condition is possible.
•Edge-selectable interrupt input capability for all the eight bits of port P1and the two bits of port P2.
•Read/write access to port-control registers is supported by all instructions.
•Each I/O has an individually programmable pull-up/pull-down resistor.
WDT+Watchdog Timer
The primary function of the watchdog timer(WDT+)module is to perform a controlled system restart after a software problem occurs.If the selected time interval expires,a system reset is generated.If the watchdog function is not needed in an application,the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals.
Timer_A2is a16-bit timer/counter with two capture/compare registers.Timer_A2can support multiple capture/compares,PWM outputs,and interval timing.Timer_A2also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers.
Table10.Timer_A2Signal Connections–Device With ADC10
INPUT PIN NUMBER MODULE OUTPUT PIN NUMBER
DEVICE INPUT MODULE MODULE
OUTPUT
SIGNAL INPUT NAME BLOCK
PW,N RSA PW,N RSA
SIGNAL
2-P1.01-P1.0TACLK TACLK
ACLK ACLK
Timer NA
SMCLK SMCLK
2-P1.01-P1.0TACLK INCLK
3-P1.12-P1.1TA0CCI0A3-P1.12-P1.1
ACLK(internal)CCI0B7-P1.56-P1.5
CCR0TA0
VSS GND
VCC VCC
4-P1.23-P1.2TA1CCI1A4-P1.23-P1.2
8-P1.67-P1.6TA1CCI1B8-P1.67-P1.6
CCR1TA1
VSS GND13-P2.612-P2.6
VCC VCC
USI
The universal serial interface(USI)module is used for serial data communication and provides the basic hardware for synchronous communication protocols like SPI and I2C.
ADC10(MSP430G2x31only)
The ADC10module supports fast,10-bit analog-to-digital conversions.The module implements a10-bit SAR core,sample select control,reference generator and data transfer controller,or DTC,for automatic conversion result handling,allowing ADC samples to be converted and stored without any CPU intervention.
Peripheral File Map
Table11.Peripherals With Word Access
REGISTER
MODULE REGISTER DESCRIPTION OFFSET
NAME
ADC10(MSP430G2x31only)ADC data transfer start address ADC10SA1BCh
ADC control0ADC10CTL001B0h
ADC control1ADC10CTL001B2h
ADC memory ADC10MEM01B4h Timer_A Capture/compare register TACCR10174h
Capture/compare register TACCR00172h
Timer_A register TAR0170h
Capture/compare control TACCTL10164h
Capture/compare control TACCTL00162h
Timer_A control TACTL0160h
Timer_A interrupt vector TAIV012Eh Flash Memory Flash control3FCTL3012Ch
Flash control2FCTL2012Ah
Flash control1FCTL10128h Watchdog Timer+Watchdog/timer control WDTCTL0120h
Table12.Peripherals With Byte Access
REGISTER
MODULE REGISTER DESCRIPTION OFFSET
NAME
ADC10(MSP430G2x31only)ADC analog enable ADC10AE004Ah
ADC data transfer control1ADC10DTC1049h
ADC data transfer control0ADC10DTC0048h USI USI control0USICTL0078h
USI control1USICTL1079h
USI clock control USICKCTL07Ah
USI bit counter USICNT07Bh
USI shift register USISR07Ch Basic Clock System+Basic clock system control3BCSCTL3053h
Basic clock system control2BCSCTL2058h
Basic clock system control1BCSCTL1057h
DCO clock frequency control DCOCTL056h Port P2Port P2resistor enable P2REN02Fh
Port P2selection P2SEL02Eh
Port P2interrupt enable P2IE02Dh
Port P2interrupt edge select P2IES02Ch
Port P2interrupt flag P2IFG02Bh
Port P2direction P2DIR02Ah
Port P2output P2OUT029h
Port P2input P2IN028h
Table12.Peripherals With Byte Access(continued)
REGISTER MODULE REGISTER DESCRIPTION OFFSET
NAME
Port P1Port P1resistor enable P1REN027h
Port P1selection P1SEL026h
Port P1interrupt enable P1IE025h
Port P1interrupt edge select P1IES024h
Port P1interrupt flag P1IFG023h
Port P1direction P1DIR022h
Port P1output P1OUT021h
Port P1input P1IN020h Special Function SFR interrupt flag2IFG2003h
SFR interrupt flag1IFG1002h
SFR interrupt enable2IE2001h
SFR interrupt enable1IE1000h
Absolute Maximum Ratings(1)
Voltage applied at V CC to V SS–0.3V to4.1V Voltage applied to any pin(2)–0.3V to V CC+0.3V Diode current at any device pin±2mA
Unprogrammed device–55°C to150°C Storage temperature range,T stg(3)
Programmed device–55°C to150°C
(1)Stresses beyond those listed under"absolute maximum ratings"may cause permanent damage to the device.These are stress ratings
only,and functional operation of the device at these or any other conditions beyond those indicated under"recommended operating conditions"is not implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)All voltages referenced to V SS.The JTAG fuse-blow voltage,V FB,is allowed to exceed the absolute maximum rating.The voltage is
applied to the TEST pin when blowing the JTAG fuse.
(3)Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020specification with peak reflow
temperatures not higher than classified on the device label on the shipping boxes or reels.
0.01.0
2.0
3.0
4.05.0
1.5
2.0 2.5
3.0 3.5
4.0V CC −Supply Voltage −V A c t i v e M o d e C u r r e n t −m A
0.01.0
2.0
3.0
4.0
0.0
4.08.012.016.0
f DCO −DCO Frequency −MHz
A c t i v e M o d e C u r r e n t −m A
Electrical Characteristics
Active Mode Supply Current Into V CC Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER
TEST CONDITIONS
T A
V CC MIN
TYP MAX
UNIT
f DCO =f MCLK =f SMCLK =1MHz, 2.2V
220
f ACLK =32768Hz,
Program executes in flash,Active mode (AM)I AM,1MHz
BCSCTL1=CALBC1_1MHZ,µA
current (1MHz)
3V 300370
DCOCTL =CALDCO_1MHZ,
CPUOFF =0,SCG0=0,SCG1=0,OSCOFF =0
(1)All inputs are tied to 0V or to V CC .Outputs do not source or sink any current.
(2)
The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9pF.The internal and external load capacitance is chosen to closely match the required 9pF.
Typical Characteristics –Active Mode Supply Current (Into V CC )
Figure 2.Active Mode Current vs V CC ,T A =25°C
Figure 3.Active Mode Current vs DCO Frequency
-40
I –L o w -P o w e r M o d e C u r r e n t –µA
L P M 4T –Temperature –°C A -20
20
40
60
80
I –L o w -P o w e r M o d e C u r r e n t –µA
T –Temperature –°C
A Low-Power Mode Supply Currents (Into V CC )Excluding External Current
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)
(2)
PARAMETER
TEST CONDITIONS
T A
V CC
MIN
TYP MAX UNIT
f MCLK =0MHz,
f SMCLK =f DCO =1MHz,f ACLK =32768Hz,
Low-power mode 0I LPM0,1MHz
BCSCTL1=CALBC1_1MHZ,25°C 2.2V 65µA
(LPM0)current (3)
DCOCTL =CALDCO_1MHZ,
CPUOFF =1,SCG0=0,SCG1=0,OSCOFF =0
f MCLK =f SMCLK =0MHz,f DCO =1MHz,f ACLK =32768Hz,
Low-power mode 2I LPM2
BCSCTL1=CALBC1_1MHZ,25°C 2.2V 22µA
(LPM2)current (4)
DCOCTL =CALDCO_1MHZ,
CPUOFF =1,SCG0=0,SCG1=1,OSCOFF =0
f DCO =f MCLK =f SMCLK =0MHz,Low-power mode 3f ACLK =32768Hz,
I LPM3,LFXT1
25°C 2.2V 0.7 1.5µA
(LPM3)current (4)
CPUOFF =1,SCG0=1,SCG1=1,OSCOFF =0
f DCO =f MCLK =f SMCLK =0MHz,
Low-power mode 3f ACLK from internal LF oscillator (VLO),I LPM3,VLO
25°C 2.2V 0.50.7µA current,(LPM3)(4)
CPUOFF =1,SCG0=1,SCG1=1,OSCOFF =0
f DCO =f MCLK =f SMCLK =0MHz,25°C 2.2V 0.10.5µA Low-power mode 4f ACLK =0Hz,
I LPM4
(LPM4)current (5)
CPUOFF =1,SCG0=1,SCG1=1,85°C
2.2V
0.8
1.5
µA
OSCOFF =1
(1)All inputs are tied to 0V or to V CC .Outputs do not source or sink any current.
(2)The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9pF.(3)Current for brownout and WDT clocked by SMCLK included.(4)Current for brownout and WDT clocked by ACLK included.(5)Current for brownout included.
Typical Characteristics Low-Power Mode Supply Currents
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
Figure 4.LPM3Current vs Temperature Figure 5.LPM4Current vs Temperature
Schmitt-Trigger Inputs–Ports Px
over recommended ranges of supply voltage and operating free-air temperature(unless otherwise noted)
PARAMETER TEST CONDITIONS V CC MIN TYP MAX UNIT
0.45V CC0.75V CC
V IT+Positive-going input threshold voltage V
3V 1.35 2.25
0.25V CC0.55V CC
V IT–Negative-going input threshold voltage V
3V0.75 1.65
V hys Input voltage hysteresis(V IT+–V IT–)3V0.31V
For pullup:V IN=V SS
R Pull Pullup/pulldown resistor3V203550kΩ
For pulldown:V IN=V CC
C I Input capacitance V IN=V SS or V CC5pF Leakage Current–Ports Px
over recommended ranges of supply voltage and operating free-air temperature(unless otherwise noted)
PARAMETER TEST CONDITIONS V CC MIN MAX UNIT
I lkg(Px.y)High-impedance leakage current(1)(2)3V±50nA
(1)The leakage current is measured with V SS or V CC applied to the corresponding pin(s),unless otherwise noted.
(2)The leakage of the digital port pins is measured individually.The port pin is selected for input and the pullup/pulldown resistor is
disabled.
Outputs–Ports Px
over recommended ranges of supply voltage and operating free-air temperature(unless otherwise noted)
PARAMETER TEST CONDITIONS V CC MIN TYP MAX UNIT V OH High-level output voltage I(OHmax)=–6mA(1)3V V CC–0.3V
V OL Low-level output voltage I(OLmax)=6mA(1)3V V SS+0.3V (1)The maximum total current,I(OHmax)and I(OLmax),for all outputs combined should not exceed±48mA to hold the maximum voltage drop
specified.
Output Frequency–Ports Px
over recommended ranges of supply voltage and operating free-air temperature(unless otherwise noted)
PARAMETER TEST CONDITIONS V CC MIN TYP MAX UNIT
Port output frequency
f Px.y Px.y,C L=20pF,R L=1kΩ(1)(2)3V12MHz
(with load)
f Port_CLK Clock output frequency Px.y,C L=20pF(2)3V16MHz
(1)A resistive divider with2×0.5kΩbetween V CC and V SS is used as load.The output is connected to the center tap of the divider.
(2)The output voltage reaches at least10%and90%V CC at the specified toggle frequency.。