盖伟新简历_北京大学

盖伟新
教授、博士生导师
北京大学信息科学技术学院
Email: wgai@
研究兴趣
•高速数据通讯核心芯片研究
•数据传输均衡技术和自适应技术研究
•高效能低抖动全数字锁相环研究
•高速高精度低功耗ADC研究
•无线（包括RF）互连、光互连集成电路研究
•高效电源管理芯片研究
工作和学习简历
•美国富士通实验室，资深研究员
•美国双元科技，CTO
•美国ABAQoS通讯公司，资深经理
•美国AMD（先进微器件）公司，Sr. MTS
•美国HAL计算机公司，资深设计师、项目负责人
•清华大学，电子工程系，获博士学位、硕士学位、学士学位
主要论文
∙“A 4-channel 1.25-10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control”, IEEE J. Solid-State Circuits, vol.44, pp.3547-3559, Dec. 2009.
∙“A 4-channel 10.3Gb/s backplane transceiver macro with 35dB equalizer and sign-based zero-forcing adaptive control”, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp.188-189, Feb. 2009.
∙“A 4-channel 3.1/10.3Gb/s transceiver macro with a pattern-tolerant adaptive equalizer”, in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 442–443, Feb. 2007.
∙“Design consideration of 6.25Gbps signaling for high-performance server”, in Proc. Asia and South Pacific Design Automation Conference (ASP-DAC), pp. 854-857, Jun. 2007
∙“Gain-phase co-equalization for widely-used high-speed cables”, in IEEE Symp. VLSI Circuits Dig. Tech. Papers, vol. 19, pp.194–197, Jun. 2005.
∙“4-channel 3.125Gbits/s/ch transceiver with 30dB compensation”, in IEEE Symp. VLSI Circuits Dig. Tech. Papers, vol. 18, pp. 138–141, Jun. 2004.
∙“A fully-pipeline linear systolic architecture for modular multiplier in public-key crypto-systems,” J.
of VLSI Signal Processing, vol. 33, no. 1-2, pp. 191-197, Jan. 2003
∙“A 2-byte parallel 1.25Gb/s interconnect with self-configurable link and plesiochronous clocking,”
in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 180 –181, 1999.
∙“VLSI implementation of modular exponentiation for large operands,” Acta Electronica Sinica, vol.
27, pp. 8-11, 1999.
∙"A novel systolic implementation of modular multiplication for large operands," Journal of Tsinghua University, vol.38, No.3, 1998.
∙“Quadratic-translinear CMOS multiplier-divider circuit,” Electronics Letters, vol. 33, no. 10, pp.
860-861, May 1997.
∙“A systolic linear array for modular multiplication,” in Proc.2nd International Conference on ASIC (ASICON), pp. 171-174, Oct. 1996.
∙"A CMOS current-mode analog multiplier based on the translinear principle," Chinese Journal of Electronics, vol. 5, no. 1, pp. 40-43, July 1996.
∙“A novel variable radix fast multiplication hardware algorithm for public-key cryptosystem,” Acta Electronica Sinica, vol. 23, no. 11, pp. 77-80, Nov. 1995.
∙“A current-mode analog multi plier based on translinear principle,” in the Proc. 4th International Conference on Solid-State and Integrated-Circuit Technology (ICSICT), pp. 196-198, Oct. 1995. ∙“Smart card: a novel information processing tool,” Electronic Science & Technology Review, no.
3, pp. 2-5, Mar. 1995.
美国发明专利
∙“Decision feedback equalizer (DFE)”, U.S. Pub. No. 2009/0316769, Dec. 24, 2009
∙“System and method for combining a plurality of signals of various phases having a wide frequency r ange,” U.S. Patent 7778344, Aug. 17, 2010.
∙“Equalizing a signal for transmission,” U.S. Patent 7512178, May 31, 2009.
∙“Adaptive equalizer with DC offset compensation,” U.S. Patent 7295605, Nov. 13, 2007.
∙“Equalizing a signal for transmission,” U.S. Patent 7173965, Feb. 6, 2007.
∙“Correcting DC offsets in a multi-stage amplifier,” U.S. Patent 7034608, Apr. 25, 2006.
∙“Feedback control for termination adjustment,” U.S. Patent 6418500, July 9, 2002.
∙“Supply noise immunity low-jittery voltage-controlled oscillator design,” U.S. Patent 6246294, June 12, 2001.
∙“Systolic linear-array modular multiplier with pipeline processing elements,” U.S. Patent 6061706, May 9, 2000.
∙“CMOS current-mode four-quadrant analog multiplier,” U.S. Patent 5966040, Oct.12, 1999.
∙“Multiplier based on a variable radix multiplier coding,” U.S. Patent 5828590, Oct.27, 1998.
∙“Method of modular reduction and modular reduction circuit,” U.S. Patent 5793659, Aug.11, 1998.。