009_gblox

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Y.T.Chang/2001.02/XLNX_PC
gblox-6
Memories
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CIC
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Customed sized RAM, ROM, or dual-port RAM Creates the input decoder and output multiplexer when necessary Specify the necessary bus width and memory depth to customize the size Enter a memory filename to initialize a memory (for example, tenths.mem)
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Y.T.Chang/2001.02/XLNX_PC
gblox-2
Module Types
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CIC
Clock Dividers Comparators Data Registers Inputs/Outputs Memories Shift Registers Simple Gates Tristate Buffers Adders Subtracters Counters Constants Pads Multiplexers Decoders
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Y.T.Chang/2001.02/XLNX_PC
gblox-13
Y.T.Chang/2001.02/XLNX_PC
gblox-7
Multiplexers
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CIC
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The Multiplexer module can have up to eight input busses This module can be optimized for area and speed The Mux module can utilize the tristate buffers by selecting the Wired-AND Style
CIC
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Options
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CORE Generator preforms a similar function as LogiBLOX Generates an edif netlist (LogiBLOX generates .ngc file). Modify settings through Project > Project Each Core is associated with a Core Datasheet Core is automatically placed in project library Supports Virtex, 4000E/EX/XL/XLA/XV, and Spartan
Y.T.Chang/2001.02/XLNX_PC
gblox-4
Counters
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CIC
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resources used for the module For example, choosing the Maximum Speed option tells the software to use the Carry Logic resources if the appropriate FPGA has been selected The Counters module can be binary, Johnson, LFSR, or One-Hot encoded
Y.T.Chang/2001.02/XLNX_PC
About CoreGenerator
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CIC
CORE Generator
Menu command: Tools => Design Entry =>
Y.T.Chang/2001.02/XLNX_PC
gblox-11
CORE Generator
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Y.T.Chang/2001.02/XLNX_PC
gblox-8
Simple GAND, NOR, OR,XNOR, and XOR
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Creates generic bused gate functions of common logic primitives: AND,
LogiBLOX & CORE Generator
Y.T.Chang/2001.02/XLNX_PC
gblox-1
About LogiBLOX
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CIC
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LogiBLOX is a GUI for creating high-level modules LogiBLOX customizes components for size and the FPGAs architectural resources The GUI disables selections that are incompatible with your design selections LogiBLOX components are entered just like a macro Functional simulation is possible without implementation Note: use CORE Generator for Virtex designs
gblox-3
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Y.T.Chang/2001.02/XLNX_PC
After selecting a module...
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CIC
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Name the module Specify a bus width Select the desired ports Choose a Style and Operation Choose a loading value An asynchronous reset will require an Async Val of “0000” for a 4 bit binary counter
Style will determine the
Y.T.Chang/2001.02/XLNX_PC
gblox-5
Adder/Subtracters
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CIC
All arithmetic functions can utilize the Carry Logic resources Adders/Subtracters, Accumulators, and the Comparators modules can be customized for signed or unsigned binary logic
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Logic function is customized by the Gate Type you select Individual inputs can be inverted by using the Inversion Mask or Decode Mask attributes
gblox-9
Y.T.Chang/2001.02/XLNX_PC
gblox-12
Questions
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CIC
How can Adders/Subtracters modules be customized? Arithmetic functions can use what special architecture resource to improve performance and density? What advantage is there in using a LogiBLOX Ram rather than a Ram from the Xilinx Unified Library? The Multiplexers module has what special style?