DP8422V中文资料

TL F 11109DP8420V 21V 22V-33 DP84T22-25 microCMOS Programmable 256k 1M 4M Dynamic RAM Controller DriversMay1992 DP8420V 21V 22V-33 DP84T22-25microCMOS Programmable256k 1M 4M Dynamic RAMController DriversGeneral DescriptionThe DP8420V 21V 22V-33 DP84T22-25dynamic RAMcontrollers provide a low cost single chip interface betweendynamic RAM and all8- 16-and32-bit systems TheDP8420V 21V 22V-33 DP84T22-25generate all the re-quired access control signal timing for DRAMs An on-chiprefresh request clock is used to automatically refresh theDRAM array Refreshes and accesses are arbitrated onchip If necessary a WAIT or DTACK output inserts waitstates into system access cycles including burst mode ac-cesses RAS low time during refreshes and RAS prechargetime after refreshes and back to back accesses are guaran-teed through the insertion of wait states Separate on-chipprecharge counters for each RAS output can be used formemory interleaving to avoid delayed back to back access-es because of precharge An additional feature of theDP8422V DP84T22is two access ports to simplify dual ac-cessing Arbitration among these ports and refresh is doneon chip To make board level circuit testing easier theDP84T22incorporates TRI-STATE output buffersFeaturesY On chip high precision delay line to guarantee criticalDRAM access timing parametersY microCMOS process for low powerY High capacitance drivers for RAS CAS WE and DRAMaddress on chipY On chip support for nibble page and static columnDRAMsY TRI-STATE outputs(DP84T22only)Y Byte enable signals on chip allow byte writing in a wordsize up to32bits with no external logicY Selection of controller speeds 25MHz and33MHzY On board Port A Port B(DP8422V DP84T22only) re-fresh arbitration logicY Direct interface to all major microprocessors(applica-tion notes available)Y4RAS and4CAS drivers(the RAS and CAS configura-tion is programmable)of Pins of AddressLargest Direct Drive AccessControl(PLCC)OutputsDRAM Memory PortsPossible Capacity Available DP8420V689256kbit4Mbytes Single Access PortDP8421V68101Mbit16Mbytes Single Access PortDP8422V84114Mbit64Mbytes Dual Access Ports(A and B) DP84T2284114Mbit64Mbytes Dual Access and TRI-STATE Block DiagramDP8420V 21V 22V DP74T22DRAM ControllerTL F 11109–1FIGURE1TRI-STATE is a registered trademark of National Semiconductor CorporationStaggered Refresh TM is a trademark of National Semiconductor CorporationC1995National Semiconductor Corporation RRD-B30M105 Printed in U S ATable of Contents1 0INTRODUCTION2 0SIGNAL DESCRIPTIONS2 1Address R W and Programming Signals2 2DRAM Control Signals2 3Refresh Signals2 4Port A Access Signals2 5Port B Access Signals(DP8422V DP84T22)2 6Common Dual Port Signals(DP8422V DP84T22) 2 7Power Signals and Capacitor Input2 8Clock Inputs3 0PROGRAMMING AND RESETTING3 1External Reset3 2Programming Methods3 2 1Mode Load Only Programming3 2 2Chip Selected Access Programming3 3Internal Programming Modes4 0PORT A ACCESS MODES4 1Access Mode04 2Access Mode14 3Extending CAS with Either Access Mode4 4Read-Modify-Write Cycles with Either Access Mode 4 5Additional Access Support Features4 5 1Address Latches and Column Increment4 5 2Address Pipelining4 5 3Delay CAS during Write Accesses5 0REFRESH OPTIONS5 1Refresh Control Modes5 1 1Automatic Internal Refresh5 1 2Externally Controlled Burst Refresh5 1 3Refresh Request Acknowledge5 2Refresh Cycle Types5 2 1Conventional Refresh5 2 2Staggered Refresh TM5 2 3Error Scrubbing Refresh5 3Extending Refresh5 4Clearing the Refresh Address Counter5 5Clearing the Refresh Request Clock6 0PORT A WAIT STATE SUPPORT6 1WAIT Type Output6 2DTACK Type Output6 3Dynamically Increasing the Number of Wait States6 4Guaranteeing RAS Low Time and RAS PrechargeTime7 0RAS AND CAS CONFIGURATION MODES7 1Byte Writing7 2Memory Interleaving7 3Address Pipelining7 4Error Scrubbing7 5Page Burst Mode8 0TEST MODE9 0DRAM CRITICAL TIMING PARAMETERS9 1Programmable Values of t RAH and t ASC9 2Calculation of t RAH and t ASC10 0DUAL ACCESSING(DP8422V and DP84T22V)10 1Port B Access Mode10 2Port B Wait State Support10 3Common Port A and Port B Dual Port Functions10 3 1GRANTB Output10 3 2LOCK Input10 4TRI-STATE Outputs(DP84T22Only)11 0ABSOLUTE MAXIMUM RATINGS12 0DC ELECTRICAL CHARACTERISTICS13 0AC TIMING PARAMETERS14 0FUNCTIONAL DIFFERENCES BETWEEN THEDP8420V 21V 22V DP84T22AND THEDP8420 21 2215 0DP8420V 21V 22V DP84T22USER HINTS21 0IntroductionThe DP8420V 21V 22V DP84T22are CMOS Dynamic RAM controllers that incorporate many advanced features which include address latches refresh counter refresh clock row column and refresh address multiplexer delay line refresh access arbitration logic and high capacitive drivers The programmable system interface allows any manufacturer’s microprocessor or bus to directly interface via the DP8420V 21V 22V DP84T22to DRAM arrays up to 64Mbytes in sizeAfter power up the user must first reset and program the DP8420V 21V 22V DP84T22before accessing the DRAM The chip is programmed through the address busResetDue to the differences in power supplies an External(hard-ware)Reset must be performed before programming the chipProgrammingAfter resetting the chip the user can program the controller by either one of two methods Mode Load Only Program-ming or Chip Select Access ProgrammingInitialization PeriodOnce the DP8420V 21V 22V DP84T22has been pro-grammed for the first time a60ms initialization period is entered During this time the DRC performs refreshes to the DRAM array so further warm up cycles are unnecessary The initialization period is entered only after the first pro-gramming after a resetAccessing ModesAfter resetting and programming the chip the DP8420V 21V 22V DP84T22is ready to access the DRAM There are two modes of accessing with these con-trollers Mode0 which indicates RAS synchronously and Mode1 which indicates RAS asynchronouslyRefresh ModesThe DP8420V 21V 22V DP84T22have expanded refresh capabilities compared to previous DRAM controllers There are three modes of refreshing available Internal Automatic Refreshing Externally Controlled Burst Refreshing and Re-fresh Request Acknowledge Refreshing Any of these modes can be used together or separately to achieve the desired resultsRefresh TypesThese controllers have three types of refreshing available Conventional Staggered and Error Scrubbing Any refresh control mode can be used with any type of refreshWait SupportThe DP8420V 21V 22V DP84T22have wait support avail-able as DTACK or WAIT Both are programmable DTACK Data Transfer ACKnowledge is useful for processors whose wait signal is active high WAIT is useful for those processors whose wait signal is active low The user can choose either at programming These signals are used by the on chip arbiter to insert wait states to guarantee the arbitration between accesses refreshes and precharge Both signals are independent of the access mode chosen and both signals can be dynamically delayed further through the WAITIN signal to the DP8420V 21V 22V DP84T22 Sequential Accesses(Static Column Page Mode)The DP8420V 21V 22V DP84T22have address latches used to latch the bank row and column address inputsOnce the address is latched a COLumn INCrement(COL-INC)feature can be used to increment the column address The address latches can also be programmed to be fall through COLINC can be used for Sequential Accesses of Static Column DRAMs Also COLINC in conjunction with ECAS inputs can be used for Sequential Accesses to Page Mode DRAMsRAS and CAS Configuration(Byte Writing)The RAS and CAS drivers can be configured to drive a one two or four bank memory array up to32bits in width The ECAS signals can then be used to select one of four CAS drivers for Byte Writing with no extra logicMemory InterleavingWhen configuring the DP8420V 21V 22V DP84T22for more than one bank Memory Interleaving can be used By tying the low order address bits to the bank select lines B0 and B1 sequential back to back accesses will not be de-layed since these controllers have separate precharge counters per bankAddress PipeliningThe DP8420V 21V 22V DP84T22are capable of perform-ing Address Pipelining In address pipelining the DRC will guarantee the column address hold time and switch the in-ternal multiplexor to place the row address on the address bus At this time another memory access to another bank can be initiatedDual AccessingThe DP8422V DP84T22have all the features previously mentioned and unlike the DP8420V 21V the DP8422V DP84T22have a second port to allow a second CPU to access the same memory array The DP8422V DP84T22 have four signals to support Dual Accessing these signals are AREQB ATACKB LOCK and GRANTB All arbitration for the two ports and refresh is done on chip by the control-ler through the insertion of wait states Since the DP8422V DP84T22have only one input address bus the address lines must be multiplexed externally The signal GRANTB can be used for this purposeTRI-STATE OutputsThe DP84T22implements TRI-STATE outputs When the input OE is asserted the output buffers are enabled when OE is negated logic1 the output buffers at TRI-STATE (high Z)TerminologyThe following explains the terminology used in this data sheet The terms negated and asserted are used Asserted refers to a‘‘true’’signal Thus ‘‘ECAS0asserted’’means the ECAS0input is at a logic0 The term‘‘COLINC assert-ed’’means the COLINC input is at a logic1 The term negat-ed refers to a‘‘false’’signal Thus ‘‘ECAS0negated’’means the ECAS0input is at a logic1 The term‘‘COLINC negated’’means the input COLINC is at a logic0 The table shown below clarifies this terminologySignal Action Logic LevelActive High Asserted HighActive High Negated LowActive Low Asserted LowActive Low Negated High3Connection DiagramsTL F 11109–2Top View FIGURE 2Order Number DP8420V-33See NS Package Number V68ATL F 11109–3Top View FIGURE 3Order Number DP8421V-33See NS Package Number V68ATL F 11109–4Top View FIGURE 4Order Number DP8422V-33or DP84T22-25See NS Package Number V84A42 0Signal DescriptionsPin Device(If Not InputDescriptionName Applicable to All)Output2 1ADDRESS R W AND PROGRAMMING SIGNALSR0–10DP8422V T22I ROW ADDRESS These inputs are used to specify the row address during an accessto the DRAM They are also used to program the chip when ML is asserted(exceptR0–9DP8420V 21V IR10)C0–10DP8422V T22I COLUMN ADDRESS These inputs are used to specify the column address during anaccess to the DRAM They are also used to program the chip when ML is assertedC0–9DP8420V 21V I(except C10)B0 B1I BANK SELECT Depending on programming these inputs are used to select a groupof RAS and CAS outputs to assert during an access They are also used to programthe chip when ML is assertedECAS0–3I ENABLE CAS These inputs are used to enable a single or group of CAS outputswhen asserted In combination with the B0 B1and the programming bits theseinputs select which CAS output or CAS outputs will assert during an access TheECAS signals can also be used to toggle a group of CAS outputs for page nibblemode accesses They also can be used for byte write operations If ECAS0isnegated during programming continuing to assert the ECAS0while negating AREQor AREQB during an access will cause the CAS outputs to be extended while theRAS outputs are negated(the ECASn inputs have no effect during scrubbingrefreshes)WIN I WRITE ENABLE IN This input is used to signify a write operation to the DRAM IfECAS0is asserted during programming the WE output will follow this input Thisinput asserted will also cause CAS to delay to the next positive clock edge if addressbit C9is asserted during programmingCOLINC I COLUMN INCREMENT When the address latches are used and RFIP is negatedthis input functions as COLINC Asserting this signal causes the column address to (EXTNDRF)Ibe incremented by one When RFIP is asserted this signal is used to extend therefresh cycle by any number of periods of CLK until it is negatedML I MODE LOAD This input signal when low enables the internal programming registerthat stores the programming information2 2DRAM CONTROL SIGNALSQ0–10DP8422V T22O DRAM ADDRESS These outputs are the multiplexed output of the R0–9 10andC0–9 10and form the DRAM address bus These outputs contain the refreshQ0–9DP8421V Oaddress whenever RFIP is asserted They contain high capacitive drivers with20XQ0–8DP8421V Oseries damping resistorsRAS0–3O ROW ADDRESS STROBES These outputs are asserted to latch the row addresscontained on the outputs Q0–8 9 10into the DRAM When RFIP is asserted theRAS outputs are used to latch the refresh row address contained on the Q0–8 9 10outputs in the DRAM These outputs contain high capacitive drivers with20X seriesdamping resistorsCAS0–3O COLUMN ADDRESS STROBES These outputs are asserted to latch the columnaddress contained on the outputs Q0–8 9 10into the DRAM These outputs havehigh capacitive drivers with20X series damping resistorsWE O WRITE ENABLE or REFRESH REQUEST This output asserted specifies a writeoperation to the DRAM When negated this output specifies a read operation to the (RFRQ)ODRAM When the controller is programmed in address pipelining mode or whenECAS0is negated during programming this output will function as RFRQ Whenasserted this pin specifies that13m s or15m s have passed If DISRFSH is negatedthe DP8420V 21V 22V DP84T22will perform an internal refresh as soon aspossible If DISRFRSH is asserted RFRQ can be used to externally request a refreshthrough the input RFSH This output has a high capacitive driver and a20X seriesdamping resistorOE DP84T22I OUTPUT ENABLE This input asserted enables the output buffers for the rowcolumn RASs CASs and WE If this input is disabled logic1 the output buffers are at (Only)TRI-STATE facilitating the board level circuit testing52 0Signal Descriptions(Continued)Pin Device(If Not InputDescriptionName Applicable to All)Output2 3REFRESH SIGNALSRFIP O REFRESH IN PROGRESS This output is asserted prior to a refresh cycle and isnegated when all the RAS outputs are negated for that refreshRFSH I REFRESH This input asserted with DISRFRSH already asserted will request arefresh If this input is continually asserted the DP8420V 21V 22V DP84T22willperform refresh cycles in a burst refresh fashion until the input is negated If RFSH isasserted with DISRFSH negated the internal refresh address counter is cleared(useful for burst refreshes)DISRFSH I DISABLE REFRESH This input is used to disable internal refreshes and must beasserted when using RFSH for externally requested refreshes2 4PORT A ACCESS SIGNALSADS I ADDRESS STROBE or ADDRESS LATCH ENABLE Depending on programmingthis input can function as ADS or ALE In mode0 the input functions as ALE and (ALE)Iwhen asserted along with CS causes an internal latch to be set Once this latch is setan access will start from the positive clock edge of CLK as soon as possible In Mode1 the input functions as ADS and when asserted along with CS causes the accessRAS to assert if no other event is taking place If an event is taking place RAS will beasserted from the positive edge of CLK as soon as possible In both cases the lowgoing edge of this signal latches the bank row and column address if programmed todo soCS I CHIP SELECT This input signal must be asserted to enable a Port A accessAREQ I ACCESS REQUEST This input signal in Mode0must be asserted some time afterthe first positive clock edge after ALE has been asserted When this signal isnegated RAS is negated for the access In Mode1 this signal must be assertedbefore ADS can be negated When this signal is negated RAS is negated for theaccessWAIT O WAIT or DTACK This output can be programmed to insert wait states into a CPUaccess cycle With R7negated during programming the output will function as a (DTACK)OWAIT type output In this case the output will be active low to signal a wait conditionWith R7asserted during programming the output will function as DTACK In thiscase the output will be negated to signify a wait condition and will be asserted tosignify the access has taken place Each of these signals can be delayed by anumber of positive clock edges or negative clock levels of CLK to increase themicroprocessor’s access cycle through the insertion of wait statesWAITIN I WAIT INCREASE This input can be used to dynamically increase the number ofpositive clock edges of CLK until DTACK will be asserted or WAIT will be negatedduring a DRAM access62 0Signal Descriptions(Continued)Pin Device(If Not InputDescriptionName Applicable to All)Output2 5PORT B ACCESS SIGNALSAREQB DP8422V T22I PORT B ACCESS REQUEST This input asserted will latch the row column and bankaddress if programmed and requests an access to take place for Port B If the onlyaccess can take place RAS will assert immediately If the access has to be delayedRAS will assert as soon as possible from a positive edge of CLKATACKB DP8422V T22O ADVANCED TRANSFER ACKNOWLEDGE PORT B This output is asserted whenthe access RAS is asserted for a Port B access This signal can be used to generate onlythe appropriate DTACK or WAIT type signal for Port B’s CPU or bus2 6COMMON DUAL PORT SIGNALSGRANTB DP8422V T22O GRANT B This output indicates which port is currently granted access to the DRAMarray When GRANTB is asserted Port B has access to the array When GRANTB is onlynegated Port A has access to the DRAM array This signal is used to multiplex thesignals R0–8 9 10 C0–8 9 10 B0–1 WIN LOCK and ECAS0–3to the DP8422Vwhen using dual accessingLOCK DP8422V T22I LOCK This input can be used by the currently granted port to‘‘lock out’’the otherport from the DRAM array by inserting wait states into the locked out port’s access onlycycle until LOCK is negated2 7POWER SIGNALS AND CAPACITOR INPUTV CC I POWER Supply VoltageGND I GROUND Supply Voltage ReferenceCAP I CAPACITOR This input is used by the internal PLL for stabilization The value of theceramic capacitor should be0 1m F and should be connected between this input andground2 8CLOCK INPUTSThere are two clock inputs to the DP8420V 21V 22V DP84T22CLK and DELCLK These two clocks may both be tied to the same clock input or they may be two separate clocks running at different frequencies asynchronous to each otherCLK I SYSTEM CLOCK This input may be in the range of0Hz up to33MHz(up to25MHzin the DP84T22V) This input is generally a constant frequency but it may becontrolled externally to change frequencies or perhaps be stopped for some arbitraryperiod of timeThis input provides the clock to the internal state machine that arbitrates betweenaccesses and refreshes This clock’s positive edges and negative levels are used toextend the WAIT(DTACK)signals This clock is also used as the reference for theRAS precharge time and RAS low time during refreshAll Port A and Port B accesses are assumed to be synchronous to the system clockCLKDELCLK I DELAY LINE CLOCK The clock input DELCLK may be in the range of6MHz to20MHz and should be a multiple of2(i e 6 8 10 12 14 16 18 20MHz)to havethe DP8420V 21V 22V DP84T22switching characteristics hold If DELCLK is notone of the above frequencies the accuracy of the internal delay line will suffer This isbecause the phase locked loop that generates the delay line assumes an input clockfrequency of a multiple of2MHzFor example if the DELCLK input is at7MHz and we choose a divide by3(programbits C0–2)this will produce2 333MHz which is16 667%off of2MHz Therefore theDP8420V 21V 22V DP84T22delay line would produce delays that are shorter(faster delays)than what is intended If divide by4was chosen the delay line wouldbe longer(slower delays)than intended(1 75MHz instead of2MHz) (See Section9for more information )This clock is also divided to create the internal refresh clock73 0Programming and ResettingDue to the variety in power supplies power-up times an EXTERNAL RESET must be performed before the DRAM controller can be programmed and usedAfter going through the reset procedure the DP8420V 21V 22V DP84T22can be programmed by either of two methods Mode Load Only Programming or Chip Select Ac-cess Programming After programming the DRC for the first time after reset the chip enters a 60ms initialization period during this period the controller performs refreshes every 13m s or 15m s this makes further DRAM warm up cycles unnecessary After this stage the chip can be repro-grammed as many times as the user wishes and the 60ms period will not be entered into unless the chip is reset and programmed againDuring the 60ms initialization period RFIP is asserted low and RAS toggles every 13m s or 15m s depending on the programming bit for refresh (C3) CAS will be inactive (logic 1)and the ‘‘Q’’outputs will count from 0to 2047refreshing the entire DRAM array The actual initialization time period is given by the following formula T e 4096 (Clock Divisor Select) (Refresh Clock Fine Tune) (DELCLK Frq )3 1EXTERNAL RESETAt power up if the internal power up reset worked all inter-nal latches and flip-flops are cleared and the part is ready to be programmed The power up state can also be achieved by performing an External Reset which is required to insure proper operation External Reset is achieved by asserting ML and DISRFSH for at least 16positive clock edges In order to perform simply a Reset the ML signal must be negated before DISRFSH is negated as shown in Figure 5a This procedure will only reset the controller which now is ready for programmingWhile performing an External Reset if the user negates DISRFSH at least one clock period before negating ML as shown in Figure 5b ML negated will program the DP8420V 21V 22V DP84T22with the values in R0–9 C0–9 B0–1and ECAS0 The 60ms initialization period will be entered since it is the first programming after reset This is a good way of resetting and programming the part at the same time Make sure the right programming bits are on the address bus before ML is negatedThe DRC may be programmed any time on the fly but the user must make sure that No Access or Refresh is in prog-ress Reset is asynchronousTL F 11109–5FIGURE 5a Chip Reset but Not ProgrammedTL F 11109–6FIGURE 5b Chip Reset and Programmed83 0Programming and Resetting (Continued)3 2PROGRAMMING METHODS 3 2 1Mode Load Only ProgrammingTo use this method the user asserts ML enabling the inter-nal programming register After ML is asserted a valid pro-gramming selection is placed on the address bus B0 B1and ECAS0inputs then ML is negated When ML is negat-ed the programming bits are latched into the internal pro-gramming register and the DP8420V 21V 22V DP84T22is programmed see Figure 6 When programming the chip the controller must not be refreshing RFIP must be high (1)to have a successful programming3 2 2Chip Selected Access ProgrammingThe chip can also be programmed by performing a chip selected access To program the chip using this method ML is asserted then CS is asserted and a valid program-ming selection is placed on the address bus When AREQ is asserted the programming bits affecting the wait logic be-come effective immediately then DTACK is asserted allow-ing the access to terminate After the access ML is negated and the rest of the programming bits take effectTL F 11109–7FIGURE 6 ML Only ProgrammingTL F 11109–8FIGURE 7 CS Access Programming93 0Programming and Resetting(Continued)3 3PROGRAMMING BIT DEFINITIONSSymbol DescriptionECAS0Extend CAS Refresh Request Select0The CASn outputs will be negated with the RASn outputs when AREQ(or AREQB DP8422V DP84T22only)is negated The WE output pin will function as write enable1The CASn outputs will be negated during an acccess(Port A(or Port B DP8422V DP84T22only))when their corresponding ECASn inputs are negated This feature allows the CAS outputs to be extended beyond the RASoutputs negating Scrubbing refreshes are NOT affected During scrubbing refreshes the CAS outputs will negatealong with the RAS outputs regardless of the state of the ECAS inputsThe WE output will function as ReFresh ReQuest(RFRQ)when this mode is programmedB1Access Mode Select0ACCESS MODE0 ALE pulsing high sets an internal latch On the next positive edge of CLK the access(RAS) will start AREQ will terminate the access1ACCESS MODE1 ADS asserted starts the access(RAS)immediately AREQ will terminate the accessB0Address Latch Mode0ADS or ALE asserted for Port A or AREQB asserted for Port B with the appropriate GRANT latch the input row column and bank address1The row column and bank latches are fall throughC9Delay CAS during WRITE Accesses0CAS is treated the same for both READ and WRITE accesses1During WRITE accesses CAS will be asserted by the event that occurs last CAS asserted by the internal delay line or CAS asserted on the positive edge of CLK after RAS is assertedC8Row Address Hold Time0Row Address Hold Time e25ns minimum1Row Address Hold Time e15ns minimumC7Column Address Setup Time0Column Address Setup Time e10ns miniumum1Column Address Setup Time e0ns minimumC6 C5 C4RAS and CAS Configuration Modes Error Scrubbing during Refresh0 0 0RAS0–3and CAS0–3are all selected during an access ECASn must be asserted for CASn to be assertedB0and B1are not used during an access Error scrubbing during refresh0 0 1RAS and CAS pairs are selected during an access by B1 ECASn must be asserted for CASn to be assertedB1e0during an access selects RAS0–1and CAS0–1B1e1during an access selects RAS2–3and CAS2–3B0is not used during an AccessError scrubbing during refresh0 1 0RAS and CAS singles are selected during an access by B0–1 ECASn must be asserted for CASn to be assertedB1e0 B0e0during an access selects RAS0and CAS0B1e0 B0e1during an access selects RAS1and CAS1B1e1 B0e0during an access selects RAS2and CAS2B1e1 B0e1during an access selects RAS3and CAS3Error scrubbing during refresh0 1 1RAS0–3and CAS0–3are all selected during an access ECASn must be asserted for CASn to be assertedB1 B0are not used during an accessNo error scrubbing (RAS only refreshing)1 0 0RAS pairs are selected by B1 CAS0–3are all selected ECASn must be asserted for CASn to be assertedB1e0during an access selects RAS0–1and CAS0–3B1e1during an access selects RAS2–3and CAS0–3B0is not used during an accessNo error scrubbing103 0Programming and Resetting(Continued)3 3PROGRAMMING BIT DEFINITIONS(Continued)Symbol DescriptionC6 C5 C4RAS and CAS Configuration Modes(Continued)1 0 1RAS and CAS pairs are selected by B1 ECASn must be asserted for CASn to be assertedB1e0during an access selects RAS0–1and CAS0–1B1e1during an access selects RAS2–3and CAS2–3B0is not used during an accessNo error scrubbing1 1 0RAS singles are selected by B0–1 CAS0–3are all selected ECASn must be asserted for CASn to beassertedB1e0 B0e0during an access selects RAS0and CAS0–3B1e0 B0e1during an access selects RAS1and CAS0–3B1e1 B0e0during an access selects RAS2and CAS0–3B1e1 B0e1during an access selects RAS3and CAS0–3No error scrubbing1 1 1RAS and CAS singles are selected by B0 1 ECASn must be asserted for CASn to be assertedB1e0 B0e0during an access selects RAS0and CAS0B1e0 B0e1during an access selects RAS1and CAS1B1e1 B0e0during an access selects RAS2and CAS2B1e1 B0e1during an access selects RAS3and CAS3No error scrubbingC3Refresh Clock Fine Tune Divisor0Divide delay line refresh clock further by30(If DELCLK Refresh Clock Clock Divisor e2MHz e15m s refresh period)1Divide delay line refresh clock further by26(If DELCLK Refresh Clock Clock Divisor e2MHz e13m s refresh period)C2 C1 C0Delay Line Refresh Clock Divisor Select0 0 0Divide DELCLK by10to get as close to2MHz as possible0 0 1Divide DELCLK by9to get as close to2MHz as possible0 1 0Divide DELCLK by8to get as close to2MHz as possible0 1 1Divide DELCLK by7to get as close to2MHz as possible1 0 0Divide DELCLK by6to get as close to2MHz as possible1 0 1Divide DELCLK by5to get as close to2MHz as possible1 1 0Divide DELCLK by4to get as close to2MHz as possible1 1 1Divide DELCLK by3to get as close to2MHz as possibleR9Refresh Mode Select0RAS0–3will all assert and negate at the same time during a refresh1Staggered Refresh RAS outputs during refresh are separated by one positive clock edge Depending on the configuration mode chosen either one or two RASs will be assertedR8Address Pipelining Select0Address pipelining is selected The DRAM controller will switch the DRAM column address back to the row address after guaranteeing the column address hold time1Non-address pipelining is selected The DRAM controller will hold the column address on the DRAM address bus until the access RASs are negatedR7WAIT or DTACK Select0WAIT type output is selected1DTACK(Data Transfer ACKnowledge)type output is selectedR6Add Wait States to the Current Access if WAITIN is Low0WAIT or DTACK will be delayed by one additional positive edge of CLK1WAIT or DTACK will be delayed by two additional positive edges of CLK11。