基于单片机的指纹识别英文资料和中文翻译

英文资料及中文翻译
A hybrid ASIC and FPGA Architecture
FPGA is English Field Programmable Gate Array abbreviation, namely the scene programmable gate array, it is the product which in PAL, GAL, EPLD and so on in the programmable component foundation further develops. It is took in the special-purpose integrated circuit (ASIC) domain one kind partly has custom-made, both solves has had custom-made the electric circuit which the electric circuit appears the insufficiency, and has overcome the original programmable component gate number limited shortcoming.
FPGA used logical unit array LCA (Logic Cell Array) this kind of new concept, the interior including has been possible to dispose logical module CLB (Configurable Logic Block), output load module IOB (Input Output Block) and internal segment (Interconnect) three parts. The FPGA essential feature mainly has:
1)Uses FPGA to design the ASIC electric circuit, the user does not need to throw the piece production, can obtain the chip which comes in handy. - - 2) FPGA may make other all to have custom-made or partly to have custom-made the ASIC electric circuit the experimental preview.
2)The FPGA interior has the rich trigger and the I/O pin.
3)FPGA is in the ASIC electric circuit designs the cycle to be shortest, the development cost is lowest, one of risk smallest components.
4)FPGA is in the ASIC electric circuit designs the cycle to be shortest, the development cost is lowest, one of risk smallest components.
5)FPGA uses the high speed CHMOS craft, the power loss is low, may and CMOS, the TTL level is compatible.
It can be said that, the FPGA chip is the small batch system enhances the system integration rate, one of reliable best choices. FPGA is by deposits the procedure establishes its active status in internal RAM, therefore, time work needs to carry on the programming to internal RAM .The user may act according to the different disposition pattern, selects the different programming method.
When adds the electricity, the FPGA chip the data read-in internal programs EPROM in RAM, after the disposition completes, FPGA thrust build-up .After falls the electricity, FPGA restores the unsoldered glass, internal logic relations vanishing, therefore, FPGA can use repeatedly. The FPGA programming does not need the special-purpose FPGA programmer, only must use general EPROM, the PROM programmer then. When needs to revise the FPGA function, only must trade piece of EPROM then. Thus, identical piece FPGA, the different programming data, may have the different electric circuit function. Therefore the FPGA use is extremely flexible. FPGA has many kinds of disposition pattern: Parallel principal-mode -like is piece of FPGA adds piece of EPROM the way; The host may support piece of PROM from the pattern to program multi-piece FPGA; The serial pattern may use serial PROM to program FPGA; The peripheral pattern may FPGA take the microprocessor the peripheral, programs by the microprocessor to it.
In the electrical observation and control system, needs to gather each kind of simulation quantity signal, the digital quantity signal frequently, and carries on corresponding processing to them. In the ordinary circumstances, in the observation and control system with ordinary MCU (for example 51, 196 and so on monolithic integrated circuits or control DSP) is may complete the system task.。

But when in the system must gather the signal quantity are specially many when (is specially each kind of signal quantity, condition quantity), depends on merely with the ordinary MCU resources on often with difficulty completes the task。

This time, generally only can adopt the multi-MCU in-line processing pattern, or depends on other chip expansion system resources to complete the system the monitor duty. Not only did this increased the massive exterior electric circuits and the system cost, moreover increased the system complexity greatly, thus the system reliability could receive certain influence, this was not obviously the designer is willing to see. One kind based on the FPGA technology simulation quantity, digital quantity gathering and the processing system, uses FPGA the I/O port to be many, also may program the control freely, define its function the characteristic, matches by VHDL the compilation FPGA interior execution software, can solve gathering signal way many problems well。

Because compiles
with VHDL the execution software interior to each group of digital quantity is according to the parallel processing, moreover the FPGA hardware speed is the ns level, this is a speed which current any MCU all with difficulty achieved, therefore this system compared to other systems can real-time, monitor the signal quantity fast the change。

Therefore in the condition quantity specially many monitor system, this system will be able to display own superiority.
The practice proved that, Designs the DDS electric circuit with FPGA to use the special-purpose DDS chip to be more nimble. Because, so long as changes in FPGA the ROM data, DDS may have the random profile, thus has the quite big flexibility。

Comparatively: The FPGA function is decided completely by the design demand, may complex also be possible to be simple, moreover the FPGA chip also supports in the system scene promotes, although has the insufficiency slightly in the precision and the speed, but also can satisfy the overwhelming majority system basically the operation requirements. Moreover, inserts the DDS design in the system which constitutes to the FPGA chip, its system cost cannot increase how many, but purchases the special-purpose chip the price is the former very many times. Therefore uses FPGA to design the DDS system to have the very high performance-to-price ratio.
1 Applications Emerge for Hybrid Devices
Implementation using an ASIC approach typically yields a faster, smaller, and lower power design than implementation in FPGA technology. The growing requirements in the marketplace for design flexibility however, are driving the need for hybrid ASIC/FPGA devices. The potential to change hardware configuration in real time, to support multiple design options with a single mask set, and to prolong a product’s usable life, all compel designers to look for a blending of high density ASIC circuits along with the inherent FPGA circuit flexibility.
The ability to create a “base design” and then reuse the base with minimal changes for subsequent devices helps reduce design time and encourages standardization. Since many consumer and office products are offered with a range of low to high-end options, this base design concept can be effectively used---with features added to each successive model. Printers, fax machines, PC’ s and digital imaging equipment are example where this concept can be useful
DSP applications are also well suited to FPGA fast multiply and accumulate (MAC) processing capability. When building a DSP system, the design can take advantage of parallel structures and arithmetic algorithms to minimize resources and exceed performance of single or multiple purpose DSP devices. DSP designers using both ASIC and FOGA within the same design can optimize a system for performance beyond the capabilities of either separate circuit technology.
Other applications that lend themselves to the hybrid ASIC/FPGA approach are designs that support multiple standards such as USB, Fire Wire and Camera LINK, in a single device. Similarly, designs that are finalized, with the exception of any undefined features or emerging standard, are excellent candidates for this technology. Without the benefit of programmable logic, the designer must decide between taping-out the chip knowing that the PCI logic has a high probability for change, or waiting until the design requirements are firm-potentially impacting the end product’s schedule. With both programmable logic and ASIC working together on a single device, some situation like these can be accommodated. Other similar issues like differing geographic or I/O standards could also be incorporated within the FPGA cores, without requiring mask and fabrication updates for each change.
10.2 Economics Play a Role in Using Hybrid Devices
While technical applications are emerging for the hybrid architecture, it is unlikely that design teams would utilize this new capability unless it is also economically viable. We will now explore the economics behind this new architecture.
To realize the performance and density advantages of an ASIC ,design teams must accept higher NRE and longer TAT than a FPGA. Unlike off-the-shift FPGA, each ASIC design requires a custom set of masks for silicon fabrication. The custom mask set allows circuitility and interconnections to be tailored to the requirements of each unique application---yielding high performance and density .However, the cost of the mask sets is rapidly increasing(nearly doubling with each successive technology node).as a result, mask costs are becoming as significant portion of the per-die cost in many cases.
For example, consider the case wher e’re mask set costs $1,000,000.For applications where only 1,000 chip are required, each chip will over $1000,
since the mask cost (plus many other expenses) must be amortized over the volume of chip sold. As the volume for this same ASIC rise, effective cost of each die decrease..
Conversely, FPGA are standard products, where the mask charges for small number of design passes are amortized over a large number of customers and chips, so the mask cost per chip sold is minimal. As a result, for each technology node there is a volume threshold, below which it’more cost-effective to buy an FPGA chip vs. a smaller ASIC chip. TAT is another primary economic driver, having a direct impact on time-to-market for many applications. The time required for ASIC layout and fabrication is typically in the range 2-5months---much longer than FPGA, which generally require 1-4weeks once a customer’s RTL is firm.
These NRE and TAT issues are compounded by customers’needs for multiple design passes. Since each ASIC design requires a unique mask set, if a custom discover logic error or need to add features after tape out, they must initiate another ASIC design pass, requiring additional NRE charges and silicon fabrication time. As silicon technologies progress and chip become more complex, design verification becomes increasingly difficult, and the chance for logic errors grows. In many cases, time to market pressures drive design teams to continue verification well into layout and sometimes beyond chip tape out. This increases the risk that logic updates will be required, and therefore cost per chip will increase.
In summary, ASIC to date have offered higher performance in smaller chip sizes than FPGA. However, the NRE for current technology nodes has rendered them very expensive for applications that require low quantities of chips---particularly when multiple design passes are required.
10.3 T he Hybrid ASIC/FPGA Solution
Enter the hybrid ASIC/FPGA. Like an ASIC, the initial mask set must be purchased. But with the incorporation of FPGA cores into the ASIC, it is now possible to use the programmable circuitry to enable a single physical chip designs to satisfy several different applications .This has the potential to eliminate multiple design and in some cases, avoid costly repines. In the case where a customer requires similar ASIC for a family of products, FPGA circuitry can be added to the base ASIC logic and configured as needed to satisfy the
multiple applications. Similarly, logic updates required to correct bugs discovered late in the verification process, or to accommodate changing market needs, can be handled with appropriately placed FPGA cores.
The question must be asked: why embed FPGA into an ASIC if a two chips solution could achieve the same results? The answer is both technical and economic. Technically, for a certain class of applications, the embedded solution offers greater performance with lower power dissipation. By embedding the FPGA into the ASIC, signals that must propagate from the ASIC through the FPGA, then back to the ASIC can avoid four chip boundary delays, two card crossings, and the associated power dissipation. By keeping the ASIC to FPGA interconnections on the die, valuable ASIC I/O pins are also conserved.
Economically, the embedded solution can be the less expensive option. As we will discuss, the FPGA fabric does not require any unique semiconductor processing above and beyond the base ASIC (unlike embedded flash or embedded DRAM). The resulting increase in ASIC cost is associated with the area occupied by the embedded FPGA core. In addition, the cost of assembly, test and packaging of a secong chip are eliminated.
In certain cases, it can be advantageous to include embedded FPGA on an ASIC if that FPGA eliminates the need for additional design passes. For example, at volumes of up to 250000 pieces, 50K gates of embedded FPGA are cost effectives. Similarly, 10K gates of embedded FPGA are cost effective versus a 2 pass ASIC design at volume of up to 1M. In general, if mask costs rise, volumes decrease, or more design passes are avoided, then the embedded FPGA approach becomes progressively more cost-effective compared to the ASIC approach. This is because at low volumes, the mask costs (and NRE) for additional design passes becomes a significant adder to per-chip cost, and this can outweigh the cost impact of the larger die area required by the embedded FPGA circuitry. This analysis leads us to conclude that technology and market trends have created a need for the development of the hybrid ASIC/FPGA product. Mask costs for advanced technologies are growing –marking multiple design passes too costly for many applications. Fortunately, the technology advancements that have driven this trend have also opened up the potential to embed significant amounts of FPGA gates onto an ASIC die –enough to handle some of the design updates that would otherwise require additional
design passes.
10．4 Hybrid Offering Overview
The IBM/Xilinx hybrid will first be available in IBM’s Cu-08 90nm ASIC offering, and will consist of three FPGA block sizes. Multiple blocks used can be mixed and matched.
Physically, the FPGA cores are being ported to the same semiconductor process that the ASIC product uses. The issues encountered in doing this porting are similar to those of other 3rd party IP ports. One of the largest challenges is full chip physical verification. Common design rules and transistor design points are critical in blending of IP between suppliers. Minor difference in design rules can be accommodated, assuming that checking decks and other verification software are able to handle the mixture of design rules. Designing these tools for increased flexibility will likely be needed as more companies share IP.
To ensure that the FPGA can be integrated with the rest of the ASIC power, agreement must be reached on metal stack options. In the case of the Cu-08 hybrid offering,5 level of metal were allocated to the FPGA blocks. This requires a re-layout of the FPGA cores, which were originally designed for a standard product with 9 levels of metal.
As part of the re-layout, the power distribution of the FPGA blocks will be designed to integrate easily into the ASIC power distribution methodology. Care needs to be taken to ensure the power density required by the FPGA blocks are within the capability of the ASIC power supply routing. Due to extensive use of pass-gate structures, the FPGA blocks require standard 1.2V levels, while the bulk of the chip operates at lower levels.
The embedded FPGA blocks consist of programmable logic blocks, configuration logic, test interface logic, and simplified IO buffers for use in driving and receiving on-chip nets. Multiple end user configuration mode are supported including FPGA, serial and parallel modes. Individual cores can be configured asynchronously, allowing for “on-the-fly” reconfiguration.
To design the new hybrid chips, a modified design methodology is being developed as shown in Figure 10.1. This hybrid design flow incorporates two proven design methodologies, the IBM ASIC flow and the XILINX FPGA flow, including several third party vendor synthesis options. The ASIC methodology
integrates the embedded FPGA as a hard core with appropriate ASIC label models. The FPGA flow, including timing closure of the FPGA configuration, is done using XILINX tools, the designer has the choice of using constraints or detailed timing from the Xilinx tool flow to close the ASIC timing at the FPGA cote interfaces. If an FPGA configuration is known prior to the design of the ASIC, actual timing information can be passed to the ASIC tools from the FPGA tools. If the logic content of the embedded FPGA is unknown, the ASIC design can be completed using timing assertions and the embedded FPGA design can be completed later. If the embedded FPGA design is being reconfigured after the ASIC is in manufacturing, the final timing constraints from the completed ASIC can be passed to the FPGA tools for the new FPGA design.
The logic design of the chip must be partitioned prior to final synthesis. The logic destined for an FPGA block is processed independently of the logic design for ASIC logic .When multiple FPGA logic are used ,each must be designed and optimized independently.
The logical design of the chip must be partitioned prior to final synthesis. The logic destined for an FPGA block is processed independently of the logic destined for ASIC logic. When multiple FPGA logic blocks are used, each must be designed and optimized independently.
The ASIC physical design process treats the FPGA macro similarly to other large place able objects, except for port assignment. During the initial ASIC design, the port assignment of each embedded FPGA block can be modified to accommodate floor planning or timing requirements. Once the final ASIC design is tape-out ,the port assignments are fixed of subsequent FPGA configurations.
The IBM ASIC methodology has been described in references, and the Xilinx FPGA methodology is described in reference. As to be expected, most of the issues in cresting the hybrid methodology occur at the boundary between the two methodologies. The mechanics of the communications between the two stems can be accomplished by creating data translators, however, optimization between the two systems can be difficult, due to the significant architectural differences between traditional ASIC flows and traditional FPGA flows.
ASIC和FPGA的混合系统
FPGA是英文Field Programmable Gate Array的缩写，即现场可编程门阵列，它是在PAL、GAL、EPLD等可编程器件的基础上进一步发展的产物。

它是作为专用集成电路（ASIC）领域中的一种半定制电路而出现的，既解决了定制电路的不足，又克服了原有可编程器件门电路数有限的缺点。

FPGA采用了逻辑单元阵列LCA （Logic Cell Array）这样一个新概念，我们知道它的内部包括可配置逻辑模块CLB （Configurable Logic Block）、输出输入模块IOB（Input Output Block）和内部连线（Interconnect）三个部分。

FPGA的基本特点主要有：
1.采用FPGA设计ASIC电路，用户不需要投片生产，就能得到合用的芯片
2.FPGA。

可做其它全定制或半定制ASIC电路的中试样片
3.FPGA内部有丰富的触发器和I／O引脚。

4.FPGA是ASIC电路中设计周期最短、开发费用最低、风险最小的器件之一。

5.FPGA采用高速CHMOS工艺，功耗低，可以与CMOS、TTL电平兼容。

FPGA是由存放在片内RAM中的程序来设置其工作状态的，因此，工作时需要对片内的RAM进行编程。

用户可以根据不同的配置模式，采用不同的编程方式。

加电时，FPGA芯片将EPROM中数据读入片内编程RAM中，配置完成后，FPGA进入工作状态。

掉电后，FPGA恢复成白片，内部逻辑关系消失，因此，FPGA能够反复使用。

FPGA的编程无须专用的FPGA编程器，只须用通用的EPROM、PROM编程器即可。

当需要修改FPGA功能时，只需换一片EPROM即可。

这样，同一片FPGA，不同的编程数据，可以产生不同的电路功能。

因此，FPGA的使用非常灵活。

FPGA有多种配置模式：并行主模式为一片FPGA加一片EPROM的方式；主从模式可以支持一片PROM编程多片FPGA；串行模式可以采用串行PROM编程FPGA；外设模式可以将FPGA作为微处理器的外设，由微处理器对其编程。

实践证明：用FPGA设计DDS电路较采用专用DDS芯片更为灵活。

因为，只要改变FPGA中的ROM数据，DDS就可以产生任意波形，因而具有相当大的灵活性。

相比之下：FPGA的功能完全取决于设计需求，可以复杂也可以简单，而且FPGA芯片还支持在系统现场升级，虽然在精度和速度上略有不足，但也能基本满足绝大多数系统的使用要求。

另外，将DDS设计嵌入到FPGA芯片所构成的系统中，其系统成本并不会增加多少，而购买专用芯片的价格则是前者的很多倍。

因此，采用FPGA来设计DDS 系统具有很高的性价比。

1．混合设计应用的出现
通常专用集成电路ASIC（Application Specific Integrated Circuit）方法设计的电路在速度、尺寸及功能等方面优于用现场可编程门阵列FPGA(Field Programmable Gate Array)方法设计的电路。

随着市场上对设计灵活性的要求日渐增强，ASIC和FPGA混合系统变得十分必要。

电路实现要求具有如下能力：可实时更改硬件配置，能支持单套掩膜下的多种设计方案，并能延长产品使用寿命，所有这些促使设计人员寻找一种可以将具有集成度特性的ASIC电路与具有良好适应性的FPGA 电路结合起来的混合系统。

设计人员可以设计一个基本的方案，并在后续的设计中再利用该方案，而使改动最小，这种设计思想能够缩短设计时间、提高标准化程度。

由于消费类和办公类产品从低端到高端覆盖范围很广，可以有效地运用这种基础设计方法——每个系列的产品都可以加上不同的特性。

打印机、传真机、计算机和数字成像装置都是利用这种设计思想的实例。

由于FPGA处理乘法与加法的速度很快，它也适合于DSP应用的设计。

在构建DSP 系统时，可采用并行结构和运算算法来减少资源的使用，且其性能优于单用途或多用途DSP芯片的性能。

同时采用ASIC和FPGA优化系统性能的DSP设计人员将获得比单独使用两者中任何一种器件更好的性能。

ASIC/FPGA混合系统适用于其他支持多种标准的设计，比如在单个芯片上设计支持USB接口、1394接口和相机接口的器件。

与此类似，除没有定义的特性或新标准外，其他都已成形，这种设计特别适合用ASIC/FPGA混合方法实现。

如果不使用可编程逻辑，设计者必须在下列两种方法之间做出抉择：一是在明知PCI逻辑单元很可能会发生改变的情况下进行芯片流片；二是待到设计要求非常稳定时再行流片——这样很可能会影响最终产品的进度。

如果同一个器件上既有可编程逻辑模块又有ASIC芯片，上述情形就可以避免。

其他类似的问题，比如说不同尺寸或是输入/输出方面的要求都可以在FPGA设计部分予以解决，而不是一有改动就要改变掩膜或制版。

在电气测控系统中，常常需要采集各种模拟量信号、数字量信号，并对它们进行相应的处理。

一般情况下，测控系统中用普通MCU（如51、96等单片机或控制型DSP）是可以完成系统任务的。

但当系统中要采集的信号量特别多时（特别是各种信号量、状态量），仅仅靠用普通MCU的资源就往往难以完成任务。

此时，一般只能采取多MCU联机处理模式，或者靠其它芯片扩展系统资源来完成系统的监测任务。

这样做不仅增加了大量的外部电路和系统成本，而且大大增加了系统的复杂性，因而系统的可靠性就会受一定影响，这显然不是设计者所愿意看到的。

本文所提出的一种基于FPGA 技术的模拟量、数字量采集与处理系统，利用FPGA的I/O端口多，且可以自由编程支配、定义其功能的特点，配以VHDL编写的FPGA内部执行软件，能很好地解决采集
的信号路数多的问题。

因为用VHDL编写的执行软件内部对各组数字量是按并行处理的，而且FPGA硬件的速度是ns级的，这是当前任何MCU都难以达到的速度，因此本系统比其它系统更能实时地快速地监测信号量的变化
2．经济因素影响混合系统的使用
尽管从技术上可以将ASIC与FPGA相结合形成混合系统，但除非它在经济上合算，否则也不可能获得设计人员的青睐。

现在我们就来研究这个混合系统背后的经济因素。

要利用ASIC的性能与密度优势，设计人员必须接收比FPGA设计更高的NRE（非经常性工程成本）和更长的TAT（周转时间）。

与现成的FPGA不同，每个ASIC设计都需要定制的用于硅晶制版的掩膜。

自定义的掩膜能使得线路和内部连接，以使其更适于特定应用的需要，应而具有性能好、密度高的优点。

然而，掩膜的成本随节点数的增加从而增长很快（几乎每增加一个节点就翻倍），因此，多数情况下掩膜成本占芯片成本的很大一部分。

举例来说，假设一组掩膜的花费为1百万美元，对于只需用1000片这种芯片的应用系统而言，单个芯片的成本远远超过1000美元，因为掩膜的成本（包括许多其他的费用）必须由所售芯片分摊，所以只有该类ASIC芯片的需求量越大，单个芯片的成本才会下降。

相反，FPGA是标准化产品，对于少量的设计过程，它的掩膜费用由大量的用户和芯片分摊，所以所售出的单个芯片上的掩膜费用很小。

结果，对于每个技术节点都有一个用量门限，低于这个数值时采用FPGA芯片比用更小的ASIC芯片更为划算。

周转时间TAT是另一主要的价格因素，直接影响到许多设计的面市时间。

通常ASIC设计从布线到最终形成产品大概需要2-5个月，而如果采用FPGA，一旦顾客的RTL（寄存器传输级）描述方式确定下来，通常1-4周就能完成。

有时，客户需要采用多种设计流程，这使得有关NRE和TAT方面的问题更为复杂。

由于每个ASIC设计都需要一套不同的掩膜，所以如果客户发现完成的设计存在逻辑错误或是想再增加一些功能的话，那就必须从头开始另外一次ASIC设计过程，这需要额外的NRE和硅晶制版时间。

随着硅制作技术的不断提高及芯片设计日趋复杂，设计校验往往变得更为困难，出现逻辑错误的可能性也大大增加。

多数情况下，设计人员迫于产品上市时间的压力会在布线时进行设计校验，有时会超出芯片流片的范围，这样就很有可能要对芯片进行逻辑更新，使单片芯片的成本增加。

总而言之，与FPGA设计相比，如今的ASIC设计能使芯片具有更好的性能和更小的体积。

但是，过高的NER使得对非大批量生产，尤其对要求进行多种设计流程的产品而言，价格非常昂贵。

3．混合ASIC/FPGA解决方案
说到混合ASIC/FPGA系统，与ASIC系统一样，必须购买原始掩膜。

但是当将FPGA 芯片与ASIC想结合时，就可使用可编程电路使单片芯片同时满足多种应用。

这就有可能放弃原来的多重设计，某些情况下避免了费用高昂的重新设计。

如果客户要求用相似的ASIC芯片来制造同一系列产品，就可以将FPGA线路与基础ASIC逻辑单元想结合，并根据需要进行配置以满足多种应用要求。

类似地，在后续校验过程中用于纠正错误或者是为适应市场变化所需要的逻辑更新，均可以采取适当的嵌入FPGA内核的办法加以解决。

问题是如果使用FPGA和ASIC两片芯片能达到同样的结果，为什么还要把FPGA嵌入ASIC呢？答案还得从技术和经济两方面因素说起。

从技术层面来看，对于某些特定的应用，嵌入法能以更低的功耗获得更高的系统性能。

在ASIC芯片中嵌入FPGA，信号必须从ASIC传到FPGA，然后再返回ASIC，这样就避免了四次芯片边界延迟，两次卡交叉，以及由此引起的功耗。

由于采用了ASIC和FPGA的片上连接，节省了ASIC输入/输出端口。

从经济层面来看，嵌入法应该是更为廉价的选择。

正如我们即将讨论的那样，FPGA 结构并不需要在基础ASIC（与嵌入式快闪存储器和嵌入式DRAM）之上或者之外添加任何半导体处理流程。

ASIC成本的增加与嵌入式FPGA内核所占据的面积有关，但是却节省了第二个芯片的组装、测试和封装费用。

在某些情况下，如果在ASIC上嵌入FPGA并不需要重新设计系统，采用混合结构会非常有利。

例如，如果芯片的用量高达250000片，5万个门的嵌入式FPGA具有较高的性价比。

类似地，如果芯片的用量高达100000片，1万个门的嵌入式FPGA比双通路ASIC设计流程，那么相比ASIC方法，采用嵌入FPGA方案就更为划算。

这是因为需求量小时，附加设计过程所需的掩膜费用（和NRE）占有单位芯片成本较大的比例，该附加成本比采用嵌入式FPGA电路所需要的较大面积的母片所产生的额外费用要多。

由以上分析可知技术与市场趋势两方面的要求是混合型ASIC/FPGA系统得以发展的主要原因。

随着科技的发展，掩膜成本越来越高，这使得在许多应用中多重设计流程成本过于高昂。

尽管如此，让我们倍感幸运的是，技术的发展同时使得将大量的FPGA逻辑门嵌入ASIC电路成为可能，足以解决某些设计更新问题；否则，就需要采用额外的设计流程。

4．混合系统产品总览
IBM的Cu-08（90nm）ASIC产品是IBM/Xilinx最早的混合产品（集成Xilinx公司的FPGA技术）。

它由具有不同尺寸的三种FPGA模块组成。

在同一芯片上可以嵌入多个模块，各个模块的尺寸可以相互混合和匹配。

具体来说，要将FPGA内核移植到与ASIC产品所采用的半导体加工相同的半导体加工工艺上。

移植过程中所遇到的问题与那些第三方IP移植的情形相类似。

最大难点之一就是芯片的全面物理验证。

通用的设计规则和晶体管设计要点多不同厂商间的
IP兼容性要求相当严格。

如果检测平台和验证软件能够处理不同的设计规则，那么微小的差异是可以接受的。

随着越来越多的厂商共享IP，很可能需要设计这类具有较大灵活性的工具软件。

为了确保FPGA的嵌入能与ASIC的其余部分相兼容。

必须在金属层数的选择上相一致。

例如Cu-08混合系统，FPGA模块中配置了5层金属层，这就需要对FPGA内核重新布线，它原来是为拥有9层金属层的标准产品而设计的。

作为重新布线工作的一部分，设计FPGA模块的功率分配时应使其能与ASIC模块的功率分配方案融为一体。

注意要确保FPGA模块需要的功率密度在ASIC模块所供应的范围之内。

由于广泛采用传输门结构，FPGA模块要求用1 .2V标准电压下，而系统中其他的部分则工作在更低的电源电压。

嵌入式FPGA模块由可编程逻辑块、配置逻辑、测试接口逻辑和与芯片内网络控制相关的简化I/O缓冲构成，同时支持多种终端用户配置模式，包括JTAG调试端口、串行和并行模式。

每个FPGA内核可在不同时间配置，所以可以对所以FPGA内核即时重配置。

为设计新型混合芯片，人们正研制一种改进的设计方法，见表10.1，其设计流程包含两种成熟的设计方法：IBM的ASIC设计流程和XILINX和FPGA流程，还包括几个第三方销售商的合成工具。

采用ASIC技术可将嵌入式FPGA与ASIC某层模型融合成一体。

利用XILINX工具，可设计FPGA流，包括设计FPGA的时序收敛。

设计者选择使用约束条件或者是从XILINX工具流中详细的时序方法使FPGA内核接口处的ASIC系统时序收敛。

如果先于ASIC设计就已知FPGA的配置，那么实际的时序信息就可以从FPGA工具传至ASIC工具。

如果嵌入式FPGA的配置未知，那么可利用时序信息完成ASIC设计，进而完成嵌入式FPGA设计。

如果在ASIC模块制作过程中突然要改变嵌入式FPGA的设计方案，那么最终的时序信息将由先完成的ASIC模块传递给FPGA工具，使新的FPGA模块设计满足时序闭合要求。

芯片的逻辑设计必须先分割再进行最后的合成。

用做FPGA的逻辑设计必须与用做ASIC的逻辑设计分开处理。

当采用多个FPGA模块时，各个模块的设计与优化都必须独立完成。

ASIC设计流程中处理FPGA模块与处理其他大的可配置模块相似，只是在端口分配上有所不同。

在ASIC设计的初始阶段，各个嵌入式FPGA模块的端口分配可以调整以满足布局规划或时序要求。

一旦ASIC的最终设计完成，那么接下来FPGA 模块配置时的端口分配就固定下来。

IBM的ASIC设计方案和XILINX的FPGA设计方法都已经有相关的书目可以参考。

正如所预料的那样，混合系统设计方法的大部分问题都体现在这两种方法的结合处。

两种系统之间的通信机制可以通过创建数据转换器来完成，然而，由于传统的ASIC 和FPGA设计流程存在明显的结构性差异，怎样在两个系统之间达到最优确是个难题。