FPGA可编程逻辑器件芯片EP4SE230F35C4中文规格书
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TriMatrix Memory
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block contains 576 RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes:
2.562 2.558 -0.083 -0.087
-4 Speed Grade
2.940 2.936 -0.107 -0.111
-5 Speed Grade
Unit
3.899
ns
3.575
ns
0.355
ns
0.031
ns
-5 Speed Grade
Unit
3.453
ns
3.448
ns
-0.128
ns
When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents.
M512 RAM blocks can have different clocks on its inputs and outputs. The wren, datain, and write address registers are all clocked together from one of the two clocks feeding the block. The read address, rden, and output registers can be clocked by either of the two clocks driving the block. This allows the RAM block to operate in read/write or input/output clock modes. Only the output register can be bypassed. The six labclk signals or local interconnect can drive the inclock, outclock, wren, rden, and outclr signals. Because of the advanced interconnect between the LAB and M512 RAM blocks, ALMs can also control the wren and rden signals and the RAM clock, clock enable, and asynchronous clear signals. Figure 2–19 shows the M512 RAM block control signal generation logic.
Parameter
tC I N tC O U T tP L L C I N tP L L C O U T
Minimum Timing
Industrial Commercial
1.439 1.444 -0.161 -0.156
1.508 1.513 -0.174 -0.169
-3 Speed Grade
1.532 1.537 -0.167 -0.162
-3 Speed Grade
2.591 2.587 -0.079 -0.083
-4 Speed Grade
2.972 2.968 -0.099 -0.103
Table 5–55. EP2S60 Row Pins Global Clock Timing Parameters
-0.133
ns
-5 Speed Grade
Unit
3.421
ns
3.416
ns
-0.126
ns
-0.131
ns
Stratix II Device Handbook, Volume 1
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–53. EP2S60 Column Pins Global Clock Timing Parameters
Parameter
tC I N tC O U T tP L L C I N tP L L C O U T
Part Number (16 Bits)
Manufacturer Identity (11 Bits)
LSB (1 Bit) (2)
0010 0000 1001 0001
000 0110 1110
1
0010 0000 1001 0010
000 0110 1110
1
0010 0000 1001 0011
Table 3–3. 32-Bit Stratix II Device IDCODE
Device
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
Version (4 Bits) 0000 0000 0001 0000 0000 0000
IDCODE (32 Bits) (1)
The RAM blocks in Stratix II devices have local interconnects to allow ALMs and interconnects to drive into RAM blocks. The M512 RAM block local interconnect is driven by the R4, C4, and direct link interconnects from adjacent LABs. The M512 RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects. The M512 RAM block has up to 16 direct link input connections from the left adjacent LABs and another 16 from the right adjacent LAB. M512 RAM outputs can also connect to left and right LABs through direct link interconnect. The M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. Figure 2–20 shows the M512 RAM block to logic array interface.
Stratix II Device Handbook, Volume 1
Configuration & Testing
The Quartus II software has an Auto Usercode feature where you can choose to use the checksum value of a programming file as the JTAG user code. If selected, the checksum is automatically loaded to the USERCODE register. Turn on the Auto Usercode option by clicking Device & Pin Options, then General, in the Settings dialog box (Assignments menu).
Minimum Timing
Industrial Commercial
1.658 1.501 0.06 -0.097
1.739 1.574 0.057 -0.108
-3 Speed Grade
2.920 2.678 0.278 0.036
-4 Speed Grade
3.350 3.072 0.304 0.026
1 Stratix, Stratix II, Cyclone, and Cyclone II devices must be within the first 17 devices in a JTAG chain. All of these devices have the same JTAG controller. If any of the Stratix, Stratix II, Cyclone, and Cyclone II devices are in the 18th or after they fail configuration. This does not affect SignalTap II.
Table 5–54. EP2S60 Row Pins Regional Clock Timing Parameters
Parameter
tC I N tC O U T tP L L C I N tP L L C O U T
Minimum Timing
Industrial Commercial
1.463 1.468 -0.153 -0.148
Table 3–2. Stratix II Boundary-Scan Register Length
Device
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
Boundary-Scan Register Length
1,140 1,692 2,196 2,748 3,420 3,948
■ Simple dual-port RAM ■ Single-port RAM ■ FIFO ■ ROM ■ Shift register
1 Violating the setup or hold time on the memory block address registers could corrupt memory contents. This applies to both read and write operations.
000 0110 1110
1
0010 0000 1001 0100
000 011Βιβλιοθήκη 111010010 0000 1001 0101
000 0110 1110
1
0010 0000 1001 0110
000 0110 1110
1
Notes to Table 3–3: (1) The most significant bit (MSB) is on the left. (2) The IDCODE's least significant bit (LSB) is always 1.
M512 RAM Block
The M512 RAM block is a simple dual-port memory block and is useful for implementing small FIFO buffers, DSP, and clock domain transfer applications. Each block contains 576 RAM bits (including parity bits). M512 RAM blocks can be configured in the following modes:
2.562 2.558 -0.083 -0.087
-4 Speed Grade
2.940 2.936 -0.107 -0.111
-5 Speed Grade
Unit
3.899
ns
3.575
ns
0.355
ns
0.031
ns
-5 Speed Grade
Unit
3.453
ns
3.448
ns
-0.128
ns
When configured as RAM or ROM, you can use an initialization file to pre-load the memory contents.
M512 RAM blocks can have different clocks on its inputs and outputs. The wren, datain, and write address registers are all clocked together from one of the two clocks feeding the block. The read address, rden, and output registers can be clocked by either of the two clocks driving the block. This allows the RAM block to operate in read/write or input/output clock modes. Only the output register can be bypassed. The six labclk signals or local interconnect can drive the inclock, outclock, wren, rden, and outclr signals. Because of the advanced interconnect between the LAB and M512 RAM blocks, ALMs can also control the wren and rden signals and the RAM clock, clock enable, and asynchronous clear signals. Figure 2–19 shows the M512 RAM block control signal generation logic.
Parameter
tC I N tC O U T tP L L C I N tP L L C O U T
Minimum Timing
Industrial Commercial
1.439 1.444 -0.161 -0.156
1.508 1.513 -0.174 -0.169
-3 Speed Grade
1.532 1.537 -0.167 -0.162
-3 Speed Grade
2.591 2.587 -0.079 -0.083
-4 Speed Grade
2.972 2.968 -0.099 -0.103
Table 5–55. EP2S60 Row Pins Global Clock Timing Parameters
-0.133
ns
-5 Speed Grade
Unit
3.421
ns
3.416
ns
-0.126
ns
-0.131
ns
Stratix II Device Handbook, Volume 1
Stratix II Device Handbook, Volume 1
DC & Switching Characteristics
Table 5–53. EP2S60 Column Pins Global Clock Timing Parameters
Parameter
tC I N tC O U T tP L L C I N tP L L C O U T
Part Number (16 Bits)
Manufacturer Identity (11 Bits)
LSB (1 Bit) (2)
0010 0000 1001 0001
000 0110 1110
1
0010 0000 1001 0010
000 0110 1110
1
0010 0000 1001 0011
Table 3–3. 32-Bit Stratix II Device IDCODE
Device
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
Version (4 Bits) 0000 0000 0001 0000 0000 0000
IDCODE (32 Bits) (1)
The RAM blocks in Stratix II devices have local interconnects to allow ALMs and interconnects to drive into RAM blocks. The M512 RAM block local interconnect is driven by the R4, C4, and direct link interconnects from adjacent LABs. The M512 RAM blocks can communicate with LABs on either the left or right side through these row interconnects or with LAB columns on the left or right side with the column interconnects. The M512 RAM block has up to 16 direct link input connections from the left adjacent LABs and another 16 from the right adjacent LAB. M512 RAM outputs can also connect to left and right LABs through direct link interconnect. The M512 RAM block has equal opportunity for access and performance to and from LABs on either its left or right side. Figure 2–20 shows the M512 RAM block to logic array interface.
Stratix II Device Handbook, Volume 1
Configuration & Testing
The Quartus II software has an Auto Usercode feature where you can choose to use the checksum value of a programming file as the JTAG user code. If selected, the checksum is automatically loaded to the USERCODE register. Turn on the Auto Usercode option by clicking Device & Pin Options, then General, in the Settings dialog box (Assignments menu).
Minimum Timing
Industrial Commercial
1.658 1.501 0.06 -0.097
1.739 1.574 0.057 -0.108
-3 Speed Grade
2.920 2.678 0.278 0.036
-4 Speed Grade
3.350 3.072 0.304 0.026
1 Stratix, Stratix II, Cyclone, and Cyclone II devices must be within the first 17 devices in a JTAG chain. All of these devices have the same JTAG controller. If any of the Stratix, Stratix II, Cyclone, and Cyclone II devices are in the 18th or after they fail configuration. This does not affect SignalTap II.
Table 5–54. EP2S60 Row Pins Regional Clock Timing Parameters
Parameter
tC I N tC O U T tP L L C I N tP L L C O U T
Minimum Timing
Industrial Commercial
1.463 1.468 -0.153 -0.148
Table 3–2. Stratix II Boundary-Scan Register Length
Device
EP2S15 EP2S30 EP2S60 EP2S90 EP2S130 EP2S180
Boundary-Scan Register Length
1,140 1,692 2,196 2,748 3,420 3,948
■ Simple dual-port RAM ■ Single-port RAM ■ FIFO ■ ROM ■ Shift register
1 Violating the setup or hold time on the memory block address registers could corrupt memory contents. This applies to both read and write operations.
000 0110 1110
1
0010 0000 1001 0100
000 011Βιβλιοθήκη 111010010 0000 1001 0101
000 0110 1110
1
0010 0000 1001 0110
000 0110 1110
1
Notes to Table 3–3: (1) The most significant bit (MSB) is on the left. (2) The IDCODE's least significant bit (LSB) is always 1.