FPGA可编程逻辑器件芯片XC3S1400AN-4FGG676中文规格书

Chapter 4: Designing with the Subsystem
RS-FEC Functional Description
The RS-FEC feature of the 10G/25G Subsystem provides error correction capability according to IEEE 802.3 Clause 108 or Schedule 3 of the 25G Ethernet Consortium.
The feature requires the insertion of PCS alignment markers as defined in IEEE 802.3 Table 82-2. Inputs are provided for the alignment markers and also for the value of words between alignment markers.
It is possible to bypass the RS-FEC function by means of the enable signals. This will bypass the RS-FEC function and connect the PCS directly to the transceiver, with the benefit of reduced latency. Refer to 25G IEEE 802.3by Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG217) (registration required) for the latest latency performance data in the various bypass modes, defined as follows:
•FEC Bypass Correction: The decoder performs error detection without correction, (see IEEE Std 802.3by section 108.5.3.2. The latency is reduced in this mode (see 25G IEEE 802.3by Reed-Solomon Forward Error Correction LogiCORE IP Product Guide (PG217) (registration
required) for latency figures).
Additionally, you can optionally generate a 64-bit standalone version of the MAC for 10 Gb/s operation. The block diagram is shown in the following figure.
Figure 4: 64-bit Standalone Version of the MAC for 10 Gb/s Operation
AXI4-Streaming AXI4-Streaming
Clocks and Resets XGMII RX XGMII TX X20136-120417
Standards
The 10G/25G Ethernet Subsystem is designed to the standard specified in the 25G and 50G Ethernet Consortium and the IEEE Std 802.3.
Performance and Resource Utilization
For full details about performance and resource utilization, visit the Performance and Resource Utilization web page .
Chapter 3: Product Specification
Chapter 3: Product Specification
CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_LSB: 008C
Table 82: CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_LSB: 008C
Bits Default Type Signal
31:00RW ctl_tx_sa_ppp[31:0]
CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_MSB: 0090
Table 83: CONFIGURATION_TX_FLOW_CONTROL_PPP_SA_REG_MSB: 0090
Bits Default Type Signal
15:00RW ctl_tx_sa_ppp[47:32]
CONFIGURATION_RX_FLOW_CONTROL_REG1: 0094
Table 84: CONFIGURATION_RX_FLOW_CONTROL_REG1: 0094
Bits Default Type Signal
8:00RW ctl_rx_pause_enable
90RW ctl_rx_forward_control
100RW ctl_rx_enable_gcp
110RW ctl_rx_enable_pcp
120RW ctl_rx_enable_gpp
130RW ctl_rx_enable_ppp
140RW ctl_rx_check_ack
CONFIGURATION_RX_FLOW_CONTROL_REG2: 0098
Table 85: CONFIGURATION_RX_FLOW_CONTROL_REG2: 0098
Bits Default Type Signal
00RW ctl_rx_check_mcast_gcp
10RW ctl_rx_check_ucast_gcp
20RW ctl_rx_check_sa_gcp
30RW ctl_rx_check_etype_gcp
40RW ctl_rx_check_opcode_gcp
50RW ctl_rx_check_mcast_pcp
60RW ctl_rx_check_ucast_pcp
70RW ctl_rx_check_sa_pcp
80RW ctl_rx_check_etype_pcp
90RW ctl_rx_check_opcode_pcp
100RW ctl_rx_check_mcast_gpp。