66138中文资料

合集下载

66164;66166;66167;66168;66169;中文规格书,Datasheet资料

COMMON POINT GROUND
Per ANSI/ESD S6.1, Grounding section 4.1.1 “Every element to be grounded at an ESD protected station shall be connected to the same common point ground.” ESD Handbook ESD TR20.20 section 5.1.3 Basic Grounding Requirements “The first step in ensuring that everything in an EPA is at the same electrical potential is to ground all conductive components of the work area (worksurfaces, people, equipment, etc.) to the same electrical ground point. This point is called the common point ground. The next step in completing the ground circuit is to connect the common point ground to the equipment ground (third wire, green).”
General Grounding Guidelines
1. ANSI/ESD S20.20 requires that all conductors in an ESD protected area, including personnel, must be grounded. 2. The ESD ground must be tied directly to and at the same potential as the building or “green wire” equipment ground. 3. Per ANSI/ESD S20.20, the ESD control program can in no way replace or supercede any requirements for personnel safety. Ground fault circuit interrupters (GFCI) and other safety protection should be considered wherever personnel might come into contact with electrical sources. 4. All electrical outlets should be verified for proper wiring configuration, resistance or impedance and GFCI function when the mat is installed and periodically thereafter.

psr661说明书

psr661说明书PSR60系列数字式综合测控装置技术说明书国电南京自动化股份有限公司GUODIAN NANJING AUTOMATION CO.，LTDPSR60系列数字式综合测控装置技术说明书编写审核批准V ：1.1国电南京自动化股份有限公司2005年12月安全声明注意：对装置进行测试时，请使用可靠精确的测试仪进行测试。

有些模块的输入量程是通过板上跳线实现的，请在接线前仔细核对跳线，以免损坏模块。

危险：请不要用手触摸装置除机壳外的裸露带电部分和印制板上的器件管脚。

其他：出厂时，运行密码为1000，检修密码为2000，请用户重设。

请注意密码管理，以免由于越权使用密码，造成误操作。

版本声明本说明书适用于PSR60系列数字式综合测控装置主CPU 模块V1.49版本，详见下表。

1．软件本说明书对应的各模件最新版本号分别如下表：2．硬件初始版本。

产品说明书版本修改记录表* 技术支持电话：83537292传真：83537201* 本说明书可能会被修改，请注意核对实际产品与说明书的版本是否相符 * 005年12月第2版第1次印刷 * 国电南自技术部监制目录安全声明版本声明 1 概述 ................................................ ....................... 1 1.1 适用范围 ................................................ ................. 1. 性能特点 ................................................ ................. 技术参数 ....................................................................1 额定电气参数 ................................................ .............. 主要技术指标 ................................................ .............. 环境条件 ................................................ .................. 绝缘性能 ................................................ .................. 耐湿热性能 ................................................ ................ 电磁兼容性 ................................................ .............. 10. 机械性能 ................................................ ................ 10 装置硬件简介 ................................................ .............. 11.1 机箱结构 ................................................ ................ 11. 关于校准 ................................................ ................ 1 典型配置方案 .............................................................. 14.1 单模块类型定值简介 ................................................ ...... 14. 装置典型配置方案 ................................................ ........ 1 定值整定简介 ................................................ .............. 1 输入输出数据 ................................................ .............. 1 模块说明 ................................................ .................. 18.1 智能交流采集模块 ....................... 18.1.1 交流模块硬件说明 ................................................ ...... 18.1. 交流模块典型配置 ................................................ ...... 19.1. 交流模块定值及整定说明 ................................................2.1. 交流模块输入输出数据 ................................................ ..0. 管理主模块 ................................................ ..7.2.1 管理主模块硬件说....7.2. 管理主模块定值及整定说明 ..............................................8.2. 管理主模块输入输出数据 ................................................2. 电源模块 ................................................ .......5.3.1 电源模块硬件说明 ................................................ ......5. 智能开入模块 ................................................ ......5.4.1 开入模块硬件说明 ................................................ ......5.4. 开入模块典型配置 ................................................ ......6.4. 开入模块定值及整定说明 ................................................7.4. 开入模块输入输出数据 ................................................ ..1. 智能控制模块 ................................................ .....2.5.1 控制模块硬件说......2.5. 控制模块定值及整定说明 (3)PSRC1900系列微机式保护测控装置 PSRC1900系列保护控制自动化系统技术使用说明书杭州博瑞电气有限公司2012年2月目录1 概述 ................................................ . (1)1.1 产品特点 ................................................ ............................................... 1 1. PSRC1900系列装置分类 ................................................ ...................... 1 1. PSRC1900系列装置用途及主要功能 ................................................ .. 技术指....2.1 额定数据 ................................................ ................................................ 功率消耗 ................................................ ................................................ 过载能力 ................................................ ................................................ 测量及精度 ................................................ ............................................ 绝缘性能 ................................................ ................................................ 触点性能 ................................................ ................................................ 电磁兼容性 ................................................ ............................................ 环境条................................................ 应用标准 ................................................ ............................................... 装置硬件 ................................................ ....3.1 机械结构图 ................................................ ............................................ 电源插件 ................................................ ...................................... 操作插件 ................................................ ...................................... 遥信插件 ................................................ ...................................... 交流插件 ................................................ ...................................... CPU 板 ................................................ .................................................... 面板显示及操作说明 ..........................................4.1 面板显示 ................................................ ................................................ 菜单级别及说明 ................................................ .................................... 装置参数设定 ................................................ ..................................... 1 PSRC1910线路保护测控装置 . (14)5.1 基本配置及规格 ................................................ ................................. 14. 保护原理 ................................................ ............................................. 15. 定值设置 ................................................ ............................................. 15. 背板端子图111 ............................................... ................................... 18. 典型接线原理图 ................................................................................. 19. 保护逻辑框图 ................................................ .....................................1 PSRC1913线路自投保护测控装置 (2)6.1 基本配置及规格 ................................................ .................................6. 保护原理 ................................................ .............................................6. 定值设置 ................................................ .............................................6. 背板端子图 ................................................ .........................................6. 典型接线原理图 ................................................ .................................6. 保护逻辑框图 ................................................ ..................................... PSRC1920电容器保护测控装置 .. 07.1 基本配置及规 0机式保护测控装置7. 保护原理 ................................................ .............................................1. 定值设置 ................................................ .............................................2. 背板端子图 ................................................ .........................................3. 典型接线原理图 ................................................ .................................4. 保护逻辑框图 ................................................ ..................................... PSRC1950配变保护测控装置 . (7)8.1 基本配置及规格 ................................................ .................................8. 保护原理 ................................................值设置 ................................................ .............................................9. 装置背板端子图 ................................................ .................................0. 典型接线原理图 ................................................ .................................1. 保护逻辑框图 ................................................ ..................................... PSRC1960电动机保护测控装置 .. (4)9.1 基本配置及规格 ................................................ .................................9. 保护原理 ................................................ .............................................9. 定值设置 ................................................ .............................................6. 背板端子图 ................................................线原理图 ................................................ .................................9. 保护逻辑框图 ................................................ .....................................1 10 PSRC1982电压综合保护兼并列装置 (2)10.1 基本配置及规格 ................................................ ...............................10. 保护原理 ................................................ ...........................................10. 定值设置 ................................................ ...........................................10. 背板端子图 ................................................ .......................................10. 典型接线原理图 ................................................ ...............................10. 保护逻辑框图 ...................................................................................11 保护参考整定计算说明 ......................................1 用户安装调试说明 ..........................................1 通讯规约 ................................................ ..1 订货须知 ................................................ ..2PSRC1900系列微机式保护测控装置1 概述PSRC1900系列数字式保护测控装置是公司积累多年研发、生产数字式保护测控装置的基础上，经过大量的市场调研、配置方案论证所推出的面向35KV及以下电压等级的输配电元件及线路的保护、测量及控制系统。

CS42438_07中文资料

FEATURESSix 24-bit A/D, Eight 24-bit D/A Converters ADC Dynamic Range–105 dB Differential –102 dB Single-Ended DAC Dynamic Range–108 dB Differential –105 dB Single-Ended ADC/DAC THD+N–-98 dB Differential –-95 dB Single-EndedCompatible with Industry-Standard TimeDivision Multiplexed (TDM) Serial InterfaceDAC Sampling Rates up to 192 kHz ADC Sampling Rates up to 96 kHzProgrammable ADC High-Pass Filter for DCOffset CalibrationLogarithmic Digital Volume Control Hardware Mode or Software I²C ® & SPI ™ Supports Logic Levels Between 5V and 1.8VGENERAL DESCRIPTIONThe CS42438 CODEC provides six multi-bit analog-to-digital and eight multi-bit digital-to-analog delta-sigma converters. The CODEC is capable of operation with ei-ther differential or single-ended inputs and outputs, in a 52-pin MQFP package.Six fully differential, or single-ended, inputs are avail-able on stereo ADC1, ADC2, and ADC3. When operating in Single-Ended Mode, an internal MUX be-fore ADC3 allows selection from up to four single-ended inputs. Digital volume control is provided for each ADC channel, with selectable overflow detection.All eight DAC channels provide digital volume control and can operate with differential or single-ended outputs.An auxiliary serial input is available for an additional two channels of PCM data.The CS42438 is available in a 52-pin MQFP package in Commercial (-10°C to +70°C) and Automotive (-40°C to +105°C) grades. The CDB42438 Customer Demonstra-tion board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 61 for complete ordering information.The CS42438 is ideal for audio systems requiring wide dynamic range, negligible distortion and low noise, such as A/V receivers, DVD receivers, and automotive audio systems.CS42438TABLE OF CONTENTS1. PIN DESCRIPTIONS - SOFTWARE MODE (6)1.1 Digital I/O Pin Characteristics (8)2. PIN DESCRIPTIONS - HARDWARE MODE (9)3. TYPICAL CONNECTION DIAGRAMS (11)4. CHARACTERISTICS AND SPECIFICATIONS (13)RECOMMENDED OPERATING CONDITIONS (13)ABSOLUTE MAXIMUM RATINGS (13)ANALOG INPUT CHARACTERISTICS (COMMERCIAL) (14)ANALOG INPUT CHARACTERISTICS (AUTOMOTIVE) (15)ADC DIGITAL FILTER CHARACTERISTICS (16)ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL) (17)ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE) (18)COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (20)SWITCHING SPECIFICATIONS - ADC/DAC PORT (21)SWITCHING CHARACTERISTICS - AUX PORT (22)SWITCHING SPECIFICATIONS - CONTROL PORT - I²C MODE (23)SWITCHING SPECIFICATIONS - CONTROL PORT - SPI FORMAT (24)DC ELECTRICAL CHARACTERISTICS (25)DIGITAL INTERFACE SPECIFICATIONS & CHARACTERISTICS (25)5. APPLICATIONS (26)5.1 Overview (26)5.2 Analog Inputs (27)5.2.1 Line-Level Inputs (27)5.2.1.1 Hardware Mode (27)5.2.1.2 Software Mode (27)5.2.2 ADC3 Analog Input (28)5.2.3 Hardware Mode (29)5.2.4 Software Mode (29)5.2.5 High-Pass Filter and DC Offset Calibration (29)5.2.5.1 Hardware Mode (29)5.2.5.2 Software Mode (29)5.3 Analog Outputs (30)5.3.1 Initialization (30)5.3.2 Line-Level Outputs and Filtering (30)5.3.3 Digital Volume Control (32)5.3.3.1 Hardware Mode (32)5.3.3.2 Software Mode (32)5.3.4 De-Emphasis Filter (32)5.4 System Clocking (33)5.4.1 Hardware Mode (33)5.4.2 Software Mode (33)5.5 CODEC Digital Interface (33)5.5.1 TDM (33)5.5.2 I/O Channel Allocation (34)5.6 AUX Port Digital Interface Formats (34)5.6.1 Hardware Mode (34)5.6.2 Software Mode (34)5.6.3 I²S (34)5.6.4 Left-Justified (35)5.7 Control Port Description and Timing (35)5.7.1 SPI Mode (35)5.7.2 I²C Mode (36)5.8 Recommended Power-Up Sequence (37)5.8.1 Hardware Mode (37)5.8.2 Software Mode (38)5.9 Reset and Power-Up (38)5.10 Power Supply, Grounding, and PCB Layout (38)6. REGISTER QUICK REFERENCE (39)7. REGISTER DESCRIPTION (41)7.1 Memory Address Pointer (MAP) (41)7.1.1 Increment (INCR) (41)7.1.2 Memory Address Pointer (MAP[6:0]) (41)7.2 Chip I.D. and Revision Register (Address 01h) (Read Only) (41)7.2.1 Chip I.D. (CHIP_ID[3:0]) (41)7.2.2 Chip Revision (REV_ID[3:0]) (41)7.3 Power Control (Address 02h) (42)7.3.1 Power Down ADC Pairs (PDN_ADCX) (42)7.3.2 Power Down DAC Pairs (PDN_DACX) (42)7.3.3 Power Down (PDN) (42)7.4 Functional Mode (Address 03h) (43)7.4.1 MCLK Frequency (MFREQ[2:0]) (43)7.5 Miscellaneous Control (Address 04h) (43)7.5.1 Freeze Controls (FREEZE) (43)7.5.2 Auxiliary Digital Interface Format (AUX_DIF) (43)7.6 ADC Control & DAC De-Emphasis (Address 05h) (44)7.6.1 ADC1-2 High-Pass Filter Freeze (ADC1-2_HPF FREEZE) (44)7.6.2 ADC3 High Pass Filter Freeze (ADC3_HPF FREEZE) (44)7.6.3 DAC De-Emphasis Control (DAC_DEM) (44)7.6.4 ADC1 Single-Ended Mode (ADC1 SINGLE) (44)7.6.5 ADC2 Single-Ended Mode (ADC2 SINGLE) (44)7.6.6 ADC3 Single-Ended Mode (ADC3 SINGLE) (45)7.6.7 Analog Input Ch. 5 Multiplexer (AIN5_MUX) (45)7.6.8 Analog Input Ch. 6 Multiplexer (AIN6_MUX) (45)7.7 Transition Control (Address 06h) (45)7.7.1 Single Volume Control (DAC_SNGVOL, ADC_SNGVOL) (45)7.7.2 Soft Ramp and Zero Cross Control (ADC_SZC[1:0], DAC_SZC[1:0]) (46)7.7.3 Auto-Mute (AMUTE) (46)7.7.4 Mute ADC Serial Port (MUTE ADC_SP) (47)7.8 DAC Channel Mute (Address 07h) (47)7.8.1 Independent Channel Mute (AOUTX_MUTE) (47)7.9 AOUTX Volume Control (Addresses 08h- 0Fh) (47)7.9.1 Volume Control (AOUTX_VOL[7:0]) (47)7.10 DAC Channel Invert (Address 10h) (48)7.10.1 Invert Signal Polarity (INV_AOUTX) (48)7.11 AINX Volume Control (Address 11h-16h) (48)7.11.1 AINX Volume Control (AINX_VOL[7:0]) (48)7.12 ADC Channel Invert (Address 17h) (49)7.12.1 Invert Signal Polarity (INV_AINX) (49)7.13 Status (Address 19h) (Read Only) (49)7.13.1 CLOCK ERROR (CLK ERROR) (49)7.13.2 ADC Overflow (ADCX_OVFL) (49)7.14 Status Mask (Address 1Ah) (49)8. EXTERNAL FILTERS (50)8.1 ADC Input Filter (50)8.1.1 Passive Input Filter (51)8.1.2 Passive Input Filter w/Attenuation (52)9. ADC FILTER PLOTS (54)10. DAC FILTER PLOTS (56)11. PARAMETER DEFINITIONS (58)12. REFERENCES (59)13. PACKAGE INFORMATION (60)13.1 Thermal Characteristics (60)14. ORDERING INFORMATION (61)15. REVISION HISTORY (61)LIST OF FIGURESFigure 1.Typical Connection Diagram (Software Mode) (11)Figure 2.Typical Connection Diagram (Hardware Mode) (12)Figure 3.Output Test Circuit for Maximum Load (19)Figure 4.Maximum Loading (19)Figure 5.TDM Serial Audio Interface Timing (21)Figure 6.Serial Audio Interface Slave Mode Timing (22)Figure 7.Control Port Timing - I²C Format (23)Figure 8.Control Port Timing - SPI Format (24)Figure 9.Full-Scale Input (28)Figure 10.ADC3 Input Topology (28)Figure 11.Audio Output Initialization Flow Chart (31)Figure 12.Full-Scale Output (32)Figure 13.De-Emphasis Curve (33)Figure 14.TDM Serial Audio Format (34)Figure 15.AUX I²S Format (34)Figure 16.AUX Left-Justified Format (35)Figure 17.Control Port Timing in SPI Mode (36)Figure 18.Control Port Timing, I²C Write (36)Figure 19.Control Port Timing, I²C Read (37)Figure 20.Single to Differential Active Input Filter (50)Figure 21.Single-Ended Active Input Filter (50)Figure 22.Passive Input Filter (51)Figure 23.Passive Input Filter w/Attenuation (52)Figure 24.Active Analog Output Filter (53)Figure 25.Passive Analog Output Filter (53)Figure 26.SSM Stopband Rejection (54)Figure 27.SSM Transition Band (54)Figure 28.SSM Transition Band (Detail) (54)Figure 29.SSM Passband Ripple (54)Figure 30.DSM Stopband Rejection (54)Figure 31.DSM Transition Band (54)Figure 32.DSM Transition Band (Detail) (55)Figure 33.DSM Passband Ripple (55)Figure 34.SSM Stopband Rejection (56)Figure 35.SSM Transition Band (56)Figure 36.SSM Transition Band (detail) (56)Figure 37.SSM Passband Ripple (56)Figure 38.DSM Stopband Rejection (56)Figure 39.DSM Transition Band (56)Figure 40.DSM Transition Band (detail) (57)Figure 41.DSM Passband Ripple (57)Figure 42.QSM Stopband Rejection (57)Figure 44.QSM Transition Band (detail) (57)Figure 45.QSM Passband Ripple (57)LIST OF TABLESTable 1. I/O Power Rails (8)Table 2. Hardware Configurable Settings (26)Table 3. AIN5 Analog Input Selection (29)Table 4. AIN6 Analog Input Selection (29)Table 5. MCLK Frequency Settings (33)Table 6. Serial Audio Interface Channel Allocations (34)Table 7. MCLK Frequency Settings (43)Table 8. Example AOUT Volume Settings (47)Table 9. Example AIN Volume Settings (48)1.PIN DESCRIPTIONS - SOFTWARE MODEPin Name#Pin DescriptionSCL/CCLK1Serial Control Port Clock (Input) - Serial clock for the control port interface.SDA/CDOUT2Serial Control Data I/O (Input/Output) - Input/Output for I²C data. Output for SPI data.AD0/CS3Address Bit [0]/ Chip Select (Input) - Chip address bit in I²C Mode. Control signal used to select the chip in SPI Mode.AD1/CDIN4Address Bit [1]/ SPI Data Input (Input) - Chip address bit in I²C Mode. Input for SPI data.RST5Reset (Input) - The device enters a low-power mode and all internal registers are reset to their default settings when low.VLC6Control Port Power (Input) - Determines the required signal level for the control port interface. See “Digital I/O Pin Characteristics” on page8.FS7Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. VD8Digital Power (Input) - Positive power supply for the digital section.DGND9,18Digital Ground (Input) -VLS10Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter-faces. See “Digital I/O Pin Characteristics” on page8.SCLK11Serial Clock(Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs. MCLK12Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters.ADC_SDOUT13Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data.DAC_SDIN14DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data.AUX_LRCK15Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line.AUX_SCLK16Auxiliary Serial Clock(Output) - Serial clock for the Auxiliary serial audio interface.AUX_SDIN17Auxiliary Serial Input (Input) - The 42438 provides an additional serial input for two’s comple-ment serial audio data.AOUT1 +,-AOUT2 +,-AOUT3 +,-AOUT4 +,-AOUT5 +,-AOUT6 +,-AOUT7 +,-AOUT8 +,-20,1921,2224,2325,2628,2729,3031,3233,34Differential Analog Output (Output) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. Each positive leg of the differential outputs may also be used single-ended.AGND35,48Analog Ground (Input) - Ground reference for the analog section.VQ36Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. VA37,46Analog Power (Input) - Positive power supply for the analog section.AIN1 +,-AIN2 +,-AIN3 +,-AIN4 +,-AIN5 +,-AIN6 +,-39,3841,4043,4245,4450,4952,51Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-tors. The full-scale input level is specified in the Analog Characteristics specification table. Single-ended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled.Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven tocommon mode. See below for a description of AIN5-AIN6 in Single-Ended Mode.AIN5 A,B AIN6 A,B 50,4952,51Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allowsselection between two channels for both analog inputs AIN5 and AIN6 (see Sections 7.6.6-7.6.8 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table.FILT+47Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-cuits.1.1Digital I/O Pin CharacteristicsVarious pins on the CS42438 are powered from separate power supply rails. The logic level for each input should adhere to the corresponding power rail and should not exceed the maximum ratings.Power Rail Pin NameSW/(HW)I/O Driver ReceiverVLC RST Input- 1.8 V - 5.0 V, CMOS SCL/CCLK(AIN5_MUX)Input- 1.8 V - 5.0 V, CMOS, with HysteresisSDA/CDOUT (AIN6_MUX)Input/Output1.8 V - 5.0 V, CMOS/Open Drain 1.8 V - 5.0 V, CMOS, with HysteresisAD0/CS(MFREQ)Input- 1.8 V - 5.0 V, CMOS AD1/CDIN(ADC3_HPF)Input- 1.8 V - 5.0 V, CMOS VLS MCLK Input- 1.8 V - 5.0 V, CMOS LRCK Input- 1.8 V - 5.0 V, CMOSSCLK Input- 1.8 V - 5.0 V, CMOSADC_SDOUT3 (ADC3_SINGLE)Input/Output1.8 V - 5.0 V, CMOS-DAC_SDIN Input- 1.8 V - 5.0 V, CMOS AUX_LRCK Output 1.8 V - 5.0 V, CMOS-AUX_SCLK Output 1.8 V - 5.0 V, CMOS-AUX_SDIN Input- 1.8 V - 5.0 V, CMOSTable 1. I/O Power Rails2.Pin Name#Pin DescriptionAIN5_MUX AIN6_MUX 12Analog Input Multiplexer (Input) - Allows selection between the A and B single-ended inputs of ADC3.MFREQ3MCLK Frequency (Input) - Sets the required frequency range of the input Master Clock.ADC3_HPF4ADC3 High-Pass Filter Freeze (Input) - When this pin is driven high, the internal high-pass filter will be disabled for ADC3.The current DC offset value will be frozen and continue to be subtractedfrom the conversion result.RST5Reset (Input) - The device enters a low-power mode and all internal registers are reset to their default settings when low.VLC6Control Port Power (Input) - Determines the required signal level for the control port interface. See “Digital I/O Pin Characteristics” on page8.FS7Frame Sync (Input) - Signals the start of a new TDM frame in the TDM digital interface format. VD8Digital Power (Input) - Positive power supply for the digital section.DGND9,18Digital Ground (Input) - Ground reference for the digital section.VLS10Serial Port Interface Power (Input) - Determines the required signal level for the serial port inter-faces. See “Digital I/O Pin Characteristics” on page8.SCLK11Serial Clock(Input) - Serial clock for the serial audio interface. Input frequency must be 256 x Fs. MCLK12Master Clock (Input) - Clock source for the delta-sigma modulators and digital filters.ADC_SDOUT13Serial Audio Data Output (Output) - TDM output for two’s complement serial audio data.DAC_SDIN14DAC Serial Audio Data Input (Input) - TDM Input for two’s complement serial audio data.AUX_LRCK15Auxiliary Left/Right Clock (Output) - Determines which channel, Left or Right, is currently active on the Auxiliary serial audio data line.AUX_SCLK16Auxiliary Serial Clock(Output) - Serial clock for the Auxiliary serial audio interface.AUX_SDIN17Auxiliary Serial Input (Input) - The 42438 provides an additional serial input for two’s comple-ment serial audio data.AOUT1 +,-AOUT2 +,-AOUT3 +,-AOUT4 +,-AOUT5 +,-AOUT6 +,-AOUT7 +,-AOUT8 +,-20,1921,2224,2325,2628,2729,3032,31,33,34Differential Analog Output (Output) - The full-scale differential analog output level is specified in the Analog Characteristics specification table. Each positive leg of the differential outputs mayalso be used single-ended.AGND35,48Analog Ground (Input) - Ground reference for the analog section.VQ36Quiescent Voltage (Output) - Filter connection for internal quiescent reference voltage. VA37,46Analog Power (Input) - Positive power supply for the analog section.AIN1 +,-AIN2 +,-AIN3 +,-AIN4 +,-AIN5 +,-AIN6 +,-39,3841,4043,4245,4450,4952,51Differential Analog Input (Input) - Signals are presented differentially to the delta-sigma modula-tors. The full-scale input level is specified in the Analog Characteristics specification table. Single-ended inputs may be applied to the positive terminals when the ADCx SINGLE bit is enabled.Once in Single-Ended Mode, the negative terminal of AIN1-AIN4 must be externally driven tocommon mode. See below for a description of AIN5-AIN6 in Single-Ended Mode.AIN5 A,B AIN6 A,B 50,4952,51Single-Ended Analog Input (Input) - In Single-Ended Mode, an internal analog mux allowsselection between two channels for both analog inputs AIN5 and AIN6 (see Sections 7.6.6-7.6.8 for details). The unused leg of each input is internally connected to common mode. The full-scale input level is specified in the Analog Characteristics specification table.FILT+47Positive Voltage Reference (Output) - Positive reference voltage for the internal sampling cir-cuits.3.TYPICAL CONNECTION DIAGRAMSFigure 1. Typical Connection Diagram (Software Mode)Figure 2. Typical Connection Diagram (Hardware Mode)4.CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS(AGND=DGND=0 V, all voltages with respect to ground.)ABSOLUTE MAXIMUM RATINGS(AGND = DGND = 0 V; all voltages with respect to ground.)WARNING:Operation at or beyond these limits may result in permanent damage to the device. Normal operationis not guaranteed at these extremes.Notes:1.Typical Analog input/output performance will slightly degrade at VA = 3.3 V.2.The ADC_SDOUT may not meet timing requirements in Double-Speed Mode.3.Any pin except supplies. Transient currents of up to ±100 mA on the analog input pins will not causeSCR latch-up.4.The maximum over/under voltage is limited by the input current.ParametersSymbol MinMax Units DC Power Supply Analog (Note 1)VA 3.14 5.25V Digital VD 3.14 3.47V Serial Audio Interface (Note 2)VLS 1.71 5.25V Control Port Interface VLC 1.71 5.25V Ambient TemperatureCommercial -CMZAutomotive -DMZT A-10-40+70+105°C °CParametersSymbol Min Max Units DC Power SupplyAnalogDigitalSerial Port Interface Control Port InterfaceVA VD VLS VLC -0.3-0.3-0.3-0.3 6.06.06.06.0V V V V Input Current(Note 3)I in -±10mA Analog Input Voltage (Note 4)V IN AGND-0.7VA+0.7V Digital Input Voltage Serial Port Interface (Note 4)Control Port InterfaceV IND-S V IND-C -0.3-0.3VLS+ 0.4VLC+ 0.4V V Ambient Operating Temperature (power applied)T A -50+125°C Storage TemperatureT stg-65+150°C(Test Conditions (unless otherwise specified): T A=-10to+70°C; VD = VLS = VLC = 3.3V±5%, VA = 5V±5%; Full-scale input sine wave: 1 kHz through the active input filter in Figure 20 on page 50 and Figure 21 on page 50; Measurement Bandwidth is 10Hz to 20kHz.)Differential Single-EndedParameter Min Typ Max Min Typ Max Unit Fs=48 kHz, 96 kHzDynamic Range A-weightedunweighted40 kHz bandwidth unweighted 9996-10510299---96931029996---dBdBdBTotal Harmonic Distortion + Noise -1dB (Note 5) -20dB-60dB40 kHz bandwidth -1 dB -----98-82-42-90-92--------95-79-39-90-89---dBdBdBdBADC1-3 Interchannel Isolation-90--90-dB ADC3 MUX Interchannel Isolation-90--90-dB DC AccuracyInterchannel Gain Mismatch-0.1--0.1-dB Gain Drift-±100--±100-ppm/°C Analog InputFull-Scale Input Voltage 1.06*VA 1.12*VA 1.18*VA0.53*VA0.56*VA0.59*VA Vpp Differential Input Impedance (Notes 6 & 8)232932kΩSingle-Ended Input Impedance(Notes 7 & 8)---232932kΩCommon Mode Rejection Ratio (CMRR)-82----dB(Test Conditions (unless otherwise specified): T A =-40 to +85°C; VD = VLS = VLC = 3.3V±5%, VA = 5V±5%; Full-scale input sine wave: 1 kHz through the active input filter in Figure 20 on page 50 and Figure 21 on page 50; Measurement Bandwidth is 10Hz to 20kHz.)Notes:5.Referred to the typical full-scale voltage.6.Measured between AINx+ and AINx-.7.Measured between AINxx and AGND.8.The input impedance scales inversely proportionate to the sample rate of the ADC modulatorDifferentialSingle-Ended ParameterMin Typ MaxMin Typ MaxUnitFs=48 kHz, 96 kHz Dynamic RangeA-weighted unweighted 40 kHz bandwidth unweighted 9794-10510299---9491-1029996---dB dBdBTotal Harmonic Distortion + Noise -1dB(Note 5) -20dB-60dB40 kHz bandwidth -1 dB-----98-82-42-87-90--------95-79-39-87-87---dB dB dB dB ADC1-3 Interchannel Isolation -90--90-dB ADC3 MUX Interchannel Isolation -85--85-dB DC AccuracyInterchannel Gain Mismatch -0.1--0.1-dB Gain Drift -±100--±100-ppm/°C Analog InputFull-Scale Input Voltage 1.04*VA 1.12*VA 1.20*VA 0.52*VA 0.56*VA 0.60*VA Vpp Differential Input Impedance (Notes 6 & 8)232932k ΩSingle-Ended Input Impedance(Notes 7 & 8)---232932k ΩCommon Mode Rejection Ratio (CMRR)-82----dBADC DIGITAL FILTER CHARACTERISTICSNotes:9.Filter response is guaranteed by design.10.Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 26to 33) havebeen normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.Parameter (Notes 9, 10)MinTypMaxUnitSingle-Speed Mode (Note 10)Passband (Frequency Response) to -0.1 dB corner0-0.4896Fs Passband Ripple --0.08dB Stopband0.5688--Fs Stopband Attenuation 70--dB Total Group Delay-12/Fs-sDouble-Speed Mode (Note 10)Passband (Frequency Response) to -0.1 dB corner0-0.4896Fs Passband Ripple --0.16dB Stopband0.5604--Fs Stopband Attenuation 69--dB Total Group Delay-9/Fs-sHigh-Pass Filter Characteristics Frequency Response -3.0 dB -0.13 dB -120--Hz Hz Phase Deviation @ 20Hz-10-Deg Passband Ripple --0dB Filter Settling Time -105/Fss(Test Conditions (unless otherwise specified): T A=-10 to +70°C; VD = VLS = VLC = 3.3V±5%, VA = 5V±5%; Full-scale 997 Hz output sine wave (see Note 12) into passive filter in Figure 26 on page 54 and active filter in Fig-ure 26 on page 54; Measurement Bandwidth is 10Hz to 20kHz.)ParameterDifferentialMin Typ MaxSingle-EndedMin Typ Max UnitFs = 48 kHz, 96 kHz, 192 kHz Dynamic Range18 to 24-Bit A-weightedunweighted 16-Bit A-weightedunweighted 10299--1081059996----9996--1051029693----dBdBdBdBTotal Harmonic Distortion + Noise18 to 24-Bit0 dB-20 dB-60 dB 16-Bit0 dB-20 dB-60 dB -------98-85-45-93-76-36-92-----------95-82-42-90-73-33-89-----dBdBdBdBdBdBInterchannel Isolation (1 kHz)-100--100-dB Analog OutputFull-Scale Output 1.235•VA 1.300•VA 1.365•VA0.618•VA0.650•VA0.683•VA Vpp Interchannel Gain Mismatch-0.10.25-0.10.25dB Gain Drift-±100--±100-ppm/°C Output Impedance-100--100-ΩDC Current draw from an AOUT pin(Note 11)--10--10μA AC-Load Resistance (R L)(Note 13)3--3--kΩLoad Capacitance (C L)(Note 13)--100--100pF(Test Conditions (unless otherwise specified): T A =-40to +85°C; VD = VLS = VLC = 3.3V±5%, VA = 5V±5%; Full-scale 997 Hz output sine wave (see Note 12) in Figure 26 on page 54 and Figure 26 on page 54; Measure-ment Bandwidth is 10Hz to 20kHz.)Notes:11.Guaranteed by design. The DC current draw represents the allowed current draw from the AOUT pindue to typical leakage through the electrolytic DC-blocking capacitors.12.One-half LSB of triangular PDF dither is added to data.13.Guaranteed by design. See Figure 3. R L and C L reflect the recommended minimum resistance andmaximum capacitance required for the internal op-amp's stability and signal integrity. In this circuit to-pology, C L will effectively move the dominant pole of the two-pole amp in the output stage. Increasing this value beyond the recommended 100 pF can cause the internal op-amp to become unstable. See “External Filters” on page 50 for a recommended output filter.ParameterDifferentialMin Typ MaxSingle-EndedMin Typ MaxUnitFs = 48 kHz, 96 kHz, 192 kHz Dynamic Range18 to 24-Bit A-weightedunweighted16-Bit A-weightedunweighted10097--1081059996----9794--1051029693----dB dB dB dB Total Harmonic Distortion + Noise18 to 24-Bit 0 dB-20 dB-60 dB16-Bit 0 dB-20 dB-60 dB-------98-85-45-93-76-36-90------------95-82-42-90-73-33-87-----dB dB dB dB dB dB Interchannel Isolation (1 kHz)-100--100-dBAnalog Output Full-Scale Output 1.210•VA 1.300•VA 1.392•VA 0.605•VA 0.650•VA 0.696•VA Vpp Interchannel Gain Mismatch -0.10.25-0.10.25dB Gain Drift -±100--±100-ppm/°C Output Impedance -100--100-ΩDC Current draw from an AOUT pin (Note 11)--10--10μAAC-Load Resistance (R L ) (Note 13)3--3--k ΩLoad Capacitance (C L )(Note 13)--100--100pFFigure 3. Output Test Circuit for Maximum Load Figure 4. Maximum LoadingCOMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSENotes:14.Response is clock-dependent and will scale with Fs. Note that the response plots (Figures 34to 45) havebeen normalized to Fs and can be de-normalized by multiplying the X-axis scale by Fs.15.Single- and Double-Speed Mode Measurement Bandwidth is from Stopband to 3 Fs.Quad-Speed Mode Measurement Bandwidth is from Stopband to 1.34 Fs.16.De-emphasis is only available in Single-Speed Mode.Parameter (Notes 9, 14)MinTypMaxUnitSingle-Speed ModePassband (Frequency Response)to -0.05dB corner to -3dB corner00--0.47800.4996Fs Fs Frequency Response 10Hz to 20kHz -0.2-+0.08dB StopBand0.5465--Fs StopBand Attenuation (Note 15)50--dB Group Delay-10/Fs -sDe-emphasis Error (Note 16)Fs = 32kHz Fs = 44.1 kHz Fs = 48 kHz------+1.5/+0+0.05/-0.25-0.2/-0.4dB dB dBDouble-Speed ModePassband (Frequency Response)to -0.1dB corner to -3dB corner00--0.46500.4982Fs Fs Frequency Response 10Hz to 20kHz -0.2-+0.7dB StopBand0.5770--Fs StopBand Attenuation (Note 15)55--dB Group Delay -5/Fs-sQuad-Speed ModePassband (Frequency Response)to -0.1dB corner to -3dB corner00--0.3970.476Fs Fs Frequency Response 10Hz to 20kHz -0.2-+0.05dB StopBand0.7--Fs StopBand Attenuation (Note 15)51--dB Group Delay - 2.5/Fs-sSWITCHING SPECIFICATIONS - ADC/DAC PORT(Inputs: Logic 0 = DGND, Logic 1 = VLS, ADC_SDOUT C LOAD = 15 pF.)Notes:17.After powering up the CS42438, RST should be held low after the power supplies and clocks are settled.18.See Table 7 on page 43 for suggested MCLK frequencies.19.VLS is limited to nominal 2.5 V to 5.0V operation only.20.ADC does not meet timing specification for Quad-Speed Mode.Parameters Symbol Min Max UnitsSlave ModeRST pin Low Pulse Width(Note 17)1-ms MCLK Frequency 0.51250MHz MCLK Duty Cycle(Note 18)4555%Input Sample Rate (FS pin)Single-Speed ModeDouble-Speed Mode (Note 19)Quad-Speed Mode (Note 20)F s F s F s 45010050100200kHz kHz kHz SCLK Duty Cycle 4555%SCLK High Time t sckh 8-ns SCLK Low Timet sckl 8-ns FS Rising Edge to SCLK Rising Edge t fss 5-ns SCLK Rising Edge to FS Falling Edget fsh 16-ns DAC_SDIN Setup Time Before SCLK Rising Edge t ds 3-ns DAC_SDIN Hold Time After SCLK Rising Edge t dh 5-ns DAC_SDIN Hold Time After SCLK Rising Edge t dh15-ns ADC_SDOUT Hold Time After SCLK Rising Edge t dh210-ns ADC_SDOUT Valid Before SCLK Rising Edget dval15-nsFigure 5. TDM Serial Audio Interface Timing。

33811资料

12 11 10 9
Figure 3. 33811 Pin Connections Table 1. 33811 Pin Definitions A functional description of each pin can be found in the Functional Pin Description section beginning on page 11.
元器件交易网
PIN CONNECTIONS
PIN CONNECTIONS
VDD D_GND SO SI CS SCLK RESET VSPI 1 2 3 4 5 6 7 8 16 15 14
13
A_GND N/C SOLM1 SOLM2 SOLM3 SOLM4 SOLM5 VPWR
33811
SOLENOID MONITOR
EG SUFFIX (PB_FREE) 98ASB42567B 16-PIN SOICW
ORDERING INFORMATION
Device PCZ33811EG/R2 Temperature Range (TA) -40°C to 125°C Package 16 SOICW
© Freescale Semiconductor, Inc., 2007. All rights reserved.
元器件交易网
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
VPWR VDD
VPWR, VDD, 5.0 V Oscillator and Clock Generator
Pin Number 1 2 3 Pin Name VDD D_GND SO Pin Function Power Ground Output Formal Name Digital Voltage Supply Digital Ground Serial Output Data Definition The VDD pin is the digital logic supply voltage used internally in the IC. Digital ground for the internal control circuits of the IC. This ground should be used for decoupling of the VDD supply. The SO output pin is used to transmit serial data from the device to the MCU. The SO pin remains tri-state until selected by the active low CS. The serial output data is available to be latched by the MCU on the rising edge of SCLK. The SO data transitions on falling edge of the SCLK. The SI input pin is used to receive serial data from the MCU. The serial input data is latched on the rising edge of SCLK, and the input data transitions on the falling edge of SCLK. The Chip Select input pin is an active low signal sent by the MCU to indicate that the device is being addressed. This input requires CMOS logic levels and has an internal active pull-up current source. The SCLK input pin is used to clock in and out the serial data on the SI and SO pins while being addressed by the CS. The SCLK signal consists of a 50% duty cycle with CMOS logic levels. Input data is latched by the device on the rising edge of SCLK while output data is changed on the falling edge. SCLK is ignored by the device while CS is high. The RESET pin, when pulled high, clears any fault bits and causes the Serial Output pin to be tri-stated. The RESET pin operates at the CMOS levels dictated by the VDD line and the state of the VSPI pin. The VSPI pin determines the voltage levels for the SPI interface. It must be connected to the same voltage supply (+5 volts or +3.3 Volts) as the MCU’s SPI interface.

ERJ-S08F2432V中文资料(panasonic)中文数据手册「EasyDatasheet - 矽搜」

× Resistance Values, or Limiting Element Voltage × Power Rating or max. Overload Voltage listed above
Type
（英制）
ERJS6S (0805) ERJS6Q (0805)
PowerRating电阻
在70℃下公差
Ambient Temperature (°C)
Type: ERJ S02,S03,S06,S08,S14中 S12中,S1D,S1T（Au类内电极型）
Type: ERJ S6S,S6Q（银钯基内电极型）
Type: ERJ U01, U02, U03, U06, U08, U14, U12,U1D,U1T（银钯基内电极型）
■ 特征
● 高抗硫化通过采用金基内电极来实现（ERJS0 / S1型）
ERJS1T ERJU1T (2512)
额定功率
在70℃下 (W) 0.05 0.1
0.1
0.125
0.25
0.5
0.75
0.75
1.0
限制因素电压
(V) 25 50
75
150
200
200
200
200
200
极大超载电压
(V) 50 100
150
200
400
400
500
500
500
抵抗性公差
Example: 222 2.2 k, 1002 10 k
Packaging Methods
Code Packaging C 2 mPrmesspeitdchC,a1r5ri,e0r0T0appcins.g

AN6612中文资料

元器件交易网
ICs for Motor
AN6612, AN6612S
Motor Control Circuits
s Overview
The AN6612 and the AN6612S are the electronic governor circuits suitable for the rotating speed control of a low voltage and compact DC motor which is used for a small tape recorder, etc.
2.54
6
0.5±0.1 1.2±0.25
元器件交易网
AN6612, AN6612S
s Pin Descriptions
Pin No. 1 2 3 4 Pin Name Current Sensor Reference Voltage Control VCC Pin No. 5 6 7 8 GND Base Output Base Motor pin Pin Name
ICs for Motor
s Absolute Maximum Ratings (Ta= 25˚C)
Parameter Supply Voltage Supply Current Power Dissipation AN6612 AN6612S AN6612 AN6612S Symbol VCC I4 PD Topr Tstg Rating 10 5 400 200 –20 ~ + 75 –40 ~ +150 –40 ~ +125 Unit V mA mW ˚C ˚C
s Application Circuit
0.5Ω M 10Ω Motor

8002301FA中文资料

Copyright © 1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date.PACKAGING INFORMATIONOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)5962-7603701VEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 5962-7603701VFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 5962-7603701VFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 7603701EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 7603701EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 7603701FA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 7603701FA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 76038012A ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC 76038012A ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC 7603801EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 7603801EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 7603801FA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 7603801FA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 8002301EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 8002301EA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC 8002301FA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC 8002301FA ACTIVE CFP W161TBD Call TI Level-NC-NC-NCJM38510/07906BEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NCJM38510/07906BEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NCJM38510/07906BFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NCJM38510/07906BFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NCJM38510/30906B2A ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NCJM38510/30906B2A ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NCJM38510/30906BEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NCJM38510/30906BEA ACTIVE CDIP J161TBD Call TI Level-NC-NC-NCJM38510/30906BFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NCJM38510/30906BFA ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SN54LS257BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54LS257BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54LS258BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54LS258BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54S257J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54S257J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54S258J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN54S258J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SN74LS257BD ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BD ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BDE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BDE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)SN74LS257BDR ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BDR ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BDRE4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BDRE4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BN ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS257BN ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NC SN74LS257BN3OBSOLETE PDIP N16TBD Call TI Call TISN74LS257BN3OBSOLETE PDIP N16TBD Call TI Call TISN74LS257BNE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS257BNE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS257BNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS257BNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BD ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BD ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BDE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BDE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BDR ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BDR ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BDRE4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BDRE4ACTIVE SOIC D162500Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BN ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS258BN ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS258BN3OBSOLETE PDIP N16TBD Call TI Call TISN74LS258BN3OBSOLETE PDIP N16TBD Call TI Call TISN74LS258BNE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74LS258BNE4ACTIVE PDIP N1625Pb-Free CU NIPDAU Level-NC-NC-NCOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)(RoHS)SN74LS258BNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BNSR ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74LS258BNSRE4ACTIVE SO NS162000Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S257D ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S257D ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S257DE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S257DE4ACTIVE SOIC D1640Green(RoHS&no Sb/Br)CU NIPDAU Level-1-260C-UNLIMSN74S257N ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74S257N ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NC SN74S257N3OBSOLETE PDIP N16TBD Call TI Call TISN74S257N3OBSOLETE PDIP N16TBD Call TI Call TISN74S257NE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NCSN74S257NE4ACTIVE PDIP N1625Pb-Free(RoHS)CU NIPDAU Level-NC-NC-NC SN74S258DR OBSOLETE SOIC D16TBD Call TI Call TISN74S258DR OBSOLETE SOIC D16TBD Call TI Call TISN74S258N OBSOLETE PDIP N16TBD Call TI Call TISN74S258N OBSOLETE PDIP N16TBD Call TI Call TISN74S258N3OBSOLETE PDIP N16TBD Call TI Call TISN74S258N3OBSOLETE PDIP N16TBD Call TI Call TISNJ54LS257BFK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54LS257BFK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54LS257BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54LS257BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54LS257BW ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54LS257BW ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54LS258BFK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54LS258BFK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54LS258BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54LS258BJ ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54LS258BW ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54LS258BW ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54S257FK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54S257FK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NCOrderable Device Status(1)PackageType PackageDrawingPins PackageQtyEco Plan(2)Lead/Ball Finish MSL Peak Temp(3)SNJ54S257J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54S257J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54S257W ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54S257W ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54S258FK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54S258FK ACTIVE LCCC FK201TBD Call TI Level-NC-NC-NC SNJ54S258J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54S258J ACTIVE CDIP J161TBD Call TI Level-NC-NC-NC SNJ54S258W ACTIVE CFP W161TBD Call TI Level-NC-NC-NC SNJ54S258W ACTIVE CFP W161TBD Call TI Level-NC-NC-NC (1)The marketing status values are defined as follows:ACTIVE:Product device recommended for new designs.LIFEBUY:TI has announced that the device will be discontinued,and a lifetime-buy period is in effect.NRND:Not recommended for new designs.Device is in production to support existing customers,but TI does not recommend using this part in a new design.PREVIEW:Device has been announced but is not in production.Samples may or may not be available.OBSOLETE:TI has discontinued the production of the device.(2)Eco Plan-The planned eco-friendly classification:Pb-Free(RoHS)or Green(RoHS&no Sb/Br)-please check /productcontent for the latest availability information and additional product content details.TBD:The Pb-Free/Green conversion plan has not been defined.Pb-Free(RoHS):TI's terms"Lead-Free"or"Pb-Free"mean semiconductor products that are compatible with the current RoHS requirements for all6substances,including the requirement that lead not exceed0.1%by weight in homogeneous materials.Where designed to be soldered at high temperatures,TI Pb-Free products are suitable for use in specified lead-free processes.Green(RoHS&no Sb/Br):TI defines"Green"to mean Pb-Free(RoHS compatible),and free of Bromine(Br)and Antimony(Sb)based flame retardants(Br or Sb do not exceed0.1%by weight in homogeneous material)(3)MSL,Peak Temp.--The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications,and peak solder temperature.Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.TI bases its knowledge and belief on information provided by third parties,and makes no representation or warranty as to the accuracy of such information.Efforts are underway to better integrate information from third parties.TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary,and thus CAS numbers and other limited information may not be available for release.In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s)at issue in this document sold by TI to Customer on an annual basis.元器件交易网IMPORTANT NOTICETexas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. T esting and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed.TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. T o minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards.TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI.Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation.Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions:Products ApplicationsAmplifiers Audio /audioData Converters Automotive /automotiveDSP Broadband /broadbandInterface Digital Control /digitalcontrolLogic Military /militaryPower Mgmt Optical Networking /opticalnetwork Microcontrollers Security /securityTelephony /telephonyVideo & Imaging /videoWireless /wirelessMailing Address:Texas InstrumentsPost Office Box 655303 Dallas, Texas 75265Copyright 2005, Texas Instruments Incorporated。

13368资料

31700 Hicks Road • Rolling Meadows, IL 60008 USAT elephone: 847.392.3500 • Fax: 847.392.9404email: mcpsales@ • Web Page: Connector Products PART NUMBER CODING X XX 68 X - XX X DIELECTRIC INSULATION 00=INDICATES I/O CONNECTORS(CONSULT FACTORY)L =LABEL RECESS (OMIT INDICATES NO LABEL)68=NUMBER OF CONTACTS: 68, 8833= 3.3MM BACK 50= 5.0MM BACK 1=TYPE I2=TYPE II Note: Consult factory for board layout Type I & Type II Frame Kit - Sonic WeldedFeaturesMethode/Duel Systems offers reliable, sonic weldedsolutions for your most demanding PC card applications.All Methode/Duel Systems packages feature two-pieceassembly, stainless steel covers and flexible assemblyoptions.Benefits Methode/Duel Systems have a number of design advantages for PC card packages including:s A 10 second cycle time s Low tooling cost on custom design packages including Type II extended back and Type III packages s Reduced per-unit assembly costs s Increased package strength. (The circuit board is not used as part of the package strength) This minimizes stress on the board and potential damage to sensitive board components.s Packages available with or without a label recess s Accepts various PC board thicknessess Accommodates most 68 or 88 pin connectorss Accepts most I/O connectorss Increased interior real estate 86331I E P Y T M M 3.3N I P 86LA N O I T P O L 86331I E P Y T M M 3.3NI P 86L E B A L ()S S E C E R LA N O I T P O -86332I I E P Y T M M 3.3N I P 86LA N O I T P O -L 86332I I E P Y T M M 3.3NI P 86L E B A L ()S S E C C A LA N O I T P O -86052I I E P Y T M M 0.5N I P 86LA N O I T P O -L 86052I I E P Y T M M 0.5NI P 86L E B A L ()S S E C C A LA N O I T P O -86052M I I E P Y T M M 0.5M O T S U C LA N O I T P O .O N T R A P E P Y T D N E K C AB S S E N KC I H T T N O R F R O T C E N N O C O/I R A E R NO I T P O 元器件交易网。

1935187资料

Extract from the online catalogThe illustration shows a 15-position version Printed circuit terminal block, nominal current: 16 A, rated voltage: 250 V, pitch: 5.0 mm, no. of positions: 4, mounting: Soldering, type of connection: Screw connection, connection direction from the conductor to the PCB: 0°Order No.1935187Ord designation PT 1,5/ 4-5,0-H Catalog page information Page 308 (CC-2005) Technical dataTightening torque, min 0.4 NmTechnical dataInsulating material group IRated surge voltage (III/3) 4 kV Rated surge voltage (III/2) 4 kV Rated surge voltage (II/2) 4 kV Rated voltage (III/2) 320 V Rated voltage (II/2) 630 V Connection in acc. with standard EN-VDE16 A Nominal current IN250 V Nominal voltage UNNominal cross section 1.5 mm²Maximum load current 16 A Insulating material PA Inflammability class acc. to UL 94 V0 Internal cylindrical gage A1 Stripping length 5 mm Connection dataConductor cross section, rigid min. 0.2 mm²Conductor cross section, rigid max. 2.5 mm²Conductor cross section flexible min. 0.2 mm²Conductor cross section, flexible max. 2.5 mm²0.25 mm²Conductor cross section flexible, with ferrule withoutplastic sleeve min.Conductor cross section flexible, with ferrule without1.5 mm²plastic sleeve max.0.25 mm²Conductor cross section flexible, with ferrule with plasticsleeve min.1.5 mm²Conductor cross section flexible, with ferrule with plasticsleeve max.Conductor cross section AWG/kcmil min. 26 Conductor cross section AWG/kcmil max 142 conductors with same cross section, solid min. 0.2 mm²2 conductors with same cross section, solid max. 0.75 mm²2 conductors with same cross section, flexible, min. 0.2 mm²2 conductors with same cross section, flexible max. 0.75 mm²0.25 mm²2 conductors with same cross section, flexible, ferruleswithout plastic sleeve min.0.34 mm²2 conductors with same cross section, flexible, ferruleswithout plastic sleeve, max.2 conductors with same cross section, flexible, TWIN0.5 mm²ferrules with plastic sleeve, min.2 conductors with identical cross section, flexible TWIN0.75 mm²ferrules with plastic sleeve, max.CertificatesCUL300 V Nominal voltage UNNominal current I10 ANAWG/kcmil 26-12 Nominal voltage U300 VNNominal current I15 ANAWG/kcmil 26-12300 V Nominal voltage UN16 A Nominal current INAWG/kcmil 26-12 UL300 V Nominal voltage UNNominal current I10 ANAWG/kcmil 26-12300 V Nominal voltage UNNominal current I15 ANAWG/kcmil 26-12300 V Nominal voltage UNNominal current I16 ANAWG/kcmil 26-12Drawings Drilling diagramDimensioned drawingApproval logoAccessoriesItem Designation DescriptionMarking0804183SK 5/3,8:FORTL.ZAHLEN Marker card, printed horizontally, self-adhesive, 12 identicaldecades marked 1-10, 11-20 etc. up to 91-(99)100, sufficient for120 terminal blocksTools1205053SZS 0,6X3,5Screwdriver, bladed, matches all screw terminal blocks up to 4.0mm² connection cross section, blade: 0.6 x 3.5 mm, without VDEapprovalAddressPHOENIX CONTACT GmbH & Co. KG Flachsmarktstr. 832825 BlombergGermanyPhone +49 5235 3 00Fax +49 5235 3 41200 Phoenix ContactTechnical modifications reserved;。

ISL88731CHRTZ-T;ISL88731CHRTZ;ISL88731CEVAL2Z;中文规格书,Datasheet资料

SMBus Level 2 Battery ChargerISL88731CThe ISL88731C is a highly integrated Lithium-ion battery charger controller, programmable over the SMBus system management bus (SMBus). The ISL88731C is intended to be used in a smart battery charger (SBC) within a smart battery system (SBS) that throttles the charge power such that the current from the AC-adapter is automatically limited. Highefficiency is achieved with a DC/DC synchronous-rectifier buck converter, equipped with diode emulation for enhanced light load efficiency and system bus boosting prevention. The ISL88731C charges one to four Lithium-ion series cells, and delivers up to 8A charge current. Integrated MOSFET drivers and bootstrap diode result in fewer components and smaller implementation area. Low offset current-sense amplifiers provide high accuracy with 10m Ω sense resistors. The ISL88731C provides 0.5% end-of-charge battery voltage accuracy.The ISL88731C provides a digital output that indicates the presence of the AC adapter as well as an analog output which indicates the adapter current within 4% accuracy.The ISL88731C is available in a small 5mmx5mm 28Ld Thin (0.8mm) QFN package. An evaluation kit is available to reduce design time. The ISL88731C is available in Pb-Free packages.Related Literature•See AN1404 for “ISL88731EVAL2Z and ISL88731CEVAL2Z Evaluation Boards Setup Procedure”Features•0.5% Battery Voltage Accuracy •3% Adapter Current Limit Accuracy •3% Charge Current Accuracy •SMBus 2-Wire Serial Interface •Battery Short Circuit Protection •Fast Response for Pulse-Charging •Fast System-Load Transient Response •Monitor Outputs-Adapter Current (3% Accuracy)-AC-Adapter Detection •11-Bit Battery Voltage Setting•6 Bit Charge Current/Adapter Current Setting •8A Maximum Battery Charger Current •11A Maximum Adapter Current •+8V to +26V Adapter Voltage Range •Pb-Free (RoHS Compliant)Applications•Notebook Computers •Tablet PCs•Portable Equipment with Rechargeable BatteriesFIGURE 1.TYPICAL CHARGING VOLTAGE AND CURRENTFIGURE 2.EFFICIENCY vs CHARGE CURRENT AND BATTERYVOLTAGECHARGE TIME (MINUTES)10.010.511.011.512.012.513.0020406080100120140160B A T T E R Y V O L T A G E0.00.51.01.52.02.53.03.5BATTERY CURRENTVCHG (V)ICHG (A)808590951000.01.02.03.04.05.06.07.08.0I OUT (A)E F F I C I E N C Y (%)8.4V BATTERY12.6V BATTERY 16.8V BATTERY 4.2V BATTERYFIGURE 3.FUNCTIONAL BLOCK DIAGRAMPHASEBOOT UGATE LGATEPGNDISL88731CCSSN CSSP CSOP CSON ACIN SCL VREFDCINSDA VDDSMBICM ICOMP VCOMP VCCACOK VDDP GNDAC ADAPTERTO BATTERYTO SYSTEMH O S TVFB RS1RS2AGNDPGNDAGNDFIGURE 4.TYPICAL APPLICATION CIRCUITPin ConfigurationISL88731C (28 LD TQFN)TOP VIEWC S S PC S S N V C CB O O TU G A T E P H A S E D C I N I C MS D AS C LV D D S M BG N DA C O KN CNC ACIN VREF ICOMPNC VCOMPNCVDDP LGATE PGND CSOP CSON NC VFB12345672120191817161528272625242322891011121314PDFunctional Pin DescriptionsPIN NUMBERSYMBOL DESCRIPTION2ACIN AC Adapter Detection Input. Connect to a resistor divider from the AC adapter output. Range zero to 5.5V.3VREF Reference Voltage output. Range 3.168V to 3.232V. It is internally compensated. Do not connect a decoupling capacitor.4ICOMP Compensation Point for the charging current and adapter current regulation Loop. Connect 0.01µF to GND. See “Voltage Control Loop” on page 21 for details on selecting the ICOMP capacitor. Range zero to 5.5V.6VCOMP Compensation Point for the voltage regulation loop. Connect 4.7k Ω in series with 0.01µF to GND. See “Voltage Control Loop” on page 21 for details on selecting VCOMP components. Range zero to 5.5V.8ICM Input Current Monitor Output. ICM voltage equals 20 x (V CSSP - V CSSN ). Range zero to 3V.9SDA SMBus Data I/O. Open-drain Output. Connect an external pull-up resistor according to SMBus specifications. Range zero to 5.5V.10SCL SMBus Clock Input. Connect an external pull-up resistor according to SMBus specifications. Range zero to 5.5V.11VDDSMB SMBus interface Supply Voltage Input. Bypass with a 0.1µF capacitor to GND. Range 3.3V to 5.5V.12GND Analog Ground. Connect directly to the backside paddle. Connect to the backside paddle and PGND at one point close to (under) the IC.13ACOK AC Detect Output. This open drain output is high impedance when ACIN is greater than 3.2V. The ACOK output remains low when the ISL88731C is powered down. Connect a 10k pull-up resistor from ACOK to VDDSMB. Range 3.3V to 5.5V.15VFB Feedback for the Battery Voltage. Range 1V to 19V.17CSON Charge Current-Sense Negative Input. Range 1V to 19V.18CSOP Charge Current-Sense Positive Input. Range 1V to 19V.19PGND Power Ground. Connect PGND to the source of the low side MOSFET and the negative side of capacitors to the charger output and the drain of the upper switching FET. Connect this area to the Backside paddle at one location very near (under) the IC.20LGATELow-Side Power MOSFET Driver Output. Connect to low-side N channel MOSFET. LGATE drives between VDDP and PGND. Range is -0.3V to 5.23V.21VDDPLinear Regulator Output. VDDP is the output of the 5.2V linear regulator supplied from DCIN. VDDP also directlysupplies the LGATE driver and the BOOT strap diode. Bypass with a 1µF ceramic capacitor from VDDP to PGND. Range is 5.0V to 5.23V.22DCIN Charger Bias Supply Input. Bypass DCIN with a 0.1µF capacitor to GND. Range 8V to +26V.23PHASE High-Side Power MOSFET Driver Source Connection. Connect to the source of the high-side N-Channel MOSFET. Range -2V to +26V.24UGATE High-Side Power MOSFET Driver Output. Connect to the high-side N-channel MOSFET gate. Range -2V to +33V.25BOOT High-Side Power MOSFET Driver Power-Supply Connection. Connect a 0.1µF capacitor from BOOT-to-PHASE. Range -2V to +33V.26VCC Power input for internal analog circuits. Connect a 4.7Ω resistor from VCC to VDDP and a 1µF ceramic capacitor from VCC to ground. Range 4V to 5.23V.27CSSN Input Current-Sense Negative Input. Range 8V to 26V.28CSSP Input Current-Sense Positive Input. Range 8V to 26V.PDConnect the backside paddle to GND. This pad has the lowest thermal resistance to the die. It should be connected to a large area of ground with 3 to 5 vias for good thermal performance. The recommended potential of the thermal pad is zero (0) Volts.1, 5, 7, 14, 16NCNo Connect. Pins are not connected internally.Ordering InformationPART NUMBER (Notes 1, 2, 3)PART MARKINGTEMP RANGE(°C)PACKAGE (Pb-Free)PKG.DWG. #ISL88731CHRTZ 88731C HRTZ -10 to +10028 Ld 5x5 TQFNL28.5x5BISL88731CEVAL2Z Evaluation BoardNOTES:1.Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.2.These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.3.For Moisture Sensitivity Level (MSL), please see device information page for ISL88731C . For more information on MSL please see tech brief TB363.Functional Pin Descriptions (Continued)PIN NUMBERSYMBOL DESCRIPTIONTable of ContentsAbsolute Maximum Ratings (6)Thermal Information (6)Electrical Specifications (6)SMBus Timing Specifications (8)Typical Operating Performance (9)Theory of Operation (11)Introduction (11)PWM Control (11)AC-Adapter Detection (11)Current Measurement (11)VDDP Regulator (11)VDDSMB Supply (11)Short Circuit Protection and 0V Battery Charging (11)Undervoltage Detect and Battery Trickle Charging (11)Over-Temperature Protection (12)Overvoltage Protection (12)The System Management Bus (12)General SMBus Architecture (12)Data Validity (12)START and STOP Conditions (12)Acknowledge (13)SMBus Transactions (13)Byte Format (13)ISL88731C and SMBus (13)Battery Charger Registers (14)Enabling and Disabling Charging (14)Setting Charge Voltage (14)Setting Charge Current (15)Setting Input-Current Limit (16)Charger Timeout (17)ISL88731C Data Byte Order..................................................17Writing to the Internal Registers.. (17)Reading from the Internal Registers (17)Application Information (17)Inductor Selection (17)Output Capacitor Selection (18)MOSFET Selection (18)Snubber Design (19)Input Capacitor Selection (19)Loop Compensation Design (19)Transconductance Amplifiers GMV, GMI and GMS (19)PWM Gain Fm (19)Charge Current Control Loop (20)Adapter Current Limit Control Loop (20)Voltage Control Loop (21)Output LC Filter Transfer Functions (21)Compensation Break Frequency Equations (22)PCB Layout Considerations (22)Power and Signal Layers Placement on the PCB (22)Component Placement (22)Signal Ground and Power Ground Connection (22)GND and VCC Pin (22)LGATE Pin (22)PGND Pin (22)PHASE Pin (23)UGATE Pin (23)BOOT Pin (23)CSOP, CSON, CSSP and CSSN Pins (23)DCIN Pin (23)Copper Size for the Phase Node (23)Identify the Power and Signal Ground (23)Clamping Capacitor for Switching MOSFET (23)Revision History (24)Products (24)Package Outline Drawing (25)Absolute Maximum Ratings Thermal InformationDCIN, CSSP, CSSN, CSOP, CSON, VFB . . . . . . . . . . . . . . . . . . .-0.3V to +28V CSSP-CSSN, CSOP-CSON, PGND-GND . . . . . . . . . . . . . . . . . . -0.3V to +0.3V PHASE to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -6V to +30V BOOT to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +33V BOOT to PHASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V UGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PHASE - 0.3V to BOOT + 0.3V LGATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PGND - 0.3V to VDDP + 0.3V ICOMP, VCOMP, VREF, to GND. . . . . . . . . . . . . . . . . . . . .-0.3V to VCC + 0.3V VDDSMB, SCL, SDA, ACIN, ACOK . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +6V VDDP, ICM, VCC to GND, VDDP to PGND . . . . . . . . . . . . . . . . . .-0.3V to +6V Thermal Resistance (Typical)θJA (°C/W)θJC (°C/W) 28 Ld TQFN Package (Notes 4, 5) . . . . . . . 38 6.5 Junction Temperature Range . . . . . . . . . . . . . . . . . . . . . . .-55°C to +150°C Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below /pbfree/Pb-FreeReflow.aspCAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.NOTES:4.θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See TechBrief TB379.5.For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.Electrical Specifications DCIN = CSSP = CSSN = 18V, CSOP = CSON = 12V, VDDP = 5V, BOOT-PHASE = 5.0V, GND = PGND = 0V, CVDDP=1µF, IVDDP = 0mA, T A = -10°C to +100°C. Boldface limits apply over the operating temperature range, -10°C to +100°C.PARAMETER CONDITIONSMIN(Note 7)TYPMAX(Note 7)UNITSCHARGE VOLTAGE REGULATIONBattery Full Charge Voltage and Accuracy ChargeVoltage = 0x41A016.71616.816.884V-0.50.5%ChargeVoltage = 0x313012.52912.59212.655V-0.50.5%ChargeVoltage = 0x20D08.3508.48.450V-0.60.6%ChargeVoltage = 0x1060 4.163 4.192 4.221V-0.70.7% Battery Undervoltage Lockout Trip Point forTrickle ChargeVFB rising 2.55 2.7 2.85VBattery Undervoltage Lockout Trip PointHysteresis100250400mV CHARGE CURRENT REGULATIONCSOP to CSON Full-ScaleCurrent-Sense Voltage78.2280.6483.06mVCharge Current and Accuracy RS2 = 10mΩ (see Figure4)ChargingCurrent = 0x1f80 7.8228.0648.306A -33%RS2 = 10mΩ (see Figure4) ChargingCurrent = 0x0f803.809 3.968 4.126A -44%RS2 = 10mΩ (see Figure4)ChargingCurrent = 0x008064128220mA Charge Current Gain Error Based on charge current = 128mA and 8.064A-1.6 1.4% CSOP/CSON Input Voltage Range019VBattery Quiescent CurrentAdapter present, not charging,I CSOP + I CSON + I PHASE + I CSSP + I CSSN + I FB V PHASE = V CSON = V CSOP = V DCIN = 19V, V ACIN = 5V135200µAAdapter AbsentI CSOP + I CSON + I PHASE + I CSSP + I CSSN + I FB V PHASE = V CSON = V CSOP = 19V, V DCIN = 0V-10.22µAAdapter Quiescent CurrentI DCIN + I CSSP + I CSSNVadapter = 8V to 26V, Vbattery 4V to 16.8V35mAINPUT CURRENT REGULATIONCSSP to CSSN Full-Scale Current-Sense VoltageCSSP = 19V106.7110113.3mV Input Current AccuracyRS1 = 10m Ω (see Figure 4)Adapter Current = 11004mA or 3584mA -33%RS1 = 10m Ω (see Figure 4)Adapter Current = 2048mA-55%Input Current Limit Gain Error Based on InputCurrent = 1024mA and 11004mA-1.5 1.5%Input Current Limit Offset -11mV CSSP/CSSN Input Voltage Range 826V ICM Gain V CSSP-CSSN = 110mV 20V/V ICM AccuracyV CSSP-CSSN = 110mV -2.5 2.5%V CSSP-CSSN = 55mV or 35mV -44%V CSSP-CSSN = 20mV-88%ICM Max Output CurrentV CSSP-CSSN = 0.1V500µASUPPLY AND LINEAR REGULATORDCIN, Input Voltage Range 826V VDDP Output Voltage 8.0V < V DCIN < 28V, no load 5.05.1 5.23V VDDP Load Regulation 0 < I VDDP < 30mA35100mV VDDSMB Range 2.7 5.5V VDDSMB UVLO Rising 2.4 2.5 2.6V VDDSMB UVLO Hysteresis 40100150mV VDDSMB Quiescent CurrentVDDP = SCL = SDA = 5.5V 2027µAV REFERENCEVREF Output Voltage0 < I VREF < 300µA3.1683.23.232VACOKACOK Sink Current V ACOK = 0.4V, ACIN = 1.5V 28mA ACOK Leakage CurrentV ACOK = 5.5V, ACIN = 3.7V1µAACINACIN rising Threshold 3.15 3.2 3.25V ACIN Threshold Hysteresis 406090mV ACIN Input Bias Current-11µAPARAMETERCONDITIONSMIN (Note 7)TYP MAX (Note 7)UNITSSWITCHING REGULATORFrequency330400440kHz BOOT Supply Current UGATE High170290400µA PHASE Input Bias Current V DCON = 28V, V CSON = V PHASE = 20V 02µA UGATE On-Resistance Low I UGATE = -100mA 0.9 1.6ΩUGATE On-Resistance High I UGATE = 10mA 1.4 2.5ΩLGATE On-Resistance High I LGATE = +10mA 1.4 2.5ΩLGATE On-Resistance Low I LGATE = -100mA0.9 1.6ΩDead TimeFalling UGATE to rising LGATE or falling LGATE to rising UGATE355080nsERROR AMPLIFIERSGMV Amplifier Transconductance 200250300µA/V GMI Amplifier Transconductance 405060µA/V GMS Amplifier Transconductance 405060µA/V GMI/GMS Saturation Current 152125µA GMV Saturation Current 101730µA ICOMP, VCOMP Clamp Voltage0.25V < V ICOMP, VCOMP < 3.5V200300400mVLOGIC LEVELSSDA/SCL Input Low Voltage VDDSMB = 2.7V to 5.5V 0.8V SDA/SCL Input High Voltage VDDSMB = 2.7V to 5.5V 2V SDA/SCL Input Bias Current VDDSMB = 2.7V to 5.5V -11µA SDA, Output Sink CurrentV SDA = 0.4V715mAPARAMETERCONDITIONSMIN (Note 7)TYPMAX (Note 7)UNITSSMBus Timing SpecificationsVDDSMB = 2.7V to 5.5V.PARAMETERSYMBOL CONDITIONSMIN TYPMAX UNITS SMBus Frequency FSMB 10100kHz Bus Free Timet BUF 4.7µs Start Condition Hold Time from SCL t HD:STA 4µs Start Condition Setup Time from SCL t SU:STA 4.7µs Stop Condition Setup Time from SCL t SU:STO 4µs SDA Hold Time from SCL t HD:DAT 300ns SDA Setup Time from SCL t SU:DAT 250ns SCL Low Timeout (Note 6)t TIMEOUT 222530ms SCL Low Period t LOW 4.7µs SCL High Periodt HIGH4µs Maximum Charging Period without an SMBus Write to ChargeVoltage or ChargeCurrent Register 140180220sNOTES:6.If SCL is low for longer than the specified time, the charger is disabled.7.Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization and are not production tested.Typical Operating PerformanceDCIN = 20V, 3S2P Li-Battery, T A = +25°C, unless otherwise noted.FIGURE 5.VDD LOAD REGULATION FIGURE 6.VREF LOAD REGULATIONFIGURE 7.ICM ACCURACY vs AC-ADAPTER CURRENT FIGURE 8.TYPICAL CHARGING VOLTAGE AND CURRENTFIGURE 9.CHARGE ENABLE FIGURE 10.CHARGE DISABLE4.854.904.955.005.055.105.15020406080100VDDP LOAD CURRENT (mA)V D D P (V )3.173.183.193.203.213.223.23050100150200I VREF (µA)V R E F (V )-1.0%-0.5%0.0%0.5%1.0%-15-10-5051015123567AC-ADAPTER CURRENT (A)I C M A C C U R A C Y (%)4810.010.511.011.512.012.513.0020406080100120140160TIME (MINUTES)B A T T E R Y V O L T A G E0.00.51.01.52.02.53.03.5BATTERY CURRENTVCHG (V)ICHG (A)VCOMP ICOMPINDUCTOR CURRENTCHARGE CURRENTVCOMPICOMP INDUCTOR CURRENTCHARGE CURRENTFIGURE 11.SWITCHING WAVEFORMS AT DIODE EMULATION FIGURE 12.SWITCHING WAVEFORMS IN CC MODEFIGURE 13.BATTERY REMOVAL FIGURE 14.BATTERY INSERTIONFIGURE 15.LOAD TRANSIENT RESPONSEFIGURE 16.EFFICIENCY vs CHARGE CURRENT AND BATTERYVOLTAGETypical Operating PerformanceDCIN = 20V, 3S2P Li-Battery, T A = +25°C, unless otherwise noted. (Continued)UGATELGATEINDUCTOR CURRENTPHASEUGATELGATEINDUCTOR CURRENTPHASECSON/V BATTERYBATTERY CURRENTBATTERY CURRENTCSON/V BATTERYSYSTEM LOAD BATTERY VOLTAGE CHARGE CURRENTADAPTER CURRENT808590951000.01.02.03.04.05.06.07.08.0I OUT (A)E F F I C I E N C Y (%)8.4V BATTERY12.6V BATTERY 16.8V BATTERY 4.2V BATTERY分销商库存信息:INTERSILISL88731CHRTZ-T ISL88731CHRTZ ISL88731CEVAL2Z。

66155-101中文资料

61055SILICON PHOTOTRANSISTOR “PILL PACK” (TYPE GS1020)Mii OPTOELECTRONIC PRODUCTSDIVISIONREVISION B 02/22/01Features:• Hermeticallysealed• Highsensitivity• Smallpackage•Suitable for high-density pc board mounting •Spectrally matched to the 62000 Series LED.A pplications:• IncrementalEncoding • ReflectiveSensors • PositionSensors • LevelSensorsDESCRIPTIONThe 61055 is an N-P-N Planar Silicon Transistor in a package designed to be mounted in a double-clad printed circuit board. It is available in a range of sensitivities and is lensed for minimum response to stray light. High sensitivity, low dark current leakage, and low saturation voltage make this device ideal for interfacing with TTL circuits. Available custom binned to customer specifications or screened to MIL-PRF-19500.ABSOLUTE MAXIMUM RATINGSStorage Temperature..........................................................................................................................................-65°C to +150°C Operating Temperature ....................................................................................................................................-55°C to +125°C Collector-Emitter Voltage.. (50V)Emitter-Collector Voltage (6V)Power Dissipation (Derate at the rate of 0.5 mW/°C above 25°C)....................................................................................50mWELECTRICAL CHARACTERISTICS T A = 25°C unless otherwise specified.PARAMETER SYMBOL MIN TYP MAXUNITSTEST CONDITIONSNOTELight Current 61055-X0161055-X02 61055-X03 61055-X04 61055-X05 61055-X06I L0.52.04.07.012.020.0 3.05.08.012.020.0--mAV CE = 5.0V, H = 20Mw/cm 21Dark Current61055-XXXI D25nA V CE = 30V, H = 01Collector-Emitter Breakdown Voltage 61055-XXX BV CEO50V I C = 100µA Emitter-Collector Breakdown Voltage 61055-XXX BV ECO7VI E = 100µA Light Current Rise Time 61055-X01 61055-X02 61055-X03 61055-X04 61055-X05 61055-X06t r2.03.05.07.09.012.0 12.020.0--µsecR L = 1K Ω, V CC = 5V,I L = 1.0mASaturation Voltage61055-X0XV CE (sat)0.3V I C = 0.4mA, H = 20mW/cm 2Angular Response 61055-X0Xθ24degreesR L = 1K Ω, V CC = 5V,I L = 1.0mA2NOTES:1. Irradiance in mW/cm 2from a tungsten source at a color temperature of 2870K.2. The angle between incidence for peak response and incidence for 50% of peak response.SELECTION GUIDEPART NUMBER PART DESCRIPTION I L Range 61055-001Silicon Phototransistor in pill package, commercial version0.5 to 3mA 66155-101Silicon Phototransistor in pill package (-55° to +125°C) with 100% screening0.5 to 3mA 61055-002Silicon Phototransistor in pill package, commercial version 2 to 5mA 61055-102Silicon Phototransistor in pill package (-55° to +125°C) with 100% screening 2 to 5mA 61055-003Silicon Phototransistor in pill package, commercial version 4 to 8mA 61055-103Silicon Phototransistor in pill package (-55° to +125°C) with 100% screening 4 to 8mA 61055-004Silicon Phototransistor in pill package, commercial version7 to 12mA 61055-104Silicon Phototransistor in pill package, (-55° to +125°C) with 100% screening7 to 12 mA 61055-005Silicon Phototransistor in pill package, commercial version12to 20mA 61055-105Silicon Phototransistor in pill package, (-55° to +125°C) with 100% screening12 to 20mA 61055-006Silicon Phototransistor in pill package, commercial version20+mA 61055-106Silicon Phototransistor in pill package, (-55° to +125°C) with 100% screening20+mA。

HM-6617883中文资料

March 1997HM-6617/8832K x 8 CMOS PROMFeatures•This Circuit is Processed in Accordance to MIL-STD-883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1.•Low Power Standby and Operating Power-ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA -ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .20mA at 1MHz•Fast Access Time. . . . . . . . . . . . . . . . . . . . . . .90/120ns•Industry Standard Pinout•Single 5.0V Supply•CMOS/TTL Compatible Inputs•High Output Drive . . . . . . . . . . . . . . . .12 LSTTL Loads•Synchronous Operation•On-Chip Address Latches•Separate Output Enable•Operating Temperature Range. . . . . .-55o C to +125o C DescriptionThe HM-6617/883 is a 16,384-bit fuse link CMOS PROM in a 2K word by 8-bit/word format with “Three-State” outputs. This PROM is available in the standard 0.600 inch wide 24 pin SBDIP, the 0.300 inch wide slim SBDIP, and the JEDEC standard 32 pad CLCC.The HM-6617/883 utilizes a synchronous design technique. This includes on-chip address latches and a separate output enable control which makes this device ideal for applications utilizing recent generation microprocessors. This design technique, combined with the Intersil advanced self-aligned silicon gate CMOS process technology offers ultra-low standby current. Low ICCSB is ideal for battery applications or other systems with low power requirements.The Intersil NiCr fuse link technology is utilized on this and other Intersil CMOS PROMs. This gives the user a PROM with permanent, stable storage characteristics over the full industrial and military temperature voltage ranges. NiCr fuse technology combined with the low power characteristics of CMOS provides an excellent alternative to standard bipolar PROMs or NMOS EPROMs.All bits are manufactured storing a logical “0” and can be selectively programmed for a logical “1” at any bit location.Ordering InformationPACKAGE TEMPERATURE RANGE90ns120ns PACKAGE NO. SBDIP-55o C to +125o C HM1-6617B/883HM1-6617B/883D24.6SLIM SBDIP-55o C to +125o C HM6-6617B/883HM6-6617B/883D24.3CLCC-55o C to +125o C HM4-6617B/883HM4-6617B/883J32.A PinoutsHM-6617/883 (SBDIP)TOP VIEW HM-6617/883 (CLCC)TOP VIEW1 2 3 4 5 6 7 89 10 11 1216 17 18 19 20 21 22 23 24 151413A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND V CCA9PGA10Q7Q5Q4Q3A8EQ65678111091312272829262524232221321432313016171819201415A6A5A4A3A2A1A0NCQ0Q1Q2GNDNCQ3Q4Q5VCCNCNCA7NCNCNCA8A9NCGA10EQ7Q6PPIN DESCRIPTIONPIN DESCRIPTIONNC No ConnectA0-A10Address InputsE Chip EnableQ Data OutputV CC Power (+5V)G Output EnableP (Note)Program EnableNOTE:P should be hardwired to V CCexcept during programming.File Number3016.1CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.Functional DiagramLATCHED ADDRESS REGISTERGATED ROW DECODER16128 x 128MATRIX12877AAEAGGA10A9A7A8A6A5A4MSBLLATCHED ADDRESSREGISTERA0A1A2A3GATED COLUMN DECODER AND DATA OUTPUT CONTROL 4LMSBLSBLSB16161616161616A4GADDRESS LATCHES AND GATED DECODERS:GATE ON FALLING EDGE OF GLATCH ON FALLING EDGE OF E ALL LINES POSITIVE LOGIC:ACTIVE HIGHA HIGH OUTPUT ACTIVE THREE-STATE BUFFERS:8Q0Q1Q2Q3Q4Q5Q6Q7Absolute Maximum Ratings Thermal InformationSupply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V Input, Output or I/O Voltage . . . . . . . . . . .GND -0.3V to VCC +0.3V Typical Derating Factor. . . . . . . . . . . .5mA/MHz Increase in ICCOP ESD Classiﬁcation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Class 1 Operating ConditionsOperating Voltage Range. . . . . . . . . . . . . . . . . . . . .+4.5V to +5.5V Operating Temperature Range. . . . . . . . . . . . . . . .-55o C to +125o C Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to +0.8V Input High Voltage . . . . . . . . . . . . . . . . . . . . . . +2.4V to VCC +0.3V Thermal ResistanceθJAθJC SBDIP Package. . . . . . . . . . . . . . . . . .48o C/W9o C/W Slim SBDIP . . . . . . . . . . . . . . . . . . . . .65o C/W14o C/W CLCC Package . . . . . . . . . . . . . . . . . .58o C/W19o C/W Maximum Storage Temperature Range . . . . . . . . .-65o C to +150o C Maximum Junction T emperature. . . . . . . . . . . . . . . . . . . . . .+175o C Maximum Lead T emperature (Soldering 10s). . . . . . . . . . . .+300o C Die CharacteristicsGate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5473 GatesCAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.TABLE1.HM-6617/883 DC ELECTRICAL PERFORMANCE SPECIFICATIONSDevice Guaranteed and 100% TestedPARAMETER SYMBOL (NOTES 1, 4)CONDITIONSGROUP ASUBGROUPS TEMPERATURELIMITSUNITSMIN MAXHigh Level Output Voltage VOH1VCC = 4.5V, IO = -2.0mA1, 2, 3-55o C≤ TA≤ +125o C 2.4-V Low Level Output Voltage VOL VCC = 4.5V, IO = +4.8mA1, 2, 3-55o C≤ TA≤ +125o C-0.4VHigh Impedance Output Leakage Current IIOZ VCC = 5.5V,G = 5.5V,VI/O = GND or VCC1, 2, 3-55o C≤ TA≤ +125o C-1.0 1.0µAInput Leakage Current II VCC = 5.5V, VI = GND orVCC,P Not Tested1, 2, 3-55o C≤ TA≤ +125o C-1.0 1.0µAStandby Supply Current ICCSB VI = VCC or GND,VCC = 5.5V, IO = 0mA1, 2, 3-55o C≤ TA≤ +125o C -100µAOperating Supply Current ICCOP VCC = 5.5V,G = GND,(Note 3), f = 1MHz, IO =0mA, VI = VCC or GND1, 2, 3-55o C≤ TA≤ +125o C-20mA Functional Test FT VCC = 4.5V (Note 6)7, 8A, 8B-55o C≤ TA≤ +125o C--TABLE2.HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONSDevice Guaranteed and 100% TestedPARAMETER SYMBOL (NOTES 1, 2, 4)CONDITIONSGROUP ASUBGROUPS TEMPERATURELIMITSHM-6617B/883LIMITSHM-6617/883UNITSMIN MAX MIN MAXAddress Access Time T AVQV VCC = 4.5V and 5.5V(Note 5)9, 10, 11-55o C≤T A≤ +125o C-105-140nsOutput Enable AccessTimeTGLQV VCC = 4.5V and 5.5V9, 10, 11-55o C≤T A≤ +125o C-40-50nsChip Enable AccessTimeTELQV VCC = 4.5V and 5.5V9, 10, 11-55o C≤T A≤ +125o C-90-120ns Address Setup Time T AVEL VCC = 4.5V and 5.5V9, 10, 11-55o C≤T A≤ +125o C15-20-ns Address Hold Time TELAX VCC = 4.5V and 5.5V9, 10, 11-55o C≤T A≤ +125o C20-25-ns Chip Enable Low Width TELEH VCC = 4.5V and 5.5V9, 10, 11-55o C≤T A≤ +125o C95-120-ns Chip Enable High Width TEHEL VCC = 4.5V and 5.5V9, 10, 11-55o C≤T A≤ +125o C40-40-nsRead Cycle TimeTELELVCC = 4.5V and 5.5V9, 10, 11-55o C ≤ TA ≤ +125o C136-160-nsNOTES:1.All voltages referenced to Device GND.2.AC measurements assume transition time ≤ 5ns; input levels = 0.0V to3.0V; timing reference levels = 1.5V; output load = 1TTL equiva-lent load and CL ≅ 50pF.3.Typical derating = 5mA/MHz increase in ICCOP.4.All tests performed with P hardwired to VCC.5.TAVQV = TELQV + TAVEL.6.Tested as follows: f = 1MHz, VIH = 2.4V, VIL = 0.8V, IOH = -1mA, IOL = +1mA, VOH ≥ 1.5V, VOL ≤ 1.5V.TABLE 3.HM-6617/883 AC AND DC ELECTRICAL PERFORMANCE SPECIFICATIONSPARAMETERSYMBOL(NOTES 1, 2)CONDITIONSNOTESTEMPERATURELIMITS HM-6617B/883LIMITS HM-6617/883UNITSMINMAXMINMAXInput CapacitanceCINVCC = Open, f = 1MHz, All Measurements Referenced to Device GND2, 3+25o C-10-10pFVCC = Open, f = 1MHz, All Measurements Referenced to Device GND2, 4+25o C -12-12pF 2, 5+25o C -10-10pF I/O Capacitance CI/OVCC = Open, f = 1MHz, All Measurements Referenced to Device GND2, 3+25o C-12-12pFVCC = Open, f = 1MHz, All Measurements Referenced to Device GND2, 4+25o C -14-14pF 2, 5+25o C-12-12pF Chip Enable Time TELQX VCC = 4.5V and 5.5V 2-55o C ≤ T A ≤ +125o C 5-5-ns Output Enable Time TGLQX VCC = 4.5V and 5.5V 2-55o C ≤ T A ≤ +125o C 5-5-ns Chip Disable Time TEHQZ VCC = 4.5V and 5.5V 2-55o C ≤ T A ≤ +125o C -45-50ns Output Disable Time TGHQZ VCC = 4.5V and 5.5V 2-55o C ≤ T A ≤ +125o C -40-50ns Output High VoltageVOH2VCC = 4.5V , IO = 100µA2-55o C ≤ T A ≤ +125o CVCC-1V-VCC-1V-VNOTES:1.All tests performed with P hardwired to VCC.2.The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are char-acterized upon initial design changes which would affect these characteristics.3.Applies to 0.600 inch SBDIP device types only.4.Applies to 0.300 inch SBDIP device types only.5.Applies to Ceramic Leadless Chip Carrier (CLCC) device types only.TABLE 2.HM-6617/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)Device Guaranteed and 100% TestedPARAMETERSYMBOL(NOTES 1, 2, 4)CONDITIONSGROUP A SUBGROUPSTEMPERATURELIMITS HM-6617B/883LIMITS HM-6617/883UNITSMINMAXMINMAXTABLE 4.APPLICABLE SUBGROUPSCONFORMANCE GROUPS METHOD SUBGROUPSInitial Test 100%/5004-Interim Test 100%/50041, 7, 9PDA 100%/50041Final Test 100%/50042, 3, 8A, 8B, 10, 11Group A Samples/50051, 2, 3, 7, 8A, 8B, 9, 10, 11Groups C & DSamples/50051, 7, 9Switching WaveformsFIGURE 1.READ CYCLETest CircuitFIGURE 2.TEST CIRCUITTAVQVTELELTELEHTAVELTEHELTELQXTGHQZTEHQZTGLQXTELQVTGLQVTELAX ADDRESSESEGDATA 1.5V1.5V1.5V1.5V3.0V 0V 3.0V0V3.0V 0V T S1.5V ADDRESSESVALID DATAVALID ADDRESS VALID 1.5V1.5VOUTPUT Q0-Q71.5VDUT EQUIVALENT CIRCUIT1.5VI OLI OHC L TEST HEAD CAPACITANCE±(NOTE)NOTE:Burn-In CircuitsHM-6617/883 (.300 INCH) SBDIPHM-6617/883 (.600 INCH) SBDIPHM-6617/883 CLCCNOTES:f0 = 100KHz ± 10%.All resistors = 47k Ω Unless Otherwise Noted.VCC = 5.5V ± 0.05V .C = 0.01µF min.123456789101112161718192021222324151413GNDA7A6A5A4A3A2A1A0Q0Q1Q2Q7Q6Q5Q4Q3VCC A8A9P G A10E VCC/2VCC/2C2.4K2.4K 2.4K2.4K 2.4K 2.4K 2.4KGNDVCCf7f6f3f4f5f1f2f12VCC f10f0f112.4K f8f9123456789111216171819202122232415141310VCC f13Cf1f12GNDf11f0VCC/2f7f6f3f4f5f1f2f8VCCVCC/2Q7Q6Q5Q4Q3VCC A6A5P G A10E GNDA7A6A5A4A3A2A1A0Q0Q1Q22728292625242332143231305678111091617181920141522211213NCNC NC NC NC NC NC NC f10CVCCVCCf12VCC/2f1f13f0f11VCC/2VCC/2VCC/2f7f6f3f4f5f8f9All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certiﬁcation.Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or speciﬁcations at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.For information regarding Intersil Corporation and its products, see web site Die CharacteristicsDIE DIMENSIONS:140 x 232 x 19± 1mils METALLIZATION:T ype: Si - AlThickness: 11k Å±15k ÅGLASSIVATION:Type: SiO 2Thickness: 7k Å± 9k ÅWORST CASE CURRENT DENSITY:1.7 x 105 A/cm 2Metallization Mask LayoutHM-6617/883A4A5A6A7VCCA8A9PG A10E Q7Q6Q5Q4Q3GNDQ2Q1Q0A0A1A2A3。

IRF6618PBF中文资料

Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
3
元器件交易网
IRFP260PbF
4

元器件交易网网
IRFP260PbF
6

元器件交易网

7
元器件交易网
IRFP260PbF
TO-247AC Package Outline
Dimensions are shown in millimeters (inches)
TO-247AC Part Marking Information
N EXA PLE: THIS IS A IRFPE30 M WITH A SSEMBLY LOT CODE 5657 ASSEMBLED O WW35, 2000 N IN THE A SSEM BLY LINE "H"
Note: "P" in assembly line position indicates "Lead-Free"
PA NUM RT BER INTERNATIONA L RECTIFIER LOG O A SSEM BLY LOT CO DE
IRFPE30
56 035H 57
DA CO TE DE YEA 0 = 2000 R W EEK 35 LINE H
IRFP260PbF
Peak Diode Recovery dv/dt Test Circuit

MB98D81123资料

2M/4M-BYTE 3 V-ONL Y FLASH MINIATURE CARDThe Fujitsu Flash Miniature cards conform to “Miniature Card Speciﬁcation” pubulished by MCIF; Miniature Card Implementers Forum.The Fujitsu Flash Miniature cards are small form factor Flash memory cards targeted various markets; digital pho-tography, audio recording, hand held PCs and other small portable equipments. Miniature cards’ high performance, small size (38 mm × 33 mm × 3.5 mm), low cost and simple interface are ideal for portable applications that require high speed ﬂash disk drives or eXecute In Place (XIP).The Flash Miniature cards are 5 V-only operational and allow the users to use as ×8 or ×16 organization on low power at high speed.•Small size: 33.0 mm (length) × 38.0 mm (width) × 3.5 mm (thickness)•+3.3 V power supply program and erase•Command control for Automated Program/Automated Erase operation•Erase Suspend Read/Program Capability•128 KB Sector Erase (at ×16 mode)•Any Combination of Sectors Erase and Full Chip Erase•Detection of completion of program/erase operation with Data# Polling or Toggle bit.•Ready/Busy Output with BUSY#•Reset Function with RESET# pin•Write protect function with WP switch•Low VCC Write Inhibit•AIS (Attribute Information Structure) is available from the address “0000H” of Lower Byte.2MB98D81123/81223-15s PACKAGEs DESCRIPTIONDIFFERENCESMB98D81123MB98D81223 Density 2 MB 4 MB Memory Device8 M bit8 M bit Quantity24 Read 1 B unit←Program 1 B unit←Chip Erase 1 MB unit 1 MB unit Sector Erase64 KB unit←Number of Sectors3264 Erase Suspend Read Yes Yes Erase Suspend Program Yes Yes Address A0 to A19A0 to A20 RESET#Yes Yes BUSY#Yes Yes(CRD-60P-M02)MB98D81123/81223-15s PAD ASSIGNMENTSPad No Symbol Pad No Symbol Pad No Symbol Pad No Symbol 1A1816N.C.31A1946CD#2A1617N.C.32A1747N.C.3A1418OE#33A1548BUSY#4N.C.19D1534A1349WE#5CEH#20D1335A1250D146A1121D1236RESET#51RFU7A922D1037A1052D118A823D938VS1#53VS2#9A624D039A754D810A525D240N.C.55D111A326D441A456D312A227N.C.42CEL#57D513A028D743A158D614N.C.29N.C.44N.C.59N.C.15N.C.30N.C.45N.C.60A20 *EX 1V CC EX 2GND EX 3CINS#* :A20 is “N.C.” for MB98D81123.34MB98D81123/81223-15s PAD DESCRIPTIONS* :T ake notice that those pads are connected internally.s PAD LOCATIONSSymbol I/O Pad Name Symbol I/O Pad Name A0 to A20I Address Input BUSY#O Ready/BusyD0 to D15I/O Data Input/Output CD#O Card Detect *CEL#I Card Enable for Lower Byte VS1#, VS2#O Voltage Sense CEH#I Card Enable for Upper Byte N.C.—Non Connection OE#I Output Enable V CC—Power SupplyWE#I Write Enable GND—GroundRESET#I Hardware Reset CINS#OCard InsertionMB98D81123/81223-15s BLOCK DIAGRAMMB98D8112356MB98D81123/81223-15 MB98D812237MB98D81123/81223-15s CHIP AND SECTOR DECODINGERASE SECTOR DECODING TABLESector Address (SA)A 19A 18A 17A 16Sector 151111Sector 141110Sector 13111Total 16 sectors per 1 chip••••••••••••••••Sector 20010Sector 10001Sector 08MB98D81123/81223-15s CHIP CONFIGURATIONThe miniature cards use 2 or 4 pcs of Flash Memory.•2 pcs of Flash Memory are operated simultaneously at 16 bit mode and even number of chip is applied to lower byte and odd number of chip is applied to upper byte.At ×8 bit mode, even address and odd address are selected with CEL# and CEH#.× 16 bit mode1CEL# = “L”, CEH# = “L”::Odd Number of Chip + Even Number of ChipOdd Number of Chip + Even Number of ChipOdd Number of Chip + Even Number of ChipOdd Number of Chip + Even Number of ChipD15 • • • • • • • • • • • • • • D0003h002h001h000h2× 8 bit modeCEL# = “H”, CEH# = “L”::odd Number of Chipodd Number of Chipodd Number of Chipodd Number of ChipD15 • • • •D8003h002h001h000hCEL# = “L”, CEH# = “H”::even Number of Chipeven Number of Chipeven Number of Chipeven Number of ChipD7 • • • • •D0003h002h001h000hMB98D81123/81223-15s FUNCTION DESCRIPTIONS1.Read ModeThe data in the common can be read with “OE#=VIL” and “WE#=VIH”. The address is selected with A0-A20.And CEL# and CEH# select output mode.2.Standby Mode–CEL# and CEH# at “VIH” place the card in Standby mode. D0-D15 are placed in a high-Z state independent of the status “OE#” and “WE#”.3.Output Disable Mode–The outputs are disabled with OE# and WE# at “VIH”. D0-D15 are placed in high-Z state.4.Write Mode1) Common Memory Write–The card is in Write mode with “OE#=VIH” and “WE# and CE#=VIL”.–Commands can be written at the Write mode.–Two types of the Write mode, “WE# control” and “CE# control” are available.mand Deﬁnitions–User can select the card operation by writing the speciﬁc address and data sequences into the command register. If incollect address and data are written or improper sequence is done, the card is reseted to read mode. See “COMMAND DEFINISION T ABLE”.6.Automated Program Capability–Programming operation can switch the data from “1” to “0”.–The data is programmed on a byte-by-byte or word-by-word basis.–The card will automatically provide adequate internally generated programming pulses and verify the pro-grammed cell margin by writing four bus cycle operation. The card returns to Common Memory Read mode automatically after the programming is completed.–Addresses are latched at falling edge of WE# or CE# and data is latched at rising edge of WE# or CE#. The fourth rising edge of WE# or CE# on the command write cycle begins programming operation.–We can check whether a byte (word) programming operation is completed successfully by sequence ﬂug with BUSY#, Data# Polling or Toggle Bit function. See “WRITE OPERATION STATUS”.–Any commands written to the chip during programming operation will be ignored.7.Automated Chip Erase Capability–We can execute chip erase operation by 6 bus cycle operation. Chip erase does not require the user to program the chip prior to erase. Upon executing the Erase command sequence the chip automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timing during these operations.–The card returns to Common Memory Read mode automatically after the chip erasing is completed.–Whether or not chip erase operation is completed successfully can be checked by sequence ﬂug with BUSY#, Data# Polling or Toggle Bit function. See “WRITE OPERATION STATUS”.–Any commands written to the chip during programming operation will be ignored.910MB98D81123/81223-158.Automated Sector Erase Capability–We can execute the erase operation on any sectors by 6 bus cycle operation.–A time-out of 50 µs (typ.) from the rising edge of the last Sector Erase command will initiate the Sector Erase command(s).–Multiple sectors in a chip can be erased concurrently. This sequence is followed with writes of 30H to addresses in other sectors desired to be concurrently erased. The time between writes 30H must be less than 50 µs, otherwise that command will not be accepted. Any command other than Sector Erase or Erase Suspend during this time-out period will reset the chip to Read mode. The automated sector erase begins after the 50µs (typ.) time out from the rising edge of WE# pulse for the last Sector Erase command pulse. Whether the sector erase window is still open can be monitored with D3 and D11.–Sector Erase does not require the user to program the chip prior to erase. The chip automatically programs “0” to all memory locations in the sector(s) prior to electrical erase. The system is not required to provide any controls or timing during these operations.–The card returns to Common Memory Read mode automatically after the chip erasing is completed.–Whether or not sector erase operation is completed successfully can be checked by sequence ﬂug with BUSY#, Data# Polling or T oggle Bit function. The sequence ﬂug must be read from the address of the sector involved in erase operation. See “WRITE OPERATION STA TUS”.9.Erase Suspend–Erase Suspend command allows the user to interrupt the sector erase operation and then do data reads or program from or to a non-busy sector in the chip which has the sector(s) suspended erase. This command is applicable only during the sector erase operation (including the sector erase time-out period after the sector erase commands 30H) and will be ignored if written during the chip erase or programming operation. Writing this command during the time-out will result in immediate termination of the time-out period. The addresses are “don’t cares” in wrinting the Erase Suspend or Resume commands in the chip.–When the Erase Suspend command is written during a Sector Erase operation, the chip will enter the Erase Suspend Read mode. User can read the data from other sectors than those in suspention. The read operation from sectors in suspention results D2/D10 toggling. User can program to non-busy sectors by writing program commands.–A read from a sector being erase suspended may result in invalid data.10. Intelligent Identiﬁer (ID) Read Mode–Each common memory can execute an Intelligent Identiﬁer operation, initiated by writing Intelligent ID com-mand (90H). Following the command write, a read cycle from address 00H retrieves the manufacture code, and a read cycle from address 01H returns the device code as follows. To terminate the operation, it is necessary to write Read/Reset command.11. Hardware Reset–The Card may be reset by driving the RESET# pin to VIL. The RESET# pin must be kept High (VIL) for at least 500 ns. Any operation in progress will be terminated and the card will be reset to the read mode 20 µs after the RESET# pin is driven Low. If a hardware reset occurs during a program operation, the data at that particular location will be indeterminate.–When the RESET# pin is Low and the internal reset is complete, the Card goes to standby mode and cannot be accessed. Also, note that all the data output pins are High-Z for the duration of the RESET# pulse. Once the RESET# pin is taken high, the Card requires 500 ns of wake up time until outputs are valid for read access.–If hardware reset occurs during a erase operation, there is a possibility that the erasing sector(s) cannot be used.12. Data Protection–The card has WP (Write Protect) switch for write lockout.–To avoid initiation of a write cycle during V CC power-up and power-down, a write cycle is locked out for V CC less than 3.2 V. If V CC < V LKO, the command register is disabled and all internal program/erase circuits are disabled.Under this condition the device will reset to the read mode. Subsequent writes will be ignored until the V CC level is greater than V LKO.It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when V CC is above 3.2 V.–If V CC would be less than V LKO during program/erase operation, the operation will stop. And after that, the operation will not resume even if V CC returns recommended voltage level. Therefore, program command must be written again because the data on the address interrupted program operation is invalid. And regarding interrupting erase operation, there is possibility that the erasing sector(s) cannot be used.–Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# will not initiate a write cycle.s FUNCTION TRUTH TABLEH : “H” level, L : “L ” level , X : “H” or “L ”Note:*1.WPSW = Write Protect Switch, NP = NON-PROTECT, P = PROTECTMode RESET#CEH#CEL#OE#WE#WPSW *1Data Input/Output D8 to D15D0 to D7Hardware ResetLX X X X P or NP High-Z High-Z Standby H H H XXP or NPHigh-Z High-Z Read (×8 bit)H L LHP or NPHigh-Z DOUT L H DOUT High-Z Read (×16 bit)L L DOUT DOUT Write (×8 bit)H L HLNPHigh-Z DIN L H DIN High-Z Write (×16 bit)L L DIN DIN Output DisableHL P High-Z High-Z L H High-Z High-Z LLHigh-ZHigh-Zs COMMAND DEFINITION TABLECommand Table for 8-bit ModeNote:CA:Chip Address.(address in chip selected by A20 for MB98D81223)SA:Sector Address (address in 64 KB selected by A16, A17, A18, A19 and A20)P A:Program Address (address to be programmed)RA:Read Address (address to be read)IA:Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H)PD:Programming data RD:Read dataID:Intelligent Identiﬁer (ID) CodeCommandBusCycle 1st Bus Write Cycle 2nd BusWrite/Read Cycle 3rd BusWrite Cycle 4th BusWrite/Read Cycle5th BusWrite Cycle 6th Bus Write CycleRead/Reset 12Write Read CAF0HRARDRead/Reset 24Write Write Write Read CAAAHCA55HCAF0HRARDRead Intelligent ID Codes 4Write Write Write Read CAAAHCA55HCA90HIAIDByte Program4Write Write Write Write CAAAHCA55HCAA0HPAPDSector Erase 6Write Write Write Write Write Write CAAAHCA55HCA80HCAAAHCA55HSA30HChip Erase 6Write Write Write Write Write Write CAAAHCA55HCA80HCAAAHCA55HCA10HSector Erase Suspend 1Write CAB0HSector Erase Resume 1Write CA30HCommand Table for 16-bit ModeNote:CA:Chip Address.(address in chip selected by A20 for MB98D81223)SA:Sector Address (address in 128 KB selected by A16, A17, A18, A19 and A20)P A:Program Address (address to be programmed)RA:Read Address (address to be read)IA:Intelligent ID read address (Manufacture Code 0000H, Device Code 0001H)PD:Programming data RD:Read dataID:Intelligent Identiﬁer (ID) CodeCommandBusCycle 1st Bus Write Cycle 2nd BusWrite/Read Cycle 3rd BusWrite Cycle 4th BusWrite/Read Cycle5th BusWrite Cycle 6th Bus Write CycleRead/Reset 12Write Read CAF0F0HRARDRead/Reset 24Write Write Write Read CAAAAAHCA5555HCAF0F0HRARDRead Intelligent ID Codes 4Write Write Write Read CAAAAAHCA5555HCA9090HIAIDByte Program4Write Write Write Write CAAAAAHCA5555HCAA0A0HPAPDSector Erase 6Write Write Write Write Write Write CAAAAAHCA5555HCA8080HCAAAAAHCA5555HSA3030HChip Erase 6Write Write Write Write Write Write CAAAAAHCA5555HCA8080HCAAAAAHCA5555HCA1010HSector Erase Suspend 1Write CAB0B0HSector Erase Resume 1Write CA3030Hs WRITE OPERATION STATUSHardware Sequence Flag Table(1): Erase Suspended Sector (2): Non-Erase Suspended SectorNotes:*1.Performing successive read operations from the erase-suspended sector will cause D 2, D 10 to toggle.*2.Performing successive read operations from any address will cause D 6, D 14 to toggle.*3.Reading the byte address being programmed while in the erase-suspend program mode will indicatelogic ‘1’ at the D 2, D 10 bit. However, successive reads from the erase-suspended sector will cause D 2,D 10 to toggle.D7, D15 (Data# Polling)The card features Data# Polling as a method to indicate to the host that the Program/Erase Operation are in progress or completed. During the program operation an attempt to read the program address will produce the compliment of the data last written to D 7/D 15. Upon completion of the program operation, an attempt to read the program address will produce the true data last written to D 7/D 15. During the erase operation, an attempt to read the program address will produce a “0” at the D 7/D 15 output. Upon completion of the erase operation an attempt to read the device will produce a “1” at the D 7/D 15 output.For Chip Erase, the Data# Polling is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the Data# Polling is valid after the last rising edge of the sector erase WE# pulse.Even if the device has completed the operation and D 7/D 15 has a valid data, the data outputs on D 0 to D 6/D 8 to D 14 may be still invalid. The valid data on D 0 to D 7/D 8 to D 15 will be read on the successive read attempts.The Data# Polling feature is only active during the programming operation, erase operation, sector erase time-out, Erase Suspend Read mode and Erase Supend Program mode.D6, D14 (Toggle Bit I)The card also features the “Toggle Bit” as a method to indicate to the host system that the Program/Erase Operation are in progress or completed.During an Program or Erase cycle, successive attempts to read (OE# or CE# toggling) data from the card will result in D 6/D 14 toggling between one and zero. Once the Program or Erase cycle is completed, D 6/D 14 will stop toggling and valid data will be read on the next successive attempts. During programming, the Toggle Bit is valid after the rising edge of the fourth WE# pulse in the four write pulse sequence. For chip erase, the Toggle Bit is valid after the rising edge of the sixth WE# pulse in the six write pulse sequence. For sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE# pulse. The Toggle Bit is also active during the sector time out.Either CE# or OE# toggling will cause the D 6/D 14 to toggle.Status D 7, D 15D 6, D 14D 5, D 13D 3, D 11D 2, D 10BUSY#InProgressProgramming D 7#, D 15#Toggle 0010Erasing0Toggle 01Toggle 0Erase Suspend Read(1)1100Toggle *11(2)Data Data Data Data Data 1Erase Suspend Program D 7#, D 15#T oggle *200*1, *30Exceeded Time LimitsProgrammingD 7#, D 15#Toggle 1010Erasing 0Toggle 11N/A 0Erase Suspend ProgramD 7#, D 15#Toggle1N/AD5, D13 (Exceeded Timing Limits)D5/D13 will indicate if the program or erase time has exceeded the speciﬁed limits (internal pulse count). Under these conditions D5/D13 will produce a “1”. This is a failure condition which indicates that the program or erase cycle was not successfully completed. Data# Polling is the only operating function of the card under this condition.If this failure condition occurs during sector erase operation, it speciﬁes that a particular sector is bad and it may not be reused, however, other sectors are still functional and may be used for the program or erase operation.The chip must be reset to use other sectors. Write the Reset command sequence to the chip, and then execute Program or Erase command sequence. This allows the system to continue to use the other active sectors in the chip.If this failure condition occurs during the chip erase operation, it speciﬁes that the entire chip is bad or combination of sectors are bad.If this failure condition occurs during the byte programming operation, it speciﬁes that the entire sector containing that byte is bad and this sector may not be reused, (other sectors are still functional and can be reused).The D5/D13 failure condition may also appear if a user tries to program a non blank location without erasing. In this case the card locks out and never completes the card operation. Hence, the system never reads a valid data on D7/D15 bit and D6/D14 never stops toggling. Once the card has exceeded timing limits, the D5/D13 bit will indicate a “1”. Please note that this is not a device failure condition since the device was incorrectly used.D3, D11 (Sector Erase Timer)After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3/D11 will remain low until the time-out is complete. Data# Polling and Toggle Bit are valid after the initial sector erase command sequence.If Data# Polling or the T oggle Bit indicates the card has been written with a valid erase command, D3/D11 may be used to determine if the sector erase timer window is still open. If D3/D11 is high (“1”) the internally controlled erase cycle has begun; attempts to write subsequent commands to the card will be ignored until the erase operation is completed as indicated by Data# Polling or Toggle Bit. If D3/D11 is low (“0”), the card will accept additional sector erase commands. T o insure the command has been accepted, the system software should check the status of D3/D11 prior to and following each subsequent sector erase command. If D3/D11 were high on the second status check, the command may not have been accepted.Refer to T able: Hardware Sequence Flags.D2, D10This T oggle bit, along with D6, can be used to determine whether the card is in the Erase operation or in Erase Suspend.Successive reads from the erasing sector will cause D2 to toggle during the Erase operation. If the card is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause D2 to toggle. When the card is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indicate a logic ‘1’ at the D2 bit.D6 is different from D2 in that D6 toggles only when the standard Program or Erase, or Erase Suspend Program operation is in progress.BUSY#The card provides a BUSY# open-drain output pin as a way to indicate to the system that the program or erase operation are either in progress or has been completed. If the output is low, the card is busy with either a program or erase operation. If the card is placed in an Erase Suspend mode, the BUSY# output will be high.During programming, the BUSY# pin is driven low after the rising edge of the fourth WE# pulse. During an erase operation, the BUSY# pin is driven low after the rising edge of the sixth WE# pulse. The BUSY# pin will indicatea busy condition during the RESET# pulse.s PROGRAM/ERASE FLOWCHARTs ABSOLUTE MAXIMUM RATINGS *1*1.Permanent device damage may occur if the above Absolute Maximum Ratings are exceeded. Functionaloperation should be restricted to the conditions as detailed in the operational sections of this data sheet.Exposure to absolute maximum rating conditions for extended periods may affect device reliability.s RECOMMENDED OPERATING CONDITIONSs DC CHARACTERISTICSNotes:*1.This value does not apply to CEL#, CEH# and WE#.*2.This value does not apply to CD# and CINS#.ParameterSymbol Value Unit Supply Voltage V CC –0.5 to +5.5V Input Voltage V IN –0.5 to V CC +0.5V Output VoltageV OUT –0.5 to V CC +0.5V Temperature under Bias T A 0 to +60°C Storage T emperatureT STG–30 to +70°CParameterSymbol Min Typ Max Unit V CC Supply Voltage V CC 3.1353.30 3.465V GroundGND 0V Ambient T emperatureT A055°CParameterTest ConditionsSymbol ValueUnit MinTypMax Input Leakage Current *1V CC = V CC max., V IN = GND or V CCI LI ±10µA Output Leakage Current *2V CC = V CC max., V IN = GND or V CC I LO ±10µA Standby CurrentCEL#, CEH#,RESET# = V CC ±0.3 V I SB1—1070µA CEL#, CEH#, RESET# = V IHI SB2 5.0mA Active Read Current V CC = V CC max., CEL#, CEH# = V IL Cycle = 150 ns, I OUT = 0 mA I CC15080mA Program Current Program in progress (×16 mode)I CC260100mA Erase Current Erase in progress (×16 mode)I CC360100mA Input Low Voltage —V IL –0.5—0.6V Input High Voltage —V IH 0.7 V CC—V CC +0.5V Output Low Voltage I OL = 4.0 mA, V CC = V CC min.V OL 0.45V Output High Voltage I OH = –2.0 mA, V CC = V CC min.V OH 2.4V Low V CC Lock-out Voltage—V LKO2.3—2.5Vs CAPACITANCE (T A = 25°C, f = 1 MHz, V IN = V I/O = GND)Parameter Symbol Min Max Unit Input Capacitance *1C IN40pF I/O Capacitance *2C I/O40pF Notes:*1.This value does not apply to CEL#, CEH# and WE#.*2.This value does not apply to VS1#, CD# and CINS#.s AC TEST CONDITIONS•Input Pulse Levels: V IH = 3.0 V, V IL = 0.0 V•Input Pulse Rise and Fall Times: 5 ns•Timing Reference LevelsInput: V IL = 1.5 V, V IH = 1.5 VOutput: V OL = 1.5 V, V OH = 1.5 VOutput Load: 1TTL +100 pFs PROGRAM AND ERASE PERFORMANCESParameter Min Typ Max Unit Byte Program Time *183600µs Chip Programming Time *18.4T.B.D.Sec. Sector Erase Time *2115Sec. Program/Erase Cycles100,000Cycles Notes:*1.Excludes system-level overhead.*2.Excludes 00H programming prior to erasure.s AC CHARACTERISTICS(Recommended operating conditions unless otherwise noted.)READ CYCLE *1Parameter Symbol Min Max Unit Read Cycle Time t RC150ns Card Enable Access Time t CE150ns Address Access Time t ACC150ns Output Enable Access Time t OE75ns Card Enable to Output in Low-Z *2t CLZ5ns Card Disable to Output in High-Z *2t CHZ75ns Output Enable to Output in Low-Z *2t OLZ5ns Output Disable to Output in High-Z *2t OHZ60ns Output Hold from Address Change t OH0ns Ready Time from RESET#t RDY20µs Notes:*1.Rise/Fall time < 5 ns.*2.T ransition is measured at the point of ±500 mV from steady state voltage.PROGRAM/ERASE CYCLENotes:*1.These do not include the preprogramming time.*2.Not 100% tested.ParameterSymbol Min TypMaxUnit Write Cycle Time t WC 150ns Address Setup Time t AS 20ns Address Hold Time t AH 20ns Data Setup Time t DS 50ns Data Hold Timet DH 20ns Read Recovery Time (WE# control)t GHWL 10ns Read Recovery Time (CE# control)t GHEL 10ns Output Enable Hold Time t OEH 10ns Card Enable Setup Time t CS 0ns Card Enable Hold Time t CH 10ns Write Enable Pulse Width t WP 80ns Write Enable Setup Time t WS 0ns Write Enable Hold Time t WH 10ns Card Enable Pulse Widtht CP 100ns Duration of Byte Program Operation (/WE Control)t WHWH18µs Duration of Erase Operation *1 (/WE Control)t WHWH2115s Duration of Byte Program Operation (/CE Control)t EHEH18µs Duration of Erase Operation *1(/CE Control)t EHEH2115s V CC Setup Time *2t VCS 50µs Reset Pulse Width t RP 500ns Busy Delay Timet BSY90nss TIMING DIAGRAMREAD CYCLE TIMING DIAGRAM (WE# = V IH, RESET# = V IH)READ CYCLE TIMING DIAGRAM (continued) (WE# = V IH, RESET# = V IH)READ CYCLE TIMING DIAGRAM (continued) (WE# = V IH, RESET# = V IH)3132PROGRAM CYCLE TIMING DIAGRAM (WE# = CONTROLLED, RESET# = V IH)Notes:*1.See “FUNCTION TRUTH TABLE”.*2.PCMA1/PCMA2 = Command Address for Program, PA = Program Address, PD = Program Data. See “COMMAND DEFINITION TABLE”.PROGRAM CYCLE TIMING DIAGRAM (CE# = CONTROLLED, RESET# = V IH)Notes:*1.See “FUNCTION TRUTH TABLE”.*2.PCMA1/PCMA2 = Command Address for Program, PA = Program Address, PD = Program Data. See “COMMAND DEFINITION TABLE”.3334ERASE CYCLE TIMING DIAGRAM (WE# = CONTROLLED, RESET# = V IH)Notes:*1.See “FUNCTION TRUTH TABLE”.*MA1/CCMA2 = Command Address for Chip Erase, SCMA1/SCMA2 = Command Address for Sector Erase, SA = Sector Address. See “COMMAND DEFINITION TABLE”.ERASE CYCLE TIMING DIAGRAM (CE# = CONTROLLED, RESET# = V IH)Notes:*1.See “FUNCTION TRUTH TABLE”.*MA1/CCMA2 = Command Address for Chip Erase, SCMA1/SCMA2 = Command Address for Sector Erase, SA = Sector Address. See “COMMAND DEFINITION TABLE”.3536DATA# POLLING CYCLE TIMING DIAGRAM (RESET# = V IH)Notes:*1.VA = PA for Programming Cycle, VA = SA for Sector Erase, VA = CA for Chip Erase.*2.See “FUNCTION TRUTH TABLE”.*3.t EHEH1,2 for CE# Control.*4.Program/Erase operation is ﬁnished.。

唐山伍壹捌科技有限公司介绍企业发展分析报告模板

Enterprise Development专业品质权威Analysis Report企业发展分析报告唐山伍壹捌科技有限公司免责声明:本报告通过对该企业公开数据进行分析生成，并不完全代表我方对该企业的意见，如有错误请及时联系;本报告出于对企业发展研究目的产生，仅供参考，在任何情况下，使用本报告所引起的一切后果，我方不承担任何责任:本报告不得用于一切商业用途，如需引用或合作，请与我方联系:唐山伍壹捌科技有限公司1企业发展分析结果1.1 企业发展指数得分企业发展指数得分唐山伍壹捌科技有限公司综合得分说明：企业发展指数根据企业规模、企业创新、企业风险、企业活力四个维度对企业发展情况进行评价。

该企业的综合评价得分需要您得到该公司授权后，我们将协助您分析给出。

1.2 企业画像类别内容行业空资质增值税一般纳税人产品服务：新材料技术推广服务；建筑材料销售；煤炭及1.3 发展历程2工商2.1工商信息2.2工商变更2.3股东结构2.4主要人员2.5分支机构2.6对外投资2.7企业年报2.8股权出质2.9动产抵押2.10司法协助2.11清算2.12注销3投融资3.1融资历史3.2投资事件3.3核心团队3.4企业业务4企业信用4.1企业信用4.2行政许可-工商局4.3行政处罚-信用中国4.5税务评级4.6税务处罚4.7经营异常4.8经营异常-工商局4.9采购不良行为4.10产品抽查4.12欠税公告4.13环保处罚4.14被执行人5司法文书5.1法律诉讼（当事人）5.2法律诉讼（相关人）5.3开庭公告5.4被执行人5.5法院公告5.6破产暂无破产数据6企业资质6.1资质许可6.2人员资质6.3产品许可6.4特殊许可7知识产权7.1商标7.2专利7.3软件著作权7.4作品著作权7.5网站备案7.6应用APP7.7微信公众号8招标中标8.1政府招标8.2政府中标8.3央企招标8.4央企中标9标准9.1国家标准9.2行业标准9.3团体标准9.4地方标准10成果奖励10.1国家奖励10.2省部奖励10.3社会奖励10.4科技成果11 土地11.1大块土地出让11.2出让公告11.3土地抵押11.4地块公示11.5大企业购地11.6土地出租11.7土地结果11.8土地转让12基金12.1国家自然基金12.2国家自然基金成果12.3国家社科基金13招聘13.1招聘信息感谢阅读:感谢您耐心地阅读这份企业调查分析报告。

安平淼越金属制品有限公司介绍企业发展分析报告模板

Enterprise Development专业品质权威Analysis Report企业发展分析报告安平淼越金属制品有限公司免责声明:本报告通过对该企业公开数据进行分析生成，并不完全代表我方对该企业的意见，如有错误请及时联系;本报告出于对企业发展研究目的产生，仅供参考，在任何情况下，使用本报告所引起的一切后果，我方不承担任何责任:本报告不得用于一切商业用途，如需引用或合作，请与我方联系:安平淼越金属制品有限公司1企业发展分析结果1.1 企业发展指数得分企业发展指数得分安平淼越金属制品有限公司综合得分说明：企业发展指数根据企业规模、企业创新、企业风险、企业活力四个维度对企业发展情况进行评价。

该企业的综合评价得分需要您得到该公司授权后，我们将协助您分析给出。

1.2 企业画像类别内容行业空资质空产品服务：建设工程施工。

（依法须经批准的项目，经相1.3 发展历程2工商2.1工商信息2.2工商变更2.3股东结构2.4主要人员2.5分支机构2.6对外投资2.7企业年报2.8股权出质2.9动产抵押2.10司法协助2.11清算2.12注销3投融资3.1融资历史3.2投资事件3.3核心团队3.4企业业务4企业信用4.1企业信用4.2行政许可-工商局4.3行政处罚-信用中国4.4行政处罚-工商局4.5税务评级4.6税务处罚4.7经营异常4.8经营异常-工商局4.9采购不良行为4.10产品抽查4.11产品抽查-工商局4.12欠税公告4.13环保处罚4.14被执行人5司法文书5.1法律诉讼（当事人）5.2法律诉讼（相关人）5.3开庭公告5.4被执行人5.5法院公告5.6破产暂无破产数据6企业资质6.1资质许可6.2人员资质6.3产品许可6.4特殊许可7知识产权7.1商标7.2专利7.3软件著作权7.4作品著作权7.5网站备案7.6应用APP7.7微信公众号8招标中标8.1政府招标8.2政府中标8.3央企招标8.4央企中标9标准9.1国家标准9.2行业标准9.3团体标准9.4地方标准10成果奖励10.1国家奖励10.2省部奖励10.3社会奖励10.4科技成果11土地11.1大块土地出让11.2出让公告11.3土地抵押11.4地块公示11.5大企业购地11.6土地出租11.7土地结果11.8土地转让12基金12.1国家自然基金12.2国家自然基金成果12.3国家社科基金13招聘13.1招聘信息感谢阅读:感谢您耐心地阅读这份企业调查分析报告。

福州华衍淼科技有限公司介绍企业发展分析报告模板

Enterprise Development专业品质权威Analysis Report企业发展分析报告福州华衍淼科技有限公司免责声明:本报告通过对该企业公开数据进行分析生成，并不完全代表我方对该企业的意见，如有错误请及时联系;本报告出于对企业发展研究目的产生，仅供参考，在任何情况下，使用本报告所引起的一切后果，我方不承担任何责任:本报告不得用于一切商业用途，如需引用或合作，请与我方联系:福州华衍淼科技有限公司1企业发展分析结果1.1 企业发展指数得分企业发展指数得分福州华衍淼科技有限公司综合得分说明：企业发展指数根据企业规模、企业创新、企业风险、企业活力四个维度对企业发展情况进行评价。

该企业的综合评价得分需要您得到该公司授权后，我们将协助您分析给出。

1.2 企业画像类别内容行业空资质空产品服务开发；应用软件开发；网络与信息安全软件开发1.3 发展历程2工商2.1工商信息2.2工商变更2.3股东结构2.4主要人员2.5分支机构2.6对外投资2.7企业年报2.8股权出质2.9动产抵押2.10司法协助2.11清算2.12注销3投融资3.1融资历史3.2投资事件3.3核心团队3.4企业业务4企业信用4.1企业信用4.2行政许可-工商局4.3行政处罚-信用中国4.4行政处罚-工商局4.5税务评级4.6税务处罚4.7经营异常4.8经营异常-工商局4.9采购不良行为4.10产品抽查4.11产品抽查-工商局4.12欠税公告4.13环保处罚4.14被执行人5司法文书5.1法律诉讼（当事人）5.2法律诉讼（相关人）5.3开庭公告5.4被执行人5.5法院公告5.6破产暂无破产数据6企业资质6.1资质许可6.2人员资质6.3产品许可6.4特殊许可7知识产权7.1商标7.2专利7.3软件著作权7.4作品著作权7.5网站备案7.6应用APP7.7微信公众号8招标中标8.1政府招标8.2政府中标8.3央企招标8.4央企中标9标准9.1国家标准9.2行业标准9.3团体标准9.4地方标准10成果奖励10.1国家奖励10.2省部奖励10.3社会奖励10.4科技成果11土地11.1大块土地出让11.2出让公告11.3土地抵押11.4地块公示11.5大企业购地11.6土地出租11.7土地结果11.8土地转让12基金12.1国家自然基金12.2国家自然基金成果12.3国家社科基金13招聘13.1招聘信息感谢阅读:感谢您耐心地阅读这份企业调查分析报告。