Pxi_carrier_board_fpga_r000v005

FPGA Application Note (Document Control: Pxi_carrier_board_fpga.doc)
GEIP CIC
251204222.doc Confidential
Contents
Contents (i)
Figures (i)
Tables (i)
1General Description (1)
2Module Block (1)
3Module Description (1)
4Trigger Module (2)
4.1Introduction and Features (2)
4.2Data Path and Pin description (2)
4.3Register definition (3)
Figures
Figure 2-1 PXI Carrier Board FPGA Module Block (1)
Tables
Table 3-1 Module Description Table (1)
1General Description
This document gives out the customer-oriented register list and several notes of register settings. 2Module Block
Table 3-1 Module Description Table
4Trigger Module
4.1Introduction and Features
Support 8bit PXI Trigger Bus, Before Enable the Trigger function, all the 8 bit Trigger Lines keep high impedance state. If the Trigger bus function enabled, the trigger module can support the following function:
1)Configure the Trigger Line as Input or Output independently.
Figure 6-1 Trigger Module Datapath
支持8位PXI背板触发总线，PXI触发功能使能前，8根触发线处于高阻状态，使能后，可提供如下功能：
1)配置某一位/几位触发线为输入或输出
2)控制某一位/几位触发线输出高电平或低电平
3)读取触发总线输入状态
4)采样某一位触发线上的上升沿或下降沿触发事件
Bit Name Description
0 T.EN PXI触发模块全局使能位。

1 = 使能PXI触发模块
0 = 禁止PXI触发模块，PXI触发线驱动器处于断开模式，PXI
触发线处于高阻状态(power-up state)
1 Route.EN PXI触发线路由使能位。

当使能该位时，PXI Trigger0~7将从输
出端口BANK0对应输出。

（无效）
1 = 使能路由功能
0 = 禁止路由功能(power-up state)
8 TRIG.EN PXI触发使能位。

当使能该位时，可通过背板PXI触发总线的某
一位触发PXI2PMC在规定的条件下改变输出端口的输出值，用
于PXI系统多个模块的同步工作。

1 = 使能PXI触发
系
Bit Name Description
7-0 TRIG.O<7:0> PXI触发线输出数据寄存器，TRIG.O0～7分别对应PXI Trigger
Line 0~7。

1 = 输出高电平
0 = 输出低电平(power-up state) 9 EXT.O 前面板外部触发信号输出寄存器
1 = 输出高电平
0 = 输出低电平(power-up state) PXI Trigger Output Enable Register
Address Offset: 0x18
Type:Read and Write
Size:16
Default Value:0xFD00
Bit Map:
Bit Name Description
7-0 TRIG.M<7:0> 1 = 使能屏蔽，输出寄存器对应位不可控制对应通道，输出通道
保持当前值
0 = 禁止屏蔽，输出寄存器对应位可控制对应通道(power-up state)
9 EXT.M 1 = 使能屏蔽，输出寄存器对应位不可控制对应通道，输出通道
PXI
PXI Trigger To Out-port Polarity Register（无效）
PXI触发线路由输出极性控制寄存器（PXI Trigger To Out-port Polarity Register）为一个8位的可读可写寄存器。

当使能PXI触发线路由至输出端口BANK0时，可通过本寄存器设置输出是否反相。

Address Offset: 0x20
Type:Read and Write
Size:8
Default Value:0x00
Bit Map:
Bit Name Description
7-0 TRIG.P<7:0> 1 = 反相
0 = 同相(power-up state)
9 EXT.P 1 = 反相
0 = 同相(power-up state)
PXI触发模块使用技巧
PXI2PMC的PXI触发模块提供两个功能：
1)通过上层软件控制PXI2PMC在PXI触发总线的某一位/几位上输出高/低电平，从而产生各种
触发条件（高、低、上升沿、下降沿等）。

2)响应PXI背板触发总线上的触发条件（高、低、上升沿、下降沿等），使能该功能后，PXI2PMC
只在触发总线上的触发条件满足设定条件时刷新输出端口的输出值，可用于PXI系统中各模块的同步控制。

功能1)的设置：
a)通过PXI Trigger Control Register使能PXI模块
b)通过PXI Trigger Output Enable Register将需要的位设为输出
c)将PXI Trigger Output Mask Register中对应位设为禁止屏蔽
d)通过PXI Trigger Output Register控制输出高/低电平
功能2)的设置：
a)通过PXI Trigger Control Register使能PXI模块
b)通过PXI Trigger Control Register使能PXI触发功能
c)通过PXI Trigger Control Register设定PXI触发模式
d)通过PXI Trigger Control Register设定响应触发条件的触发线
通过PXI Trigger Output Enable Register将需要的位设为输入
The eight PXI bused trigger lines are highly flexible and can be used in a variety
of ways. For example, triggers can be used to synchronize the operation of
several different PXI peripheral modules. In other applications, one module can
control carefully timed sequences of operations performed on other modules in
the system. Triggers may be passed from one module to another, allowing
precisely timed responses to asynchronous external events that are being
monitored or controlled. The number of triggers that a particular application
requires varies with the complexity and number of events involved.。