GS8640E32GT-250V中文资料

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GT、GS、GE、LE显卡说明

GT、GS、GE、LE显卡说明一、相对老一些的解释：LE:NVIDA显卡型号采用的后缀。

全名为“Limited Edition”（限制版）代表系列中的低端产品，到现在为止，还有某些LE显卡因为精简过管线而被大家戏称为“阉割卡”或“太监卡”。

SE:ATI显卡型号采用的后缀。

全名为“Special Edition”（特殊版），同样代表系列中的低端产品。

通常SE后缀的显卡只有64bit内存界面，如9200SE ，9550SE，9600SE，9800SE（此型号有128 bit和256 bit），X300SE等。

又或者是像素流水线数量减少（如9800SE）。

ZT:NVIDA 新增加的型号，现在只有 GeForce FX 5900一款。

ZT 代表着比XT更低的市场定位，使系列中中低端的产品。

XT：最容易让人混淆的型号。

ATI与NVIDA显卡均在使用。

在ATI方面，代表系列中最高端的产品，如9600XT,9800XT,X800XT,X1300XT 等等。

而NVIDA则将之用作低端型号，如5900XT,6800XT等等。

GT/Pro：分别为NVIDA 和ATI公司用作中端显卡型号的后缀。

代表产品有7600GT，9600Pro,X800 Pro等，唯一例外的是新推出的GeForce 6600 GT显卡，它是系列中暂时最高端的显卡。

Ultra：NVIDA 显卡中最顶端的显卡，与ATI中的“XT”类似。

代表产品有6800 Ultra，5700Ultra。

二、系统一些的解释：nVidia的：Ultra旗舰级，在GF7系列之前代表着最高端，但7系列最高端的命名就改为GTX。

GTX是高端中的高端一般可以理解为GT eXtreme。

GT就是比GS更高一级的，是该系列中的高端，不过这在GeForce 8600系列显卡中表现得不是很明显，似乎已经成为主打产品，有点汽车中GT的味道。

GS不得而知，只知道GS是该系列中的主打产品，如之前的7600GS、7900GS。

GS881Z36BGD-150V中文资料

GS881Z18/32/36B(T/D)-xxxV9Mb Pipelined and Flow ThroughSynchronous NBT SRAM250 MHz–150 MHz 1.8 V or 2.5 V V DD 1.8 V or 2.5 V I/O100-Pin TQFP & 165-Bump BGA Commercial Temp Industrial Temp Features• User-configurable Pipeline and Flow Through mode• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization• Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs• IEEE 1149.1 JTAG-compatible Boundary Scan• On-chip write parity checking; even or odd selectable • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply• LBO pin for Linear or Interleave Burst mode • Pin-compatible with 2M, 4M, and 18M devices • Byte write operation (9-bit Bytes)• 3 chip enable signals for easy depth expansion • ZZ pin for automatic power-down • JEDEC-standard packages• RoHS-compliant 100-lead TQFP and 165-bump BGA packages availableFunctional DescriptionThe GS881Z18/32/36B(T/D)-xxxV is a 9Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable, ZZ and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.The GS881Z18/32/36B(T/D)-xxxV may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, in addition to the rising-edge-triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.The GS881Z18/32/36B(T/D)-xxxV is implemented with GSI's high performance CMOS technology and is available inJEDEC-standard 100-pin TQFP and 165-bump BGA packages.Paramter Synopsis-250-200-150UnitPipeline 3-1-1-1KQ tCycle 4.0 5.0 6.7ns Curr (x18)Curr (x32/x36)200230170195140160mA mA Flow Through 2-1-1-1t KQ tCycle 5.55.5 6.56.57.57.5ns ns Curr (x18)Curr (x32/x36)160185140160128145mA mA807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B FT V DD NC V SS DQ B DQ B6V DD V SS DQ B DQ B DQP BV SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A A 1A A E 1E 2 N C N C B BB AE 3C K W C K E VD DV S SG A D V N C A A AA 512K x 18Top View DQP A A NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881Z18/32/36B(T/D)-xxxVGS881Z18BT-xxxV 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D2V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A E 1E 2 B DB CB BB AE 3C K W C K E VD DV S SG A D V N C A A AA 256K x 32Top View DQB NC DQ B DQ B DQ B DQ A DQ A DQ A DQ A NCDQ C DQ C DQ C DQ D DQ D DQ D NCDQ C NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881Z18/32/36B(T/D)-xxxVGS881Z32BT-xxxV 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D2V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0T M S T D I V S SV D DT D O T C K A A A A A AA A E 1E 2 B DB CB BB AE 3C K W C K E VD DV S SG A D V N C A A AA 256K x 36Top View DQB DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP ADQ C DQ C DQ C DQ D DQ D DQ D DQP DDQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS881Z18/32/36B(T/D)-xxxVGS881Z36BT-xxxV 100-Pin TQFP Pinout (Package T)100-Pin TQFP Pin DescriptionsSymbolTypeDescriptionA 0, A 1In Burst Address Inputs; Preload the burst counterA In Address Inputs CK In Clock Input SignalB A In Byte Write signal for data inputs DQ A1–DQ A9; active low B B In Byte Write signal for data inputs DQ B1–DQ B9; active low BC In Byte Write signal for data inputs DQ C1–DQ C9; active low BD In Byte Write signal for data inputs DQ D1–DQ D9; active lowW In Write Enable; active low E 1In Chip Enable; active lowE 2In Chip Enable—Active High. For self decoded depth expansion E 3In Chip Enable—Active Low. For self decoded depth expansionG In Output Enable; active lowADV In Advance/Load; Burst address counter control pinCKE In Clock Input Buffer Enable; active lowNC —No ConnectDQ A I/O Byte A Data Input and Output pins DQ B I/O Byte B Data Input and Output pins DQ C I/O Byte C Data Input and Output pins DQ D I/O Byte D Data Input and Output pins ZZ In Power down control; active high FT In Pipeline/Flow Through Mode Control; active lowLBO InLinear Burst Order; active low.TMS Scan Test Mode Select TDI Scan Test Data In TDO Scan Test Data Out TCK Scan Test Clock V DD In Core power supplyV SS In GroundV DDQInOutput driver power supplyGS881Z18/32/36B(T/D)-xxxVGS881Z18/32/36B(T/D)-xxxV165 Bump BGA—x18 Commom I/O—Top View 1234567891011A NC A E1BB NC E3CKE ADV A17A A A B NC A E2NC BA CK W G NC A NC B C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQA C D NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA D E NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA E F NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA F G NC DQB V DDQ V DD V SS V SS V SS V DD V DDQ NC DQA G H FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC J K DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC K L DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC L M DQB NC V DDQ V DD V SS V SS V SS V DD V DDQ DQA NC M N DQB NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A NC P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS881Z18/32/36B(T/D)-xxxV165 Bump BGA—x32 Common I/O—Top View 1234567891011A NC A E1BC BB E3CKE ADV A17A NC A B NC A E2BD BA CK W G NC A NC B C NC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC NC C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N NC NC V DDQ V SS NC NC NC V SS V DDQ NC NC N P NC NC A A TDI A1TDO A A A NC P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS881Z18/32/36B(T/D)-xxxV165 Bump BGA—x36 Common I/O—Top View 1234567891011A NC A E1BC BB E3CKE ADV A A NC A B NC A E2BD BA CK W G NC A NC B C DQPC NC V DDQ V SS V SS V SS V SS V SS V DDQ NC DQPB C D DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB D E DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB E F DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB F G DQC DQC V DDQ V DD V SS V SS V SS V DD V DDQ DQB DQB G H FT MCH NC V DD V SS V SS V SS V DD NC NC ZZ H J DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA J K DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA K L DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA L M DQD DQD V DDQ V DD V SS V SS V SS V DD V DDQ DQA DQA M N DQPD NC V DDQ V SS NC NC NC V SS V DDQ NC DQPA N P NC NC A A TDI A1TDO A A A NC P RLBONCAATMSA0TCKAAAAR11 x 15 Bump BGA—13 mm x 15 mm Body—1.0 mm Bump Pitch(Package D)GS881Z18/32/36D-xxxV165-Bump BGA Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter Preset InputsA I Address Inputs DQ A DQB DQC DQD I/O Data Input and Output pinsB A , B B , BC , B DI Byte Write Enable for DQ A , DQ B , DQ C , DQ D I/Os; active lowNC —No ConnectCK I Clock Input Signal; active high CKE I Clock Enable; active low W I Write Enable; active low E 1I Chip Enable; active low E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active highZZ I Sleep mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowTMS I Scan Test Mode Select TDI I Scan Test Data In TDO O Scan Test Data Out TCK I Scan Test Clock MCH —Must Connect High DNU —Do Not Use V DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS881Z18/32/36B(T/D)-xxxVK18S A 1S A 0Bu r s t C o u n t e rL B OA D VM e m o r y A r r a yGC KC K ED QF TN CN CD Q a –D Q nKS A 1’S A 0’D QM a t c hW r i t e A d d r e s sR e g i s t e r 2W r i t e A d d r e s sR e g i s t e r 1W r i t e D a t aR e g i s t e r 2W r i t e D a t aR e g i s t e r 1KKKKKKS e n s e A m p sW r i t e D r i v e r sR e a d , W r i t e a n dD a t a C o h e r e n c yC o n t r o l L o g i cD QKP a r i t y C h e c kF TA 0–A nE 3E 2E 1WB DB CB BB AGS881Z18/32/36B(T/D)-xxxVGS881Z18/32/36B(T/D)-xxxV NBT SRAM Functional Block DiagramGS881Z18/32/36B(T/D)-xxxVFunctional DetailsClockingDeassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.Pipeline Mode Read and Write OperationsAll inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E 1, E 2 and E 3). Deassertion of any one of the Enable inputs will deactivate the device. Function W B A B B B C B D Read H X X X X Write Byte “a”L L H H H Write Byte “b”L H L H H Write Byte “c”L H H L H Write Byte “d”L H H H L Write all Bytes L L L L L Write Abort/NOPLHHHHRead operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted low, all three chip enables (E 1, E 2, and E 3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.Write operation occurs when the RAM is selected, CKE is active and the write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (B A , B B , B C & B D ) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality, matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.Flow Through Mode Read and Write OperationsOperation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a read cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.Synchronous Truth TableOperationType Address CK CKE ADV W Bx E 1E 2E 3G ZZDQNotesRead Cycle, Begin Burst R External L-H L L H X L H L L L Q Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3Write Cycle, Continue Burst B Next L-H L H X L X X X X L D1,3,10Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z Deselect Cycle D None L-H L L L H L H L X L High-Z 1Deselect Cycle, Continue DNone L-H L H X X X X X X L High-Z 1Sleep ModeNone X X X X X X X X X H High-Z Clock Edge Ignore, StallCurrentL-HHXXXXXXXL-4Notes:1.Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-lect cycle is executed first.2.Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the Wpin is sampled low but no Byte Write pins are active so no write operation is performed.3.G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off duringwrite cycles.4.If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the buswill remain in High Z.5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Writesignals are Low6.All inputs, except G and ZZ must meet setup and hold times of rising clock edge.7.Wait states can be inserted by setting CKE high.8.This device contains circuitry that ensures all outputs are in High Z during power-up.9. A 2-bit burst counter is incorporated.10.The address counter is incriminated for all Burst continue cycles.GS881Z18/32/36B(T/D)-xxxVGS881Z18/32/36B(T/D)-xxxVDeselectNew ReadNew WriteBurst ReadBurst WriteWRBRBWDDBBWRD BWRDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input commandcodes as indicated in the Synchronous Truth Table.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipelined and Flow Through Read/Write Control State DiagramWRPipelined and Flow Through Read Write Control State DiagramGS881Z18/32/36B(T/D)-xxxVIntermediateIntermediateIntermediateIntermediateIntermediateIntermediateHigh Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)TransitionƒInput Command CodeKeyTransitionIntermediate State (N+1)Notes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateIntermediate ƒn n+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipeline Mode Data I/O State DiagramNext StateStatePipeline Mode Data I/O State DiagramGS881Z18/32/36B(T/D)-xxxVFlow Through Mode Data I/O State Diagram High Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for: Pipeline and Flow through Read Write Control State DiagramGS881Z18/32/36B(T/D)-xxxVBurst CyclesAlthough NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.Burst OrderThe burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have beenaccessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down ControlZZL or NC Active HStandby, I DD = I SBNote:There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table.Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS881Z18/32/36B(T/D)-xxxVSleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after ZZ recovery time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZStKLtKHtKCCKZZDesigning for CompatibilityThe GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipelinemode via the FT signal found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V DD or V DDQ on pipelined parts and V SS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.Pin 66, a No Connect (NC) on GSI’s GS8160Z18/36 NBT SRAM, the Parity Error open drain output on GSI’s GS881Z18/36B NBT SRAM, is often marked as a power pin on other vendor’s NBT compatible SRAMs. Specifically, it is marked V DD or V DDQ on pipelined parts and V SS on flow through parts. Users of GSI NBT devices who are not actually using the ByteSafe™ parity feature may want to design the board site for the RAM with Pin 66 tied high through a 1k ohm resistor in Pipeline modeapplications or tied low in Flow Through mode applications in order to keep the option to use non-configurable devices open.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage on V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS881Z18/32/36B(T/D)-xxxVNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version)ParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD1 1.7 1.82.0V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 1.8 V V DDQ I/O Supply Voltage V DDQ1 1.7 1.8V DD V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.5V DDVNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS881Z18/32/36B(T/D)-xxxVV DDQ2 & V DDQ1 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low VoltageV IL–0.3—0.3*V DDV1Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceFigure 1Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS881Z18/32/36B(T/D)-xxxVDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA FT, ZZ Input Current I IN V DD ≥ V IN ≥ 0 V –100 uA 100 uA Output Leakage CurrentI OLOutput Disable, V OUT = 0 to V DD–1 uA1 uADC Output Characteristics (1.8 V/2.5 V Version)ParameterSymbolTest ConditionsMinMax1.8 V Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V —2.5 V Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V1.7 V —1.8 V Output Low Voltage V OL1I OL = 4 mA —0.4 V2.5 V Output Low VoltageV OL2I OL = 8 mA—0.4 VGS881Z18/32/36B(T/D)-xxxVOperating CurrentsParameterTest ConditionsModeSymbol-250-200-150Unit0to 70°C–40 to 85°C0to 70°C –40to 85°C 0 to 70°C –40to 85°COperating CurrentDevice Selected; All other inputs ≥V IH o r ≤ V IL Output open(x32/x36)PipelineI DD I DDQ 200302203017025190251402016020mA Flow Through I DD I DDQ 160251802514020160201301515015mA (x18)PipelineI DD I DDQ 185152051515515175151301015010mA Flow ThroughI DD I DDQ 1451516515130101501012081408mA Standby Current ZZ ≥ V DD – 0.2 V —Pipeline I SB 405040504050mA Flow Through I SB 405040504050mA Deselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—PipelineI DD 859075806065mA Flow Through I DD606550555055mA1.I DD and I DDQ apply to any combination of V DD1, V DD2, V DDQ1, and V DDQ2 operation.2.All parameters listed are worst case scenario.。

GS8662S08E-250I资料

PreliminaryGS8662S08/09/18/36E-333/300/250/200/16772Mb Burst of 2DDR SigmaSIO-II SRAM333 MHz–167 MHz1.8 V V DD1.8 V and 1.5 V I/O165-Bump BGA Commercial Temp Industrial Temp Features• Simultaneous Read and Write SigmaSIO™ Interface • JEDEC-standard pinout and package • Dual Double Data Rate interface• Byte Write controls sampled at data-in time• DLL circuitry for wide output data valid window and future frequency scaling• Burst of 2 Read and Write• 1.8 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation• Fully coherent read and write pipelines• ZQ mode pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • Pin-compatible with future 144Mb devices• 165-bump, 15 mm x 17 mm, 1 mm bump pitch BGA package • RoHS-compliant 165-bump BGA package availableSigmaRAM ™ Family OverviewGS8662S08/09/18/36 are built in compliance with the SigmaSIO-II SRAM pinout standard for Separate I/O synchronous SRAMs. They are 75,497,472-bit (72Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems.165-Bump, 15 mm x 17 mm BGA 1 mm Bump Pitch, 11 x 15 Bump Array Bottom ViewJEDEC Std. MO-216, Variation CAB-1Clocking and Addressing SchemesA Burst of 2 SigmaSIO-II SRAM is a synchronous device. It employs dual input register clock inputs, K and K. The device also allows the user to manipulate the output register clock input quasi independently with dual output register clock inputs, C and C. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Each Burst of 2 SigmaSIO-II SRAM also supplies Echo Clock outputs, CQ and CQ, which are synchronized with read data output. When used in a source synchronous clocking scheme, the Echo Clock outputs can be used to fire input registers at the data’s destination.Because Separate I/O Burst of 2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a Burst of 2 RAM is always one address pin less than the advertised index depth (e.g., the 4M x 18 has a 1M addressable index).Parameter Synopsis- 333-300-250-200-167tKHKH 3.0 ns 3.3 ns 4.0 ns 5.0 ns 6.0 ns tKHQV0.45 ns0.45 ns0.45 ns0.45 ns0.5 ns8M x 8 SigmaQuad SRAM—Top View1234567891011ACQ SA SA R/W NW1K NC LD SA SA CQ B NC NC NC SA NC K NW0SA NC NC Q3C NC NC NC V SS SA SA SA V SS NC NC D3D NC D4NC V SS V SS V SS V SS V SS NC NC NC E NC NC Q4 V DDQ V SS V SS V SS V DDQ NC D2Q2F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC D5Q5 V DDQ V DD V SS V DD V DDQ NC NC NC H D OFF V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC Q1D1K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC Q6D6 V DDQ V SS V SS V SS V DDQ NC NC Q0M NC NC NC V SS V SS V SS V SS V SS NC NC D0N NC D7NC V SS SA SA SA V SS NC NC NC P NC NC Q7SA SA C SA SA NC NC NC RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.NW0 controls writes to D0:D3. NW1 controls writes to D4:D7.2.It is recommended that H1 be tied low for compatibility with future devices.GS8662S08/09/18/36E-333/300/250/200/1678M x 9 SigmaQuad SRAM—Top View1234567891011ACQ SA SA R/W NC K NC LD SA SA CQ B NC NC NC SA NC K BW SA NC NC Q4C NC NC NC V SS SA SA SA V SS NC NC D4D NC D5NC V SS V SS V SS V SS V SS NC NC NC E NC NC Q5 V DDQ V SS V SS V SS V DDQ NC D3Q3F NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC G NC D6Q6 V DDQ V DD V SS V DD V DDQ NC NC NC H Doff V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC NC V DDQ V DD V SS V DD V DDQ NC Q2D2K NC NC NC V DDQ V DD V SS V DD V DDQ NC NC NC L NC Q7D7 V DDQ V SS V SS V SS V DDQ NC NC Q1M NC NC NC V SS V SS V SS V SS V SS NC NC D1N NC D8NC V SS SA SA SA V SS NC NC NC P NC NC Q8SA SA C SA SA NC D0NC RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW controls writes to D0:D71.It is recommended that H1 be tied low for compatibility with future devices.GS8662S08/09/18/36E-333/300/250/200/1674M x 18 SigmaQuad SRAM—Top View1234567891011ACQ V SS /SA (144Mb)SA R/W BW1K NC LD SA SA CQ B NC Q9D9SA NC K BW0SA NC NC Q8C NC NC D10V SS SA SA SA V SS NC Q7D8D NC D11Q10V SS V SS V SS V SS V SS NC NC D7E NC NC Q11 V DDQ V SS V SS V SS V DDQ NC D6Q6F NC Q12D12 V DDQ V DD V SS V DD V DDQ NC NC Q5G NC D13Q13 V DDQ V DD V SS V DD V DDQ NC NC D5H D OFF V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J NC NC D14 V DDQ V DD V SS V DD V DDQ NC Q4D4K NC NC Q14V DDQ V DD V SS V DD V DDQ NC D3Q3L NC Q15D15 V DDQ V SS V SS V SS V DDQ NC NC Q2M NC NC D16 V SS V SS V SS V SS V SS NC Q1D2N NC D17Q16 V SS SA SA SA V SS NC NC D1P NC NC Q17SA SA C SA SA NC D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.2.It is recommended that H1 be tied low for compatibility with future devices.GS8662S08/09/18/36E-333/300/250/200/1672M x 36 SigmaQuad SRAM—Top View1234567891011ACQ V SS /SA (288Mb)SA R/W BW2K BW1LD SA V SS /SA (144Mb)CQ B Q27Q18D18SA BW3K BW0SA D17Q17Q8C D27Q28D19V SS SA SA SA V SS D16Q7D8D D28D20Q19V SS V SS V SS V SS V SS Q16D15D7E Q29D29Q20 V DDQ V SS V SS V SS V DDQ Q15D6Q6F Q30Q21D21 V DDQ V DD V SS V DD V DDQ D14Q14Q5G D30D22Q22 V DDQ V DD V SS V DD V DDQ Q13D13D5H D OFF V REF V DDQ V DDQ V DD V SS V DD V DDQ V DDQ V REF ZQ J D31Q31D23 V DDQ V DD V SS V DD V DDQ D12Q4D4K Q32D32Q23V DDQ V DD V SS V DD V DDQ Q12D3Q3L Q33Q24D24 V DDQ V SS V SS V SS V DDQ D11Q11Q2M D33Q34D25 V SS V SS V SS V SS V SS D10Q1D2N D34D26Q25 V SS SA SA SA V SS Q10D9D1P Q35D35Q26SA SA C SA SA Q9D0Q0RTDOTCKSASASACSASASATMSTDI11 x 15 Bump BGA—15 x 17 mm 2 Body—1 mm Bump PitchNotes:1.BW0 controls writes to D0:D8. BW1 controls writes to D9:D17.2.BW2 controls writes to D18:D26. BW3 controls writes to D27:D35.3.It is recommended that H1 be tied low for compatibility with future devices.GS8662S08/09/18/36E-333/300/250/200/167Pin Description TableSymbolDescriptionTypeCommentsSA Synchronous Address InputsInput —NC No Connect ——R/W Read/Write Contol Pin Input Write Active Low; Read Active HighNW0–NW1Synchronous Nybble Writes Input Active Low x08 Version BW0–BW1Synchronous Byte Writes Input Active Low x18 Version BW0–BW3Synchronous Byte WritesInput Active Low x36 Version K Input Clock Input Active High C Output Clock Input Active HighTMS Test Mode Select Input —TDI Test Data Input Input —TCK Test Clock Input Input —TDO Test Data Output Output —V REF HSTL Input Reference Voltage Input —ZQ Output Impedance Matching InputInput —K Input Clock Input Active Low C Output Clock Output Active Low D OFF DLL Disable —Active Low LD Synchronous Load Pin —Active Low CQ Output Echo Clock Output Active Low CQ Output Echo Clock Output Active HighDn Synchronous Data Inputs Input Qn Synchronous Data OutputsOutput V DD Power Supply Supply 1.8 V Nominal V DDQ Isolated Output Buffer Supply Supply 1.8 or 1.5 V NominalV SSPower Supply: GroundSupply—1.C, C, K, or K cannot be set to V REF voltage.2.When ZQ pin is directly connected to V DD , output impedance is set to minimum value and it cannot be connected to ground or leftunconnected.3.NC = Not Connected to die or any other pinGS8662S08/09/18/36E-333/300/250/200/167GS8662S08/09/18/36E-333/300/250/200/167BackgroundSeparate I/O SRAMs, like SigmaQuad SRAMs, are attractive in applications where alternating reads and writes are needed. On the other hand, Common I/O SRAMs like the SigmaCIO family are popular in applications where bursts of read or write traffic are needed. The SigmaSIO SRAM is a hybrid of these two devices. Like the SigmaQuad family devices, the SigmaSIO features a separate I/O data path, offering the user independent Data In and Data Out pins. However, the SigmaSIO devices offer a control protocol like that offered on the SigmaCIO devices. Therefore, while SigmaQuad SRAMs allow a user to operate both data ports at the same time, they force alternating loads of read and write addresses. SigmaSIO SRAMs allow continuous loads of read or write addresses like SigmaCIO SRAMs, but in a separate I/O configuration.Like a SigmaQuad SRAM, a SigmaSIO-II SRAM can execute an alternating sequence of reads and writes. However, doing so results in the Data In port and the Data Out port stalling with nothing to do on alternate transfers. A SigmaQuad device would keep both ports running at capacity full time. On the other hand, the SigmaSIO device can accept a continuous stream of read commands and read data or a continuous stream of write commands and write data. The SigmaQuad device, by contrast, restricts the user from loading a continuous stream of read or write addresses. The advantage of the SigmaSIO device is that it allows twice the random address bandwidth for either reads or writes than could be acheived with a SigmaQuad version of the device. SigmaCIO SRAMs offer this same advantage, but do not have the separate Data In and Data Out pins offered on the SigmaSIO SRAMs. Therefore, SigmaSIO devices are useful in psuedo dual port SRAM applications where communication of burst traffic between two electrically independent busses is desired.Each of the three SigmaQuad Family SRAMs—SigmaQuad, SigmaCIO, and SigmaSIO—supports similar address rates because random address rate is determined by the internal performance of the RAM. In addition, all three SigmaQuad Family SRAMs are based on the same internal circuits. Differences between the truth tables of the different devices proceed from differences in how the RAM’s interface is contrived to interact with the rest of the system. Each mode of operation has its own advantages and disadvantages. The user should consider the nature of the work to be done by the RAM to evaluate which version is best suited to the application at hand.Burst of 2 Sigma SIO-II SRAM DDR ReadThe status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A high on the R/W pin begins a read cycle. The two resulting data output transfers begin after the next rising edge of the K clock. Data is clocked out by the next rising edge of the C if it is active. Otherwise, data is clocked out at the next rising edge of K. The next data chunk is clocked out on the rising edge of C, if active. Otherwise, data is clocked out on the rising edge of K.Burst of 2 Sigma SIO-II SRAM DDR WriteThe status of the Address Input, R/W, and LD pins are sampled at each rising edge of K. LD high causes chip disable. A low on the R/W pin, begins a write cycle. Data is clocked in by the next rising edge of K and then the rising edge of K.GS8662S08/09/18/36E-333/300/250/200/167Power-Up Sequence for SigmaQuad-II SRAMsSigmaQuad-II SRAMs must be powered-up in a specific sequence in order to avoid undefined operations.Power-Up Sequence1. Power-up and maintain Doff at low state.1a.Apply V DD .1b. Apply V DDQ .1c. Apply V REF (may also be applied at the same time as V DDQ ).2. After power is achieved and clocks (K, K, C, C) are stablized, change Doff to high.3. An additional 1024 clock cycles are required to lock the DLL after it has been enabled.Note:If you want to tie Doff high with an unstable clock, you must stop the clock for a minimum of 30 seconds to reset the DLL after the clocks become stablized.DLL Constraints•The DLL synchronizes to either K or C clock. These clocks should have low phase jitter (t KCVar on page 21).•The DLL cannot operate at a frequency lower than 119 MHz.•If the incoming clock is not stablized when DLL is enabled, the DLL may lock on the wrong frequency and cause undefined errors or failures during the initial stage.Power-Up Sequence (Doff controlled)Power UP IntervalUnstable Clocking IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoffPower-Up Sequence (Doff tied High)Power UP IntervalUnstable Clocking IntervalStop Clock IntervalDLL Locking Interval (1024 Cycles)Normal OperationKKV DDV DDQV REFDoff30ns MinNote:If the frequency is changed, DLL reset is required. After reset, a minimum of 1024 cycles is required for DLL lock.GS8662S08/09/18/36E-333/300/250/200/167Special FunctionsByte Write and Nybble Write ControlByte Write Enable pins are sampled at the same time that Data In is sampled. A high on the Byte Write Enable pin associated with a particular byte (e.g., BW0 controls D0–D8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. Any or all of the Byte Write Enable pins may be driven high or low during the data in sample times in a write sequence.Each write enable command and write address loaded into the RAM provides the base address for a 2 beat data transfer. The x18 version of the RAM, for example, may write 36 bits in association with each address loaded. Any 9-bit byte may be masked in any write sequence.Nybble Write (4-bit) control is implemented on the 8-bit-wide version of the device. For the x8 version of the device, “Nybble Write Enable” and “NWx” may be substituted in all the discussion above.Example x18 RAM Write Sequence using Byte Write EnablesData In SampleBW0BW1D0–D8D9–D17TimeBeat 101Data In Don’t CareBeat 210Don’t Care Data InResulting Write OperationBeat 1Beat 2D0–D8D9–D17D0–D8D9–D17Written Unchanged Unchanged WrittenOutput Register ControlSigmaSIO-II SRAMs offer two mechanisms for controlling the output data registers. Typically, control is handled by the Output Register Clock inputs, C and C. The Output Register Clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of the K and K clocks. If the C and C clock inputs are tied high, the RAM reverts to K and K control of the outputs.A K LD R/WA 0–A nK LD 0D 1–D nBank 0Bank 1Bank 2Bank 3R/W 0D A K R/W D A K R/W D A KR/W D LDLDLD QQQ QCCCCQ 1–Q nC LD 1R/W 1LD 2R/W 2LD 3R/W 3Note:For simplicity BWn is not shown.GS8662S08/09/18/36E-333/300/250/200/167Example Four Bank Depth Expansion SchematicGS8662S08/09/18/36E-333/300/250/200/167Burst of 2 SigmaSIO-II SRAM Depth ExpansionWrite BRead C Write D Read E Write F Read G Read H Read J NOPBCDEFGHJBB+1FF+1DD+1EE+1HH+1CC+1GG+1JK K Address LD Bank 1LD Bank 2R/W Bank 1R/W Bank 2BWx Bank 1BWx Bank 2D Bank 1D Bank 2C Bank 1C Bank 1Q Bank 1CQ Bank 1CQ Bank 1C Bank 2C Bank 2Q Bank 2CQ Bank 2CQ Bank 2GS8662S08/09/18/36E-333/300/250/200/167FLXDrive-II Output Driver Impedance ControlHSTL I/O SigmaSIO-II SRAMs are supplied with programmable impedance output drivers. The ZQ pin must be connected to V SS via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a vendor-specified tolerance is between 150Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and temperature. The SRAM’s output impedance circuitry compensates for drifts in supply voltage and temperature every 1024 cycles. A clock cycle counter periodically triggers an impedance evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. Impedance updates for “0s” occur whenever the SRAM is driving “1s” for the same DQs (and vice-versa for “1s”) or the SRAM is in HI-Z.Separate I/O Burst of 2 Sigma SIO-II SRAM Truth TableA LD R/WCurrentOperationD D Q QK ↑(t n)K ↑(t n)K ↑(t n)K ↑(t n)K ↑(t n+1)K ↑(t n+1)K ↑(t n+1)K ↑(t n+1)X1X Deselect X—Hi-Z—V01Read X—Q0Q1 V00Write D0D1Hi-Z—Notes:1.“1” = input “high”; “0” = input “low”; “V” = input “valid”; “X” = input “don’t care”2.“—” indicates that the input requirement or output state is determined by the next operation.3.Q0 and Q1 indicate the first and second pieces of output data transferred during Read operations.4.D0 and D1 indicate the first and second pieces of input data transferred during Write operations.5.Qs are tristated for one cycle in response to Deselect and Write commands, one cycle after the command is sampled, except when pre-ceded by a Read command.6.CQ is never tristated.ers should not clock in metastable addresses.x18 Byte Write Clock Truth TableBW BW Current OperationD D K ↑(t n+1)K ↑(t n+2)K ↑(t n )K ↑(t n+1)K ↑(t n+2)TTWriteDx stored if BWn = 0 in both data transfers D1D2T F WriteDx stored if BWn = 0 in 1st data transfer only D1XF T WriteDx stored if BWn = 0 in 2nd data transfer onlyX D2F F Write AbortNo Dx stored in either data transferX XNotes:1.“1” = input “high”; “0” = input “low”; “X” = input “don’t care”; “T” = input “true”; “F” = input “false”.2.If one or more BWn = 0, then BW = “T”, else BW = “F”.GS8662S08/09/18/36E-333/300/250/200/167x36 Byte Write Enable (BWn) Truth TableBW3BW2BW1BW0D27–D35D18–D26D9–D17D0–D81111Don’t Care Don’t Care Don’t Care Don’t Care 0111Don’t Care Don’t Care Don’t Care Data In 1011Don’t Care Don’t Care Data In Don’t Care 0011Don’t Care Don’t Care Data In Data In 1101Don’t Care Data In Don’t Care Don’t Care 0101Don’t Care Data In Don’t Care Data In 1001Don’t Care Data In Data In Don’t Care 0001Don’t Care Data In Data In Data In 1110Data In Don’t Care Don’t Care Don’t Care 0110Data In Don’t Care Don’t Care Data In 1010Data In Don’t Care Data In Don’t Care 0010Data In Don’t Care Data In Data In 1100Data In Data In Don’t Care Don’t Care 0100Data In Data In Don’t Care Data In 1000Data In Data In Data In Don’t Care 0Data InData InData InData Inx8 Nybble Write Enable (NWn) Truth Table NW1NW0D9–D17D0–D811Don’t Care Don’t Care 01Don’t Care Data In 10Data In Don’t Care 0Data InData InGS8662S08/09/18/36E-333/300/250/200/167GS8662S08/09/18/36E-333/300/250/200/167State DiagramPower-UpNOPLoad NewDDR Read DDR WriteREADLOADWRITELOADLOADLOADLOADLOADAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 2.9V V DDQ Voltage in V DDQ Pins –0.5 to V DD V V REF Voltage in V REF Pins –0.5 to V DDQV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.3 (≤ 2.9 V max.)V V IN Voltage on Other Input Pins –0.5 to V DDQ +0.3 (≤ 2.9 V max.)V I IN Input Current on Any Pin +/–100mA dc I OUT Output Current on Any I/O Pin +/–100mA dcT J Maximum Junction Temperature125o C T STGStorage Temperature–55 to 125oCNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Recommended Operating Conditions, for an extended period of time, may affect reliability of this component.GS8662S08/09/18/36E-333/300/250/200/167Recommended Operating ConditionsPower SuppliesParameterSymbolMin.Typ.Max.UnitSupply Voltage V DD 1.7 1.8 1.9V I/O Supply Voltage V DDQ 1.7 1.8 1.9V Reference VoltageV REF0.68—0.95VNotes:1.Unless otherwise noted, all performance specifications quoted are evaluated for worst case at both 1.4 V ≤ V DDQ ≤ 1.6 V (i.e., 1.5 V I/O)and 1.7 V ≤ V DDQ ≤ 1.95 V (i.e., 1.8 V I/O) and quoted at whichever condition is worst case.2.The power supplies need to be powered up simultaneously or in the following sequence: V DD , V DDQ , V REF , followed by signal inputs. Thepower down sequence must be the reverse. V DDQ must not exceed V DD .Operating TemperatureParameterSymbolMin.Typ.Max.UnitAmbient Temperature (Commercial Range Versions)T A 02570°C Ambient Temperature (Industrial Range Versions)T A–402585°CGS8662S08/09/18/36E-333/300/250/200/167HSTL I/O DC Input CharacteristicsParameterSymbolMinMaxUnitsNotesDC Input Logic High V IH (dc)V REF + 0.1V DDQ + 0.3mV 1DC Input Logic LowV IL (dc)–0.3V REF – 0.1mV1Note:Compatible with both 1.8 V and 1.5 V I/O driversHSTL I/O AC Input CharacteristicsParameterSymbolMinMaxUnitsNotesAC Input Logic High V IH (ac)V REF + 0.2—mV 3,4AC Input Logic LowV IL (ac)—V REF – 0.2mV 3,4V REF Peak to Peak AC VoltageV REF (ac)—5% V REF (DC)mV1Notes:1.The peak to peak AC component superimposed on V REF may not exceed 5% of the DC component of V REF .2.To guarantee AC characteristics, V IH ,V IL , Trise, and Tfall of inputs and clocks must be within 10% of each other.3.For devices supplied with HSTL I/O input buffers. Compatible with both 1.8 V and 1.5 V I/O drivers.4.See AC Input Definition drawing below.V IH (ac)V REF V IL (ac)HSTL I/O AC Input Definitions20% tKHKHV SS – 1.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKHKHV DD + 1.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DDParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Output CapacitanceC OUTV OUT = 0 V67pFNote: This parameter is sample tested.GS8662S08/09/18/36E-333/300/250/200/167AC Test ConditionsParameterConditionsInput high level V DDQ Input low level 0 V Max. input slew rate 2 V/ns Input reference level V DDQ /2Output reference levelV DDQ /2Note:Test conditions as specified with output loading as shown unless otherwise noted.DQVT = V DDQ /250ΩRQ = 250 Ω (HSTL I/O)V REF = 0.75 VAC Test Load DiagramInput and Output Leakage CharacteristicsParameterSymbolTest ConditionsMin.MaxNotesInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –2 uA 2 uA DoffI INDOFF V DD ≥ V IN ≥ V IL 0 V ≤ V IN ≤ V IL –100 uA –2 uA 2 uA 2 uA Output Leakage CurrentI OLOutput Disable,V OUT = 0 to V DDQ–2 uA2 uA(T A = 25= 3.3 V)GS8662S08/09/18/36E-333/300/250/200/167Programmable Impedance HSTL Output Driver DC Electrical CharacteristicsParameterSymbolMin.Max.UnitsNotesOutput High Voltage V OH1 V DDQ /2 – 0.12V DDQ /2 + 0.12V 1, 3Output Low Voltage V OL1 V DDQ /2 – 0.12V DDQ /2 + 0.12V 2, 3Output High Voltage V OH2 V DDQ – 0.2V DDQ V 4, 5Output Low VoltageV OL2Vss0.2V4, 6Notes:1. I OH = (V DDQ /2) / (RQ/5) +/– 15% @ V OH = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).2. I OL = (V DDQ /2) / (RQ/5) +/– 15% @ V OL = V DDQ /2 (for: 175Ω ≤ RQ ≤ 350Ω).3.Parameter tested with RQ = 250Ω and V DDQ = 1.5 V or 1.8 V4.Minimum Impedance mode, ZQ = V SS5.I OH = –1.0 mA6.I OL = 1.0 mAOperating CurrentsParameterSymbolTest Conditions-333-300-250-200-167Notes0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C 0to 70°C –40 to 85°C Operating Current (x36): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBDTBDTBDTBDTBDTBDTBDTBDTBDTBD2, 3Operating Current (x18): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x9): DDR I DD V DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Operating Current (x8): DDR I DDV DD = Max, I OUT = 0 mA Cycle Time ≥ t KHKH Min TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 3Standby Current (NOP): DDR I SB1Device deselected,I OUT= 0 mA, f = Max,All Inputs ≤ 0.2 V or ≥ V DD – 0.2 VTBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 2, 4Notes:1.Power measured with output pins floating.2.Minimum cycle, I OUT = 0 mA3.Operating current is calculated with 50% read cycles and 50% write cycles.4.Standby Current is only after all pending read and write burst operations are completed.GS8662S08/09/18/36E-333/300/250/200/167GS8662S08/09/18/36E-333/300/250/200/167AC Electrical CharacteristicsParameterSymbol-333-300-250-200-167UnitsN o t e sMin Max Min Max Min Max Min Max Min MaxClockK, K Clock Cycle Time C, C Clock Cycle Time t KHKH t CHCH 3.0 3.5 3.3 4.2 4.0 6.3 5.07.9 6.08.4ns tTKC Variablet KCVar —0.2—0.2—0.2—0.2—0.2ns 5K, K Clock High Pulse Width C, C Clock High Pulse Width t KHKL t CHCL 1.2— 1.32— 1.6— 2.0— 2.4—ns K, K Clock Low Pulse Width C, C Clock Low Pulse Width t KLKH t CLCH 1.2— 1.32— 1.6— 2.0— 2.4—ns K to K High C to C Hight KHKH 1.35— 1.49— 1.8— 2.2— 2.7—ns K, K Clock High to C, C Clock High t KHCH 0 1.30 1.450 1.80 2.30 2.8ns DLL Lock Time t KCLock 1024—1024—1024—1024—1024—cycle 6K Static to DLL resett KCReset 30—30—30—30—30—nsOutput TimesK, K Clock High to Data Output Valid C, C Clock High to Data Output Valid t KHQV t CHQV —0.45—0.45—0.45—0.45—0.5ns 3K, K Clock High to Data Output Hold C, C Clock High to Data Output Hold t KHQX t CHQX –0.45—–0.45—–0.45—–0.45—–0.5—ns 3K, K Clock High to Echo Clock Valid C, C Clock High to Echo Clock Valid t KHCQV t CHCQV —0.45—0.45—0.45—0.45—0.5ns K, K Clock High to Echo Clock Hold C, C Clock High to Echo Clock Hold t KHCQX t CHCQX –0.45—–0.45—–0.45—–0.45—–0.5—ns CQ, CQ High Output Valid t CQHQV —0.25—0.27—0.30—0.35—0.40ns 7CQ, CQ High Output Hold t CQHQX –0.25—–0.27—–0.30—–0.35—–0.40—ns 7K Clock High to Data Output High-Z C Clock High to Data Output High-Z t KHQZ t CHQZ —0.45—0.45—0.45—0.45—0.5ns 3K Clock High to Data Output Low-Z C Clock High to Data Output Low-Zt KHQX1t CHQX1–0.45—–0.45—–0.45—–0.45—–0.5—ns3Setup TimesAddress Input Setup Time t AVKH 0.4—0.4—0.5—0.6—0.7—ns Control Input Setup Time t IVKH 0.4—0.4—0.5—0.6—0.7—ns 2Data Input Setup Timet DVKH0.28—0.3—0.35—0.4—0.5—nsGS8662S08/09/18/36E-333/300/250/200/167Hold TimesAddress Input Hold Time t KHAX 0.4—0.4—0.5—0.6—0.7—ns Control Input Hold Time t KHIX 0.4—0.4—0.5—0.6—0.7—ns Data Input Hold Timet KHDX0.28—0.3—0.35—0.4—0.5—nsNotes:1.All Address inputs must meet the specified setup and hold times for all latching clock edges.2.Control singles are R, W, BW0, BW1, and (NW0, NW1 for x8) and (BW2, BW3 for x36).3.If C, C are tied high, K, K become the references for C, C timing parameters4.To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ. The specs as shown do not imply bus conten-tion because tCHQX1 is a MIN parameter that is worst case at totally different test conditions (0°C, 1.9 V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7 V). It is not possible for two SRAMs on the same board to be at such different voltages and tempera-tures.5.Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge.6.V DD slew rate must be less than 0.1 V DC per 50 ns for DLL lock retention. DLL lock time begins once V DD and input clock are stable.7.Echo clock is very tightly controlled to data valid/data hold. By design, there is a ±0.1 ns variation from echo clock to data. The datasheetparameters reflect tester guard bands and test setup variations.AC Electrical Characteristics (Continued)ParameterSymbol-333-300-250-200-167UnitsN o t e sMin Max Min Max Min Max Min Max Min Max。

MEMORY存储芯片MT29F64G08CBABBWP-12ITB中文规格书

Micron Parallel NOR Flash Embedded Memory (P30-65nm)JS28F256P30B/TFx, RC28F256P30B/TFx, PC28F256P30B/TFx,RD48F4400P0VBQEx, RC48F4400P0VB0Ex,PC48F4400P0VB0Ex, PF48F4000P0ZB/TQExFeatures•High performance–100ns initial access for Easy BGA–110ns initial access for TSOP–25ns 16-word asychronous page read mode–52 MHz (Easy BGA) with zero WAIT states and 17ns clock-to-data output synchronous burstread mode–4-, 8-, 16-, and continuous word options for burst mode–Buffered enhanced factory programming (BEFP) at 2 MB/s (TYP) using a 512-word buffer– 1.8V buffered programming at 1.14 MB/s (TYP) using a 512-word buffer•Architecture–MLC: highest density at lowest cost–Asymmetrically blocked architecture–Four 32KB parameter blocks: top or bottom con-figuration–128KB main blocks–Blank check to verify an erased block•Voltage and power–V CC (core) voltage: 1.7V to 2.0V–V CCQ (I/O) voltage: 1.7V to 3.6V–Standy current: 65µA (TYP) for 256Mb–52 MHz continuous synchronous read current: 21mA (TYP), 24mA (MAX)•Security–One-time programmable register: 64 OTP bits, programmed with unique information from Mi-cron; 2112 OTP bits available for customer pro-gramming–Absolute write protection: V PP = V SS–Power-transition erase/program lockout–Individual zero-latency block locking–Individual block lock-down–Password access•Software–25μs (TYP) program suspend–25μs (TYP) erase suspend–Flash Data Integrator optimized–Basic command set and extended function Inter-face (EFI) command set compatible–Common flash interface•Density and Packaging–56-lead TSOP package (256Mb only)–64-ball Easy BGA package (256Mb, 512Mb)–QUAD+ and SCSP packages (256Mb, 512Mb)–16-bit wide data bus•Quality and reliabilty–JESD47 compliant–Operating temperature: –40°C to +85°C–Minimum 100,000 ERASE cycles per block–65nm process technologyStatus RegisterRead Status RegisterTo read the status register, issue the READ STATUS REGISTER command at any address.Status register information is available at the address that the READ STATUS REGISTER,WORD PROGRAM, or BLOCK ERASE command is issued to. Status register data is auto-matically made available following a word program, block erase, or block lock com-mand sequence. Reads from the device after any of these command sequences will out-put the devices status until another valid command is written (e.g. READ ARRAY com-mand).The status register is read using single asynchronous mode or synchronous burst modereads. Status register data is output on DQ[7:0], while 0x00 is output on DQ[15:8]. Inasynchronous mode, the falling edge of OE# or CE# (whichever occurs first) updatesand latches the status register contents. However, when reading the status register insynchronous burst mode, CE# or ADV# must be toggled to update status data.The device write status bit (SR7) provides the overall status of the device. SR[6:1]present status and error information about the PROGRAM, ERASE, SUSPEND, V PP, andBLOCK LOCK operations.Note: Reading the status register is a nonarray READ operation. When the operation oc-curs in asynchronous page mode, only the first data is valid and all subsequent data areundefined. When the operation occurs in synchronous burst mode, the same data wordrequested will be output on successive clock edges until the burst length requirementsare satisfied.Table 16: Status Register DescriptionNotes: 1.Default value = 0x80.2.Always clear the status register prior to resuming ERASE operations. This eliminates sta-tus register ambiguity when issuing commands during ERASE SUSPEND. If a commandsequence error occurs during an ERASE SUSPEND, the status register contains the com-mand sequence error status (SR[7,5,4] set). When the ERASE operation resumes and fin-ishes, possible errors during the operation cannot be detected via the status register be-cause it contains the previous error status.3.When bits 5:4 indicate a PROGRAM/ERASE operation error, either a CLEAR STATUS REG-ISTER 50h) or a RESET command must be issued with a 15µs delay.Clear Status RegisterThe CLEAR STATUS REGISTER command clears the status register. It functions inde-pendently of V PP. The device sets and clears SR[7,6,2], but it sets bits SR[5:3,1] withoutclearing them. The status register should be cleared before starting a command se-quence to avoid any ambiguity. A device reset also clears the status register.Configuration RegisterRead Configuration RegisterThe read configuration register (RCR) is a 16-bit read/write register used to select busread mode (synchronous or asynchronous) and to configure device synchronous burstread characteristics. To modify RCR settings, use the CONFIGURE READ CONFIGURA-TION REGISTER command. RCR contents can be examined using the READ DEVICEIDENTIFIER command and then reading from offset 0x05. On power-up or exit from re-set, the RCR defaults to asynchronous mode. RCR bits are described in more detail be-low.Note: Reading the configuration register is a nonarray READ operation. When the oper-ation occurs in asynchronous page mode, only the first data is valid, and all subsequentdata are undefined. When the operation occurs in synchronous burst mode, the sameword of data requested will be output on successive clock edges until the burst lengthrequirements are satisfied.Table 17: Read Configuration RegisterRead ModeThe read mode (RM) bit selects synchronous burst mode or asynchronous page modeoperation for the device. When the RM bit is set, asynchronous page mode is selected(default). When RM is cleared, synchronous burst mode is selected.Latency CountThe latency count (LC) bits tell the device how many clock cycles must elapse from therising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until thefirst valid data word is driven to DQ[15:0]. The input clock frequency is used to deter-mine this value. The First Access Latency Count figure shows the data output latency fordifferent LC settings.Figure 13: First Access Latency CountCLK [C]Address [A]ADV# [V]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]DQ[15:0] [D/Q]Note: 1.First Access Latency Count Calculation:•1 / CLK frequency = CLK period (ns)•n x (CLK period) ≥t AVQV (ns) – t CHQV (ns)•Latency Count = n。

显卡数据库Nvidia

名称发表日期代号显示核心识别码NV1/STG2000X1995年9月17日NV10008/0009 Mutara V082不适用NV210 RIVA 1281997年4月8日NV318 RIVA 128 ZX1998年2月23日NV319 RIVA TNT1998年3月23日NV420 Vanta1999年3月22日NV6002CVanta LT1999年3月22日NV6002CRIVA TNT2 Model 641999年7月1日NV6002DRIVA TNT2 Model 64 Pro1999年7月1日NV6002DRIVA TNT21999年3月1日NV528 RIVA TNT2 Pro1999年11月1日NV50028/002A/002B RIVA TNT2 Ultra1999年5月1日NV529 GeForce 2561999年8月31日NV10100 GeForce 256 DDR2000年2月11日NV10DDR101 GeForce 256 Ultra2000年2月11日NV10Ultra103 GeForce2 MX 1002001年3月6日NV11DDR111 GeForce2 MX 2002001年3月6日NV11DDR111 GeForce2 MX2000年6月28日NV11110 GeForce2 MX Pro2001年3月6日NV11DDR111 GeForce2 MX DDR2001年3月6日NV11DDR111 GeForce2 MX 4002001年3月6日NV11110 GeForce2 GTS2000年4月26日NV15150 GeForce2 Pro2000年12月27日NV15150 GeForce2 Ti VX22001年12月14日NV15DDR151 GeForce2 Ti2001年10月1日NV15DDR151 GeForce2 Ultra2000年8月14日NV15BladeRunner152 GeForce32001年2月22日NV20200 GeForce3 Ti 2002001年10月18日NV20201 GeForce3 Ti 5002001年10月18日NV20202 GeForce4 MX 4202002年2月6日NV17SDR172 GeForce4 MX 420 8X2002年2月6日NV18SDR183 GeForce4 MX 440-SE2002年2月6日NV17SE173 GeForce4 MX 440-SE 8X2002年2月6日NV18SE182 GeForce4 MX 4402002年2月6日NV17DDR171 GeForce4 MX 440 8X2002年9月25日NV18DDR181 GeForce4 MX 4602002年2月6日NV17Pro170 GeForce4 MX 40002003年10月30日NV18B0185/0189 GeForce PCX 43002004年2月17日NV1900FFGeForce4 Ti 42002002年3月18日NV25V253 GeForce4 Ti 4200 8X2002年9月25日NV28V281 GeForce4 Ti 44002002年3月18日NV25251 GeForce4 Ti 4800 SE2002年9月25日NV28282 GeForce4 Ti 46002002年3月18日NV25Ultra250 GeForce4 Ti 48002002年9月25日NV28Ultra280 GeForce FX 51002004年8月8日NV34327 GeForce FX 52002003年3月6日NV340322/0329 GeForce FX 5200 LE/SE/XT22004年8月8日NV34323 GeForce FX 5200 Ultra2003年3月6日NV34321 GeForce PCX 53002004年2月17日NV34PCX00FCGeForce FX 55002004年3月4日NV34326 GeForce FX 5600 SE/XT/LE22003年3月6日NV31314GeForce FX 56002003年3月6日NV31312 GeForce FX 5600 Ultra2003年3月6日NV31311 GeForce FX 5600 Ultra (第二版)2004年8月8日NV31311 GeForce FX 5700 VE2004年2月17日NV36344 GeForce FX 5700 LE/SE/XT22004年2月17日NV36343 GeForce FX 57002003年10月23日NV36342 GeForce FX 5700 Ultra2003年10月23日NV36-G2341 GeForce FX 5700 Ultra (第二版)2004年3月4日NV36-G3341 GeForce PCX 57502004年2月17日NV36PCX00FAGeForce FX 58002002年11月18日NV30302 GeForce FX 5800 Ultra2002年11月18日NV30301 GeForce FX 5900 ZT2004年9月1日NV35334 GeForce FX 5900 XT/SE/LE22004年12月10日NV35332 GeForce FX 59002003年5月12日NV35331 GeForce FX 5900 Ultra2003年5月12日NV35330 GeForce PCX 59002004年2月17日NV35PCX00FBGeForce FX 5950 Ultra2003年10月23日NV38333 GeForce 61002005年11月1日C51242 GeForce 6100 + nForce 40022005年11月1日C6103D2GeForce 6100 + nForce 40522005年11月1日C6103D1GeForce 6100 + nForce 42022005年11月1日C6103D5GeForce 6150 LE2006年6月1日C510241/0245 GeForce 6151 LE2006年6月2日C520241/0246 GeForce 61502006年6月1日C51240 GeForce 6150 SE + nForce 43022006年6月1日C6103D0GeForce 62002004年10月12日NV4300F3GeForce 6200 (PCI-E版)2004年10月12日NV43014FGeForce 6200 (PCI-E第二版)2004年12月16日NV44221 GeForce 6200 TurboCache2004年12月16日NV44161 GeForce 6200 SE TurboCache2004年12月16日NV44162 GeForce 6200 LE2004年12月16日NV44163 GeForce 6200 A LE2004年12月16日NV44A222 GeForce 62502005年8月30日NV44169 GeForce 65002005年10月1日NV44160 GeForce 6600 VE2006年4月2日NV43143 GeForce 6600 LE2005年7月15日NV4300F4GeForce 6600 LE (PCI-E版)2005年7月15日NV43142 GeForce 66002004年8月12日NV4300F2GeForce 6600 (PCI-E版)2004年8月12日NV43141 GeForce 6600 GT2004年8月12日NV4300F1GeForce 6600 GT (PCI-E版)2004年8月12日NV43140 GeForce 6610 XL2004年11月2日NV43145 GeForce 6700 XL2005年9月30日NV43147 GeForce 6800 LE2004年10月20日NV4042 GeForce 6800 LE (PCI-E版)2005年3月31日NV4200C2GeForce 6800 LE (PCI-E第二版)2005年3月15日NV48212 GeForce 6800 XT2004年10月20日NV4044 GeForce 6800 XT (PCI-E版)2004年10月20日NV4000F6GeForce 6800 XT (PCI-E第二版)2005年4月10日NV4100C3GeForce 6800 XT (PCI-E第三版)2005年11月15日NV4248 GeForce 6800 XT (PCI-E第四版)2005年3月15日NV48218 GeForce 68002004年4月21日NV40141 GeForce 6800 (PCI-E版)2005年4月10日NV4100C1GeForce 6800 (PCI-E第二版)2005年11月15日NV4200C1GeForce 6800 (PCI-E第三版)2005年3月15日NV48211 GeForce 6800 GTO2005年1月10日NV4500F9GeForce 6800 GS2004年10月20日NV4047 GeForce 6800 GS (PCI-E版)2004年10月20日NV4000F6GeForce 6800 GS (PCI-E第二版)2005年11月6日NV4200C0GeForce 6800 GT2004年4月21日NV4045 GeForce 6800 GT (PCI-E版)2005年1月10日NV4546 GeForce 6800 GT (PCI-E第二版)2005年3月15日NV48215 GeForce 6800 Ultra2004年4月14日NV4040 GeForce 6800 Ultra (PCI-E版)2005年1月10日NV4500F9GeForce 6800 Ultra (PCI-E第二版)2005年3月15日NV4800F9GeForce 7025 + nForce 630a12007年7月1日C68053EGeForce 7050 SE + nForce 630a12007年7月1日C68053AGeForce 7050 PV + nForce 630a12007年7月1日C68053A/053B GeForce 7050 + nForce 610i12007年9月1日C73C7E3GeForce 7050 + nForce 620i12007年9月1日C73C7E5GeForce 7050 + nForce 630i12007年9月1日C73C7E2GeForce 7100 + nForce 630i12007年9月1日C73C7E1GeForce 7100 GS2007年9月1日NV44016AGeForce 7150 + nForce 630i12007年9月1日C737 GeForce 7200 GS2007年8月1日G7201D3GeForce 7300 SE2006年7月1日G7201D3GeForce 7300 LE2006年3月1日G7201D1GeForce 7300 GS2006年1月1日G7201DFGeForce 7300 GT2006年5月1日G73393 GeForce 7300 GT (第二版)2006年10月1日G73395 GeForce 7300 GT (AGP版)2006年5月1日G73200 GeForce 7350 LE2006年7月1日G7201D0GeForce 7500 LE2006年7月1日G7201DDGeForce 7600 GS2006年3月1日G73392 GeForce 7600 GS (AGP版)2006年3月1日G7320 GeForce 7600 GT2006年3月1日G73391 GeForce 7600 GT (PCI-E第二版)2006年10月1日G73391 GeForce 7600 GT (AGP版)2006年3月1日G732 GeForce 7650 GS2006年7月1日G73390 GeForce 7800 GS2006年2月1日G7093 GeForce 7800 GS (AGP版)2006年2月1日G7000F5GeForce 7800 GT2005年8月1日G7092 GeForce 7800 GTX2005年8月1日G7090 GeForce 7800 GTX (第二版)2005年8月1日G7091 GeForce 7900 GS2006年9月1日G71292 GeForce 7900 GS (AGP版)2006年9月1日G712000 GeForce 7900 GT2006年3月1日G71291 GeForce 7900 GTO2006年9月1日G71291 GeForce 7900 GTX2006年3月1日G71290 GeForce 7900 GX22006年3月1日2×G71293 GeForce 7950 GT2006年9月1日G71295 GeForce 7950 GT (AGP版)2006年9月1日G7120000 GeForce 7950 GX22006年6月1日2×G71294 GeForce 8100 + nForce 720a22008年2月1日C77084FGeForce 820022008年2月1日C77849 GeForce 830022008年2月1日C77848 GeForce 8300 GS2007年6月1日G86423 GeForce 84002007年12月1日G98600GeForce 8400 SE2007年6月1日G86420 GeForce 8400 SE (第二版)2007年12月1日G986000 GeForce 8400 GS2007年6月1日G860422/0424 GeForce 8400 GS (第二版)2007年6月1日G84404 GeForce 8400 GS (第三版)2007年12月1日G9860000 GeForce 8400 GS (第四版)2009年12月1日GT21810C3GeForce 8500 GT2007年4月1日G86421 GeForce 8600 GS2007年4月1日G84403 GeForce 8600 GT2007年4月1日G840401/0402 GeForce 8600 GTS2007年4月1日G84400 GeForce 8800 GS2008年1月1日G92606 GeForce 8800 GT2007年12月1日G920602/0611 GeForce 8800 GTS2006年11月1日G80193 GeForce 8800 GTS 5122007年12月1日G92600 GeForce 8800 GTX2006年11月1日G80191 GeForce 8800 Ultra2007年5月1日G80194 GeForce 91002008年10月1日C78847 GeForce 92002008年10月1日C770846/084B GeForce 9200 (第二版)2008年10月1日C79086D/0871 GeForce 93002008年10月1日C790860/0864/0865 GeForce 9300 + nForce 730i2008年10月1日C79086CGeForce 9300 SE2008年6月1日G9860000000 GeForce 9300 GE2008年6月1日G986 GeForce 9300 GS2008年6月1日G9860 GeForce 9300 GS (第二版)2009年12月1日GT21810C0GeForce 94002008年10月1日C790861/0867/086A GeForce 9400 GT2008年8月1日G86042CGeForce 9400 GT (第二版)2008年8月1日G96641 GeForce 9400 GT (第三版)2008年8月1日G96B065BGeForce 9500 GS2008年7月1日G960644/0645 GeForce 9500 GT2008年7月1日G96640 GeForce 9500 GT (第二版)2008年7月1日G96B643 GeForce 9600 S2009年3月1日G96655 GeForce 9600 GS2008年2月1日G94623 GeForce 9600 GSO2008年5月1日G92610 GeForce 9600 GSO (第二版)2008年10月1日G94635 GeForce 9600 GSO 5122008年10月1日G94625 GeForce 9600 GT2008年2月1日G940622/062E GeForce 9600 GT (第二版)2008年8月1日G94B0622/062D/0637 GeForce 9650 S2009年3月1日G96B656 GeForce 9700 S2009年3月1日G94B630 GeForce 9800 S2009年3月1日G94B062FGeForce 9800 GT2008年7月1日G920601/0605 GeForce 9800 GT (第二版)2008年8月1日G92B0605/0614 GeForce 9800 GTX2008年4月1日G92612 GeForce 9800 GTX+2008年7月1日G92B0612/0613 GeForce 9800 GX22008年3月1日2×G92604 GeForce G 1002009年3月10日G986000000 GeForce GT 1202009年3月10日G96B646 GeForce GT 1302009年3月10日G94B626 GeForce GT 1402009年3月10日G94B627 GeForce GTS 1502009年3月10日G92B615 GeForce 2052009年11月26日GT2180A62GeForce 2102009年7月2日GT2180A23/0A65GeForce G 2102009年7月2日GT218065F/0A60 GeForce GT 2202009年7月2日GT215;GT2160A20/0CA5/0CAC GeForce GT 2302009年12月7日G92B603 GeForce GT 2402009年11月17日GT2150CA3GeForce GTS 2402009年7月27日G92B607 GeForce GTS 2502009年3月3日G92B615 GeForce GTX 2602008年6月16日GT20005EAGeForce GTX 260 (第二版)2008年9月16日GT200;GT200B500 GeForce GTX 2752009年4月9日GT200B5000000 GeForce GTX 2802008年6月17日GT20050 GeForce GTX 2852009年1月16日GT200B5000 GeForce GTX 2952009年1月8日2×GT200B5 GeForce GTX 295 (第二版)2009年5月16日2×GT200B05EBGeForce 3102009年11月27日GT2180A63/0A66 GeForce 3152010年2月1日GT2160A67GeForce GT 3202010年2月1日GT2150CA2GeForce GT 3302010年2月1日G92B410 GeForce GT 330 (第二版)2010年2月1日GT2150CA0/0CA7 GeForce GT 3402010年2月1日GT2150CA4GeForce 4052010年8月31日GT216;GT218;GF1190A26/0A27/10C5 GeForce GT 4202010年9月5日GF1080DE2GeForce GT 4302010年9月13日GF1080DE1GeForce GT 4402010年10月17日GF1060DC0GeForce GT 440 (第二版)2011年2月1日GF1080DE0GeForce GTS 4502010年9月13日GF1060DC4/0DC5/0DC6 GeForce GTS 450 (第二版)2011年3月15日GF1161245 GeForce GTX 460 SE2010年11月15日GF1040 GeForce GTX 4602010年7月12日GF1040E22/0E24 GeForce GTX 460 v22011年7月26日GF1141205 GeForce GTX 4652010年5月31日GF10006C4GeForce GTX 4702010年3月26日GF10006CDGeForce GTX 4802010年3月26日GF10006C0GeForce 5102011年7月28日GF1191042 GeForce GT 5202011年4月13日GF1191040 GeForce GT 5302011年5月14日GF1080DE5GeForce GT 545 DDR32011年5月14日GF1161243 GeForce GT 545 GDDR52011年5月14日GF1161241 GeForce GTX 550 Ti2011年3月15日GF1161244 GeForce GTX 5552012年1月18日GF1141206 GeForce GTX 560 SE2012年3月13日GF1141208 GeForce GTX 5602011年5月17日GF1141201 GeForce GTX 560 (第二版)2011年5月30日GF1101084 GeForce GTX 560 Ti2011年1月25日GF1141200 GeForce GTX 560 Ti (第二版)2011年5月30日GF1101082 GeForce GTX 560 Ti (第三版)2011年11月29日GF1101087 GeForce GTX 5702010年12月7日GF1101081/1086 GeForce GTX 5802010年11月8日GF1101080/108B GeForce GTX 5902011年3月24日2×GF1101088 GeForce 6052012年4月3日GF1191048 GeForce GT 6102012年5月15日GF119104AGeForce GT 6202012年4月3日GF1191049 GeForce GT 620 (第二版)2012年5月15日GF1080F01GeForce GT 6302012年4月14日GK1070FC2GeForce GT 630 (第二版)2012年5月15日GF1080F00GeForce GT 6402012年4月24日GF116124BGeForce GT 640 (第二版)2012年4月24日GK1070FC0GeForce GT 640 (第三版)2012年4月24日GK1070FC1GeForce GT 6452012年4月24日GF1141207 GeForce GTX 6502012年9月13日GK107GeForce GTX 650 Ti2012年10月9日GK106GeForce GTX 6602012年8月22日GK104GeForce GTX 660 (第二版)2012年9月13日GK106GeForce GTX 660 Ti2012年8月16日GK104GeForce GTX 6702012年5月10日GK1041189 GeForce GTX 6802012年3月22日GK1041180 GeForce GTX 6902012年4月29日2×GK1041188 GeForce GTX Titan2013年2月19日GK110GeForce GTX 760GK104GeForce GTX 770GK104GeForce GTX 780GK110GeForce GTX 780Ti GK110制程（nm）百万晶体管晶片面积(毫米)汇流排最大记忆体容量（MB）500?PCI41309 ???350AGP, PCI4 350AGP 2X, PCI8 350AGP 2X, PCI41502 250AGP 4X, PCI16 250AGP 4X8 220AGP 4X, PCI16/32220AGP 4X, PCI16/32250AGP 4X, PCI16/32250AGP 4X, PCI16/32250AGP 4X, PCI16/32220AGP 4X32/64220AGP 4X32/64220AGP 4X32/64180AGP 4X, PCI16/32180AGP 4X, PCI32/64180AGP 4X, PCI32/64180AGP 4X, PCI32/64180AGP 4X, PCI32/64180AGP 4X, PCI32/64180AGP 4X32/64180AGP 4X32/64150AGP 4X64 150AGP 4X64 180AGP 4X64 180AGP 4X64/128150AGP 4X64/128150AGP 4X64/128150AGP 4X64 150AGP 8X64 150AGP 4X, PCI64 150AGP 8X, PCI64 150AGP 4X, PCI64/128150AGP 8X64/128150AGP 4X64 150AGP 8X, PCI64/128150PCI-E128 150AGP 4X64/128150AGP 8X128 150AGP 4X128 150AGP 8X128 150AGP 4X128 150AGP 8X128 150AGP 8X, PCI64, 128150AGP 8X, PCI64, 128, 256150AGP 8X, PCI64, 128150AGP 8X128, 256150PCI-E ×16128 150AGP 8X, PCI64, 128, 256130AGP 8X64, 128, 256130AGP 8X128 130AGP 8X128, 256130AGP 8X128, 256130AGP 8X128, 256130AGP 8X, PCI128, 256130AGP 8X128, 256130AGP 8X128, 256130AGP 8X128, 256130PCI-E ×16128, 256130AGP 8X128 130AGP 8X128 130AGP 8X128 130AGP 8X128 130AGP 8X128, 256130AGP 8X128, 256130PCI-E ×16128 130AGP 8X256 90Hyper Transport最大共享至25690Hyper Transport最大共享至25690Hyper Transport最大共享至25690Hyper Transport最大共享至25690Hyper Transport最大共享至25691Hyper Transport最大共享至25790Hyper Transport最大共享至25690Hyper Transport最大共享至256110AGP 8X128, 256, 512110PCI-E ×16128, 256110PCI-E ×16128, 256110PCI-E ×1664 110PCI-E ×1664 110PCI-E ×16128, 256110AGP 8X128, 256, 512110PCI-E ×16256 110PCI-E ×16128, 256110PCI-E ×16,128 110AGP 8X128, 256110PCI-E ×16128, 256110AGP 8X128, 256, 512110PCI-E ×16256, 512110AGP 8X128 110PCI-E ×16128, 256110PCI-E ×16128, 256110PCI-E ×16128 130AGP 8X256 110PCI-E ×16256 110PCI-E ×16512 130AGP 8X256 130PCI-E ×16256 130PCI-E ×16256 110PCI-E ×16256 110PCI-E ×16512 130AGP 8X128, 256130PCI-E ×16128, 256110PCI-E ×16128, 256110PCI-E ×16512 130PCI-E ×16256 130AGP 8X256 130PCI-E ×16256 110PCI-E ×16256 130AGP 8X256 130PCI-E ×16256 110PCI-E ×16512 130AGP 8X256 130PCI-E ×16256 110PCI-E ×16512 90Hyper Transport最大共享至25690Hyper Transport最大共享至25690Hyper Transport最大共享至25680PCI-E ×16最大共享至25680PCI-E ×16最大共享至25680PCI-E ×16最大共享至25680PCI-E ×16最大共享至256110PCI-E ×16128 80PCI-E ×16最大共享至25690PCI-E ×1664, 128, 25690PCI-E ×16128, 25690PCI-E ×16128, 25690PCI-E ×16128, 25690PCI-E ×16256 90PCI-E ×16512 90AGP 8X256, 51290PCI-E ×16128, 25690PCI-E ×16256 90PCI-E ×16256, 51290AGP 8X256, 51290PCI-E ×16256, 51280PCI-E ×16256, 51290AGP 8X256, 51290PCI-E ×16256, 512110PCI-E ×16256 110AGP 8X256 110PCI-E ×16256 110PCI-E ×16512 110PCI-E ×16256 90PCI-E ×16256 90AGP 8X256 90PCI-E ×16256, 51290PCI-E ×16512 90PCI-E ×16512 90PCI-E ×162×51290PCI-E ×16256, 51290AGP 8X256, 51290PCI-E ×162×51280??PCI-E 2.0 ×16最大共享至51280??PCI-E 2.0 ×16最大共享至51280??PCI-E 2.0 ×16最大共享至512 8021086PCI-E ×16512 6521086PCI-E 2.0 ×16128, 25680210127PCI-E ×16128, 2566521086PCI-E 2.0 ×16128, 256, 51280210127PCI-E ×16, PCI128, 25680210127PCI-E ×16128, 25665;5521086PCI-E 2.0 ×16, PCI128, 256, 512, 1024 4026057PCI-E 2.0 ×16102480210127PCI-E ×16256, 512, 102480289169PCI-E ×16256, 51280289169PCI-E ×16256, 512, 102480289169PCI-E ×16256, 51265754324PCI-E 2.0 ×16384, 76865754324PCI-E 2.0 ×16256, 512, 102490681484PCI-E ×16320, 64065754324PCI-E 2.0 ×1651290681484PCI-E ×1676890681484PCI-E ×1676865??PCI-E 2.0 ×16最大共享至51280??PCI-E 2.0 ×16最大共享至51265??PCI-E 2.0 ×16最大共享至51265282162PCI-E 2.0 ×16最大共享至51265282162PCI-E 2.0 ×16最大共享至5126521086PCI-E 2.0 ×162566521086PCI-E 2.0 ×16128, 2566521086PCI-E 2.0 ×16128, 256, 512, 10244026057PCI-E 2.0 ×16102465282162PCI-E 2.0 ×16最大共享至51265314144PCI-E 1.0 ×16, PCI128, 25665314144PCI-E 2.0 ×16, PCI256, 512, 102455314144PCI-E 2.0 ×16, PCI256, 512, 102465314144PCI-E 2.0 ×1651265314144PCI-E 2.0 ×16256, 512, 102455314144PCI-E 2.0 ×16256, 512, 102465314144PCI-E 2.0 ×1651265505240PCI-E 2.0 ×1676865754324PCI-E 2.0 ×16384, 768, 153655505196PCI-E 2.0 ×1651265505196PCI-E 2.0 ×1651265505240PCI-E 2.0 ×16512, 102455505196PCI-E 2.0 ×16512, 102455314144PCI-E 2.0 ×16256, 512, 102455505196PCI-E 2.0 ×1651255505196PCI-E 2.0 ×16102465754324PCI-E 2.0 ×16512, 102455754260PCI-E 2.0 ×16512, 102465754324PCI-E 2.0 ×1651255754260PCI-E 2.0 ×16512, 1024652×7542×324PCI-E 2.0 ×162×5126521086PCI-E 2.0 ×16128;256;51255314121PCI-E 2.0 ×1651255505196PCI-E 2.0 ×16768;153655505196PCI-E 2.0 ×16256;512;102455754230PCI-E 2.0 ×1610244026057PCI-E 2.0 ×165124026057PCI-E 2.0 ×16256;512;10244026057PCI-E 2.0 ×1651240727;486139;100PCI-E 2.0 ×16256;512;102465754260PCI-E 2.0 ×16512;153640727139PCI-E 2.0 ×161024;51255754260PCI-E 2.0 ×16102455754260PCI-E 2.0 ×16512;1024651400576PCI-E 2.0 ×16896;179265;551400576;487PCI-E 2.0 ×16896;1792551400470PCI-E 2.0 ×16896;1792651400576PCI-E 2.0 ×161024551400470PCI-E 2.0 ×161024;2048552×14002×470PCI-E 2.0 ×162×896552×14002×470PCI-E 2.0 ×162×8964026057PCI-E 2.0 ×1651240486100PCI-E 2.0 ×1651240727144PCI-E 2.0 ×16102455754260PCI-E 2.0 ×16256/512/102440727133PCI-E 2.0 ×16512/102440727133PCI-E 2.0 ×16512/102440486;260;585100;57;116PCI-E 2.0 ×16512/102440585116PCI-E 2.0 ×161024/204840585116PCI-E 2.0 ×161024/2048401170238PCI-E 2.0 ×161536/307240585116PCI-E 2.0 ×16512/1024/2048401170238PCI-E 2.0 ×161024/1536401170238PCI-E 2.0 ×161024401950367PCI-E 2.0 ×161024401950367PCI-E 2.0 ×16768/1024/2048401950332PCI-E 2.0 ×161024/2048403200529PCI-E 2.0 ×161024403200529PCI-E 2.0 ×161280403200529PCI-E 2.0 ×16153640116PCI-E 2.0 ×161024/204840116PCI-E 2.0 ×161024/204840116PCI-E 2.0 ×161024/204840238PCI-E 2.0 ×161536/307240238PCI-E 2.0 ×161024/204840238PCI-E 2.0 ×161024/204840332PCI-E 2.0 ×16102440332PCI-E 2.0 ×16102440332PCI-E 2.0 ×161024/204840520PCI-E 2.0 ×161280/256040332PCI-E 2.0 ×161024/204840520PCI-E 2.0 ×161280/256040520PCI-E 2.0 ×161280/256040520PCI-E 2.0 ×161280/256040520PCI-E 2.0 ×161536/3072402×520PCI-E 2.0 ×162×153640未知79PCI-E 2.0 ×16512/102440未知79PCI-E 2.0 ×16102440未知79PCI-E 2.0 ×16512/102440585116PCI-E 2.0 ×16102440585116PCI-E 2.0 ×161024 401170238PCI-E 2.0 ×161536/3072281300118PCI-E 3.0 ×161024/2048281300118PCI-E 3.0 ×162048 401950332PCI-E 2.0 ×161024 281300118PCIe 3.0 x161024 282540221PCIe 3.0 x161024/2048283540294PCIe 3.0 x161536/3072282540221PCIe 3.0 x162048 283540294PCIe 3.0 x162048 283540294PCI-E 3.0 ×162048 283540294PCI-E 3.0 ×162048/4096282×35402×294PCI-E 3.0 ×162×2048287080561.4PCIe 3.0 x166144 28PCIe 3.0 x162048 28PCIe 3.0 x162048 28PCIe 3.0 x163072 28PCIe 3.0 x163072细分曲面单元时脉核心（MHz）基准加速（MHz）最高加速（MHz）流处理器（MHz）48?1001009010080100125125143150120120150143175175175175200200200225250250200175240250250250/270250/270270275300250/275275250250275275300300200250250325250300250425475475425400500325390400450425475425425425425425426475425300300350350250350 350,300300350300300300300350500500400525325325325325325325350325325350425350350350400400400425425425500500500600350630450450450550350, 400400, 500350, 400, 500450550400, 560400, 560560650, 560560450375375400550430450450450650650500550550500500120050012005001500450918;1290450918450900460910 520;5671230;14005671400450900540118054011806751450550137560015005131188650162557513506121500450120050012004501200450120045012005401300540130056714005891230580140045011805501400550135050014005501350650156550014005001250600150060015005501500 600;6501500;1625600;6251500;162565015655501500600150060015005501375675168873818366001500 500;5401300;1400500;5501250;1350500125065016257381836550;5891350;1402506;615;6251012;1335;1360500;7381250;1836550134067516207381836 518;5761080;1242576124263314046021296648147657612425761242589140247511005401302 500;550125055013405501340 1475;5891100;1402170014002700140035941189281016204783/790/8251566/1580/1804/180047833608665013007675/6501350/1300777815561160712151460712151570014011523104618101620270014003720144018701740490018007776155377761553780016007552110488221645117321464147321464157321464167721544 2×166071215 1523不适用不适用10461810不适用不适用16201810不适用不适用16202700不适用不适用14002810不适用不适用16203720不适用不适用14402950未知未知9502797/900未知未知797/9006776不适用不适用155221058不适用不适用10583928不适用不适用9256823888未知82359801033103398079159809157915980108491581006105811101006 2×891510191058915 14837876993837980103310461085863900875928核心结构填充率（MT/s）峰值填充率显示记忆体（MHz）GB像素/秒GB纹理/秒48?12???1000:1:1:11001000:1:1:11001100:2:2:21801100:2:2:22001000:2:2:21601250:2:2:22501430:2:2:22501500:2:2:22501660:2:2:22861830:2:2:23001660:4:4:44803000:4:4:44804000:4:4:46001660:2:4:25721660:2:4:27001660:2:4:27001830:2:4:27003330:2:4:27001660:2:4:28003330:4:8:416004000:4:8:416004000:4:8:418004000:4:8:420004600:4:8:420004601:4:8:416004001:4:8:414005001:4:8:419201660:2:4:210001660:2:4:21000166/3330:2:4:21100166/3330:2:4:211004000:2:4:21100500/5130:2:4:211005500:2:4:21200266/333/4000:2:4:211003330:2:4:21100444/5002:4:8:42000500/5132:4:8:420005502:4:8:422005502:4:8:422006502:4:8:424006502:4:8:424003332:4:2:4114002:4:2:4113332:4:2:4116502:4:2:4 1.3 1.34002:4:2:4115502:4:2:4 1.3 1.37002:4:2:4 1.4 1.48002:4:2:4 1.6 1.65003:4:2:4 1.2 1.24003:4:2:4115503:4:2:4 1.7 1.79003:4:2:4 1.9 1.99503:4:2:4 1.9 1.95003:4:2:4 1.7 1.78003:8:3:8 3.2 3.210003:8:3:8447003:8:4:8 3.2 3.27003:8:4:8 3.2 3.28503:8:4:8 3.2 3.28503:8:4:8 3.6 3.65503:8:4:8 3.4 3.49503:8:4:8 3.8 3.8系统共享显示记忆体1:2:2:1850425106.3系统共享显示记忆体1:2:2:1850425106.3系统共享显示记忆体1:2:2:1850425106.3系统共享显示记忆体1:2:2:1850425106.3系统共享显示记忆体1:2:2:1850425106.3系统共享显示记忆体1:2:2:2850425106.3系统共享显示记忆体1:2:2:1950475118.8系统共享显示记忆体1:2:2:1850425106.35503:4:4:212006002255503:4:4:212006002257003:4:4:212006002257003:4:4:21400700262.55003:4:4:21400700262.55322:2:2:1700350131.255503:4:4:21400;1200700;600262.5;2255503:4:4:414001400262.55503:4:4:414001400262.54003:4:4:4120012002255003:4:4:4120012002255003:4:4:4120012002255003:8:8:4240012002258003:8:8:428001400262.59003:8:8:44000200037510003:8:8:4400020003758003:8:8:44000200037511003:8:8:4420021003757004:8:8:8260026003257004:8:8:8260026003257004:8:8:8260026003257004:8:8:8260026003257004:8:8:8260026003257004:8:8:8260026003259004:8:8:8260026003257004:8:8:8260026003256005:12:12:1239003900406.37005:12:12:1239003900406.39005:12:12:1242004200437.510005:12:12:1242004200437.510005:12:12:1242004200437.510005:12:12:851003400531.2510006:16:16:165600560052510006:16:16:165600560052510006:16:16:165600560052511006:16:16:166400640060011006:16:16:166400640060011006:16:16:1664006400600系统共享显示记忆体1:2:2:2850850106.25系统共享显示记忆体1:2:2:2850850106.25系统共享显示记忆体1:2:2:2850850106.25最大至6671:2:2:210001000125最大至6671:2:2:210001000125最大至6671:2:2:210001000125最大至8001:2:2:2120012001506673:4:4:21400700262.5最大至8001:2:2:212601260157.5 667, 8002:2:2:29009002256672:2:2:29009002256673:4:4:21800900337.58103:4:4:222001100412.5 533, 6674:8:8:828002800350 800, 14004:8:8:828002800350 533, 667, 800, 14004:8:8:8280028003508003:4:4:211001100412.58003:4:4:211001100412.5 800, 5335:12:12:848003200500 800, 5335:12:12:848003200500 1400, 8005:12:12:867204480700 1600, 8005:12:12:87800, 67205200, 4480812.5, 700 1400, 8005:12:12:8672044807008005:12:12:84800320050012006:16:16:860003000562.512006:16:16:860003000562.510007:20:20:168000640070017008:24:24:16132008800110012008:24:24:1610320688094013207:20:20:1690007200822.513207:20:20:1690007200822.513208:24:24:1610800720094013208:24:24:161560010400130016008:24:24:161560010400140012002×8:24:24:162400016000200014008:24:24:16132008800110014008:24:24:16132008800110012002×8:24:24:1624000160002000 800(系统共享显示记忆体)16:04:0422 800(系统共享显示记忆体)16:04:0422 800(系统共享显示记忆体)16:04:04228008:08:04 1.8 3.610008:08:04 2.2 4.3800;12008:08:04 1.8 3.68008:08:04 1.8 3.680016:08:04 1.8 3.6120016:08:04 1.8 3.6 800;10008:08:04 2.268 4.5367008:08:04 2.356 2.35680016:08:08 3.6 3.680032:16:08 4.328.64 800;140032:16:08 4.328.64 200032:16:08 5.410.8160096:48:12 6.626.4 1400;1800112:56:169.633.6 158496:48:2010.2624.6241940128:64:1610.441.61800128:64:2413.836.82160128:64:2414.68839.168 800(系统共享显示记忆体)16:08:04 1.8 3.6 800(系统共享显示记忆体)16:04:0422 800(系统共享显示记忆体)16:08:04 1.8 3.6 800(系统共享显示记忆体)16:08:04 1.8 3.6 800(系统共享显示记忆体)16:08:04 1.8 3.6 800(系统共享显示记忆体)8:08:04 2.268 4.536 10008:08:04 2.16 4.3210008:08:04 2.268 4.5367008:08:04 2.268 4.536 1100(系统共享显示记忆体)16:08:04 2.32 4.64 100016:08:04 2.2 4.4 800;160016:08:04 2.2 4.4 800;160018:08:04 2.2 4.4 12508:16:084816008:16:08 4.48.820008:16:08 4.48.812508:16:0848102016:32:1661217000:48:12 6.626.4 700;18000:24:1610.415.6 18000:24:1610.415.6 1400;158416:32:1610.420.8 1400;1600;180016:32:169.6;1019.2;2020008:16:08 4.48.8180016:32:1610.415.6160016:32:169.619.2180016:56:169.633.6 1400;1600;180016:56:168.830.8 2200128:64:1610.843.22200128:64:1611.80847.23220002×128:64:162×9.62×38.4 800;102016:08:04 4.38 100832:16:08 4.48.8 1000;102048:24:12612 1400;180064:32:1610.420.8 2000128:64:1611.80847.232 1008;15808:04:04 2.356 2.356 700;800;160016:08:04 2.356 4.712800;1008;1400;158016:08:04 2.356 4.712 900;1000;15800:16:08510 1020;22000:48:12624 1800;2000;34000:32:08 4.417.6 220016:56:1610.837.8 2200;2000128:64:1611.80847.232 2000;2016192:64:2816.12836.864 1998216:72:2816.128;17.541.472;402268240:80:2817.72450.62214240:80:3219.26448.162484240:80:3220.73651.8419982×240:80:282×16.1282×46.0819982×240:80:282×16.1282×46.08 1000;158016:08:04 2.356 4.712 158048:16:08 3.87.6158072:24:08 4.3212.96 1020;160096:48:16 4.431.1 100096:32:08 4.425.3340096:32:08 4.417.6 1600;158016:08:042;2.3 4.2;4.7180048:08:08 2.8 5.6180096:16:04 2.811.21800144:24:2414.2614.26 1800/310096:16:04 3.2412.96 3608/3132/3300192:32:1612.5325.06 1566192:32:1612.5325.063400288:48:3220.831.2 3600/3400336:56:24/336:56:3216.2/21.637.8/28.354008336:56:242349.83206352:44:3219.4226.713348448:56:4024.28343696480:60:4833.642179648:08:04 2.02 4.2179648:08:04 3.24 6.5179696:16:08 2.811.21800144:24:2414.2614.263996192:32:1613.3326.064100192:32:2421.628.83828288:48:2424.137.23828288:48:2424.137.24000336:56:3226.644.84004384:48:3225.644.84004384:64:3226.2452.613800352:44:4029.2832.313800448:56:4029.2840.993800480:60:4029.2843.924008512:64:4837.05649.40834142×512:64:482×29.142×38.85179848:08:04 2.1 4.2180048:08:04 3.24 6.5179848:08:04 3.24 6.5180096:16:04 2.811.21782192:16:16714。

海哥尔德电子产品简介说明书

APRIL 2013Quick-Refere nce GuideLAPTOP, DESKTO P AND VIDEO STORAGE DRIVESSeagate Partner Program MembersVisit the Sales Tools section to access the latestproduct roadmap, end-of-life schedule and product information. DistributorsEMEA SPP Support00-800-6890-8282US Sales Support1-800-SEAGATE or 1-405-324-4700Visit for more information or call 1-800-SEAGATE (1-800-732-4283) © 2013 Seagate Technology LLC. All rights reserved. Printed in USA. Seagate, Seagate Technology and the Wave logo are registered trademarks of Seagate Technology LLC in the United States and/or other countries. Barracuda, G-Force Protection, Momentus, Pipeline HD, SmartAlign and SV35 Series are either trademarks or registered trademarks of Seagate Technology LLC or one of its affiliated companies in the United States and/or other countries. The FIPS logo is a certification mark of NIST, which does not imply product endorsement by NIST, the U.S., or Canadian governments. All other trademarks or registered trademarks are the property of their respective owners. When referring to drive capacity, one gigabyte, or GB, equals one billion bytes and one terabyte, or TB, equals one trillion bytes. Your computer’s operating system may use a different standard of measurement and report a lower capacity. In addition, some of the listed capacity is used for formatting and other functions, and thus will not be available for data storage. Actual data rates may vary depending on operating environment and other factors. The export or re-export of hardware or software containing encryption may be regulated by the US Department of Commerce, Bureau of Industry and Security (for more information go to ). Seagate reserves the right to change, without notice, product offerings or specifications. QR502.15-1304GB, April 2013APRIL 2013Quick-Reference GuideLAPTOP, DESKTOP AND VIDEO STORAGE DRIVESNew Seagate Model Number KeyDesktop, laptop and video storageST 500 DX 001BRANdCAPACiTySegMeNTATTRiBuTeS2 letters ST= Seagate MX= Maxtor2 to 4 digits 80 = 80GB 500 = 500GB 1500 = 1,500GB Capacities>9,999GB: 10 = 10TB 15 = 15TB2 lettersDX = Desktop Premium DM = Mainstream DL = Entry LevelLX = Laptop Premium LM = Laptop Mainstream LT = Laptop Thin VX = Surveillance VM = DVR VT = DVR Thin3 digits, non-intelligent Varies for:Z-height Form Factor RPM Cache Interface SED, FIPS Drop Sensor Interface SpeedView a brief training presentation on how our model numbering format has changed at /seagate/ModelNumber 1 One gigabyte, or GB, equals one billion bytes; and one terabyte, or TB, equals one trillion bytes when referring to drive capacity.2See FIPS 140-2 Level 2 Certificate at /groups/STM/cmvp/documents/140-1/1401vend.htm.37mm z-height expanded to 9.5mm enables compatibility with standard laptop chassis.4Advanced Format 4K sector drive with SmartAlign ™ technology resolves misalignment conditions.5Seagate makes this drive in both 4K and 512-byte sectors. SmartAlign technology is included on 4K sector drives. Both drives are functionally and physically equivalent.6Formerly Barracuda ®drive。

VCNL4010-GS08;中文规格书,Datasheet资料

Fully Integrated Proximity and Ambient Light Sensor with Infrared Emitter, I 2C Interface, and Interrupt FunctionDESCRIPTIONThe VCNL4010 is a fully integrated proximity and ambient light sensor. Fully integrated means that the infrared emitter is included in the package. It has 16 bit resolution. It includes a signal processing IC and features standard I 2C communication interface. It features an interrupt function.APPLICATIONS•Proximity sensor for mobile devices (e.g. smart phones,touch phones, PDA, GPS) for touch screen locking, power saving, etc.•Integrated ambient light function for display/keypad contrast control and dimming of mobile devices•Proximity/optical switch for consumer, computing and industrial devices and displays•Dimming control for consumer, computing and industrial displaysFEATURES•Package type: surface mount•Dimensions (L x W x H in mm): 3.95 x 3.95 x 0.75•Integrated infrared emitter, ambient light sensor,proximity sensor, and signal conditioning IC •Interrupt function•Supply voltage range V DD : 2.5 V to 3.6 V •Supply voltage range IR anode: 2.5 V to 5 V •Communication via I 2C interface •I 2C Bus H-level range: 1.7 V to 5 V •Floor life: 168 h, MSL 3, acc. J-STD-020•Low stand by current consumption: 1.5 μA•ompliant to RoHS Directive 2011/65/EU and in accordance to WEEE 2002/96/ECNote**Please see document “Vishay Material Category Policy”:/doc?99902PROXIMITY FUNCTION•Built-in infrared emitter and photo-pin-diode for proximity function•16 bit effective resolution for proximity detection range ensures excellent cross talk immunity•Programmable LED drive current from 10 mA to 200 mA in 10 mA steps•Excellent ambient light suppression by modulating the infrared signal•Proximity distance up to 200 mmAMBIENT LIGHT FUNCTION•Built-in ambient light photo-pin-diode with close-to-human-eye sensitivity•16 bit dynamic range from 0.25 lx to 16 klx •100 Hz and 120 Hz flicker noise rejectionNote(1)Adjustable through I 2C interfacePRODUCT SUMMARYPART NUMBER OPERATING RANGE (mm)OPERATING VOLTAGE RANGE (V)I 2C BUS VOLTAGE RANGE (V)LED PULSE CURRENT (1)(mA)AMBIENT LIGHT RANGE (lx)AMBIENT LIGHT RESOLUTION(lx)OUTPUT CODE VCNL40101 to 2002.5 to3.61.7 to 510 to 2000.25 to 16 3830.2516 bit, I 2CNotes(1)MOQ: minimum order quantity(2)VCNL4000 Demokit provides USB dongle, basic software including Vishay licence. The VCNL4010 sensor board could be ordered free of charge by contacting sensorstechsupport@ . Software updates for VC NL4010 can be downloaded from our web site:/???/ORDERING INFORMATIONORDERING CODE PACKAGING VOLUME (1)REMARKSVCNL4010-GS08Tape and reelMOQ: 1800 pcs 3.95 mm x 3.95 mm x 0.75 mmVCNL4010-GS18MOQ: 7000 pcsVCNL4000Demokit (2)-MOQ: 1 pc-ABSOLUTE MAXIMUM RATINGS (T amb = 25 °C, unless otherwise specified)PARAMETER TEST CONDITIONSYMBOL MIN.MAX.UNIT Supply voltageV DD - 0.3 5.5V Operation temperature range T amb - 25+ 85°C Storage temperature range T stg - 40+ 85°C Total power dissipation T amb ≤ 25 °C P tot 50mW Junction temperatureT j100°CBASIC CHARACTERISTICS (T amb = 25 °C, unless otherwise specified)PARAMETER TEST CONDITIONSYMBOLMIN.TYP.MAX.UNIT Supply voltage V DD 2.5 3.6V Supply voltage IR anode 2.55V I 2C Bus H-level range 1.75V INT H-level range 1.75V INT low voltage 3 mA sink current 0.4V Current consumptionStandby current,no IRED-operation 1.52μA Current consumptionproximity mode incl. IRED (averaged)2 measurements per second,IRED current 20 mA5μA 250 measurements per second,IRED current 20 mA 520μA 2 measurements per second,IRED current 200 mA 35μA 250 measurements per second,IRED current 200 mA 4.0mA Current consumption ambient light mode2 measurements per secondaveraging = 12.5μA 8 measurements per secondaveraging = 110μA 2 measurements per secondaveraging = 64160μA 8 measurements per secondaveraging = 64640μA Ambient light resolution Digital resolution (LSB count )0.25lx Ambient light output E V = 100 lx averaging = 64400counts I 2C clock rate rangef SCL3400kHzCIRCUIT BLOCK DIAGRAMNote•nc must not be electrically connectedPads 8 to 11 are only considered as solder padsTEST CIRCUIT BASIC CHARACTERISTICS (T amb = 25 °C, unless otherwise specified)Fig. 1 - Idle Current vs. Ambient Temperature Fig. 2 - Idle Current vs. V DDFig. 3 - Proximity Value vs. Distance Fig. 4 - Forward Current vs. TemperatureFig. 5 - Relative Radiant Intensity vs. WavelengthFig. 6 - Relative Radiant Intensity vs. Angular Displacement Fig. 7 - Relative Spectral Sensitivity vs. Wavelength(Proximity Sensor) Fig. 8 - Relative Radiant Sensitivity vs. Angular Displacement(Proximity Sensor)Fig. 9 - Ambient Light Value vs. Illuminance Fig. 10 - Relative Spectral Sensitivity vs. Wavelength(Ambient Light Sensor)Fig. 11 - Relative Radiant Sensitivity vs. Angular Displacement(Ambient Light Sensor)APPLICATION INFORMATIONVCNL4010 is a cost effective solution of proximity and ambient light sensor with I2C bus interface. The standard serial digital interface is easy to access “Proximity Signal” and “Light Intensity” without complex calculation and programming by external controller. Beside the digital output also a flexible programmable interrupt pin is available.1. Application CircuitFig. 12 - Application Circuit(x) = Pin NumberNote•The interrupt pin is an open drain output. The needed pull-up resistor may be connected to the same supply voltage as the application controller and the pull-up resistors at SDA/SCL. Proposed value R2 should be >1 kΩ , e.g. 10 kΩ to 100 kΩ.Proposed value for R3 and R4, e.g. 2.2 kΩ to 4.7 kΩ, depend also on the I2C bus speed.For detailed description about set-up and use of the interrupt as well as more application related information see AN: “Designing VCNL4010 into an Application”.2. I 2C InterfaceThe VCNL4010 contains seventeen 8 bit registers for operation control, parameter setup and result buffering. All registers are accessible via I 2C communication. Figure 13 shows the basic I 2C communication with VCNL4010.The built in I 2C interface is compatible with all I 2C modes (standard, fast and high speed).I 2C H-level range = 1.7 V to 5 V.Please refer to the I 2C specification from NXP for details.Device AddressThe VC NL4010 has a fix slave address for the host programming and accessing selection. The predefined 7 bit I 2C bus address is set to 0010 011 = 13h. The least significant bit (LSB) defines read or write mode. Accordingly the bus address is set to 0010 011x = 26h for write, 27h for read.Register AddressesVC NL4010 has seventeen user accessible 8 bit registers.The register addresses are 80h (register #0) to 90h (register #16).REGISTER FUNCTIONSRegister #0 Command RegisterRegister address = 80hThe register #0 is for starting ambient light or proximity measurements. This register contains 2 flag bits for data ready indication.Note•With setting bit 3 and bit 4 at the same write command, a simultaneously measurement of ambient light and proximity is done. Beside als_en and/or prox_en first selftimed_en needs to be set. On-demand measurement modes are disabled if selftimed_en bit is set. For the selftimed_en mode changes in reading rates (reg #4 and reg #2) can be made only when b0 (selftimed_en bit) = 0. For the als_od mode changes to the reg #4 can be made only when b4 (als_od bit) = 0; this is to avoid synchronization problems and undefined states between the clock domains. In effect this means that it is only reasonable to change rates while no selftimed conversion is ongoing.TABLE 1 - COMMAND REGISTER #0Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0config_lockals_data_rdyprox_data_rdyals_odprox_odals_enprox_enselftimed_enDescriptionconfig_lock Read only bit. Value = 1als_data_rdy Read only bit. Value = 1 when ambient light measurement data is available in the result registers. This bitwill be reset when one of the corresponding result registers (reg #5, reg #6) is read.prox_data_rdyRead only bit. Value = 1 when proximity measurement data is available in the result registers. This bit will be reset when one of the corresponding result registers (reg #7, reg #8) is read.als_od R/W bit. Starts a single on-demand measurement for ambient light. If averaging is enabled, starts a sequence of readings and stores the averaged result. Result is available at the end of conversion for reading in the registers #5(HB) and #6(LB).prox_od R/W bit. Starts a single on-demand measurement for proximity.Result is available at the end of conversion for reading in the registers #7(HB) and #8(LB).als_en R/W bit. Enables periodic als measurement prox_en R/W bit. Enables periodic proximity measurementselftimed_enR/W bit. Enables state machine and LP oscillator for self timed measurements; no measurement is performed until the corresponding bit is setRegister #1 Product ID Revision RegisterRegister address = 81h. This register contains information about product ID and product revision.Register data value of current revision = 21h.Register #2 Rate of Proximity Measurement Register address = 82h.Note•If self_timed measurement is running, any new value written in this register will not be taken over until the mode is actualy cycled.Register #3 LED Current Setting for Proximity ModeRegister address = 83h. This register is to set the LED current value for proximity measurement.The value is adjustable in steps of 10 mA from 0 mA to 200 mA.This register also contains information about the used device fuse program ID.TABLE 2 - PRODUCT ID REVISION REGISTER #1Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Product IDRevision IDDescriptionProduct ID Read only bits. Value = 2Revision IDRead only bits. Value = 1TABLE 3 - PROXIMITY RATE REGISTER #2Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0n/aRate of Proximity Measurement (no. ofmeasurements per second)DescriptionProximity rateR/W bits.000 - 1.95 measurements/s (DEFAULT)001 - 3.90625 measurements/s 010 - 7.8125 measurements/s 011 - 16.625 measurements/s 100 - 31.25 measurements/s 101 - 62.5 measurements/s 110 - 125 measurements/s 111 - 250 measurements/sTABLE 4 - IR LED CURRENT REGISTER #3Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Fuse prog IDIR LED current valueDescriptionFuse prog ID Read only bits.Information about fuse program revision used for initial setup/calibration of the device.IR LED current valueR/W bits. IR LED current = Value (dec.) x 10 mA.Valid Range = 0 to 20d. e.g. 0 = 0 mA , 1 = 10 mA, …., 20 = 200 mA (2 = 20 mA = DEFAULT) LED Current is limited to 200 mA for values higher as 20d.Register #4 Ambient Light Parameter Register Register address = 84h.Note•If self_timed measurement is running, any new value written in this register will not be taken over until the mode is actualy cycled.Register #5 and #6 Ambient Light Result RegisterRegister address = 85h and 86h. These registers are the result registers for ambient light measurement readings.The result is a 16 bit value. The high byte is stored in register #5 and the low byte in register #6.TABLE 5 - AMBIENT LIGHT PARAMETER REGISTER #4Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Cont. conv.modeals_rateAuto offset compensationAveraging function(number of measurements per run)DescriptionCont. conversion modeR/W bit. Continuous conversion mode.Enable = 1; Disable = 0 = DEFAULTThis function can be used for performing faster ambient light measurements. Please refer to the application information chapter 3.3 for details about this function. Ambient light measurement rateR/W bits. Ambient light measurement rate 000 - 1 samples/s001 - 2 samples/s = DEFAULT 010 - 3 samples/s 011 - 4 samples/s 100 - 5 samples/s 101 - 6 samples/s 110 - 8 samples/s 111 - 10 samples/sAuto offset compensationR/W bit. Automatic offset compensation.Enable = 1 = DEFAULT; Disable = 0In order to compensate a technology, package or temperature related drift of the ambient light values there is a built in automatic offset compensation function.With active auto offset compensation the offset value is measured before each ambient light measurement and subtracted automatically from actual reading.Averaging functionR/W bits. Averaging function.Bit values sets the number of single conversions done during one measurement cycle. Result is the average value of all conversions.Number of conversions = 2decimal_value e.g. 0 = 1 conv., 1 = 2 conv, 2 = 4 conv., ….7 = 128 conv.DEFAULT = 32 conv. (bit 2 to bit 0: 101)TABLE 6 - AMBIENT LIGHT RESULT REGISTER #5Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0DescriptionRead only bits. High byte (15:8) of ambient light measurement resultTABLE 7 - AMBIENT LIGHT RESULT REGISTER #6Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0DescriptionRead only bits. Low byte (7:0) of ambient light measurement resultRegister #7 and #8 Proximity Measurement Result RegisterRegister address = 87h and 88h. These registers are the result registers for proximity measurement readings.The result is a 16 bit value. The high byte is stored in register #7 and the low byte in register #8.Register #9 Interrupt Control Register Register address = 89h.TABLE 8 - PROXIMITY RESULT REGISTER #7Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0DescriptionRead only bits. High byte (15:8) of proximity measurement resultTABLE 9 - PROXIMITY RESULT REGISTER #8Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0DescriptionRead only bits. Low byte (7:0) of proximity measurement resultTABLE 10 - INTERRUPT CONTROL REGISTER #9Bit 7Bit 6Bit 5Bit 4Bit 3Bit 2Bit 1Bit 0Int count exceedn/aINT_PROX_ready_ENINT_ALS_ready_ENINT_THRES_ENINT_THRES_SELDescriptionInt count exceedR/W bits. These bits contain the number of consecutive measurements needed above/below the threshold000 - 1 count = DEFAULT 001 - 2 count 010 - 4 count 011 - 8 count 100 -16 count 101 - 32 count 110 - 64 count 111 - 128 countINT_PROX_ready_EN R/W bit. Enables interrupt generation at proximity data ready INT_ALS_ ready_EN R/W bit. Enables interrupt generation at ambient data readyINT_THRES_EN R/W bit. Enables interrupt generation when high or low threshold is exceeded INT_THRES_SELR/W bit. If 0: thresholds are applied to proximity measurements If 1: thresholds are applied to als measurementsRegister #10 and #11 Low ThresholdRegister address = 8Ah and 8Bh. These registers contain the low threshold value. The value is a 16 bit word. The high byte is stored in register #10 and the low byte in register #11.TABLE 11 - LOW THRESHOLD REGISTER #10Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0DescriptionR/W bits. High byte (15:8) of low threshold valueTABLE 12 - LOW THRESHOLD REGISTER #11Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0DescriptionR/W bits. Low byte (7:0) of low threshold valueRegister #12 and #13 High ThresholdRegister address = 8Ch and 8Dh. These registers contain the high threshold value. The value is a 16 bit word. The high byte is stored in register #12 and the low byte in register #13.TABLE 13 - HIGH THRESHOLD REGISTER #12Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0DescriptionR/W bits. High byte (15:8) of high threshold valueTABLE 14 - HIGH THRESHOLD REGISTER #13Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0DescriptionR/W bits. Low byte (7:0) of high threshold valueRegister #14 Interrupt Status RegisterRegister address = 8Eh. This register contains information about the interrupt status for either proximity or ALS function and indicates if high or low going threshold exceeded.TABLE 15 - INTERRUPT STATUS REGISTER #14Bit7Bit6Bit5Bit4Bit3Bit2Bit1Bit0n/a int_prox_ready int_als_ready int_th_low int_th_hiDescriptionint_prox_ready R/W bit. Indicates a generated interrupt for proximityint_als_ready R/W bit. Indicates a generated interrupt for alsint_th_low R/W bit. Indicates a low threshold exceedint_th_hi R/W bit. Indicates a high threshold exceedNote•Once an interrupt is generated the corresponding status bit goes to 1 and stays there unless it is cleared by writing a 1 in the corresponding bit. The int pad will be pulled down while at least one of the status bit is 1.分销商库存信息: VISHAYVCNL4010-GS08。

显卡培训讲义

2．显卡内存（显存类型、显存容量、显存带宽（显存频率×显存位宽÷8）、显存速度、显存颗粒、最高分辨率、显存时钟周期、显存封装）
3．技术支持（像素填充率、顶点着色引擎、3D API、RAMDAC频率）
4．显卡PCB板（PCB层数、显卡接口、输出接口、散热装置）
显示芯片
简介又称图型处理器-GPU。常见的生产显示芯片的厂商：Intel、AMD、nVidia、VIA（S3）、SIS、
用途：
将计算机系统所需要的显示信息进行转换驱动，并向显示器提供行扫描信号，控制显示器的正确显示，是连接显示器和个人电脑主板的重要元件，是“人机对话” 的重要设备之一。
基本结构
GPU GPU全称是Graphic Processing Unit，中文翻译为“图形处理器”。
显存显存是显示内存的简称。其主要功能就是暂时储存显示芯片要处理的数据和处
GTX>GTS>GT>GE>GS>SE≈LE≈XT>ZT
比如说GTX 560 1.第一位的5代表是系列
2.第二位的6则是产品的定位，1234是低端卡、5是中段、67是中高端（市面主流）、89是高端的了
3.最后一位占时可以忽略，有一些带5的是在原有基础上改进，如GTX285
另外也有些特殊的,比如加了TI的产品例如560TI，560是560TI的阉割版，560TI的性能比560的性能要强15%-30%
XL(eXTremeLimited 高端系列中的较低端型号)ATI最新推出的R430中的高频版。
XTX(XT eXtreme 高端版)X1000系列发布之后的新的命名规则。
CE(Crossfire Edition交叉火力版)交叉火力。 VIVO(VIDEO IN and VIDEO OUT)指显卡同时具备视频输入与视频捕捉两大功能。 HM(Hyper Memory)可以占用内存的显卡。 XTX > XT > XL> Pro > SE 第一位表示产品代数，如6870、6970都表示是第6代芯片。第二位表示级别（系列）划分，越大越好，如6970就比6870好。两者是不同的芯片，9是最高端，8是次高端。第三位表示同芯片中的性能差距（系列内型号），越大越好，6970就比 6950好

Giga-tronics 8650A系列通用电源表说明书

19818650AS ERIESU NIVERSALP OWERM ETERSThe Giga-tronics 8650A Series combines the speed,range and capabilities needed to test today’s sophisticated communications systems.sors,or from forgetting toThe Secret is the SensorsPULSE POWER MEASUREMENTS Attach a Giga-tronics 80350A Series Peak Power Sensor to an 8650A meter and directly measure the instantaneous peak power level of a pulse modulated e the ‘sample delay’ function to set the desired measurement point on the wave-form.And an external scope can be used to view the proﬁle and see the exact measurement point on the pulse.Giga-tronics power meter architecture provides for a broad choice of functional sensors.Just by changing a sensor,you can measure CW power,pulse power,and the peak and aver-age power of TDMA,GSM and CDMA signals faster,more accurately,and over a wider range.THEFASTESTCW MEASUREMENTSGiga-tronics 80300A Series CW Power Sensors let you measure CW power from 10 MHz to 40 GHz at more than 1,750readings per second over GPIB.Measure up to 90 dB with a single sensor,and select from a variety of high power sensors,up to 50 W .MODULA TEDPOWER MEASUREMENTSThe Giga-tronics 80400A Series Modulated Power Sensors let you measure the average power of ampli-tude modulated,burst modulated and other complex modulated signals — suchas TDMA signals — at bandwidths up to 40 kHz.The Giga-tronics 80600A Series Modulated Power Sensors provide bandwidth up to 1.5 MHz to measure the peak and average power of CDMA signals.And the Giga-tronics 80701A Modulated Power Sensor operating with the 8650A power meter,provides system bandwidth up to 10 MHz to measure the peak and average power of wide band,third-genera-tion CDMA signals over an 80 dB range.Displays of IntelligenceSEE FOR YOURSELFThe 8650A incorporates a 3.72” wide by 2.15” high Liquid Crystal Display (LCD)with 240 x 120 dot resolu-tion,0.38 mm dot pitch,and Cold Cathode Fluorescent Lamp (CCFL) back light for maximum detail and opti-mum viewing.The large display lets you see more information.And the display works in tandem with the meter controls to let you view menu selections and see your input data as you enter it.Y ou can view calibration information,select a standard mode,setup and recall pre-conﬁgured,custom modes,and set measurement points and durations.Each sensor uses an EEPROM to store values of cal factor.Enteringthe measurement frequency automatically calls up the correct cal factor.If the measurement frequency is between cal factor points,the meter automatically enters an interpolated value.An extensive list of help panels provide assistance in setting up special features and guidance in making the measurement.A volts per frequency input isavailable to set the cal factor when connected to an RF source.As the source frequency is modiﬁed the V/F output will automatically set the power meter to the correct cal factor,thereby eliminating the need for manual input.Peak (Pulse) power sensors can be set to the desired measurement point of a pulse signal.The trigger point can be set using an internalpower level or a TTL signal.Recall setup can be used to pre-conﬁgure measurement modes for later use.Full descriptive details help to clearly identify the settings before recall.The graphic display provides visual feedback as you set the measurement start time and duration of the time gate to measure the average power during a speciﬁc time period.View the mean power and standard deviation of the modulated signal over a time period of interest.Standard deviation offers an alter-native descriptive analysis of the power variation when compared to the traditional crest factor.ST A TISTICAL ANAL YSISExcessive cost can prove as detrimental to the success of communications equipment as inadequate performance.The 8650A provides a range of statistical power measurement analysis fea-tures that help you optimize your designs to prevent inad-equate performance due to under design or excessive cost due to over design.These features include crest factor,standard devi-ation,strip chart,CDF/CCDF ,and histogram,and they let you view and thoroughly analyze the power signal over a selected period of time.Combined,they make the 8650A the most advanced power meter available for communications systemsdesign.The histogram function allows youto view a power range distribution over a period of time.The x axis displays the minimum to maximum power levels measured during the interval time period,and the y axis displays the percent of time each power level is measured.A zoom feature lets you view smaller seg-ments of the power range to bet-ter analyze the percentage of time a speciﬁc power level has occurred.The strip chart function allows you to view the vary-ing power levels of a signal over a period of time.The x axis displays time from the start of the meas-urement to a selectable period of 1 to 200 minutes,and the y axis displays the minimum to maximum power levels measured during the selected period.Moving a cursor along the x axis displays time and the corresponding power level.The Cumulative Distribution Function (CDF) shows the percentage of time a signal is below a selected power level.Thex axis displays the amount of power at the selected level,meas-ured in dBm,and the y axis dis-plays the percentage of time the power is at or below the power speciﬁed by the x axis.The Complementary Cumulative Distribution Function (CCDF) reori-ents the CDF curve in accordance with the equation CCDF = 1-CDF for more accustomed viewing of a descending slope.Moving a cursor along the slope of the curve dis-plays the power level in dBm and the corresponding percentage of time the signal is above that level.The K connector is electrically and mechanically compatible with the APC-3.5 and SMA connec-tors.Note:Use a Type N(m) to SMA(f) adapter (part no.29835) for calibration of power sensors with Type K(m) connectors.Power coefﬁcient equals <0.01 dB/Watt.Power coefﬁcient equals <0.015 dB/Watt.For frequencies above 8 GHz,add power linearity to system linearity.Power coefﬁcient equals <0.01 dB/Watt (Average).Power coefﬁcient equals <0.015 dB/Watt (Average).Peak operating range above CW maximum range is limited to <10% duty cycle.Square root of the sum of the individual uncertainties squared (RSS).Cal Factor numbers allow for 3% repeatability when reconnecting an attenuator to a sensor and 3% for attenuator measurement uncertainty and mismatch of sensor/pad combination.Depending on sensor used.MAP (Modulated Average Power),PAP (Pulse Average Power),BAP (Burst Average Power).Speciﬁed performance applies with maximum averaging and 24 hour warm-up at constant temperature.Operates in Normal Mode only.Display contrast reduces above 50°C.Does not apply to 80701A Sensor below 500 MHz.Speciﬁcations subject to change without notice.Speciﬁcations describe the instrument’s warranted performance,and apply when using the 80300A,80400A,80600A,and 80700A Series Sensors.METERFrequency Range:10 MHz to 40 GHz 10Power Range:-70 dBm to +47 dBm (100 pW to 50 Watt) 10Single Sensor Dynamic Range:10CW Power Sensors:90 dB Peak (Pulse) Power Sensors:40 dB,Peak50 dB,CWModulation Power Sensors:87 dB,CW80 dB,MAP/PAP 1160 dB,BAP 11Display Resolution:User selectable from 1 dB to 0.001 dB in Log mode,and from 1 to 4digits of display resolution in Linear mode.Meter FunctionsMeasurement Modes (Sensors):CW (80300A,80350A,80400A,80600A,and 80700A Series)Peak (80350A Series)MAP/PAP/BAP 11(80400A,80600A,and 80700A Series)Averaging:User selectable,auto-averaging or manual from 1-512 readings.Timed averaging from 20 ms to 20 seconds.dB Rel and Offset:Power display can be offset by -99.999 to +99.999 dB to account for external loss/gain.Conﬁguration Storage Registers:Allows up to 20 front panel setups.Power Measurements and Display Conﬁgurations:Any two of the following channel conﬁgurations,simultaneously:A,B,A/B,B/A,A-B,B-A,DLYA,DLYB Number of Display Lines:4Sampling:CW and Modulation Mode: 2.5 to 5 MHz asynchronous Analog Bandwidth:CW Mode:≥3 kHzModulation Mode:>10 MHz Time Gating:Trigger Delay:0 to 327 ms Gate Time:10 µs to 327 ms Holdoff Time:0 to 327 ms ACCURACY50 MHz Calibrator:(Standard)Calibrator:+20 dBm to -30 dBmpower sweep calibration signal to dynamically linearize the power sensors.Connector:Type N,50 ΩFrequency:50 MHz,nominal0.0 dBm Accuracy:±1.2% worst case for one year,over temperature range of 5º to 35ºC.VSWR:<1.05 (Return Loss >33 dB) @0 dBm.1 GHz Calibrator:(Option 12)Required for 80700A Series Sensors.Calibrator:+20 dBm to -30 dBmpower sweep calibration signal to dynamically linearize power sensors.Connector:Type N,50 ΩFrequency:(Switchable):1 GHz,nominal;50 MHz,nominal0.0 dBm Accuracy:±1.2% worst case for one year,over temperature range of 5º to 35ºC.VSWR:<1.07 (Return Loss >30 dB) @0 dBm.800 MHz - 1 GHz Synthesizer Speciﬁcations:(Option 12)Power Range:+15 dBm to -30 dBm,settable in 1 dB steps.Frequency:800 MHz to 1 GHz,settable in 1 MHz steps.Power Stability:<0.1 dB/Hour Frequency Accuracy:±0.05%Instrumentation Linearity:±0.02 dB over any 20 dB range from -70 to +16 dBm.15±0.02 dB + (±0.05 dB/dB) from +16 to +20 dBm.±0.04 dB from -70 to +16 dBm.Graph shows linearity plus worst case zero set,and noise versus input powerTemperature Coefﬁcient ofLinearity:<0.3%/ºC temperature change following Power Sweep calibration.24 hour warm-up required.Zeroing Accuracy:(CW)Zero Set:12<±50 pW,<±100 pW with80400A and 80600A Series Modulation Power Sensors.<±200 pW with 80700A Series Sensors.Zero Drift:12<±100 pW during 1 hour,<±200 pW with 80400A and 80600A Series Sensors,<±400 pW with 80700A Series Sensors.Noise:<±50 pW,<±100 pW with 80400A and 80600A Series Modulation Power Sensors.<±200 pW with 80700A Series Sensors.Measurable over any 1 minute interval after zeroing,3 standard deviations.REMOTE INPUTS/OUTPUTSV Prop F Input (BNC):Sets calibration factors using source VpropF output.13Analog Output (2) (BNC):Provides an output voltage of 0 to 10V for Channels 1 and 2 ineither Lin or Log units.13Does not operate in Swift or Buffered modes .Trigger Input (BNC):TTL trigger input signal for Swift and Fast Buffered modes.GPIB Interface:IEEE-488 and IEC-625 remote programmingRS232 Interface:Programmable serial interface,DB-9 connector GENERAL SPECIFICATIONS Temperature Range:Operating:0º to 55ºC (+32º to +131ºF)14Storage:-40ºC to 70ºC (-40º to +158ºF)Power Requirements:100/120/220/240V ±10%,48 to 440 Hz,25VA typical Physical Characteristics:Dimensions:215 mm (8.4 in) wide,89 mm (3.5 in) high,368 mm (14.5 in) deep Weight:4.55 kg (10lbs)ORDERING INFORMATION POWER METERS 8651A Single Input Universal Power Meter(includes 1 sensor cable)8652A Dual Input Universal Power Meter(includes 2 sensor cables)ACCESSORIESOne manual,one power cord.POWER METER OPTIONS 01Rack mount kit038651A Rear Panel Sensor and Calibrator Connections 048652A Rear Panel Sensor and Calibrator Connections 05Soft Carry Case07Side Mounted Carrying Handle08Transit Case,(Includes Soft Carry Case)09Dual Rack Mount Kit (with assembly instructions)10Dual Rack Mount Kit (factory assembled)12 1 GHz,50 MHz Switchable Calibrator 138651A Rear Panel Input Connector 148652A Rear Panel Input Connectors80301A 80310A 80320A 80321A 80322A 80325A 80330A80401A, 80601A (CW)80701A (CW)-70-64-60-50-40-40-30-67-64-60-54-50-40-30-30-20-57-54-50-44-40-30-20-20-10-47-44-40-34-30-20-10-100-37-34-30-24-20-100010-27-25-20-14-100101020-17-16-10-40102020-7-7061020303033101620304040131320253040445020203210-1-2-3S E N S O R ST Y P I C A L E R R O R (d B )Input, (dBm)Giga-tronics Incorporated 4650 Norris Canyon Road San Ramon,California 94583T elephone:800 726 4442 or925 328 4650T elefax:925 328 4700Web Site:© 1999 Giga-tronics IncorporatedGT-167-B。

VLMK3102-GS08中文资料

Vishay SemiconductorsVLMK310.Document Number For technical support, please contact: LED@Standard SMD LED PLCC-2FEATURES•SMD LED with exceptional brightness •Luminous intensity categorized•Compatible with automatic placementequipment•EIA and ICE standard package•Compatible with IR reflow, vapor phase and wave solder processes according to CECC 00802 and J-STD-020B•Available in 8 mm tape •Low profile package•Non-diffused lens: excellent for coupling to light pipes and backlighting •Low power consumption •Luminous intensity ratio in one packaging unit I Vmax /I Vmin ≤ 1.6•Lead (Pb)-free device•Preconditioning acc. to JEDEC level 2a •ESD-withstand voltage: up to 2 kV according to JESD22-A114-B•Automotive qualified AEC-Q10119225DESCRIPTIONThis device has been designed to meet the increasing demand for AlInGaP technology.The package of the VLMK310. is the PLCC-2(equivalent to a size B tantalum capacitor).It consists of a lead frame which is embedded in a white thermoplast. The reflector inside this package is filled up with clear epoxy.PRODUCT GROUP AND PACKAGE DATA •Product group: LED •Package: SMD PLCC-2 •Product series: standard •Angle of half intensity: ± 60°APPLICATIONS •Automotive: backlighting in dashboards and switches •Telecommunication: indicator and backlighting in telephone and fax •Indicator and backlight for audio and video equipment•Indicator and backlight in office equipment •Flat backlight for LCDs, switches and symbols •General usePARTS TABLEPARTCOLOR, LUMINOUS INTENSITYTECHNOLOGY VLMK3100-GS08Red, I V > 11.2 mcd AllnGaP on GaAs VLMK3100-GS18Red, I V > 11.2 mcd AllnGaP on GaAs VLMK3102-GS08Red, I V = (22.4 to 56) mcd AllnGaP on GaAs VLMK3102-GS18Red, I V = (22.4 to 56) mcd AllnGaP on GaAs VLMK3105-GS08Red, I V = (35.5 to 90) mcd AllnGaP on GaAs VLMK3105-GS18Red, I V = (35.5 to 90) mcdAllnGaP on GaAs Document Number 81230Vishay SemiconductorsVLMK310.For technical support, please contact: LED@Note:1) Tamb = 25°C, unless otherwise specified 2)Driving LED in reverse direction is suitable for short term applicationNote:1) Tamb = 25°C, unless otherwise specified 2) In one packing unit IVmax /I Vmin ≤ 2.0Note:Luminous intensity is tested at a current pulse duration of 25 ms and an accuracy of ± 11 %.The above type numbers represent the order groups which include only a few brightness groups. Only one group will be shipped on each reel (there will be no mixing of two groups on each reel).In order to ensure availability, single brightness groups will not be or-derable.In a similar manner for colors where wavelength groups are mea-sured and binned, single wavelength groups will be shipped on any one reel.In order to ensure availability, single wavelength groups will not be orderable.ABSOLUTE MAXIMUM RATINGS 1) VLMK310.PARAMETER TEST CONDITIONSYMBOLVALUE UNIT Reverse voltage 2)V R 5V DC Forward current T amb ≤ 85°C I F 30mA Surge forward current t p ≤ 10 µs I FSM 0.1A Power dissipation P V 80mW Junction temperature T j 125°C Operating temperature range T amb - 40 to + 100°C Storage temperature range T stg - 40 to + 100°C Thermal resistance junction/ambientmounted on PC board (pad size > 16 mm 2)R thJA400K/WOPTICAL AND ELECTRICAL CHARACTERISTICS 1) VLMK310., REDPARAMETER TEST CONDITIONPART SYMBOLMIN.TYP.MAX.UNIT Luminous intensity 2)I F = 10 mA VLMK3100I V 11.250mcd VLMK3102I V 22.456mcd VLMK3105I V 35.590mcd Dominant wavelength I F = 10 mA λd 630nm Peak wavelength I F = 10 mA λp 643nm Angle of half intensity I F = 10 mA ϕ± 60deg Forward voltage I F = 20 mA V F 1.92.6V Reverse voltage I R = 10 µA V R 5V Junction capacitanceV R = 0, f = 1 MHzC j15pFLUMINOUS INTENSITY CLASSIFICATIONGROUP LIGHT INTENSITY (mcd)STANDARDOPTIONALMIN. MAX. L 111.214.0214.018.0M 118.022.4222.428.0N 128.035.5235.545.0P 145.056.0256.071.0Q 171.090.0290.0112.0R1112.0140.02140.0180.0CROSSING TABLEVISHAY OSRAM VLMK3100LST676VLMK3102LST676VLMK3105LST676Document Number Vishay SemiconductorsVLMK310.For technical support, please contact: LED@TYPICAL CHARACTERISTICST amb = 25°C, unless otherwise specifiedFigure 1. Max. Permissible Forward Current vs.Ambient TemperatureFigure 2. Rel. Luminous Intensity vs. Angular DisplacementFigure3. Forward Current vs. Forward Voltage 05101520253035400102030405060708090100T am b - Am b ient Temperat u re (°C)16615I F - F o r w a r d C u r r e n t (m A )0.40.295 103190.60.90.80°30°10°20°40°50°60°70°80°0.71.0I V r e l - R e l a t i v e L u m i n o u s I n t e n s i t yϕ - A n g u l a r D i s p l a c e m e n t1101001.01.52.02.53.0V F - For w ard V oltage (V )95 10878I F - F o r w a r d C u r r e n t (m A)Figure 4. Rel. Luminous Intensity vs. Ambient TemperatureFigure 5. Specific Luminous Intensity vs.Forward Current/Duty CycleFigure6. Relative Luminous Intensity vs. Forward Current0.00.20.40.60.81.01.21.41.61.82.0102030405060708090100 T am b - Am b ient Temperat u re (°C)16618I V r e l - R e l a t i v e L u m i n o u s I n t e n s i ty0.00.20.40.60.81.01.21.41.61.82.011096 11589I s p e c - S p e c i f i c L u m i n o u s I n t e n s i t yt P /TI F (mA)5052020.50.20.10.050.0210.010.1110110100I F - For w ard C u rrent (mA)96 11588I V r e l - R e l a t i v e L u m i n o u s I n t e n s i t y Document Number 81230Vishay SemiconductorsVLMK310.For technical support, please contact: LED@PACKAGE DIMENSIONS in millimetersFigure 7. Relative Intensity vs. Wavelength Figure8. Forward Voltage vs. Ambient Temperature0.00.10.20.30.40.50.60.70.80.91.01.11.2600610620630640650660670680690700λ- W a v elength (nm)96 12075I - R e l a t i v e I n t e n s i t yr e lFigure9. Permissible Forward Current vs. Pulse Length10.00100.001000.000.010.10 1.0010.00100.00t p - P u lse Length (ms)16622I - F o r w a r d C u r r e n t (m A )F MDocument Number Vishay SemiconductorsVLMK310.For technical support, please contact: LED@METHOD OF TAPING/POLARITY AND TAPE AND REEL SMD LED (VLM3-SERIES)Vishay’s LEDs in SMD packages are available in an antistatic 8 mm blister tape (in accordance with DIN IEC 40 (CO) 564) for automatic component insertion. The blister tape is a plastic strip with impressed component cavities, covered by a top tape.TAPING OF VLM.3..REEL PACKAGE DIMENSION IN MM FOR SMD LEDS, TAPE OPTION GS08(= 1500 PCS.)REEL PACKAGE DIMENSION IN MM FOR SMD LEDS, TAPE OPTION GS18(= 8000 PCS.) PREFERREDSOLDERING PROFILEFigure 10. Tape Dimensions in mm for PLCC-2Figure11. Reel Dimensions - GS08Figure 12. Reel Dimensions - GS18Figure 13. Vishay Leadfree Reflow Soldering Profile(acc. to J-STD-020B)Figure 14. Double Wave Soldering of Opto Devices (all Packages) Document Number 81230Vishay SemiconductorsVLMK310.For technical support, please contact: LED@BAR CODE PRODUCT LABELA)Type of component B)Manufacturing plantC)SEL - selection code (bin):e.g.: N2 = code for luminous intensity group D)Date code year/weekE)Day code (e.g. 1: Monday)F)Batch no.G)Total quantity H)Company codeDRY PACKINGThe reel is packed in an anti-humidity bag to protect the devices from absorbing moisture during transportation and storage.FINAL PACKINGThe sealed reel is packed into a cardboard box. A secondary cardboard box is used for shipping purposes.RECOMMENDED METHOD OF STORAGEDry box storage is recommended as soon as the aluminum bag has been opened to prevent moisture absorption. The following conditions should be observed, if dry boxes are not available:• Storage temperature 10°C to 30°C • Storage humidity ≤ 60 % RH max.After more than 672 h under these conditions moisture content will be too high for reflow soldering.In case of moisture absorption, the devices will recover to the former condition by drying under the following condition:192 h at 40°C + 5°C/- 0°C and < 5 % RH (dry air/nitrogen) or96 h at 60°C + 5°C and < 5 % RH for all device containers or24 h at 100°C + 5°C not suitable for reel or tubes.An EIA JEDEC standard JESD22-A112 level 2a label is included on all dry bags.Example of JESD22-A112 level 2a labelESD PRECAUTIONProper storage and handling procedures should be followed to prevent ESD damage to the devices especially when they are removed from the antistatic shielding bag. Electro-static sensitive devices warning labels are on the packaging.VISHAY SEMICONDUCTORS STANDARD BAR CODE LABELSThe Vishay Semiconductors standard bar code labels are printed at final packing areas. The labels are on each packing unit and contain Vishay Semiconductors specific data.V ISHAYHVishay SemiconductorsVLMK310.Document Number For technical support, please contact: LED@OZONE DEPLETING SUBSTANCES POLICY STATEMENT It is the policy of Vishay Semiconductor GmbH to1.Meet all present and future national and international statutory requirements.2.Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment.It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs).The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances.Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents.1.Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively.2.Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA.3.Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively.Vishay Semiconductor G mbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.We reserve the right to make changes to improve technical designand may do so without further notice.Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Semiconductors products for any unintended or unauthorized application, the buyer shall indemnify Vishay Semiconductors against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with suchunintended or unauthorized use.Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, GermanyDisclaimer Legal Disclaimer NoticeVishayAll product specifications and data are subject to change without notice.Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product.Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products.No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay.The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications.Product names and markings noted herein may be trademarks of their respective owners.元器件交易网Document Number: 。

场效应管使用资料

场效应管使用资料07N03L 30V 80A 150W N10N20 10A 200V N 沟道MOS管10N60 10A 600V11N80 11A 800V 156W11P06 60V 9.4A P沟道直插13N60 13A 600V N 沟道15N03L 30V 42A 83W N2N7000 60V 0.2A 0.35W N2N7000 60V 0.2A 0.35W N40N03H 30V 40A N4232 内含P沟道,N沟道MOS管各一,4532M 内含P沟道,N沟道MOS管各一,50N03L(SD 30V 47A 50W N 沟道小贴片MOS 55N03 25V 55A 103W5N90 5A 900V5P25 250V 5A6030LX 30V 52A 42W N603AL 30V 25A 60W N 沟道小贴片MOS6A60 600V 6A N6N70 700V 6A N6P25 250V 6A70L0270N06 70A 60V 125W7N60 600V 7A N,铁7N70 7A 700V85L028N25 250V ,8A ,同IRF63495N03 25V 75A 125W9916H 18V 35A 58W 小贴片，全新9N60 9A 600V9N70 9A 700VAF4502CS 内含P沟道，N沟道MOS管各一A04403 30V 6.1A 单P沟道8脚贴片A04404 30V 8.5A 单N沟道8脚贴片A04405 30V 6A 3W 单P沟道8脚贴片A04406 30V,11.5A,单N沟道,8脚贴A04407 30V 12A 3W 单P沟道,8脚贴片A04407 30V 12A 3W 单P沟道,8脚贴片A04408 30V 12A 单N沟道,8脚贴片A04409 30V 15A P沟道场效应,8脚A04410 30V 18A 单N沟道8脚贴片A04411 30V 8A 3W P沟道场效应,8脚A04413 30V 15A 3W 单P沟道,8脚贴片A04413 30V 15A 3W 单P沟道,8脚贴片A04414 30V,8.5A,3WM 单N沟道，8脚A04418 30V 11.5A N沟道8脚贴片A04422 30V 11A N 沟道8脚贴片A04423 30V 15A 3.1W 单P沟道,8脚贴A04600 内含P沟道，N沟道MOS管各一A0D405 30V，18A，P高压板MOS管贴A0D408 30V，18A，P高压板MOS管贴A0D409 60V 26/18A P 高压板MOS 管贴A0D409 60V 26/18A P 高压板MOS 管贴A0D420 30V,10A,N高压板MOS管贴A0D442 60V，38/27A，N 高压板MOS管贴A0D442 60V38/27A,N高压板MOS管贴A0D444 60V,12A,N 高压板MOS管贴A0P600 内含P,N沟道各1,30V 7.5AA0P605 内含P,N沟道各1,30V 7.5AA0P607 内含P、N沟道各1，60V 4。

RM68042中文资料

RM68041数据手册一、概述rm68041是262144色SOC的单片驱动分辨率为320rgbx480 a-tft液晶显示器点，包括一个960通道的源程序，一个480通道的栅极驱动器，345600字节克图形数据320rgbx480点，和电源电路。

该rm68041支持18 / 16 / 9 / 8位数据总线接口（DBI）和串行外设接口（SPI）。

它也提供18位或16位RGB接口（DPI）驱动的视频信号直接从应用程序控制器。

移动图片区地址可以通过窗口函数内部克指定。

指定的窗口区域可更新的选择性，使运动画面可同时显示独立的静止图像区域。

rm68041可以操作为1.65V I/O接口电压，电压跟随器电路和注册产生驱动液晶的电压水平。

该rm68041还支持功能，8种颜色显示和睡眠模式，允许通过软件精确的功率控制，这些特点使rm68041理想LCD驱动器中小型便携式产品如数字蜂窝电话，智能手机，MP3和PMP在长的电池寿命是一个重要的问题。

二、特性显示分辨率：[ 320xrgb ]（H）×480（V）输出：960源输出480门的输出常见的电极输出a-tft LCD驱动芯片上的完整的显示内存：345600字节MCU接口：mipi-dbi（符合MIPI DBI版本2）B型16 / 18位，8 / 9C型四线9bit（选项1），8位（选项3）16位，18位RGB接口（DPI）MIPI DCS的命令集3 / 4针串行接口显示方式：全彩色模式：26万色减少色彩模式：8色（3位的MSB位模式）芯片功能：VCOM发生器和调整定时发生器振荡器直流/直流转换器线/帧反转传输协议16位Id1和Id2VCOM调整为7位低功耗结构低工作电源：iovcc = 1.65V ~ 3.3V（接口的I / O）VCI = 2.5V ~ 3.3V（模拟）LCD电压驱动：源/威科姆电源电压ddvdh - GND = 4.5V ~ 6.0VVCL–GND = 1.0V ~ - 3.0伏VCI–VCL≦6.0V栅极驱动器输出电压荣总–GND = 10V ~ 18VVGL–GND = 5V的~ -12.5v荣总–VGL≦32VVcom驱动输出电压vcomh = 3.0V ~（ddvdh-0.5）VVCOML =（VCL + 0.5）V ~ 0Vvcomh-vcoml≦6.0V工作温度范围：40到85℃℃三、结构图IM[2:0] 选择微处理器系统的接口方式RESX 这个信号低将重置设备，必须采用恰当的初始化芯片。

Dell Edge Gateway 3002 规格说明书

Dell Edge Gateway 3002规格计算机型号： Dell Edge Gateway 3002管制型号： N03G管制类型： N03G001注、小心和警告注: “注”表示帮助您更好地使用该产品的重要信息。

小心: “小心”表示可能会损坏硬件或导致数据丢失，并说明如何避免此类问题。

警告: “警告”表示可能会造成财产损失、人身伤害甚至死亡。

Dell、EMC 和其他商标均为 Dell Inc. 或其附属公司的商标。

其他商标均为其各自所有者的商标。

2017 - 11Rev. A03目录1 尺寸和重量 (5)产品 (5)包装 (5)安装尺寸 (5)VESA 安装尺寸 (6)2 环境和操作条件 (7)环境条件 (7)操作条件 (7)3 功率 (9)电源 (9)点火 (10)3 V CMOS 币形电池 (11)4 操作系统 (12)5 处理器 (13)6 内存 (14)7 存储时 (15)8 外部端口和连接器 (16)9 通信 (17)无线 LAN (17)无线 WAN (17)DW5515 规格 (17)DW5815 规格 (18)DW5818 规格 (18)DW5819 规格 (18)WWAN 提供商和选项 (19)全球导航卫星系统 (GNSS) (19)蓝牙 (20)CANbus (20)10 安全性 (21)11 环境合规性 (22)12 软件 (23)313 服务和支持 (24)14 联系 Dell (25)41尺寸和重量产品表. 1: 产品高度125 毫米（4.92 英寸）宽度125 毫米（4.92 英寸）厚度51 毫米（2 英寸）重量 1 千克（2.20 磅）卷0.80 升包装注: 包装重量包含 Edge Gateway 和四个天线的总重量。

表. 2: 包装高度262 毫米（10.32 英寸）宽度139 毫米（5.47 英寸）厚度241 毫米（9.49 英寸）发运重量（包括包装材料）1.71 千克（3.77 磅）安装尺寸注: 安装尺寸包括 Edge Gateway以及各种安装选项的尺寸。

GS8640Z36GT-250V中文资料

GS8640Z18/36T-xxxV72Mb Pipelined and Flow ThroughSynchronous NBT SRAM 250 MHz –167 MHz 1.8 V or 2.5 V V DD 1.8 V or 2.5 V I/O100-Pin TQFP Commercial Temp Industrial Temp Features• NBT (No Bus Turn Around) functionality allows zero wait read-write-read bus utilization; Fully pin-compatible with both pipelined and flow through NtRAM™, NoBL™ and ZBT™ SRAMs• 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply• User-configurable Pipeline and Flow Through mode • LBO pin for Linear or Interleave Burst mode• Pin compatible with 4Mb, 9Mb, 18Mb and 36Mb devices • Byte write operation (9-bit Bytes)• 3 chip enable signals for easy depth expansion • ZZ Pin for automatic power-down• JEDEC-standard 100-lead TQFP package• RoHS-compliant 100-lead TQFP package availableFunctional DescriptionThe GS8640Z18/36T-xxxV is a 72Mbit Synchronous Static SRAM. GSI's NBT SRAMs, like ZBT, NtRAM, NoBL or other pipelined read/double late write or flow through read/single late write SRAMs, allow utilization of all available bus bandwidth by eliminating the need to insert deselect cycles when the device is switched from read to write cycles.Because it is a synchronous device, address, data inputs, and read/ write control inputs are captured on the rising edge of the input clock. Burst order control (LBO) must be tied to a power rail for proper operation. Asynchronous inputs include the Sleep mode enable (ZZ) and Output Enable. Output Enable can be used to override the synchronous control of the output drivers and turn the RAM's output drivers off at any time. Write cycles are internally self-timed and initiated by the rising edge of the clock input. This feature eliminates complex off-chip write pulse generation required by asynchronous SRAMs and simplifies input signal timing.The GS8640Z18/36T-xxxV may be configured by the user to operate in Pipeline or Flow Through mode. Operating as a pipelined synchronous device, meaning that in addition to the rising edge triggered registers that capture input signals, the device incorporates a rising-edge-triggered output register. For read cycles, pipelined SRAM output data is temporarily stored by the edge triggered output register during the access cycle and then released to the output drivers at the next rising edge of clock.The GS8640Z18/36T-xxxV is implemented with GSI's high performance CMOS technology and is available in a JEDEC-standard 100-pin TQFP package.Parameter Synopsis-250-200-167Unit Pipeline 3-1-1-1t KQ tCycle 3.04.0 3.05.0 3.56.0ns ns (x18)Curr (x32/x36)410350305mA Flow Through 2-1-1-1t KQ tCycle 6.56.57.57.58.08.0ns ns (x18)Curr (x32/x36)280250240mA807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B FT V DD NC V SS DQ B DQ B V DDQ V SS DQ B DQ B DQP BV SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0N C N C V S SV D DA A A A A A A AA A E 1E 2 N C N C B BB AE 3C K W C K E VD DV S SG A D V A A A AA 2M x 18Top View DQP A A NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS8640Z18/36T-xxxVGS8640Z18T-xxxV Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C FT V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0N C N C V S SV D DA A A A A A A AA A E 1E 2 B DB CB BB AE 3C K W C K E VD DV S SG A D V A A A AA 1M x 36Top View DQB DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP ADQ C DQ C DQ C DQ D DQ D DQ D DQP DDQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950GS8640Z18/36T-xxxVGS8640Z36T-xxxV Pinout (Package T)TQFP Pin DescriptionsSymbolTypeDescriptionA 0, A 1In Burst Address Inputs; Preload the burst counterA In Address Inputs CK In Clock Input SignalB A In Byte Write signal for data inputs DQ A1-DQ A9; active low B B In Byte Write signal for data inputs DQ B1-DQ B9; active low BC In Byte Write signal for data inputs DQ C1-DQ C9; active low BD In Byte Write signal for data inputs DQ D1-DQ D9; active lowW In Write Enable; active low E 1In Chip Enable; active lowE 2In Chip Enable; Active High. For self decoded depth expansion E 3In Chip Enable; Active Low. For self decoded depth expansionG In Output Enable; active lowADV In Advance/Load; Burst address counter control pinCKE In Clock Input Buffer Enable; active low DQ A I/O Byte A Data Input and Output pins DQ B I/O Byte B Data Input and Output pins DQ C I/O Byte C Data Input and Output pins DQ D I/O Byte D Data Input and Output pins ZZ In Power down control; active high FT In Pipeline/Flow Through Mode Control; active lowLBO In Linear Burst Order; active lowV DD In Core power supplyV SS In GroundV DDQ In Output driver power supplyNC—No ConnectGS8640Z18/36T-xxxVKS A 1S A 0B u r s t Co u nt e rL B OA D VM e m o r y A r r a yE 3E 2E 1GWB DB CB BB AC KC K ED QF TD Q a –D Q nKS A 1’S A 0’D QM a t c hW r i t e A d d r e s sR e g i s t e r 2W r i t e A d d r e s sR e g i s t e r 1W r i t e D a t aR e g i s t e r 2W r i t e D a t aR e g i s t e r 1KKKKKKS e n s e A m p sW r i t e D r i v e r sR e a d , W r i t e a n dD a t a C o h e r e n c yC o n t r o l L o g i cF TA 0–A nGS8640Z18/36T-xxxVGS8640Z18/36T-xxxV NBT SRAM Functional Block DiagramGS8640Z18/36T-xxxVFunctional DetailsClockingDeassertion of the Clock Enable (CKE) input blocks the Clock input from reaching the RAM's internal circuits. It may be used to suspend RAM operations. Failure to observe Clock Enable set-up or hold requirements will result in erratic operation.Pipeline Mode Read and Write OperationsAll inputs (with the exception of Output Enable, Linear Burst Order and Sleep) are synchronized to rising clock edges. Single cycle read and write operations must be initiated with the Advance/Load pin (ADV) held low, in order to load the new address. Device activation is accomplished by asserting all three of the Chip Enable inputs (E 1, E 2 and E 3). Deassertion of any one of the Enable inputs will deactivate the device. Function W B A B B B C B D Read H X X X X Write Byte “a”L L H H H Write Byte “b”L H L H H Write Byte “c”L H H L H Write Byte “d”L H H H L Write all Bytes L L L L L Write Abort/NOPLHHHHRead operation is initiated when the following conditions are satisfied at the rising edge of clock: CKE is asserted Low, all three chip enables (E 1, E 2, and E 3) are active, the write enable input signals W is deasserted high, and ADV is asserted low. The address presented to the address inputs is latched in to address register and presented to the memory core and control logic. The control logic determines that a read access is in progress and allows the requested data to propagate to the input of the output register. At the next rising edge of clock the read data is allowed to propagate through the output register and onto the output pins.Write operation occurs when the RAM is selected, CKE is active, and the Write input is sampled low at the rising edge of clock. The Byte Write Enable inputs (B A , B B , B C, & B D ) determine which bytes will be written. All or none may be activated. A write cycle with no Byte Write inputs active is a no-op cycle. The pipelined NBT SRAM provides double late write functionality,matching the write command versus data pipeline length (2 cycles) to the read command versus data pipeline length (2 cycles). At the first rising edge of clock, Enable, Write, Byte Write(s), and Address are registered. The Data In associated with that address is required at the third rising edge of clock.Flow Through Mode Read and Write OperationsOperation of the RAM in Flow Through mode is very similar to operations in Pipeline mode. Activation of a Read Cycle and the use of the Burst Address Counter is identical. In Flow Through mode the device may begin driving out new data immediately after new address are clocked into the RAM, rather than holding new data until the following (second) clock edge. Therefore, in Flow Through mode the read pipeline is one cycle shorter than in Pipeline mode.Write operations are initiated in the same way, but differ in that the write pipeline is one cycle shorter as well, preserving the ability to turn the bus from reads to writes without inserting any dead cycles. While the pipelined NBT RAMs implement a double late write protocol, in Flow Through mode a single late write protocol mode is observed. Therefore, in Flow Through mode, address and control are registered on the first rising edge of clock and data in is required at the data input pins at the second rising edge of clock.Synchronous Truth TableOperationType Address CK CKE ADV W Bx E 1E 2E 3G ZZDQNotesRead Cycle, Begin Burst R External L-H L L H X L H L L L Q Read Cycle, Continue Burst B Next L-H L H X X X X X L L Q 1,10NOP/Read, Begin Burst R External L-H L L H X L H L H L High-Z 2Dummy Read, Continue Burst B Next L-H L H X X X X X H L High-Z 1,2,10Write Cycle, Begin Burst W External L-H L L L L L H L X L D 3Write Cycle, Continue Burst B Next L-H L H X L X X X X L D1,3,10Write Abort, Continue Burst B Next L-H L H X H X X X X L High-Z 1,2,3,10Deselect Cycle, Power Down D None L-H L L X X H X X X L High-Z Deselect Cycle, Power Down D None L-H L L X X X X H X L High-Z Deselect Cycle, Power Down D None L-H L L X X X L X X L High-Z Deselect Cycle D None L-H L L L H L H L X L High-Z 1Deselect Cycle, Continue DNone L-H L H X X X X X X L High-Z 1Sleep ModeNone X X X X X X X X X H High-Z Clock Edge Ignore, StallCurrentL-HHXXXXXXXL-4Notes:1.Continue Burst cycles, whether read or write, use the same control inputs. A Deselect continue cycle can only be entered into if a Dese-lect cycle is executed first.2.Dummy Read and Write abort can be considered NOPs because the SRAM performs no operation. A Write abort occurs when the Wpin is sampled low but no Byte Write pins are active so no write operation is performed.3.G can be wired low to minimize the number of control signals provided to the SRAM. Output drivers will automatically turn off duringwrite cycles.4.If CKE High occurs during a pipelined read cycle, the DQ bus will remain active (Low Z). If CKE High occurs during a write cycle, the buswill remain in High Z.5. X = Don’t Care; H = Logic High; L = Logic Low; Bx = High = All Byte Write signals are high; Bx = Low = One or more Byte/Writesignals are Low6.All inputs, except G and ZZ must meet setup and hold times of rising clock edge.7.Wait states can be inserted by setting CKE high.8.This device contains circuitry that ensures all outputs are in High Z during power-up.9. A 2-bit burst counter is incorporated.10.The address counter is incriminated for all Burst continue cycles.GS8640Z18/36T-xxxVGS8640Z18/36T-xxxVDeselectNew ReadNew WriteBurst ReadBurst WriteWRBRBWDDBBWRD BWRDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B and D represent input commandcodes ,as indicated in the Synchronous Truth Table.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipeline and Flow Through Read/Write Control State DiagramWRPipeline and Flow Through Read Write Control State DiagramGS8640Z18/36T-xxxVIntermediateIntermediateIntermediateIntermediateIntermediateIntermediateHigh Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)TransitionƒInput Command CodeKeyTransitionIntermediate State (N+1)Notes:1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B, and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateIntermediate ƒn n+1n+2n+3ƒƒƒCurrent State and Next State Definition for Pipeline Mode Data I/O State DiagramNext StateStatePipeline Mode Data I/O State DiagramGS8640Z18/36T-xxxVHigh Z (Data In)Data Out (Q Valid)High Z B W B R B DRW RWDDCurrent State (n)Next State (n+1)TransitionƒInput Command CodeKeyNotes1. The Hold command (CKE Low) is notshown because it prevents any state change.2. W, R, B and D represent input command codes as indicated in the Truth Tables.Clock (CK)CommandCurrent StateNext Stateƒnn+1n+2n+3ƒƒƒCurrent State and Next State Definition for: Pipeline and Flow Through Read Write Control State DiagramFlow Through Mode Data I/O State DiagramGS8640Z18/36T-xxxVBurst CyclesAlthough NBT RAMs are designed to sustain 100% bus bandwidth by eliminating turnaround cycle when there is transition from read to write, multiple back-to-back reads or writes may also be performed. NBT SRAMs provide an on-chip burst address generator that can be utilized, if desired, to further simplify burst read or write implementations. The ADV control pin, when driven high, commands the SRAM to advance the internal address counter and use the counter generated address to read or write the SRAM. The starting address for the first cycle in a burst cycle series is loaded into the SRAM by driving the ADV pin low, into Load mode.Burst OrderThe burst address counter wraps around to its initial state after four addresses (the loaded address and three more) have beenaccessed. The burst sequence is determined by the state of the Linear Burst Order pin (LBO). When this pin is low, a linear burst sequence is selected. When the RAM is installed with the LBO pin tied high, Interleaved burst sequence is selected. See the tables below for details.Mode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down ControlZZL or NC Active HStandby, I DD = I SBNote:There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table.Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS8640Z18/36T-xxxVSleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by it’s internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a high state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a deselect or read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZStKLtKHtKCCKZZDesigning for CompatibilityThe GSI NBT SRAMs offer users a configurable selection between Flow Through mode and Pipeline mode via the FT signal found on Pin 14. Not all vendors offer this option, however most mark Pin 14 as V DD or V DDQ on pipelined parts and V SS on flow through parts. GSI NBT SRAMs are fully compatible with these sockets.Absolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage on V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125oCGS8640Z18/36T-xxxVNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version)ParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD1 1.7 1.82.0V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 1.8 V V DDQ I/O Supply Voltage V DDQ1 1.7 1.8V DD V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.5V DDVNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS8640Z18/36T-xxxVV DDQ2 & V DDQ1 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low VoltageV IL–0.3—0.3*V DDV1Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceFigure 1Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS8640Z18/36T-xxxVDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA FT, ZZ Input Current I IN V DD ≥ V IN ≥ 0 V –100 uA 100 uA Output Leakage CurrentI OLOutput Disable, V OUT = 0 to V DD–1 uA1 uADC Output Characteristics (1.8 V/2.5 V Version)ParameterSymbolTest ConditionsMinMax1.8 V Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V —2.5 V Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V1.7 V —1.8 V Output Low Voltage V OL1I OL = 4 mA —0.4 V2.5 V Output Low VoltageV OL2I OL = 8 mA—0.4 VOperating CurrentsParameterTest ConditionsModeSymbol-250-200-167Unit0to 70°C –40 to 85°C 0to 70°C –40to 85°C 0 to 70°C –40to 85°C Operating CurrentDevice Selected; All other inputs ≥V IH o r ≤ V IL Output open(x32/x36)Pipeline I DD I DDQ 360503805031040330402703529035mA Flow Through I DD I DDQ 255252752523020250202202024020mA (x18)PipelineI DD I DDQ 315253352527020290202402026020mA Flow Through I DD I DDQ 230152501520515225151951521515mA Standby Current ZZ ≥ V DD – 0.2 V —PipelineI SB 100120100120100120mA Flow Through I SB 100120100120100120mA Deselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—Pipeline I DD 140155130146125140mA Flow ThroughI DD125140120135120135mAGS8640Z18/36T-xxxVNotes:1.I DD and I DDQ apply to any combination of V DD and V DDQ operation.2.All parameters listed are worst case scenario.AC Electrical CharacteristicsParameter Symbol -250-200-167Unit Min Max Min Max Min Max PipelineClock Cycle Time tKC 4.0— 5.0— 6.0—ns Clock to Output ValidtKQ — 3.0— 3.0— 3.5ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5—ns Setup time tS 1.5— 1.5— 1.5—ns Hold time tH 0.2—0.4—0.5—ns Flow ThroughClock Cycle Time tKC 6.5—7.5—8.0—ns Clock to Output ValidtKQ — 6.5—7.5—8.0ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3—ns Clock LOW Time tKL 1.7— 1.7— 1.7—ns Clock to Output inHigh-Z tHZ 1 1.5 2.5 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.5— 3.0— 3.5ns G to output in Low-Z tOLZ 10—0—0—ns G to output in High-Z tOHZ 1— 2.5— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—ns ZZ hold time tZZH 21—1—1—ns ZZ recoverytZZR20—20—20—nsGS8640Z18/36T-xxxVNotes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS8640Z18/36T-xxxVPipeline Mode Timing (NBT)Begin Read A Cont Cont Deselect Write B Read C Read C+1Read C+2Read C+3ContDeselecttHZtKQX tKQtLZtHtStOHZtOEtHtStHtStHtStHtStHtStStHtStHtStHtSBurst ReadtKCtKL tKH Single Write Single ReadQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCDeselected with E1E1 masks ADSPE2 and E3 only sampled with ADSP and ADSCADSC initiated readCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8640Z18/36T-xxxVFlow Through Mode Timing (NBT)Begin Read A ContCont Write B Read C Read C+1Read C+2Read C+3Read C Cont DeselecttHZtKQXtKQ tLZtH tStOHZtOEtHtS tHtS tHtStHtS tHtS tHtStHtS tHtS tH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSCADSC initiated readDeselected with E1Fixed HighCK ADSPADSCADVA0–AnGWBWBa–BdE1E2E3GDQa–DQdGS8640Z18/36T-xxxVTQFP Package Drawing (Package T) D1D E1EPin 1be cLL1A2A1YθNotes:1.All dimensions are in millimeters (mm).2.Package width and length do not include mold protrusion.SymbolDescriptionMin.Nom.MaxA1Standoff 0.050.100.15A2Body Thickness 1.35 1.40 1.45b Lead Width 0.200.300.40c Lead Thickness 0.09—0.20D Terminal Dimension 21.922.022.1D1Package Body 19.920.020.1E Terminal Dimension 15.916.016.1E1Package Body 13.914.014.1e Lead Pitch —0.65—L Foot Length 0.450.600.75L1Lead Length —1.00—Y Coplanarity 0.10θLead Angle0°—7°Ordering Information —GSI NBT Synchronous SRAMOrgPart Number1TypeVoltage OptionPackageSpeed 2(MHz/ns)T A 3Status 44M x 18GS8640Z18T-250V NBT 1.8 V or 2.5 V TQFP 250/6.5C PQ 4M x 18GS8640Z18T-200V NBT 1.8 V or 2.5 V TQFP 200/7.5C PQ 4M x 18GS8640Z18T-167V NBT 1.8 V or 2.5 V TQFP 167/8C PQ 2M x 36GS8640Z36T-250V NBT 1.8 V or 2.5 V TQFP 250/6.5C PQ 2M x 36GS8640Z36T-200V NBT 1.8 V or 2.5 V TQFP 200/7.5C PQ 2M x 36GS8640Z36T-167V NBT 1.8 V or 2.5 V TQFP 167/8C PQ 4M x 18GS8640Z18T-250IV NBT 1.8 V or 2.5 V TQFP 250/6.5I PQ 4M x 18GS8640Z18T-200IV NBT 1.8 V or 2.5 V TQFP 200/7.5I PQ 4M x 18GS8640Z18T-167IV NBT 1.8 V or 2.5 V TQFP 167/8I PQ 2M x 36GS8640Z36T-250IV NBT 1.8 V or 2.5 V TQFP 250/6.5I PQ 2M x 36GS8640Z36T-200IV NBT 1.8 V or 2.5 V TQFP 200/7.5I PQ 2M x 36GS8640Z36T-167IV NBT 1.8 V or 2.5 V TQFP167/8I PQ 4M x 18GS8640Z18GT-250V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5C PQ 4M x 18GS8640Z18GT-200V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5C PQ 4M x 18GS8640Z18GT-167V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 167/8C PQ 2M x 36GS8640Z36GT-250V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5C PQ 2M x 36GS8640Z36GT-200V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5C PQ 2M x 36GS8640Z36GT-167V NBT 1.8 V or 2.5 V RoHS-compliant TQFP 167/8C PQ 4M x 18GS8640Z18GT-250IV NBT 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5I PQ 4M x 18GS8640Z18GT-200IV NBT 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5I PQ 4M x 18GS8640Z18GT-167IV NBT 1.8 V or 2.5 V RoHS-compliant TQFP 167/8I PQ 2M x 36GS8640Z36GT-250IV NBT 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5I PQ 2M x 36GS8640Z36GT-200IV NBT 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5I PQ 2M x 36GS8640Z36GT-167IVNBT1.8 V or2.5 VRoHS-compliant TQFP167/8IPQNotes:1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640Z36T-167IVT.2.The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Eachdevice is Pipeline/Flow Through mode-selectable by the user.3.T A = C = Commercial Temperature Range. T A = I = Industrial Temperature Range.4.PQ = Pre-Qualification.5.GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which arecovered in this data sheet. See the GSI Technology web site () for a complete listing of current offeringsGS8640Z18/36T-xxxV。

CB 640 冷却系统产品说明书

Ref. 1 - Foamed Cabinet Assy Version 1
Kind of Cube
Code
18 g. (Standard) 33 g. 13 g.
C11009/E C11009/E C11009/ED
Ref. 1 - Foamed Cabinet Assy Version 2
Condensation
See Table
14 Hot Gas Valve Body
Code 10213 10014 10448 10039
14089
14007 14005 14006
20410
Parts for Air Cooled Version Only
8
RReiff..
DesScpriazrioenDeeRsiccarimpbtiioon
220/240V 50 Hz 220/230V 60 Hz 110/115V 60 Hz
23010 23010 23261
23010 23781 23758
23781 23781 23758
Ref. 1 - Pump Tension
Version 1 Version 2
220/240V 50 Hz 220/230V 60 Hz 110/115V 60 Hz
See Table See Table
Current Version Till s/n. 62739 Till s/n. 227891
Version 2 Version 2 Version 2 Version 2 Version 1 Version 1
Code
C22059
D20002 10012 10305 10133 20233 10471 13006 10034 13007 10096 13109 13017 10472 10009 13005 20005 10405 13140 10404 13143 13015 13016 20009

INTELDX2资料

© INTEL CORPORATION, 1997December 1997Order Number: 272770-002Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.Intel may make changes to specifications and product descriptions at any time, without notice.Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.The Embedded IntelDX2™ processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request.Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at . Copyright © Intel Corporation, 1997*Third-party brands and names are the property of their respective owners.ContentsiiiContentsivEmbedded IntelDX2™ Processor1Embedded IntelDX2™ Processor2Embedded IntelDX2™ Processor3Embedded IntelDX2™ Processor 4Embedded IntelDX2™ Processor5Embedded IntelDX2™ Processor 6。

OLED12864参数数据（DOC）

OLED12864参数数据（DOC）⼆、模块引脚说明三、液晶硬件接⼝1、逻辑⼯作电压(VDD)：4.5～5.5V2、电源地(GND)：0V3、⼯作温度(Ta)：0～60℃(常温) / -20～75℃（宽温）4、电⽓特性见附图1 外部连接图（参考附图2）模块有并⾏和串⾏两种连接⽅法（时序如下）： 1、8位并⾏连接时序图MPU 写资料到模块RSR /WED B 0-MPU 从模块读出资料R SR/WED B0-2、串⾏连接时序图四、⽤户指令集指令表—2：（RE=1：扩充指令集）HS12864-12串⼝接线⽅式：备注：1、当模块在接受指令前，微处理顺必须先确认模块内部处于⾮忙碌状态，即读取BF标志时BF需为0，⽅可接受新的指令；如果在送出⼀个指令前并不检查BF标志，那么在前⼀个指令和这个指令中间必须延迟⼀段较长的时间，即是等待前⼀个指令确实执⾏完成，指令执⾏的时间请参考指令表中的个别指令说明。

2“RE”为基本指令集与扩充指令集的选择控制位元，当变更“RE”位元后，往后的指令集将维持在最后的状态，除⾮再次变更“RE”位元，否则使⽤相同指令集时，不需每次重设“RE”位元。

具体指令介绍：1、清除显⽰CODE：功能：清除显⽰屏幕，把DDRAM位址计数器调整为“00H”2、位址归位CODE：功能：把DDRAM位址计数器调整为“00H”，游标回原点，该功能不影响显⽰DDRAM3、位址归位CODE：功能：把DDRAM位址计数器调整为“00H”，游标回原点，该功能不影响显⽰DDRAM功能：执⾏该命令后，所设置的⾏将显⽰在屏幕的第⼀⾏。

显⽰起始⾏是由Z地址计数器控制的，该命令⾃动将A0-A5位地址送⼊Z地址计数器，起始地址可以是0-63范围内任意⼀⾏。

Z地址计数器具有循环计数功能，⽤于显⽰⾏扫描同步，当扫描完⼀⾏后⾃动加⼀。

4、显⽰状态开/关功能：D=1；整体显⽰ON C=1；游标ON B=1；游标位置ON5、游标或显⽰移位控制CODE：功能：设定游标的移动与显⽰的移位控制位：这个指令并不改变DDRAM的内容6、功能设定CODE：功能：DL=1（必须设为1）RE=1；扩充指令集动作RE=0：基本指令集动作7、设定CGRAM位址CODE：功能：设定CGRAM位址到位址计数器（AC）8、设定DDRAM位址CODE：功能：设定DDRAM位址到位址计数器（AC）9、读取忙碌状态（BF）和位址CODE：功能：读取忙碌状态（BF）可以确认内部动作是否完成，同时可以读出位址计数器（AC）的值10、写资料到RAMCODE：功能：写⼊资料到内部的RAM（DDRAM/CGRAM/TRAM/GDRAM）11、读出RAM的值CODE：功能：从内部RAM读取资料（DDRAM/CGRAM/TRAM/GDRAM）12、待命模式（12H）功能：进⼊待命模式，执⾏其他命令都可终⽌待命模式13、卷动位址或IRAM位址选择（13H）CODE：功能：SR=1；允许输⼊卷动位址SR=0；允许输⼊IRAM位址14、反⽩选择（14H）CODE：功能：选择4⾏中的任⼀⾏作反⽩显⽰，并可决定反⽩的与否15、睡眠模式（015H）CODE：功能：SL=1；脱离睡眠模式SL=0；进⼊睡眠模式16、扩充功能设定（016H）CODE：功能：RE=1；扩充指令集动作RE=0；基本指令集动作G=1；绘图显⽰ON G=0；绘图显⽰OFF 17、设定IRAM位址或卷动位址（017H）CODE：功能：SR=1；AC5~AC0为垂直卷动位址SR=0；AC3~AC0写ICONRAM位址18、设定绘图RAM位址（018H）CODE：功能：设定GDRAM位址到位址计数器（AC）五、显⽰坐标关系1、图形显⽰坐标代码（02H---7FH）六、显⽰步骤1、显⽰资料RAM（DDRAM）显⽰资料RAM提供64×2个位元组的空间，最多可以控制4⾏16字（64个字）的中⽂字型显⽰，当写⼊显⽰资料RAM时，可以分别显⽰CGROM、HCGROM与CGRAM的字型；ST7920A可以显⽰三种字型，分别是半宽的HCGROM字型、CGRAM字型及中⽂CGROM字型，三种字型的选择，由在DDRAM中写⼊的编码选择，在0000H—0006H的编码中将⾃动的结合下⼀个位元组，组成两个位元组的编码达成中⽂字型的编码（A140—D75F），各种字型详细编码如下：1、显⽰半宽字型：将8位元资料写⼊DDRAM中，范围为02H—7FH的编码。

ncep资料介绍

美国国家环境预报中心（NCEP）和国家大气研究中心（NCAR）联合执行的全球大气40年资料再分析计划通过CDC（Climate Dianogistic Center）利用磁带的形式向外发行。

南京大气资料服务中心通过NCEP朱跃建获得了磁带形式的40年再分析逐日资料。

现在把资料的基本情况作一简单的介绍。

1资料分类该资料集分：等压面资料、地面资料、通量资料1．1等压面资料资料格距：2.50 * 2.50的经纬网格网格点数：144* 73个格点资料范围：900N～900S，O0E～357.50E等压面层：共17层（hPa），1000，925，850，700，600，500，400，300，250，200，150，100，70，50，30，20，10资料文件：文件名由变量名的缩写和年份组成，如：air.83，表示1983年各等压面温度。

资料内容:各资料的说明见表1资料存放方式：每一个要素一年为一个数据文件；在文件中，先存放第1天第1层（l000）的值、…、第17层（10）的值；第2天第1～17层的值、…、该年最后一天第1～17层的值。

1．2地面资料资料格距：2．50 *2．50的经纬网格网格点数：144 *73个格点资料范围：900N～900S,00 E～357.50E资料层：地面或近地层（0．995层）表1等压面资料说明变量名缩写物理量单位air温度0.1Khgt位势高度m rhum相对湿度% shum比湿0.00001 kg/kgomega垂直速度0.001 Pa/suwnd纬向风速0.1m/svwnd经向风速0.1m/s资料文件：文件名由变量名的缩写、层和年份组成，如：air．Sig995.83，表示1983年地面温度。

资料内容：各资料的说明见表2资料存放方式：每一个要素一年为一个数据文件；在文件中，先存放第1天的值、第2天的值、…、该年最后一天的值。

表2地面资料说明变量名缩写和层物理量单位air．sig995温度0.1Klftx.sfc地面抬升指数0.1Klftx4.sfc最佳（4层）地面抬升指数0.1K omega.sig995垂直速度0.001Pa/spottmp.sig995位温0.1Kpr-wtr．eatm可降水量（整层气柱）0.1kg/m2 pres.sfc地面气压10Parhum.sig995相对湿度%slp海平面气压10Pauwnd．Sig995纬向风速0.1m/svwnd.sig995经向风速0.1m/shgt.sfc地形高度mland海陆分布1．3通量资料资料网格：T62高斯格点，192 *94个格点资料范围：88.5420N～88.5420S，00E～358.1250E资料文件：文件名由变量名的缩写和年份组成，如：pres．hcb．83，表示1983年高云底的气压。

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GS8640E18/32/36T-xxxV4M x 18, 2M x 32, 2M x 3672Mb Sync Burst SRAMs 250 MHz –167 MHz 1.8 V or 2.5 V V DD 1.8 V or 2.5 V I/O100-Pin TQFP Commercial Temp Industrial Temp Features• FT pin for user-configurable flow through or pipeline operation• Dual Cycle Deselect (DCD) operation • 1.8 V or 2.5 V core power supply • 1.8 V or 2.5 V I/O supply• LBO pin for Linear or Interleaved Burst mode• Internal input resistors on mode pins allow floating mode pins • Default to Interleaved Pipeline mode• Byte Write (BW) and/or Global Write (GW) operation • Internal self-timed write cycle• Automatic power-down for portable applications • JEDEC-standard 100-lead TQFP package• RoHS-compliant 100-lead TQFP package availableFunctional DescriptionApplicationsThe GS8640E18/32/36T-xxxV is a 75,497,472-bit high performance synchronous SRAM with a 2-bit burst address counter. Although of a type originally developed for Level 2 Cache applications supporting high performance CPUs, the device now finds application in synchronous SRAMapplications, ranging from DSP main store to networking chip set support.ControlsAddresses, data I/Os, chip enables (E1, E2, E3), address burst control inputs (ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are synchronous and are controlled by a positive-edge-triggered clock input (CK). Output enable (G) and power down control (ZZ) are asynchronous inputs. Burst cycles can be initiated with either ADSP or ADSC inputs. In Burst mode, subsequent burst addresses are generated internally and are controlled by ADV. The burst address counter may be configured to count in either linear orinterleave order with the Linear Burst Order (LBO) input. The Burst function need not be used. New addresses can be loaded on every cycle with no degradation of chip performance.Flow Through/Pipeline ReadsThe function of the Data Output register can be controlled by the user via the FT mode pin (Pin 14). Holding the FT mode pin low places the RAM in Flow Through mode, causing output data to bypass the Data Output Register. Holding FT high places the RAM in Pipeline mode, activating the rising-edge-triggered Data Output Register.DCD Pipelined ReadsThe GS8640E18/32/36T-xxxV is a DCD (Dual CycleDeselect) pipelined synchronous SRAM. SCD (Single Cycle Deselect) versions are also available. DCD SRAMs pipeline disable commands to the same degree as read commands. DCD RAMs hold the deselect command for one full cycle and then begin turning off their outputs just after the second rising edge of clock.Byte Write and Global WriteByte write operation is performed by using Byte Write enable (BW) input combined with one or more individual byte write signals (Bx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the Byte Write control inputs.Sleep ModeLow power (Sleep mode) is attained through the assertion (High) of the ZZ signal, or by stopping the clock (CK). Memory data is retained during Sleep mode.Core and Interface VoltagesThe GS8640E18/32/36T-xxxV operates on a 1.8 V or 2.5 V power supply. All inputs are 1.8 V or 2.5 V compatible. Separate output power (V DDQ ) pins are used to decouple output noise from the internal circuits and are 1.8 V or 2.5 V compatible.Parameter Synopsis-250-200-167UnitPipeline 3-1-1-1t KQ tCycle 3.04.0 3.05.0 3.56.0ns ns Curr (x32/x36)410350305mA Flow Through 2-1-1-1t KQ tCycle 6.56.57.57.58.08.0ns ns Curr (x18)Curr (x32/x36)245280220250210240mA mA807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V DD NC V SS DQ B DQ B V DDQ V SS DQ B DQ B DQP BV SS V DDQ V DDQ V SS DQ A DQ A V SS V DDQ DQ A DQ A V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0A A V S SV D DA A A A A A A AA A E 1E 2 N C N C B BB AE 3C K G W B W VD DV S SG A D S C A D S P A D V A AA 4M x 18Top View DQP A A NC NC NC NC NC NC NC NCNC NC NC NC NC NC NCNC NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950FT GS8640E18/32/36T-xxxVGS8640E18T-xxxV 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C V SS V DDQ DQ C DQ C V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0A A V S SV D DA A A A A A A AA A E 1E 2 B DB CB BB AE 3C K G W B W VD DV S SG A D S C A D S P A D V A AA 2M x 32Top View DQB NC DQ B DQ B DQ B DQ A DQ A DQ A DQ A NCDQ C DQ C DQ C DQ D DQ D DQ D NCDQ C NC 100999897969594939291908988878685848382813132333435363738394041424344454647484950FT GS8640E18/32/36T-xxxVGS8640E32T-xxxV 100-Pin TQFP Pinout (Package T)807978777675747372717069686766656463626160595857565554535251123456789101112131415161718192021222324252627282930V DDQ V SS DQ C DQ C3V SS V DDQ DQ C DQ C V DD NC V SS DQ D DQ D V DDQ V SS DQ D DQ D DQ D V SS V DDQ V DDQ V SS DQ B DQ B V SS V DDQ DQ B DQ B V SS NC V DD ZZ DQ A DQ A V DDQ V SS DQ A DQ A V SS V DDQ L B O A A A A A 1A 0A A V S SV D DA A A A A A A AA A E 1E 2 B DB CB BB AE 3C K G W B W VD DV S SG A D S C A D S P A D V A AA 2M x 36Top View DQB DQP B DQ B DQ B DQ B DQ A DQ A DQ A DQ A DQP ADQ C DQ C DQ C DQ D DQ D DQ D DQP DDQ C DQP C 100999897969594939291908988878685848382813132333435363738394041424344454647484950FT GS8640E18/32/36T-xxxVGS8640E36-xxxV 100-Pin TQFP Pinout (Package T)TQFP Pin DescriptionSymbolTypeDescriptionA 0, A 1I Address field LSBs and Address Counter preset InputsA IAddress InputsDQ A DQ B DQ C DQ D I/O Data Input and Output pinsNC No ConnectBW I Byte Write —Writes all enabled bytes; active low B A , B B I Byte Write Enable for DQ A , DQ B Data I/Os; active low B C , B D I Byte Write Enable for DQ C , DQ D Data I/Os; active lowCK I Clock Input Signal; active highGW I Global Write Enable —Writes all bytes; active lowE 1, E 3I Chip Enable; active low E 2I Chip Enable; active high G I Output Enable; active lowADV I Burst address counter advance enable; active low ADSP, ADSCI Address Strobe (Processor, Cache Controller); active lowZZ I Sleep Mode control; active high FT I Flow Through or Pipeline mode; active low LBO I Linear Burst Order mode; active lowV DD I Core power supply V SS I I/O and Core Ground V DDQIOutput driver power supplyGS8640E18/32/36T-xxxVGS8640E18/32/36T-xxxVA1A0A0A1D0D1Q1Q0Counter LoadD QDQRegisterRegisterDQRegisterDQRegisterDQRegisterD QRegisterD QRegisterD QRegisterDQR e g i s t e rDQRegisterA0–AnLBO ADV CK ADSC ADSP GW BW E 1GZZPower Down ControlMemory Array36364AQDE 2E 3DQx1–DQx9Note: Only x36 version shown for simplicity.DCD=1B AB BB CB DFT GS8640E18/32/36-xxxV Block DiagramMode Pin FunctionsMode NamePin NameStateFunctionBurst Order Control LBO L Linear Burst H Interleaved Burst Output Register Control FT L Flow Through H or NC Pipeline Power Down ControlZZL or NC Active HStandby, I DD = I SBGS8640E18/32/36T-xxxVNote:There is a pull-up device on the FT pin and a pull-down device on the ZZ pin, so this input pin can be unconnected and the chip will operate in the default states as specified in the above table.Note:The burst counter wraps to initial state on the 5th clock.Note:The burst counter wraps to initial state on the 5th clock.Linear Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 011011003rd address 101100014th address11000110Interleaved Burst SequenceA[1:0]A[1:0]A[1:0]A[1:0]1st address 000110112nd address 010011103rd address 101100014th address11100100Burst Counter SequencesBPR 1999.05.18GS8640E18/32/36T-xxxVByte Write Truth TableFunctionGWBWB AB BB CB DNotesRead H H X X X X 1Read H L H H H H 1Write byte a H L L H H H 2, 3Write byte b H L H L H H 2, 3Write byte c H L H H L H 2, 3, 4Write byte d H L H H H L 2, 3, 4Write all bytesHLLLLL2, 3, 4Write all bytes L X X X X X1.All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs.2.Byte Write Enable inputs B A , B B , B C and/or B D may be used in any combination with BW to write single or multiple bytes.3.All byte I/Os remain High-Z during all write operations regardless of the state of Byte Write Enable inputs.4.Bytes “C ” and “D ” are only available on the x32 and x36 versions.Synchronous Truth TableOperationAddress UsedState Diagram Key 5E 1E 2ADSP ADSCADVW 3DQ 4Deselect Cycle, Power Down None X H X X L X X High-Z Deselect Cycle, Power Down None X L F L X X X High-Z Deselect Cycle, Power Down None X L F H L X X High-Z Read Cycle, Begin Burst External R L T L X X X Q Read Cycle, Begin Burst External R L T H L X F Q Write Cycle, Begin Burst External W L T H L X T D Read Cycle, Continue Burst Next CR X X H H L F Q Read Cycle, Continue Burst Next CR H X X H L F Q Write Cycle, Continue Burst Next CW X X H H L T D Write Cycle, Continue Burst Next CWH X X H L T D Read Cycle, Suspend Burst Current X X H H H F Q Read Cycle, Suspend Burst Current H X X H H F Q Write Cycle, Suspend Burst Current X X H H H T D Write Cycle, Suspend BurstCurrentHXXHHTDNotes:1.X = Don’t Care, H = High, L = Low2. E = T (True) if E 2 = 1 and E 3 = 0; E = F (False) if E 2 = 0 or E 3 = 13.W = T (True) and F (False) is defined in the Byte Write Truth Table preceding.4.G is an asynchronous input. G can be driven high at any time to disable active output drivers. G low can only enable active drivers (shownas “Q” in the Truth Table above).5.All input combinations shown above are tested and supported. Input combinations shown in gray boxes need not be used to accomplishbasic synchronous or synchronous burst operations and may be avoided for simplicity.6.Tying ADSP high and ADSC low allows simple non-burst synchronous operations. See BOLD items above.7.Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above.GS8640E18/32/36T-xxxVFirst WriteFirst ReadBurst WriteBurst ReadDeselect R WCRCWXXWRRWRXXX S i m p l e S y n c h r o n o u s O p e r a t i o nS i m p l e B u r s t S y n c h r o n o u s O p e r a t i o nCR RCWCRCRNotes:1.The diagram shows only supported (tested) synchronous state transitions. The diagram presumes G is tied low.2.The upper portion of the diagram assumes active use of only the Enable (E1) and Write (B A , B B , B C , B D , BW, and GW) control inputs, andthat ADSP is tied high and ADSC is tied low.3.The upper and lower portions of the diagram together assume active use of only the Enable, Write, and ADSC control inputs, andassumes ADSP is tied high and ADV is tied low.GS8640E18/32/36T-xxxVSimplified State DiagramFirst WriteFirst ReadBurst WriteBurst ReadDeselectR WCRCWXXWRRWRXXX CRR CW CRCRW CWW CWNotes:1.The diagram shows supported (tested) synchronous state transitions plus supported transitions that depend upon the use of G.e of “Dummy Reads” (Read Cycles with G High) may be used to make the transition from Read cycles to Write cycles without passingthrough a Deselect cycle. Dummy Read cycles increment the address counter just like normal read cycles.3.Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meetData Input Set Up Time.GS8640E18/32/36T-xxxVSimplified State Diagram with GGS8640E18/32/36T-xxxVAbsolute Maximum Ratings(All voltages reference to V SS )SymbolDescriptionValueUnitV DD Voltage on V DD Pins –0.5 to 4.6V V DDQ Voltage on V DDQ Pins –0.5 to V DDV V I/O Voltage on I/O Pins –0.5 to V DDQ +0.5 (≤ 4.6 V max.)V V IN Voltage on Other Input Pins –0.5 to V DD +0.5 (≤ 4.6 V max.)V I IN Input Current on Any Pin +/–20mA I OUT Output Current on Any I/O Pin +/–20mA P D Package Power Dissipation 1.5WT STG Storage Temperature –55 to 125o C T BIASTemperature Under Bias–55 to 125o CNote:Permanent damage to the device may occur if the Absolute Maximum Ratings are exceeded. Operation should be restricted to Recommended Operating Conditions. Exposure to conditions exceeding the Absolute Maximum Ratings, for an extended period of time, may affect reliability of this component. Power Supply Voltage Ranges (1.8 V/2.5 V Version)ParameterSymbolMin.Typ.Max.UnitNotes1.8 V Supply Voltage V DD1 1.7 1.82.0V 2.5 V Supply Voltage V DD2 2.3 2.5 2.7V 1.8 V V DDQ I/O Supply Voltage V DDQ1 1.7 1.8V DD V 2.5 V V DDQ I/O Supply VoltageV DDQ22.32.5V DDVNotes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.GS8640E18/32/36T-xxxVV DDQ2 & V DDQ1 Range Logic LevelsParameterSymbolMin.Typ.Max.UnitNotesV DD Input High Voltage V IH 0.6*V DD —V DD + 0.3V 1V DD Input Low VoltageV IL–0.3—0.3*V DDV1Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.Recommended Operating TemperaturesParameterSymbolMin.Typ.Max.UnitNotesAmbient Temperature (Commercial Range Versions)T A 02570°C 2Ambient Temperature (Industrial Range Versions)T A–402585°C2Notes:1.The part numbers of Industrial Temperature Range versions end the character “I”. Unless otherwise noted, all performance specifica-tions quoted are evaluated for worst case in the temperature range marked on the device.2.Input Under/overshoot voltage must be –2 V > Vi < V DDn +2 V not to exceed 4.6 V maximum, with a pulse width not to exceed 20% tKC.20% tKCV SS – 2.0 V50%V SS V IHUndershoot Measurement and TimingOvershoot Measurement and Timing20% tKCV DD + 2.0 V50%V DDV ILCapacitanceo C, f = 1 MH Z , V DD ParameterSymbolTest conditionsTyp.Max.UnitInput Capacitance C IN V IN = 0 V 45pF Input/Output Capacitance C I/OV OUT = 0 V67pFNote:These parameters are sample tested.(T A = 25= 2.5 V)AC Test ConditionsParameterConditionsDQV DDQ/250Ω30pF *Output Load 1* Distributed Test Jig CapacitanceFigure 1Input high level V DD – 0.2 V Input low level 0.2 V Input slew rate 1 V/ns Input reference level V DD /2Output reference levelV DDQ /2Output loadFig. 11.Include scope and jig capacitance.2.Test conditions as specified with output loading as shown in Fig. 1unless otherwise noted.3.Device is deselected as defined by the Truth Table. GS8640E18/32/36T-xxxVDC Electrical CharacteristicsParameterSymbolTest ConditionsMinMaxInput Leakage Current (except mode pins)I IL V IN = 0 to V DD –1 uA 1 uA FT, ZZ Input Current I IN V DD ≥ V IN ≥ 0 V –100 uA 100 uA Output Leakage CurrentI OLOutput Disable, V OUT = 0 to V DD–1 uA1 uADC Output Characteristics (1.8 V/2.5 V Version)ParameterSymbolTest ConditionsMinMax1.8 V Output High Voltage V OH1I OH = –4 mA, V DDQ = 1.6 V V DDQ – 0.4 V —2.5 V Output High Voltage V OH2I OH = –8 mA, V DDQ = 2.375 V1.7 V —1.8 V Output Low Voltage V OL1I OL = 4 mA —0.4 V2.5 V Output Low VoltageV OL2I OL = 8 mA—0.4 VOperating CurrentsParameterTest ConditionsModeSymbol-250-200-167Unit0to 70°C –40 to 85°C 0to 70°C –40to 85°C 0 to 70°C –40to 85°C Operating CurrentDevice Selected; All other inputs ≥V IH o r ≤ V IL Output open(x32/x36)Pipeline I DD I DDQ 360503805031040330402703529035mA Flow Through I DD I DDQ 255252752523020250202202024020mA (x18)PipelineI DD I DDQ 315253352527020290202402026020mA Flow Through I DD I DDQ 230152501520515225151951521515mA Standby Current ZZ ≥ V DD – 0.2 V —PipelineI SB 100120100120100120mA Flow Through I SB 100120100120100120mA Deselect CurrentDevice Deselected; All other inputs ≥ V IH or ≤ V IL—Pipeline I DD 140155130146125140mA Flow ThroughI DD125140120135120135mAGS8640E18/32/36T-xxxVNotes:1.I DD and I DDQ apply to any combination of V DD and V DDQ operation.2.All parameters listed are worst case scenario.AC Electrical CharacteristicsParameter Symbol -250-200-167Unit Min Max Min Max Min Max PipelineClock Cycle Time tKC 4.0— 5.0— 6.0—ns Clock to Output ValidtKQ — 3.0— 3.0— 3.5ns Clock to Output Invalid tKQX 1.5— 1.5— 1.5—ns Clock to Output in Low-ZtLZ 1 1.5— 1.5— 1.5—ns Setup time tS 1.5— 1.5— 1.5—ns Hold time tH 0.2—0.4—0.5—ns Flow ThroughClock Cycle Time tKC 6.5—7.5—8.0—ns Clock to Output ValidtKQ — 6.5—7.5—8.0ns Clock to Output Invalid tKQX 3.0— 3.0— 3.0—ns Clock to Output in Low-ZtLZ 1 3.0— 3.0— 3.0—ns Setup time tS 1.5— 1.5— 1.5—ns Hold time tH 0.5—0.5—0.5—ns Clock HIGH Time tKH 1.3— 1.3— 1.3—ns Clock LOW Time tKL 1.7— 1.7— 1.7—ns Clock to Output inHigh-Z tHZ 1 1.5 2.5 1.5 3.0 1.5 3.0ns G to Output Valid tOE — 2.5— 3.0— 3.5ns G to output in Low-Z tOLZ 10—0—0—ns G to output in High-Z tOHZ 1— 2.5— 3.0— 3.0ns ZZ setup time tZZS 25—5—5—ns ZZ hold time tZZH 21—1—1—ns ZZ recoverytZZR20—20—20—nsGS8640E18/32/36T-xxxVNotes:1.These parameters are sampled and are not 100% tested.2.ZZ is an asynchronous signal. However, in order to be recognized on any given clock cycle, ZZ must meet the specified setup and holdtimes as specified above.GS8640E18/32/36T-xxxVPipeline Mode Timing (DCD)Begin Read A Cont Deselect Deselect Write BRead C Read C+1Read C+2Read C+3Cont Deselect DeselecttHZtKQXtKQtLZtHtStOHZtOEtHtStHtStHtStH tStHtStStHtStHtStHtStKCtKL tKHQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)ABCHi-ZDeselected with E1E2 and E3 only sampled with ADSCADSC initiated readCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS8640E18/32/36T-xxxVFlow Through Mode Timing (DCD)Begin Read A ContDeselect Write B Read C Read C+1Read C+2Read C+3Read C DeselecttHZtKQX tLZtH tStOHZtOE tKQtHtS tHtS tHtStH tStHtS tHtStHtS tHtS tH tStH tS tHtS tKCtKL tKHABCQ(A)D(B)Q(C)Q(C+1)Q(C+2)Q(C+3)Q(C)E2 and E3 only sampled with ADSP and ADSCE1 masks ADSPADSC initiated readDeselected with E1E1 masks ADSPFixed HighCK ADSPADSCADVAo–AnGWBWBa–BdE1E2E3GDQa–DQdGS8640E18/32/36T-xxxVSleep ModeDuring normal operation, ZZ must be pulled low, either by the user or by its internal pull down resistor. When ZZ is pulled high, the SRAM will enter a Power Sleep mode after 2 cycles. At this time, internal state of the SRAM is preserved. When ZZ returns to low, the SRAM operates normally after 2 cycles of wake up time.Sleep mode is a low current, power-down mode in which the device is deselected and current is reduced to I SB 2. The duration of Sleep mode is dictated by the length of time the ZZ is in a High state. After entering Sleep mode, all inputs except ZZ become disabled and all outputs go to High-Z The ZZ pin is an asynchronous, active high input that causes the device to enter Sleep mode. When the ZZ pin is driven high, I SB 2 is guaranteed after the time tZZI is met. Because ZZ is an asynchronous input, pending operations or operations in progress may not be properly completed if ZZ is asserted. Therefore, Sleep mode must not be initiated until valid pending operations are completed. Similarly, when exiting Sleep mode during tZZR, only a Deselect or Read commands may be applied while the SRAM is recovering from Sleep mode.Sleep Mode Timing DiagramtZZRtZZHtZZSHoldSetup tKLtKHtKCCKADSP ADSCZZGS8640E18/32/36T-xxxVTQFP Package Drawing (Package T) D1D E1EPin 1be cLL1A2A1YθNotes:1.All dimensions are in millimeters (mm).2.Package width and length do not include mold protrusion.SymbolDescriptionMin.Nom.MaxA1Standoff 0.050.100.15A2Body Thickness 1.35 1.40 1.45b Lead Width 0.200.300.40c Lead Thickness 0.09—0.20D Terminal Dimension 21.922.022.1D1Package Body 19.920.020.1E Terminal Dimension 15.916.016.1E1Package Body 13.914.014.1e Lead Pitch —0.65—L Foot Length 0.450.600.75L1Lead Length —1.00—Y Coplanarity 0.10θLead Angle0°—7°GS8640E18/32/36T-xxxVOrdering Information for GSI Synchronous Burst RAMs OrgPart Number1TypeVoltage OptionPackageSpeed 2(MHz/ns)T A3Status 44M x 18GS8640E18T-250V DCD Synchronous Burst 1.8 V or 2.5 V TQFP 250/6.5C PQ 4M x 18GS8640E18T-200V DCD Synchronous Burst 1.8 V or 2.5 V TQFP 200/7.5C PQ 4M x 18GS8640E18T-167V DCD Synchronous Burst 1.8 V or 2.5 V TQFP 167/8C PQ 2M x 32GS8640E32T-250V DCD Synchronous Burst 1.8 V or 2.5 V TQFP 250/6.5C PQ 2M x 32GS8640E32T-200V DCD Synchronous Burst 1.8 V or 2.5 V TQFP 200/7.5C PQ 2M x 32GS8640E32T-167V DCD Synchronous Burst 1.8 V or 2.5 V TQFP 167/8C PQ 2M x 36GS8640E36T-250V DCD Synchronous Burst 1.8 V or 2.5 V TQFP 250/6.5C PQ 2M x 36GS8640E36T-200V DCD Synchronous Burst 1.8 V or 2.5 V TQFP 200/7.5C PQ 2M x 36GS8640E36T-167V DCD Synchronous Burst 1.8 V or 2.5 V TQFP 167/8C PQ 4M x 18GS8640E18T-250IV DCD Synchronous Burst 1.8 V or 2.5 V TQFP 250/6.5I PQ 4M x 18GS8640E18T-200IV DCD Synchronous Burst 1.8 V or 2.5 V TQFP 200/7.5I PQ 4M x 18GS8640E18T-167IV DCD Synchronous Burst 1.8 V or 2.5 V TQFP 167/8I PQ 2M x 32GS8640E32T-250IV DCD Synchronous Burst 1.8 V or 2.5 V TQFP 250/6.5I PQ 2M x 32GS8640E32T-200IV DCD Synchronous Burst 1.8 V or 2.5 V TQFP 200/7.5I PQ 2M x 32GS8640E32T-167IV DCD Synchronous Burst 1.8 V or 2.5 V TQFP 167/8I PQ 2M x 36GS8640E36T-250IV DCD Synchronous Burst 1.8 V or 2.5 V TQFP 250/6.5I PQ 2M x 36GS8640E36T-200IV DCD Synchronous Burst 1.8 V or 2.5 V TQFP 200/7.5I PQ 2M x 36GS8640E36T-167IV DCD Synchronous Burst 1.8 V or 2.5 V TQFP167/8I PQ 4M x 18GS8640E18GT-250V DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5C PQ 4M x 18GS8640E18GT-200V DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5C PQ 4M x 18GS8640E18GT-167V DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 167/8C PQ 2M x 32GS8640E32GT-250V DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5C PQ 2M x 32GS8640E32GT-200V DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5C PQ 2M x 32GS8640E32GT-167V DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 167/8C PQ 2M x 36GS8640E36GT-250V DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5C PQ 2M x 36GS8640E36GT-200V DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5C PQ 2M x 36GS8640E36GT-167V DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 167/8C PQ 4M x 18GS8640E18GT-250IVDCD Synchronous Burst1.8 V or2.5 VRoHS-compliant TQFP250/6.5IPQ4M x 18GS8640E18GT-200IV DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5I PQ Notes:1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640E18T-300IVT.2.The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Eachdevice is Pipeline/Flow Through mode-selectable by the user.3.T A = C = Commercial Temperature Range. T A = I = Industrial Temperature Range.4.PQ = Pre-Qualification.5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which arecovered in this data sheet. See the GSI Technology web site () for a complete listing of current offerings.GS8640E18/32/36T-xxxV4M x 18GS8640E18GT-167IV DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 167/8I PQ 2M x 32GS8640E32GT-250IV DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5I PQ 2M x 32GS8640E32GT-200IV DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 200/7.5I PQ 2M x 32GS8640E32GT-167IV DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 167/8I PQ 2M x 36GS8640E36GT-250IV DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 250/6.5I PQ 2M x 36GS8640E36GT-200IVDCD Synchronous Burst1.8 V or2.5 VRoHS-compliant TQFP200/7.5IPQ2M x 36GS8640E36GT-167IV DCD Synchronous Burst 1.8 V or 2.5 V RoHS-compliant TQFP 167/8I PQ Ordering Information for GSI Synchronous Burst RAMs (Continued)OrgPart Number1TypeVoltage OptionPackageSpeed 2(MHz/ns)T A3Status 4Notes:1.Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS8640E18T-300IVT.2.The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Eachdevice is Pipeline/Flow Through mode-selectable by the user.3.T A = C = Commercial Temperature Range. T A = I = Industrial Temperature Range.4.PQ = Pre-Qualification.5. GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which arecovered in this data sheet. See the GSI Technology web site () for a complete listing of current offerings.72Mb Sync SRAM Datasheet Revision HistoryDS/DateRev. Code: Old;NewTypes of Changes Format or ContentPage;Revisions;Reason8640EVxx_r1• Creation of new datasheet8640EVxx_r1; 8640Exx_V_r_01Content• Updated entire document to reflect new part nomenclature • Removed 300 MHz speed binGS8640E18/32/36T-xxxV。