24LC22A-ISN;24LC22AT-ISN;24LC22A-IP;中文规格书,Datasheet资料

24lc256系列中文

1.8-5.5V 400 kHz (2) 2.5-5.5V 400 kHz 1.8-5.5V 400 kHz(2) 2.5-5.5V 400 kHz 4.5V-5.5V 400 kHz
8 字节
16 字节 16 字节
整个阵列
整个阵列无
无
A0, A1, A2 A0, A1, A2
I I, E
I I C, I, E
装。
封装类型（1）
PDIP/SOIC
TSSOP/MSOP（2）
A0 1 A1 2 A2 3 VSS 4
8 VCC
A0 1
7 WP(3) A1 2
6 SCL
A2 3
5 SDA VSS 4
8 VCC
A0 A1
7 WP(3) NC NC
6 SCL NC
5
SDA
A2 VSS
TSSOP
1
14
2
13
3
12
4
11
1.8-5.5V 2.5-5.5V 1.8-5.5V
400 kHz (2)
400 kHz 1 MHz(3)
64 字节
整个阵列
A0, A1, A2(4)
I
P, SN, SM, ST, MS, MF,
I, E ST14
I
256 千位器件
24AA256
1.8-5.5V 400 kHz (2)
24LC256 24FC256
2005 Microchip Technology Inc.
DS21930A_CN 第 3 页
24AAXX/24LCXX/24FCXX
2.0 电气特性
绝对最大额定值 (†)
VCC.............................................................................................................................................................................6.5V 相对于 Vss 的所有输入和输出 ............................................................................................................ -0.6V 到 VCC +1.0V 存储温度 ................................................................................................................................................. -65°C 到 +150°C 环境温度（使用电源时）........................................................................................................................ -40°C 到 +125°C 所有引脚静电保护 ....................................................................................................................................................................≥ 4 kV

24LC32A-MT资料

•ISO 7816 compliant contact locations•Single supply with operation down to 2.5V -Maximum write current 3 mA at 6.0V -Maximum read current 150 µ A at 6.0V -Standby current 1 µ A max at 2.5V•T wo wire serial interface bus, I 2 C ™ compatible •100 kHz (2.5V) and 400 kHz (5V) compatibility •Self-timed ERASE and WRITE cycles •Power on/off data protection circuitry•1,000,000 ERASE/WRITE cycles guaranteed •32 byte page or byte write modes available •Schmitt trigger inputs for noise suppression•Output slope control to eliminate ground bounce • 2 ms typical write cycle time, byte or page •Electrostatic discharge protection > 4000V •Data retention > 200 years•8-pin PDIP and SOIC packages •T emperature ranges:DESCRIPTIONThe Microchip T echnology Inc. 24LC32A is a 4K x 8(32K bit) Serial Electrically Erasable PROM in an ISO micromodule for use in smart card applications. The device has a page-write capability of up to 32 bytes.-Commercial: 0˚C to +70˚C2元器件交易网24LC32A MODULE1.0ELECTRICAL CHARACTERISTICS1.1Maximum Ratings*V CC ........................................................................7.0V All inputs and outputs w.r.t. V SS ......-0.6V to VCC +1.0V Storage temperature ..........................-65˚C to +150˚C Ambient temp. with power applied......-65˚C to +125˚C Soldering temperature of leads (10 seconds)..+300˚C ESD protection on all pins .....................................≥ 4 kV*Notice: Stresses above those listed under “Maximum Ratings”may cause permanent damage to the device. This is a stress rat-ing only and functional operation of the device at those or anyother conditions above those indicated in the operational listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.TABLE 1-1:PIN FUNCTIONSName Function V SS Ground SDA Serial Data SCL Serial ClockV CC+2.5V to 6.0V Power SupplyTABLE 1-2:DC CHARACTERISTICSVcc = +2.5V to 6.0VCommercial (C):T amb = 0˚C to +70 ° CParameterSymbolMinTypMaxUnitsConditionsSCL and SDA pins:High level input voltage V IH .7 V CC —V Low level input voltage V IL —.3 Vcc V Hysteresis of Schmitt T rigger inputsV HYS .05 V CC—V Note 1Low level output voltage V OL —.40V I OL = 3.0 mA @ V CC = 4.5V I OL = 2.1 mA @ V CC = 2.5V Input leakage current I LI -1010 µ A V IN = .1V to V CC Output leakage current I LO -1010 µ A V OUT = .1V to V CC Pin capacitance (all inputs/outputs)C IN ,C OUT —10pF V CC = 5.0V (Note 1)T amb = 25˚C, f c = 1 MHz Operating current I CC Write —3mA V CC = 6.0VI CC Read —400 µ A V CC = 6.0V , SCL = 400Khz Standby currentI CCS —1 µ A5 µ A SCL = SDA = V CC = 5.0VI CCS1µ AVCC = 2.5V (Note 1)Note 1:This parameter is periodically sampled and not 100% tested.元器件交易网24LC32A MODULETABLE 1-3:AC CHARACTERISTICSParameterSymbolVcc = 2.5 - 6.0V STD. MODE Vcc = 4.5 - 6.0V FAST MODE UnitsRemarksMinMaxMinMaxClock frequency F CLK —100—400kHz Clock high time T HIGH 4000—600—ns Clock low timeT LOW 4700—1300—ns SDA and SCL rise time T R —1000—300ns Note 1SDA and SCL fall time T F —300—300ns Note 1START condition hold timeT HD : STA 4000—600—ns After this period the ﬁrst clock pulse is generatedST ART condition setup timeT SU : STA 4700—600—ns Only relevant for repeated ST ART conditionData input hold time T HD : DAT 0—0—ns Data input setup time T SU : DAT 250—100—ns STOP condition setup timeT SU : STO 4000—600—ns Output valid from clock T AA —3500—900ns Note 2Bus free timeT BUF 4700—1300—ns Time the bus must be free before a new transmission can start Output fall time from V IH min to V IL maxT OF —25020 +0.1C B 250ns Note 1, CB ≤ 100 pF Input ﬁlter spike sup-pression (SDA and SCL pins)T SP—50—50nsNote 3Write cycle timeTWR —5—5ms Byte or Page modeNote 1: Not 100% tested. CB = total capacitance of one bus line in pF .2: As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of ST ART or STOP conditions. 3: The combined T SP and VHYSspeciﬁcations are due to Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti speciﬁcation for standard operation.元器件交易网24LC32A MODULE2.0PIN DESCRIPTIONS2.1SDA (Serial Data)This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to V CC (typical 10K Ω for 100 kHz, 1K Ω for 400kHz)For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the ST ART and STOP condi-tions.2.2SCL (Serial Clock)This input is used to synchronize the data transfer from and to the device.3.0FUNCTIONAL DESCRIPTIONThe 24LC32A supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is deﬁned as transmitter, and a device receiving data as receiver. The bus must be con-trolled by a master device which generates the serial clock (SCL), controls the bus access, and generates the ST ART and STOP conditions, while the 24LC32A works as slave. Both master and slave can operate as transmitter or receiver but the master device deter-mines which mode is activated.元器件交易网24LC32A MODULE4.0BUS CHARACTERISTICSThe following bus protocol has been deﬁned:•Data transfer may be initiated only when the bus is not busy.•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a ST ART or STOP condition.Accordingly, the following bus conditions have been deﬁned (See Figure 4-1).4.1Bus not Busy (A)Both data and clock lines remain HIGH.4.2Start Data Transfer (B)A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a ST ART condition.All commands must be preceded by a START condi-tion.4.3Stop Data Transfer (C)A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.4.4Data Valid (D)The state of the data line represents valid data when,after a ST ART condition, the data line is stable for the duration of the HIGH period of the clock signal.The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a ST ART condition and terminated with a STOP condition. The number of the data bytes transferred between the ST ART and STOP conditions is determined by the master device.4.5AcknowledgeEach receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course,setup and hold times must be taken into account. Dur-ing reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24LC32A) will leave the data line HIGH to enable the master to generate the STOP condition.(See Figure 4-2)元器件交易网24LC32A MODULE5.0DEVICE ADDRESSINGA control byte is the ﬁrst byte received following the start condition from the master device. (See Figure 5-1) The control byte consists of a four bit control code;for the 24LC32A this is set as 1010 binary for read and write operations. The next three bits are device select bits on standard devices, however, for micromodules,these must be zeros. The last bit of the control byte deﬁnes the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. The next two bytesreceived deﬁne the address of the ﬁrst data byte (see Figure 5-2). Because only A11...A0 are used, the upper four address bits must be zeros. The most signif-icant bit of the most signiﬁcant byte of the address is transferred ﬁrst.Following the start condition, the 24LC32A monitors the SDA bus checking the device type identiﬁer being transmitted. Upon receiving a valid control byte, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24LC32A will select a read or write operation元器件交易网24LC32A MODULE6.0WRITE OPERATIONS6.1Byte WriteFollowing the start condition from the master, the con-trol code (four bits), the device select (three bits), and the R/W bit which is a logic low are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowl-edge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24LC32A MODULE. The next byte is the least signiﬁcant address byte. After receiving another acknowledge signal from the 24LC32A the master device will transmit the data word to be written into the addressed memory location.The 24LC32A acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24LC32A will not generate acknowledge signals (see Figure 6-1).6.2Page WriteThe write control byte, word address and the ﬁrst data byte are transmitted to the 24LC32A in the same way as in a byte write. But instead of generating a stop con-dition, the master transmits up to 32 bytes which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. After receipt of each word, the ﬁve lower address pointer bits are internally incremented by one.If the master should transmit more than 32 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received, an internal write cycle will begin. (see Figure 6-2).元器件交易网24LC32A MODULE7.0ACKNOWLEDGE POLLINGSince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com-mand has been issued from the master, the device ini-tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master send-ing a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for ﬂow diagram.FIGURE 7-1:ACKNOWLEDGE POLLING8.0READ OPERATIONRead operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read,and sequential read.8.1Current Address ReadThe 24LC32A contains an address counter that main-tains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n (n is any legal address), the next current address read oper-ation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24LC32A issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC32A discontinues transmission (see Figure 8-1).8.2Random ReadRandom read operations allow the master to access any memory location in a random manner. T o perform this type of read operation, ﬁrst the word address must be set. This is done by sending the word address to the 24LC32A as part of a write operation (R/W bit set to 0).After the word address is sent, the master generates a start condition following the acknowledge. This termi-nates the write operation, but not before the internal address pointer is set. Then the master issues the con-trol byte again but with the R/W bit set to a one. The 24LC32A will then issue an acknowledge and transmit the eight bit data word. The master will not acknowl-edge the transfer but does generate a stop condition which causes the 24LC32A to discontinue transmis-sion (see Figure 8-2).元器件交易网24LC32A MODULE8.3Sequential ReadSequential reads are initiated in the same way as a ran-dom read except that after the 24LC32A transmits the ﬁrst data byte, the master issues an acknowledge as opposed to the stop condition used in a random read.This acknowledge directs the 24LC32A to transmit the next sequentially addressed 8 bit word (see Figure 8-3). Following the ﬁnal byte transmitted to the master,the master will NOT generate an acknowledge but will generate a stop condition.To provide sequential reads the 24LC32A contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 0FFF to address 000 if the master acknowledges the byte received from the array address 0FFF .元器件交易网24LC32A MODULE9.0SHIPPING METHODThe micromodules will be shipped to customers in clear plastic trays. Each tray holds 150 modules, and the trays can be stacked in a manner similar to shipping die in wafﬂe packs. A tray drawing with dimensions is shown in Figure 9-1.元器件交易网24LC32A MODULE元器件交易网24LC32A MODULENOTES:元器件交易网24LC32A MODULENOTES:元器件交易网24LC32A MODULENOTES:元器件交易网24LC32A MODULE24LC32A MODULE PRODUCT IDENTIFICATION SYSTEMT o order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofﬁce.Sales and SupportData SheetsProducts supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:1.Y our local Microchip sales ofﬁce.2.The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.3.The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.元器件交易网MAll rights reserved. © 1997, Microchip T echnology Incorporated, USA. 9/97 Printed on recycled paper.元器件交易网。

FR24中文资料

25 50 75 100 125 150 175 ° Ambient Temperature (°C)
100 10 Number of Cycles @ 60 Hz
Typical Instantaneous Forward Characteristics 100 Forward Current (A)
FR20 . . . 210 Series Maximum Ratings Peak Repetitive Reverse Voltage...VRRM RMS Reverse Voltage...VR(rms) DC Blocking Voltage...VDC Average Forward Rectified Current...IF(av) TA = 55°C Non-Repetitive Peak Forward Surge Current...IFSM @ Rated Current & Temp Operating & Storage Temperature Range...TJ, TSTRG Electrical Characteristics Maximum Forward Voltage @ 2.0A...VF Maximum DC Reverse Current...IR @ Rated DC Blocking Voltage @ @ 25°C 100°C ............................................. 1.3 ............................................... FR20 50 35 50 FR21 100 70 100 FR22 200 140 200 FR24 400 280 400 FR26 600 420 600 FR28 800 560 800 FR210 1000 700 1000

TL244-2010中英互译

表面保护要求TL 244-2010 Previous issues以前的版本TL 244: 1987-10, 1992-05, 1993-11, 1995-12, 2002-05, 2004-12, 2006-08, 2007-02Changes 更改The following changes have been made compared with TL 244: 2007-02:– Scope supplemented by components ≤ 1 200 MPa with heat treatment– Ofl-r647 and Ofl-r648 added– Table of surface protection types containing Cr(VI) (formerly Table 2) removed– Figures 1 and 2 added– Test acc. to PV 1209, PV 1200, and PV 1210 added– Requirement for homogeneous structure added– Upper limit of nickel content changed– Notes on testing regarding layer thickness measurement (formerly Section 4) added in Section3.9– Requirements in Section 3.11 changed– Referenced standards updated– Standard restructured相对于TL244：2007-02版本，已作了如下更改：（1）补充了热处理后零件的抗拉强度≦1200Mpa部分；（2）添加了Ofl-r647和Ofl-r648两种涂覆方法；（3）原表2中关于含铬的表面保护类型已删除；（4）添加了图1和图2；（5）添加了PV 1209,PV 1200和PV1210三种测试依据；（6）镀层表面形态的要求有所增加；（7）镍的上限值有所改变；（8）原第4条关于镀层厚度的测量的内容加入到3.9部分；（9）原3.11部分的要求有所改变；（10）参考标准有更新；（11）标准重组。

24C02中文资料

24C02/24C04/24C08/24C16/24C32/24C641.2.2K4K 8K ，16K ，32K 位和64K 位串行I C 总线EEPROM3.24C02/04/08/16/32/64PROM256/512/1024/2048/4096/8192×8-bit1.8V1μA1mA 24C02/04/08/16/32/648/16/16/16/32/3224C02/04/08/16/32/648-pin PDIP8-pin SOP ●●●●●●●●●●●●SD SCL WP V CC NC A SD A SCL WP V CC 12348765NC NC NC GND SD A SCL WP V CC 12348765 ()SD A SCL WP V CC 12348765A 0A 1A 2GND C02C1621.8V~5.5V- 1mA- 1μA- 24C02, 256 X 8 (2K bits)- 24C04, 512 X 8 (4K bits) - 24C08, 1024 X 8 (8K bits) - 24C16, 2048 X 8 (16K bits)- 24C32, 4096 X 8 (32K bits)- 24C64, 8192 X 8 (64K bits)2I CI C 1 MHz (5V), 400 kHz (1.8V, 2.5V, 2.7V) ( 5 ms)8 (24C02)16(24C04/08/16),32字节页(24C32/64)ESD 2.5kV - 100- 100 8-pin DIP 8-pin SOP RoHS ●●●●●●●22●S D A 123487651A 2GND NC NC C A 2GND C04C082.7V)00n SOP●●SD A SCL WP V CC 12348765A 0A 1A 2GND C32SD ASCL WP V CC 12348765A 0A 1A 2GNDC6424C02/24C04/24C08/24C16/24C32/24C645. Ḛ1 ḚV 6. 乱ヺ ԡⳈ⌕կ⬉⬉ Ⳉ⌕䕧 ⬉ ⏽V CC Ⳉ⌕䕧 ⬉ V IN V OUT T STG -0.3 ~ V CC +0.3-0.3 ~ V CC +0.3-0.3 ~ +6.5°C -65 ~ +150V °C7. 㤤 ԰ ӊヺ ԡⳈ⌕կ⬉⬉ V CC ԰⏽T A+855.5 1.8-40(䍙乱㛑Ӯ 㟈 ӊ )V V ( 㤤 ԰ ӊϟ ⦄ 㛑)SDASCL WP V CCNC /NC /NC /A0NC /NC /A1/A1NC /A2/A2/A2C16/C08/C04/C02GNDSTART STOPLOGICSERIAL CONTROLLOGICDEVICE ADDRESS COMPARATORDATA WORD ADDRESS COUNTER LOADCOMPLOADINCY DECODER HIGH VOLTAGE PUMP/TIMING ENDATA RECOVERYEEPROMSERIAL MUXX D E C O D E RDOUT/ACKNOWLEDGEDINESD ⬉ (Ҏԧ῵ )ESD ⬉ ( ῵ )V ESD2500200V V乱⬉ 䕧 ⬉ 乱㛑Ӯ 㟈 ӊ DOUTmA 9. Ⳉ⌕⬉⇨⡍ヺ ԡ ⬉⌕կ⬉⬉⌕I CC V CC =5V⌟䆩 ӊ100kHz 3.0䕧 Ԣ⬉ ⬉μA 3.01.0-0.6V 0.4V IN = V CC GND 0.05( ӊ˖T A = 0°C ̚ +70°C, V CC = +1.8V ̚ +5.5V ˈ䰸䴲 ⊼䞞)䕧 Ԣ⬉ ⬉ μA V IL 0.4V CC0.20.4100kHz V V CC ×0.3I SB V IN = V CC GND V OUT = V CC GND μA 䕧 ⓣ⬉⌕䕧 ⓣ⬉⌕I LI I LO V IH 䕧催⬉ ⬉ V CC +0.5V V V VV OL3V OL2V = 2.1 mA V 10. Ѹ⌕⬉⇨⡍ ( ӊ˖T A = 0°C ̚ +70°C, V = +1.8V +5.5V, C L = 100 pF ˈ䰸䴲 ⊼䞞)ヺ ԡ䩳催⬉䩳乥⥛, SCL ⌟䆩 ӊ400V CC =1.8V 1000ns 0.050.050.60.90.6 μskHz 1.20.5540V CC =5V 0.4t LOW μs ⍜䰸䯈䩳ϟ䰡⊓ 䕧䯈䱨䯈t I t AA50t HIGH䩳Ԣ⬉ μsV CC =1.8V V CC =5V V CC =1.8V V CC =5V V CC =1.8V V CC =5V V CC =1.8V V CC =5V8. 㛮⬉( ӊ˖T A = 25°C, f = 1.0 MHz, V CC = +1.8V)pFヺ ԡ䕧 /䕧 ⬉ (SDA)C I/O 䕧 ⬉ (A0, A1, A2, SCL)C IN68 pF⌟䆩 ӊV I/O = 0V V IN = 0V1.2 㒓䞞䯈t BUF0.5μs V CC =1.8V V CC =5V䇏1.03.0 mA m 042.0C =5.0V, I OL = 3.0 mA CC ×0.7GNDOL1V CC =3.0V, I OL =2.1mA CC =1.8V, I OL = 0.15 mA =C CC = +1.8V ̚+5.5f SCL10. Ѹ⌕⬉⇨⡍ (㓁)䕧 Ϟ 䯈䕧䯈0ns500.650.25ns t WRns 100ns ℶ ӊ ゟ䯈䕧䯈t R t DH t F 䕧ゟ䯈μs ms䕧 ϟ䰡䯈t SU.STOV CC =1.8V V CC =5V V CC =1.8V V CC =5Vμs 300100300t HD.DAT t SU.DAT 2 㒓3SCLSDA_INSDA _OUTt F t LOWt SU .STAt HD.STAt AA t DHt BUFt SU.STOt Rt HD.DAT t SU.DAT t HIGH t LOW8th BIT SCLSDAACKSTOPCONDITIONSTART CONDITIONt WR (1)t HD.STAμs 䍋 ӊ 䯈䍋 ӊ ゟ䯈t SU.STA V CC =1.8V V CC =5V V CC =1.8V V CC =5Vμs 0.60.250.60.25ヺ ԡ ⌟䆩 ӊ ⊼ 䯈W :5 ҢϔϾ ⱘ ℶ ӊ 㟇䚼㒧 ⱘ 䯈Ǆn 08V μ3001AHIG11.3156247A0A1A2SDA SCL WP GND V CCA2A1A024C02/32/64A2A1A0824C02/32/6424C04A2A1424C04A024C08A2224C08A0A124C1616KA2A1A0/SDA V CC10kΩSCL8WP WPWPV CC12.13. 䆺㒚 ԰䇈24CXX I C 㒓Ӵ䕧䆂ǄI C ϔ⾡ ǃϸ㒓І㸠䗮䆃 ˈ І㸠㒓SDA І㸠䩳㒓SCL Ǆϸḍ㒓䛑乏䗮䖛ϔϾϞ ⬉䰏 ⬉⑤Ǆ ⱘ 㒓䜡㕂 4 ⼎4 ϸ㒓㒓䜡㕂㒓Ϟ 䗕 ⱘ ӊ㹿⿄԰ 䗕 ˈ ⱘ ӊ㹿⿄԰ Ǆ Ѹ ⱘ ӊ㹿⿄԰Џ ӊˈ Џ ӊ ⱘ ӊ 㹿⿄԰Ң ӊǄЏ ӊѻ⫳І㸠䩳SCL ˈ㒓ⱘ䆓䯂⢊ ǃѻ⫳START STOP ӊǄ24CXX I C 㒓Ё԰ЎҢ ӊ ԰Ǆ㒓 Ѣぎ䯆⢊ ҹ Ӵ䕧Ǆ↣⃵ Ӵ䕧 ѢSTART ӊˈ㒧 ѢSTOP ӊˈѠ㗙П䯈ⱘ 㡖 ≵ 䰤 ⱘˈ⬅ 㒓ϞⱘЏ ӊ Ǆ ҹ 㡖˄8ԡ˅Ў ԡӴ䕧ˈ㄀9ԡ ⬅ ѻ⫳ ㄨǄ䍋 ℶ ӊ䩳㒓䛑Ў催⿄㒓ぎ䯆⢊ Ǆ SCL Ў催⬉ SDA ⱘϟ䰡⊓˄催 Ԣ 䍋 ӊ˄START ˈㅔ ЎS ˅ˈSDA ⱘϞ ⊓˄Ԣ 催˅ ℶ ӊ˄STOP ˈㅔ ЎP ˅Ǆ 㾕 5Ǆ5 䍋 ӊ ℶ ӊⱘ НV CCҪ24Cxx MPU SDASCLR PR Pϸ㒓І㸠S Ў催ㅔ ЎⱘϞ ⊓˄Ԣ 㒓І㸠㒓SS 䍋 ӊ222ԡӴ䕧↣Ͼ 䩳㛝 Ӵ䗕ϔԡ ǄSCL Ў催 SDA 乏〇 ˈ Ўℸ SDA ⱘ 㹿䅸Ў ǄԡӴ䕧㾕 6Ǆ6 ԡӴ䕧ㄨ㒓Ϟⱘ ↣ ϔϾ 㡖 ѻ⫳ϔϾ ㄨˈЏ ӊ 乏ѻ⫳ϔϾ ⱘ乱 ⱘ 䩳㛝 ˈ㾕 7Ǆ7 I C㒓ⱘ ㄨ ԢSDA 㒓㸼⼎ㄨˈ ㄨ㛝䯈〇 ⱘԢ⬉ Ǆ Џ ӊ԰ ˈ 乏 Ӵ䕧㒧 ⱘ 㒭䗕 ˈ ϔϾ 㡖П ⱘ ㄨ㛝䯈ϡӮѻ⫳ ㄨ ˄ϡ ԢSDA ˅Ǆ䖭⾡ ϟˈ 䗕乏䞞 SDA 㒓Ў催ҹ Џ ӊѻ⫳ ℶ ӊǄ䗕䕧 ⱘ䕧 ⱘЏ ӊ ⱘ䍋 ӊ289䴲ㄨㄨㄨ䩳㛝㒓〇䆌SDASCL2ѻ⫳ϔϾ ㄨˈЏ ӊ 乏ѻ⫳ϔԢ㒓Ӵӊ ⱘSCL 䍋 ӊS1ӊ䍋 ӊՓ㛑㢃⠛䇏 ԰ ˈEEPROM 䛑㽕∖ 8ԡⱘ ӊ ˄㾕 8˅Ǆӊ ⬅"1"ǃ"0" 㒘 ˈ 4ԡ Ё ⼎ˈ Ѣ І㸠EEPROM 䛑 ϔḋⱘ Ѣ24C02/32/64ˈ䱣 3ԡA2ǃA1 A0Ў ӊ ԡˈ 乏Ϣ⹀ӊ䕧㛮 ϔ㟈Ǆ Ѣ24C04ˈ䱣 2ԡA2 A1Ў ӊ ԡˈ 1ԡЎ义 ԡǄA2 A1 乏Ϣ⹀ӊ䕧㛮 ϔ㟈ˈ㗠A0 ぎ㛮ǄѢ24C08ˈ䱣 1ԡA2Ў ӊ ԡˈ 2ԡЎ义 ԡǄA2 乏Ϣ⹀ӊ䕧㛮 ϔ㟈ˈ㗠A1 A0 ぎ㛮ǄѢ24C16ˈ ӊ ԡˈ3ԡ䛑Ў义 ԡˈ㗠A2ǃA1 A0 ぎ㛮Ǆ ӊ ⱘLSB Ў䇏/ ԰䗝 ԡˈ催Ў䇏 ԰ˈԢЎ ԰Ǆ㢹↨䕗 ӊ ϔ㟈ˈEEPROM 䕧ㄨ"0"Ǆ ϡϔ㟈ˈ 䖨 ⢊ Ǆ8 ӊ 1010A2A1A0R/W MSBLSB1010A2A1P0R/W1010A2P1P0R/W1010P2P1P0R/Wӊ ԰῵EEPROM Ԣ 㗫 ⱘ⡍⚍ˈ ӊЎ˖˄1˅⬉⑤Ϟ⬉˗˄2˅ ℶ ӊ ӏԩ 䚼 ԰ Ǆ24C0424C0824C16Ǆ ԡ䆂Ёѻ⫳Ё ǃ ⬉ ㋏㒳 ԡ ˈI C 㒓䗮䖛ҹϟℹ偸 ԡ˖ ˄1˅ѻ⫳9Ͼ 䩳 Ǆ˄2˅ SCL Ў催 ˈSDA гЎ催Ǆ ˄3˅ѻ⫳ϔϾ䍋 ӊǄ2԰1. 㡖԰㽕∖ ӊ ACK ㄨ ˈ 8ԡⱘ Ǆ 䖭Ͼ EEPROM ㄨ"0"ˈ✊ ϔϾ8ԡ Ǆ 8ԡ ˈEEPROM ㄨ"0"ˈ ⴔ 乏⬅Џ ӊ 䗕 ℶ ӊ 㒜ℶ Ǆℸ EEPROM 䖯䚼 t WR ˈ 䴲 Ёˈ ℸ 䯈䕧䛑 Ⳉ ˈEEPROM Ӯ ㄨ˄㾕 9˅Ǆ9 㡖SDA 㒓䍋 ӊM S BL S B R /W A C K M S BL S B A C KA C Kӊℶ ӊǄ24C02/32/6413.2.图10页写24C02器件按8字节/页执行页写，24C04/08/16器件按16字节/页执行页写，24C32/64器件按32字节/页执行页写。

24c02EEPROM中文官方资料手册

测试条件 FSCL=100KHz VIN=0 ~Vcc VIN=0 ~Vcc VOUT=0 ~Vcc
IOL=3 mA IOL=1.5 mA
ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ分布电容
TA=25 , f =1.0MHz, Vcc =5V
符号
测试项
CI/O
I/O 电容 SDA 脚
CIN
输出电容 A0 A1 A2 SCL WP
管脚配置
管脚描述
管脚名称
功能
A0 A1 A2 SDA SCL
器件地址选择串行数据/地址串行时钟
WP
写保护
Vcc
+1.8V 6.0V 工作电压
Vss
地
2
方框图
海纳电子资讯网：ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ
ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ极限参数
工作温度工业级 -55 +125 商业级 0 +75
ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ
1
海纳电子资讯网：ｗｗｗ．ｆｐｇａ－ａｒｍ．ｃｏｍ
CAT24WC01/02/04/08/16 1K/2K/4K/8K/16K 位串行 E2PROM
特性
与 400KHz I2C 总线兼容
1.8 到 6.0 伏工作电压范围
低功耗 CMOS 技术
写保护功能当 WP 为高电平时进入写保护状态
数据入保持时间
0
0
ns
tSUl: DAT
数据输入建立时间
50
50
ns
tR
SDA 及 SCL 上升时间
1
0.3
s
tF
SDA 及 SCL 下降时间
300
300

(完整word版)AT24Cxx中文数据手册

AT24C01A/02/04/08A/16A提供1024/2048/4096/8192/16384个连续的可擦除的位,以及由每8位组成一个字节的可编程只读存储器（EEPROM）,其分别提供128/256/512/1024/2048个字节.该设备适用在许多低功耗和低电压操作的工业和商业应用中。

1引脚描述1.1串行时钟（SCL）SCL输入用于正向输出边缘时钟信号到每个EEPROM设备，以及每个设备输出的反向边缘时钟数据。

1.2串行数据(SDA)SDA引脚是用于串行数据双向传输。

该引脚为开漏输出，同时可以与其他开漏极或集电极开路器件进行线或.1.3设备/页地址（A2,A1，A0）对于AT24C01A和AT24C02,A2、A1和A0引脚是配置器件的硬件地址输入。

一根总线上可以连接多达八个1K / 2K的设备（器件寻址部分详细讨论了器件寻址）.AT24C04使用A2和A1引脚作为硬件地址输入，在一根总线上有4个4K 的设备可用来寻址。

A0引脚没有连接。

AT24C08A只使用A2引脚作为硬件地址输入,在一根总线上有2个8K 的设备可用来寻址.A0和A1引脚没有连接。

AT24C16A不使用设备地址引脚,这限制了一根总线上只能挂一个设备。

A0、A1和A2引脚没有连接。

1.4写保护(WP）AT24C01A / 02 / 04 / 08A/ 16A有一个写保护引脚，提供硬件数据保护。

写保护引脚允许正常读/写操作时连接到GND。

当写保护引脚连接到VCC,写保护功能启用和操作如下表所示.2设备操作2.1时钟和数据转换SDA引脚通常情况下拉高.SDA引脚上的数据只能在SCL低时间段内更改,而启动条件或停止条件在SCL 为高时进行。

2.2启动条件在任何其他指令之前，SDA由高变为低，且SCL为高。

2.3停止条件SDA由低变为高，且SCL为高。

在读取序列之后,执行停止命令后EEPROM进入备用电源模式.2.4应答所有地址和数据字都是从EEPROM串行发送和接收8位字节。

24LC02中文资料

HT24LC01/021K/2K 2-Wire CMOS Serial EEPROMBlock Diagram Pin AssignmentFeatures•Operating voltage: 2.4V~5.5V •Low power consumption –Operation: 5mA max.–Standby: 5µA max.•Internal organization –1K (HT24LC01):128×8–2K (HT24LC02): 256×8•2-wire serial interface•Write cycle time: 5ms max.•Automatic erase-before-write operation•Partial page write allowed •8-byte Page write modes•Write operation with built-in timer •Hardware controlled write protection •40-year data retention•106 erase/write cycles per word •8-pin DIP/SOP package•8-pin TSSOP (HT24LC02 only)•Commerical temperature range (0°C to +70°C)General DescriptionThe HT24LC01/02 is a 1K/2K-bit serial read/write non-volatile memory device using the CMOS floating gate process. Its 1024/2048bits of memory are organized into 128/256words and each word is 8 bits. The device is optimized for use in many industrial and com-mercial applications where low power and low voltage operation are essential. Up to eight HT24LC01/02 devices may be connected to the same two-wire bus. The HT24LC01/02 is guar-anteed for 1M erase/write cycles and 40-yeardata retention.16th May ’99Pin DescriptionAbsolute Maximum RatingsOperating Temperature (Commercial) .................................................................................. 0°C to 70°C Storage Temperature ........................................................................................................ –50°C to 125°C Applied VCC Voltage with Respect to VSS ....................................................................... –0.3V to 6.0V Applied Voltage on any Pin with Respect to VSS ...................................................................–0.3V to V CC+0.3VNote: These are stress ratings only. Stresses exceeding the range specified under “Absolute Maxi-mum Ratings” may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.D.C. Characteristics Ta=0°C to 70°CNote: These parameters are periodically sampled but not 100% tested26th May ’99A.C. Characteristics Ta=0°C to 70°C* The standard mode means V CC=2.4V to 5.5VFor relative timing, refer to timing diagrams36th May ’99Functional Description•Serial clock (SCL)The SCL input is used for positive edge clock data into each EEPROM device and negative edge clock data out of each device.•Serial data (SDA)The SDA pin is bidirectional for serial data transfer. The pin is open-drain driven and may be wired-OR with any number of other open-drain or open collector devices.•A0, A1, A2The A2, A1 and A0 pins are device address inputs that are hard wired for the HT24LC01/02. As many as eight 1K/2K de-vices may be addressed on a single bus system (the device addressing is discussed in detail under the Device Addressing section).•Write protect (WP)The HT24LC01/02 has a write protect pin that provides hardware data protection. The write protect pin allows normal read/write operations when connected to the V SS. When the write protect pin is connected to Vcc, the write protection feature is enabled and oper-Memory organization•HT24LC01, 1K Serial EEPROMInternally organized with 128 8-bit words, the 1K requires a 7-bit data word address for random word addressing.•HT24LC02, 2K Serial EEPROMInternally organized with 256 8-bit words, the 2K requires an 8-bit data word address for random word addressing.Device operations•Clock and data transitionData transfer may be initiated only when thebus is not busy. During data transfer, the data line must remain stable whenever the clock line is high. Changes in data line while the clock line is high will be interpreted as a START or STOP condition.•Start conditionA high-to-low transition of SDA with SCL highis a start condition which must precede any other command (refer to Start and Stop Defi-nition Timing diagram).•Stop conditionA low-to-high transition of SDA with SCL highis a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition Timing Diagram).•AcknowledgeAll addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero to acknow-ledge that it has received each word. This happens during the ninth clock cycle.Device addressingThe 1K and 2K EEPROM devices all require an 8-bit device address word following a start con-dition to enable the chip for a read or write operation. The device address word consist of a mandatory one, zero sequence for the first four most significant bits (refer to the diagram show-ing the Device Address). This is common to all the EEPROM device.The next three bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These three bits must compare to their correspondinghard-wired input pins.46th May ’99The 8th bit of device address is the read/write operation select bit. A read operation is initi-ated if this bit is high and a write operation is initiated if this bit is low.If the comparison of the device address succeed the EEPROM will output a zero at ACK bit. If not, the chip will return to a standby state.Write operations•Byte writeA write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this ad-dress, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. After receiving the 8-bit data word, the EEPROM will output a zero and the address-ing device, such as a microcontroller, must terminate the write sequence with a stop con-dition. At this time the EEPROM enters an internally-timed write cycle to the non-vola-tile memory . All inputs are disabled during this write cycle and EEPROM will not re-spond until the write is completed (refer to Byte write timing).•Page writeThe 1K/2K EEPROM is capable of an 8-byte page write.A page write is initiated the same as byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM ac-knowledges the receipt of the first data word,the microcontroller can transmit up to seven more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition.The data word address lower three (1K/2K)bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, re-taining the memory page row location (refer to Page write timing).•Acknowledge pollingSince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately . This involves the master sending a start condition followed by the control byte for a write command(R/W=0). If the device is still busy with the56th May ’99write cycle, then no ACK will be returned. If the cycle is completed, then the device will return the ACK and the master can then pro-ceed with the next read or write command.•Write protectThe HT24LC01/02 can be used as a serial ROM when the WP pin is connected to VCC.Programming will be inhibited and the entire memory will be write-protected.•Read operationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read opera-tions: current address read, random address read and sequential read.•Current address readThe internal data word address counter main-tains the last address accessed during the last read or write operation, incremented by one.This address stays valid between operations as long as the chip power is maintained. The address roll over during read from the last byte of the last memory page to the first byte of the first page. The address roll over during write from the last byte of the current page to the first byte of the same page. Once the de-vice address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but generates a following stop condition (refer to Current read timing).•Random readA random read requires a dummy byte write sequence to load in the data word address which is then clocked in and acknowledged by the EEPROM. The microcontroller must then generate another start condition. The micro-controller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM ac-knowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does gener-ates a following stop condition (refer to Ran-dom read timing).Acknowledge polling flow66th May ’99Timing DiagramsNote:The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the valid start condition of sequential command.•Sequential readSequential reads are initiated by either a cur-rent address read or a random address read.After the microcontroller receives a data word,it responds with an acknowledgment. As long as the EEPROM receives an acknowledgment, it will continue to increment the data word ad-dress and serially clock out sequential datawords. When the memory address limit is reached, the data word address will roll over and the sequential read continues. The se-quential read operation is terminated when the microcontroller does not respond with a zero but generates a following stopcondition.Holtek Semiconductor Inc. (Headquarters)No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.Tel: 886-3-563-1999Fax: 886-3-563-1189Holtek Semiconductor Inc. (Taipei Office)5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.Tel: 886-2-2782-9635Fax: 886-2-2782-9636Fax: 886-2-2782-7128 (International sales hotline)Holtek Microelectronics Enterprises Ltd.RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong KongTel: 852-2-745-8288Fax: 852-2-742-865786th May ’99。

24LC32中文资料

•ISO 7816 compliant contact locations•Single supply with operation down to 2.5V -Maximum write current 3 mA at 6.0V -Maximum read current 150 µ A at 6.0V -Standby current 1 µ A max at 2.5V•T wo wire serial interface bus, I 2 C ™ compatible •100 kHz (2.5V) and 400 kHz (5V) compatibility •Self-timed ERASE and WRITE cycles •Power on/off data protection circuitry•1,000,000 ERASE/WRITE cycles guaranteed •32 byte page or byte write modes available •Schmitt trigger inputs for noise suppression•Output slope control to eliminate ground bounce • 2 ms typical write cycle time, byte or page •Electrostatic discharge protection > 4000V •Data retention > 200 years•8-pin PDIP and SOIC packages •T emperature ranges:DESCRIPTIONThe Microchip T echnology Inc. 24LC32A is a 4K x 8(32K bit) Serial Electrically Erasable PROM in an ISO micromodule for use in smart card applications. The device has a page-write capability of up to 32 bytes.-Commercial: 0˚C to +70˚C2元器件交易网24LC32A MODULE1.0ELECTRICAL CHARACTERISTICS1.1Maximum Ratings*V CC ........................................................................7.0V All inputs and outputs w.r.t. V SS ......-0.6V to VCC +1.0V Storage temperature ..........................-65˚C to +150˚C Ambient temp. with power applied......-65˚C to +125˚C Soldering temperature of leads (10 seconds)..+300˚C ESD protection on all pins .....................................≥ 4 kV*Notice: Stresses above those listed under “Maximum Ratings”may cause permanent damage to the device. This is a stress rat-ing only and functional operation of the device at those or anyother conditions above those indicated in the operational listings of this speciﬁcation is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.TABLE 1-1:PIN FUNCTIONSName Function V SS Ground SDA Serial Data SCL Serial ClockV CC+2.5V to 6.0V Power SupplyTABLE 1-2:DC CHARACTERISTICSVcc = +2.5V to 6.0VCommercial (C):T amb = 0˚C to +70 ° CParameterSymbolMinTypMaxUnitsConditionsSCL and SDA pins:High level input voltage V IH .7 V CC —V Low level input voltage V IL —.3 Vcc V Hysteresis of Schmitt T rigger inputsV HYS .05 V CC—V Note 1Low level output voltage V OL —.40V I OL = 3.0 mA @ V CC = 4.5V I OL = 2.1 mA @ V CC = 2.5V Input leakage current I LI -1010 µ A V IN = .1V to V CC Output leakage current I LO -1010 µ A V OUT = .1V to V CC Pin capacitance (all inputs/outputs)C IN ,C OUT —10pF V CC = 5.0V (Note 1)T amb = 25˚C, f c = 1 MHz Operating current I CC Write —3mA V CC = 6.0VI CC Read —400 µ A V CC = 6.0V , SCL = 400Khz Standby currentI CCS —1 µ A5 µ A SCL = SDA = V CC = 5.0VI CCS1µ AVCC = 2.5V (Note 1)Note 1:This parameter is periodically sampled and not 100% tested.元器件交易网24LC32A MODULETABLE 1-3:AC CHARACTERISTICSParameterSymbolVcc = 2.5 - 6.0V STD. MODE Vcc = 4.5 - 6.0V FAST MODE UnitsRemarksMinMaxMinMaxClock frequency F CLK —100—400kHz Clock high time T HIGH 4000—600—ns Clock low timeT LOW 4700—1300—ns SDA and SCL rise time T R —1000—300ns Note 1SDA and SCL fall time T F —300—300ns Note 1START condition hold timeT HD : STA 4000—600—ns After this period the ﬁrst clock pulse is generatedST ART condition setup timeT SU : STA 4700—600—ns Only relevant for repeated ST ART conditionData input hold time T HD : DAT 0—0—ns Data input setup time T SU : DAT 250—100—ns STOP condition setup timeT SU : STO 4000—600—ns Output valid from clock T AA —3500—900ns Note 2Bus free timeT BUF 4700—1300—ns Time the bus must be free before a new transmission can start Output fall time from V IH min to V IL maxT OF —25020 +0.1C B 250ns Note 1, CB ≤ 100 pF Input ﬁlter spike sup-pression (SDA and SCL pins)T SP—50—50nsNote 3Write cycle timeTWR —5—5ms Byte or Page modeNote 1: Not 100% tested. CB = total capacitance of one bus line in pF .2: As a transmitter, the device must provide an internal minimum delay time to bridge the undeﬁned region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of ST ART or STOP conditions. 3: The combined T SP and VHYSspeciﬁcations are due to Schmitt trigger inputs which provide improved noise and spike suppression. This eliminates the need for a Ti speciﬁcation for standard operation.元器件交易网24LC32A MODULE2.0PIN DESCRIPTIONS2.1SDA (Serial Data)This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open drain terminal, therefore the SDA bus requires a pullup resistor to V CC (typical 10K Ω for 100 kHz, 1K Ω for 400kHz)For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the ST ART and STOP condi-tions.2.2SCL (Serial Clock)This input is used to synchronize the data transfer from and to the device.3.0FUNCTIONAL DESCRIPTIONThe 24LC32A supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is deﬁned as transmitter, and a device receiving data as receiver. The bus must be con-trolled by a master device which generates the serial clock (SCL), controls the bus access, and generates the ST ART and STOP conditions, while the 24LC32A works as slave. Both master and slave can operate as transmitter or receiver but the master device deter-mines which mode is activated.元器件交易网24LC32A MODULE4.0BUS CHARACTERISTICSThe following bus protocol has been deﬁned:•Data transfer may be initiated only when the bus is not busy.•During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a ST ART or STOP condition.Accordingly, the following bus conditions have been deﬁned (See Figure 4-1).4.1Bus not Busy (A)Both data and clock lines remain HIGH.4.2Start Data Transfer (B)A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a ST ART condition.All commands must be preceded by a START condi-tion.4.3Stop Data Transfer (C)A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition.4.4Data Valid (D)The state of the data line represents valid data when,after a ST ART condition, the data line is stable for the duration of the HIGH period of the clock signal.The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a ST ART condition and terminated with a STOP condition. The number of the data bytes transferred between the ST ART and STOP conditions is determined by the master device.4.5AcknowledgeEach receiving device, when addressed, is obliged to generate an acknowledge signal after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit.A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course,setup and hold times must be taken into account. Dur-ing reads, a master must signal an end of data to the slave by NOT generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24LC32A) will leave the data line HIGH to enable the master to generate the STOP condition.(See Figure 4-2)元器件交易网24LC32A MODULE5.0DEVICE ADDRESSINGA control byte is the ﬁrst byte received following the start condition from the master device. (See Figure 5-1) The control byte consists of a four bit control code;for the 24LC32A this is set as 1010 binary for read and write operations. The next three bits are device select bits on standard devices, however, for micromodules,these must be zeros. The last bit of the control byte deﬁnes the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. The next two bytesreceived deﬁne the address of the ﬁrst data byte (see Figure 5-2). Because only A11...A0 are used, the upper four address bits must be zeros. The most signif-icant bit of the most signiﬁcant byte of the address is transferred ﬁrst.Following the start condition, the 24LC32A monitors the SDA bus checking the device type identiﬁer being transmitted. Upon receiving a valid control byte, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24LC32A will select a read or write operation元器件交易网24LC32A MODULE6.0WRITE OPERATIONS6.1Byte WriteFollowing the start condition from the master, the con-trol code (four bits), the device select (three bits), and the R/W bit which is a logic low are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow after it has generated an acknowl-edge bit during the ninth clock cycle. Therefore the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24LC32A MODULE. The next byte is the least signiﬁcant address byte. After receiving another acknowledge signal from the 24LC32A the master device will transmit the data word to be written into the addressed memory location.The 24LC32A acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24LC32A will not generate acknowledge signals (see Figure 6-1).6.2Page WriteThe write control byte, word address and the ﬁrst data byte are transmitted to the 24LC32A in the same way as in a byte write. But instead of generating a stop con-dition, the master transmits up to 32 bytes which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. After receipt of each word, the ﬁve lower address pointer bits are internally incremented by one.If the master should transmit more than 32 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received, an internal write cycle will begin. (see Figure 6-2).元器件交易网24LC32A MODULE7.0ACKNOWLEDGE POLLINGSince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write com-mand has been issued from the master, the device ini-tiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master send-ing a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for ﬂow diagram.FIGURE 7-1:ACKNOWLEDGE POLLING8.0READ OPERATIONRead operations are initiated in the same way as write operations with the exception that the R/W bit of the slave address is set to one. There are three basic types of read operations: current address read, random read,and sequential read.8.1Current Address ReadThe 24LC32A contains an address counter that main-tains the address of the last word accessed, internally incremented by one. Therefore, if the previous access (either a read or write operation) was to address n (n is any legal address), the next current address read oper-ation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to one, the 24LC32A issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24LC32A discontinues transmission (see Figure 8-1).8.2Random ReadRandom read operations allow the master to access any memory location in a random manner. T o perform this type of read operation, ﬁrst the word address must be set. This is done by sending the word address to the 24LC32A as part of a write operation (R/W bit set to 0).After the word address is sent, the master generates a start condition following the acknowledge. This termi-nates the write operation, but not before the internal address pointer is set. Then the master issues the con-trol byte again but with the R/W bit set to a one. The 24LC32A will then issue an acknowledge and transmit the eight bit data word. The master will not acknowl-edge the transfer but does generate a stop condition which causes the 24LC32A to discontinue transmis-sion (see Figure 8-2).元器件交易网24LC32A MODULE8.3Sequential ReadSequential reads are initiated in the same way as a ran-dom read except that after the 24LC32A transmits the ﬁrst data byte, the master issues an acknowledge as opposed to the stop condition used in a random read.This acknowledge directs the 24LC32A to transmit the next sequentially addressed 8 bit word (see Figure 8-3). Following the ﬁnal byte transmitted to the master,the master will NOT generate an acknowledge but will generate a stop condition.To provide sequential reads the 24LC32A contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 0FFF to address 000 if the master acknowledges the byte received from the array address 0FFF .元器件交易网24LC32A MODULE9.0SHIPPING METHODThe micromodules will be shipped to customers in clear plastic trays. Each tray holds 150 modules, and the trays can be stacked in a manner similar to shipping die in wafﬂe packs. A tray drawing with dimensions is shown in Figure 9-1.元器件交易网24LC32A MODULE元器件交易网24LC32A MODULENOTES:元器件交易网24LC32A MODULENOTES:元器件交易网24LC32A MODULENOTES:元器件交易网24LC32A MODULE24LC32A MODULE PRODUCT IDENTIFICATION SYSTEMT o order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales ofﬁce.Sales and SupportData SheetsProducts supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recom-mended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:1.Y our local Microchip sales ofﬁce.2.The Microchip Corporate Literature Center U.S. FAX: (602) 786-7277.3.The Microchip’s Bulletin Board, via your local CompuServe number (CompuServe membership NOT required).Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using.元器件交易网MAll rights reserved. © 1997, Microchip T echnology Incorporated, USA. 9/97 Printed on recycled paper.元器件交易网。

24LCXX eeprom

一功能介绍1、能页操作，每页可达128字节。

2、具有的功能地址线，允许8个器件挂在同一总线上。

高达4MBit的地址空间（64k x8=512bit | 512bit x 8 = 4Mbit)3、在512k范围内，可随机读和顺序读。

4、板级供电电压范围1.7V to 5.5V。

二引脚描述引脚名功能A0 芯片选择（用户可配置）A1 芯片选择（用户可配置）A2 芯片选择（用户可配置）NC 未连接VSS 地SDA 串行数据SCL 串行时钟WP 写保护输入VCC 电源2.0 A0，A1 AND A2 芯片地址输入⏹芯片地址引脚允许8个芯片挂在同一条总线上。

当引脚的逻辑电平与芯片内部相应的设备地址相同时，芯片使能。

⏹芯片引脚的输入使能时VCC 和VSS⏹在大多数的应用中，地址线是被硬件拉高和拉低的。

在那些引脚受microcontroller 和可编程器件控制的应用中，在访问该EEPROM芯片之前，EEPROM的引脚要先拉高或拉低。

2.1 Serial Data (SDA)⏹该双向引脚是用来传输数据和地址的。

该引脚是内部开漏，所以SDA引脚要接一个上拉电阻到VCC( 典型的是10kohm/100khz, 2kohm/400Khz,1Mhz).⏹在数据传输中，SDA只有在SCL线为低时才发生改变。

在SCL线为高时SDA发生改变则被认为是开始或停止。

2.2 Serial Clock (SCL)数据同步时钟2.3 Write-Protect(WP) 写保护⏹该引脚只能连接VCC 或者VSS。

⏹当连接VCC时，允许对芯片写操作，当连接VSS，对芯片写操作禁止。

该引脚对芯片读操作没有任何影响。

三功能描述⏹24XX512支持双向2线制总线和数据传输协议。

在总线数据发送数据的成为发送方，接收数据的为接收方。

⏹当24XX512为从设备时，串行时钟（SCL）由主设备产生，来控制总线的访问和产生开始和结束条件。

⏹主设备和从设备都可以作为接收方和发送方，但是只有主设备才能决定处于那种模式。

24LC256IP中文资料

-40°C to +85°C
- Automotive (E):
-40°C to +125°C
DESCRIPTION
The Microchip Technology Inc. 24AA256/24LC256 (24xx256*) is a 32K x 8 (256K bit) Serial Electrically Erasable PROM, capable of operation across a broad voltage range (1.8V to 5.5V). It has been developed for advanced, low power applications such as personal communications or data acquisition. This device also has a page-write capability of up to 64 bytes of data. This device is capable of both random and sequential reads up to the 256K boundary. Functional address lines allow up to eight devices on the same bus, for up to 2 Mbit address space. This device is available in the standard 8-pin plastic DIP, and 8-pin SOIC (208 mil) packages.
- Standby current 100 nA typical at 5.5V
• 2-wire serial interface bus, I2C compatible

24AA014H-ISN;24LC014H-IMS;24LC014HT-IMNY;24AA014HT-IMNY;24AA014H-IP;中文规格书,Datasheet资料

24AA014H/24LC014HDevice Selection TableFeatures:•Single-Supply with Operation down to 1.7V •Low-Power CMOS Technology:-400 μA active current, maximum- 1 μA standby current, maximum (I-temp)•Organized as a Single Block of 128 Bytes(128 x 8)•2-Wire Serial Interface Bus, I2C™ Compatible •Schmitt Trigger Inputs for Noise Suppression •Output Slope Control to Eliminate Ground Bounce •100 kHz and 400 kHz Compatibility• 1 MHz Compatibility (LC)•Page Write Buffer for up to 16 Bytes•Self-Timed Write Cycle (including Auto-Erase)•Hardware Write Protection for Half Array(40h-7Fh)•Address Lines Allow up to Eight Devices on Bus • 1 Million Erase/Write Cycles•ESD Protection > 4,000V•Data Retention > 200 Years•Factory Programming (QTP) Available•Pb-Free and RoHS Compliant•8-pin PDIP, SOIC, TSSOP, TDFN and MSOP Packages•Available for Extended Temperature Ranges:Description:The Microchip Technology Inc. 24AA014H/24LC014H is a 1Kbit Serial Electrically Erasable PROM with operation down to 1.7V. The device is organized as a single block of 128 x8-bit memory with a 2-wire serial interface. Low-current design permits operation with maximum standby and active currents of only 1 μA and 400 μA, respectively. The device has a page write capability for up to 16 bytes of data. Functional address lines allow the connection of up to eight 24AA014H/ 24LC014H devices on the same bus for up to 8Kbits of contiguous EEPROM memory. The device is available in the standard 8-pin PDIP, 8-pin SOIC (150 mil), TSSOP, 2x3 TDFN and MSOP packages. Package TypesBlock DiagramPart NumberV CCRangeMax.ClockTemp.Range24AA014H 1.7V-5.5V400kHz(1)I 24LC014H 2.5V-5.5V 1 MHz I, E Note1:100 kHz for V CC < 1.8V-Industrial (I):-40°C to+85°C -Automotive (E):-40°C to+125°CA0A1A2V SSV CCWPSCLSDA12348765PDIP, MSOP SOIC, TSSOPA0A1A2V SS12348765V CCWPSCLSDATDFNA0A1A2V SSWPSCLSDAV CC87651234I/OControlLogicMemoryControlLogic XDECHV GeneratorEEPROMArrayWrite-ProtectCircuitryYDEC V CCV SSSense Amp.R/W ControlSDA SCLA0 A1 A2WP1K I2C™ Serial EEPROM with Half-Array Write-Protect© 2008 Microchip Technology Inc.Preliminary DS22077B-page 124AA014H/24LC014HDS22077B-page 2Preliminary© 2008 Microchip Technology Inc.1.0ELECTRICAL CHARACTERISTICSAbsolute Maximum Ratings (†)V CC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. V SS .........................................................................................................-0.6V to V CC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥ 4 kV † NOTICE : Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.TABLE 1-1:DC CHARACTERISTICSAll parameters apply across the specified operating ranges unless otherwise noted.Electrical Characteristics:Industrial (I):V CC = +1.7V to 5.5V T A = -40°C to +85°C Automotive (E):V CC = +2.5V to 5.5V T A = -40°C to +125°CParameterSymbol Min.Max.Units ConditionsSCL and SDA pins:High-level input voltage V IH 0.7 V CC—V Low-level input voltageV IL —0.3 V CCV Hysteresis of Schmitt Trigger inputs V HYS 0.05 V CC—V (Note 1)Low-level output voltage V OL —0.40V I OL = 3.0 mA, V CC = 4.5V I OL = 2.1 mA, V CC = 2.5V Input leakage current I LI —±1μΑV IN = V SS or V CC , WP = Vss Output leakage currentI LO —±1μA V OUT = V SS or V CC Pin capacitance (all inputs/outputs)C IN , C OUT —10pF V CC = 5.0V (Note 1)T A = 25°C, f = 1 MHz Operating current I CC Read —400μA V CC = 5.5V, SCL = 400 kHz I CC Write —3mA V CC = 5.5VStandby currentI CCS—1μAV CC = 5.5V, SDA = SCL = V CC WP = V SS , A0, A1, A2 = V SS Note 1:This parameter is periodically sampled and not 100% tested.24AA014H/24LC014H TABLE 1-2:AC CHARACTERISTICSAC CHARACTERISTICS Electrical Characteristics:Industrial (I):V CC = +1.7V to 5.5V T A = -40°C to +85°C Automotive (E):V CC = +2.5V to 5.5V T A = -40°C to +125°CParam.No.Symbol Characteristic Min.Max.Units Conditions1F CLK Clock frequency———1004001000kHz 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)2T HIGH Clock high time4000600500———ns 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)3T LOW Clock low time47001300500———ns 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)4T R SDA and SCL rise time (Note1)———1000300300ns 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)5T F SDA and SCL fall time (Note1)———1000300300ns 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)6T HD:STA Start condition hold time4000600250———ns 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)7T SU:STA Start condition setup time4700600250———ns 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)8T HD:DAT Data input hold time0—ns(Note2)9T SU:DAT Data input setup time250100100———ns 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)10T SU:STO Stop condition setup time4000600250———ns 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)11T SU:WP WP setup time4000600600———ns 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)12T HD:WP WP hold time4700600600———ns 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)13T AA Output valid from clock (Note2)———3500900400ns 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)14T BUF Bus free time: Time the bus mustbe free before a new transmissioncan start 130047004700———ns 1.7V ≤ V CC < 1.8V1.8V ≤ V CC≤ 5.5V2.5V ≤ V CC≤ 5.5V (24LC014H)16T SP Input filter spike suppression(SDA and SCL pins)—50ns24AA014H(Note1 and Note3)17T WC Write cycle time (byte or page)—5ms—18—Endurance1M—cycles25°C, V CC = 5.5V, Block mode(Note4)Note1:Not 100% tested. C B = total capacitance of one bus line in pF.2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3:The combined T SP and V HYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a T I specification for standard operation.4:This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at .© 2008 Microchip Technology Inc.Preliminary DS22077B-page 324AA014H/24LC014HDS22077B-page 4Preliminary© 2008 Microchip Technology Inc.FIGURE 1-1:BUS TIMING DATA(unprotected)(protected)SCL SDA InSDA OutWP 57616328913D441011121424AA014H/24LC014H2.0PIN DESCRIPTIONSThe descriptions of the pins are listed in Table2-1.TABLE 2-1:PIN FUNCTION TABLE2.1SDA Serial DataThis is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to V CC (typical 10 kΩ for 100 kHz, 2 kΩ for 400kHz).For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.2.2SCL Serial ClockThe SCL input is used to synchronize the data transfer to and from the device.2.3A0, A1, A2The A0, A1 and A2 inputs are used by the 24AA014H/ 24LC014H for multiple device operations. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true.Up to eight 24AA014H/24LC014H devices may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either V CC or V SS.In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’before normal device operation can proceed.2.4WPWP is the hardware write-protect pin. It must be tied to V CC or V SS. If tied to V CC, the hardware write protection is enabled and will protect half of the array (40h-7Fh). If the WP pin is tied to V SS the hardware write protection is disabled.2.5Noise ProtectionThe 24AA014H/24LC014H employs a V CC threshold detector circuit that disables the internal erase/write logic if the V CC is below 1.5 volts at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits that suppress noise spikes to assure proper device operation even on a noisy bus.Name 8-pinPDIP8-pinSOIC8-pinTSSOP8-pinMSOP8-pinTDFNFunctionA011111User Configurable Chip SelectA122222User Configurable Chip SelectA233333User Configurable Chip SelectV SS44444GroundSDA55555Serial DataSCL66666Serial ClockWP77777Write-Protect InputV CC88888+1.7V to 5.5V (24AA014H)+2.5V to 5.5V (24LC014H)© 2008 Microchip Technology Inc.Preliminary DS22077B-page 524AA014H/24LC014HDS22077B-page 6Preliminary© 2008 Microchip Technology Inc.3.0FUNCTIONAL DESCRIPTIONThe 24AA014H/24LC014H supports a bidirectional,2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter,and a device receiving data as receiver. The bus has to be controlled by a master device that generates the Serial Clock (SCL), controls the bus access and gen-erates the Start and Stop conditions while the 24AA014H/24LC014H works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.4.0BUS CHARACTERISTICSThe following bus protocol has been defined:•Data transfer may be initiated only when the bus is not busy.•During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition.Accordingly, the following bus conditions have been defined (Figure 4-1).4.1Bus Not Busy (A)Both data and clock lines remain high.4.2Start Data Transfer (B)A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.4.3Stop Data Transfer (C)A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition.4.4Data Valid (D)The state of the data line represents valid data when,after a Start condition, the data line is stable for the duration of the high period of the clock signal.The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse.Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the master device and is,theoretically, unlimited, though only the last sixteen will be stored when doing a write operation. When an overwrite does occur, it will replace data in a first-in first-out fashion.4.5AcknowledgeEach receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit.The device that acknowledges has to pull down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge-related clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case,the slave must leave the data line high to enable the master to generate the Stop condition (Figure 4-2).Note:The 24AA014H/24LC014H does not gen-erate any Acknowledge bits if an internal programming cycle is in progress.24AA014H/24LC014H© 2008 Microchip Technology Inc.Preliminary DS22077B-page 724AA014H/24LC014HDS22077B-page 8Preliminary© 2008 Microchip Technology Inc.5.0DEVICE ADDRESSINGA control byte is the first byte received following the Start condition from the master device (Figure 5-1).The control byte consists of a four-bit control code; for the 24AA014H/24LC014H this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24AA014H/24LC014H devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are in effect the three Most Significant bits of the word address.The last bit of the control byte defines the operation to be performed. When set to a ‘1’, a read operation is selected. When set to a ‘0’, a write operation is selected. Following the Start condition, the 24AA014H/24LC014H monitors the SDA bus, checking the control byte being transmitted. Upon receiving a ‘1010’ code and appropriate Chip Select bits, the slave device outputs an Acknowledge signal on the SDA line.24LC014H will select a read or write operation.FIGURE 5-1:CONTROL BYTE FORMAT5.1Contiguous Addressing Across Multiple DevicesThe Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to 8K bits by adding up to eight 24AA014H/24LC014H devices on the same bus. In this case, software can use A0 of the control byte as address bit A8, A1 as address bit A9,and A2 as address bit A10. It is not possible to sequentially read across device boundaries.11A2A1A0SACKR/W Control CodeChip SelectBits Slave AddressAcknowledge BitStart BitRead/Write Bit© 2008 Microchip Technology Inc.PreliminaryDS22077B-page 924AA014H/24LC014H6.0WRITE OPERATIONS6.1Byte WriteFollowing the Start signal from the master, the device code(4 bits), the Chip Select bits (3 bits) and the R/W bit (which is a logic low) are placed onto the bus by the master transmitter. The device will acknowledge this control byte during the ninth clock pulse. The next byte transmitted by the master is the word address and will be written into the Address Pointer of the 24AA014H/24LC014H. After receiving another Acknowledge signal from the 24AA014H/24LC014H, the master device will transmit the data word to be written into the addressed memory location. The 24AA014H/24LC014H acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and the 24AA014H/24LC014H will not generate Acknowledge signals during this time (Figure 6-1). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled, the device will acknowledge the command, but no data will be written.The write cycle time must be observed even if write protection is enabled.6.2Page WriteThe write-control byte, word address and the first data byte are transmitted to the 24AA014H/24LC014H in the same way as in a byte write. But instead of generating a Stop condition, the master transmits up to 15additional data bytes to the 24AA014H/24LC014H that are temporarily stored in the on-chip page buffer and will be written into the memory once the master has transmitted a Stop condition. Upon receipt of each word, the four lower order Address Pointer bits are internally incremented by one.The higher order four bits of the word address remain constant. If the master should transmit more than 16bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the protected portion of the array when the hardware write protection has been enabled,the device will acknowledge the command, but no data will be written. The write cycle time must be observed even if write protection is enabled.6.3Write ProtectionThe WP pin must be tied to V CC or V SS . If tied to V CC ,half of the array will be write-protected (40h-7Fh). If the WP pin is tied to V SS , write operations to all address locations are allowed.FIGURE 6-1:BYTE WRITEFIGURE 6-2:PAGE WRITENote:Page write operations are limited to writing bytes within a single physical page,regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size – 1]. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary that the application software prevent page write operations that would attempt to cross a page boundary.SPBus Activity Master SDA Line Bus ActivityS T A R T S T O P Control ByteWord AddressDataA C KA C KA C KSPBus Activity Master SDA Line Bus ActivityS T A R T Control ByteWord Address (n)Data (n)Data (n + 15)S T O P A C KA C KA C KA C KA C KData (n +1)24AA014H/24LC014HDS22077B-page 10Preliminary© 2008 Microchip Technology Inc.7.0ACKNOWLEDGE POLLINGSince the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write command has been issued from the master, the device initiates the internally-timed write cycle and ACK polling can be initiated immediately. This involves the master sending a Start condition followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, no ACK will be returned. If no ACK is returned, the Start bit and control byte must be re-sent. If the cycle is complete, the device will return the ACK and the master can then proceed with the next Read or Write command. See Figure 7-1 for a flow diagram of this operation.FIGURE 7-1:ACKNOWLEDGE POLLING FLOWSendWrite CommandSend Stop Condition to Initiate Write CycleSend StartSend Control Byte with R/W = 0Did Device Acknowledge (ACK = 0)?Next OperationNoYes分销商库存信息:MICROCHIP24AA014H-I/SN24LC014H-I/MS24LC014HT-I/MNY 24AA014HT-I/MNY24AA014H-I/P24AA014HT-I/SN 24LC014HT-I/SN24AA014H-I/MS24LC014H-I/ST24AA014H-I/ST24AA014HT-I/MS24AA014HT-I/ST 24LC014HT-I/MS24LC014HT-I/ST24LC014H-E/SN24LC014HT-E/SN24LC014H-E/MS24LC014H-E/ST24LC014HT-E/ST24LC014HT-E/MS24LC014HT-E/MNY 24LC014H-E/P24LC014H-I/SN24LC014H-I/P。

Belling BL24CM1A 1M位 EEPROM 产品说明书

Features⚫Compatible with all I2C bidirectional data transfer protocol⚫Memory array:–1024 Kbits (128 Kbytes) of EEPROM–Page size: 256 bytes–Additional Write lockable page⚫Single supply voltage and high speed:–⚫Random and sequential Read modes⚫Write:–Byte Write within 5 ms–Page Write within 5 ms–Partial Page Writes Allowed⚫Write Protect Pin for Hardware Data Protection ⚫Schmitt Trigger, Filtered Inputs for Noise Suppression⚫High-reliability–Endurance: 4 Million Write Cycles–Data Retention: 100 Years⚫Enhanced ESD/Latch-up protection–HBM 8000V⚫8-lead PDIP/SOP/TSSOP/UDFN/WLCSP packagesDescription⚫The BL24CM1A provides 1048576 bits of serial electrically erasable and programmable read-only memory (EEPROM), organized as 131072 words of 8 bits each.⚫The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. ⚫The BL24CM1A offers an additional page, named the Identification Page (256 bytes). The Identification Page can be used to store sensitive application parameters which can be (later) permanently locked in Read-only mode.Pin ConfigurationNC A1 A2 GNDVCCWPNCA1A2GNDNCA1A2GNDVCCWPVCCWP １２３４8765１２３４１２３４87658765８-lead PDIP８-lead SOP８-lead TSSOPSCLSDASCLSDASCLSDAWLCSPSDA VccSCLA2A1NCGNDWPNCA1A2GNDVCCWP１２３４8765UDFNSCLSDAPin DescriptionsPin Name Type Functions A1-A2I Address Inputs SDA I/O Serial Data SCL I Serial Clock Input WP I Write ProtectGND P Ground VccPPower SupplyBlock DiagramSTART STOP LOGICSERIAL CONTROLLOGICSCL SDAGNDVcc DEVICE ADDRESS COMPARATORLOADCCMPDATA WORD ADRESS COUNTERLOADINCX DECODERY DECODER SERIAL MUXEEPROMENDATA RECOVERY HIGH VOLTAGE PUMP/TIMINGDOUT/ACKNOWLEDGEDINDOUTA1A2WPDEVICE/PAGE ADDRESSES (A2 and A1): The A2 and A1 pins are device address inputs that are hard wirefor the BL24CM1A. Four 1M devices may be addressed on a single bus system (device addressing is discussedin detail under the Device Addressing section).SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices.SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.WRITE PROTECT (WP): The BL24CM1A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protection pin is connected to Vcc, the write protection feature is enabled and operates as shown in the following Table 2.Table 1Figure 1WP Pin Status BL24CM1AAt VCC Full(1024K)ArrayAt GND Normal Read/Write OperationsTable 2Functional Description1. Memory OrganizationBL24CM1A, 1M SERIAL EEPROM: Internally organized with 512 pages of 256 bytes each, the 1M requires a 17-bit data word address for random word addressing.2. Device OperationCLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (see Figure 2). Data changes during SCL high periods will indicate a start or stop condition as defined below.START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see Figure 3).STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see Figure 3).ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle.STANDBY MODE: The BL24CM1A features a low-power standby mode which is enabled: (a) upon power-up and (b) after the receipt of the STOP bit and the completion of any internal operations.MEMORY RESET: After an interruption in protocol, power loss or system reset, any two-wire part can be reset by following these steps:1. Clock up to 9 cycles.2. Look for SDA high in each cycle while SCL is high.3. Create a start condition.DATA STABLEDATA STABLEDATA CHANGESDASCLFigure 2. Data ValiditySDASCLSTARTSTOPFigure 3. Start and Stop DefinitionSCL DATA INDATA OUTSTARTACKNOWLEDGE189Figure 4. Output Acknowledge3. Device AddressingThe 1M EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see Figure 5)The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices.The 1M EEPROM uses A2 and A1 device address bits and one world address bit to allow as much as four devices on the same bus. These 2 device address bits must be compared to their corresponding hardwired input pins. The A2 and A1 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float.The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low.Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state.MSB LSB1010A2A1B16R/WB15B14B13B12B11B10B9B8B7B6B5B4B3B2B1B0Figure 5. Device Address and two 8-bit data word addressDATA SECURITY: The BL24CM1A has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC.4. Write OperationsBYTE WRITE: A write operation requires two 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 6).SDA LINE STARTDEVICEADDRESSWRITEMSBLSBR/WACKFIRST WORDADDRESSSECOND WORDADDRESSACKLSBACKLSBACKLSBSTOPDATAFigure 6. Byte WritePAGE WRITE: The Page Write mode allows up to 256 bytes to be written in a single Write cycle. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 255 more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 7).ST A R TDEVICEADDRESSWRITEMSBLSBR/WACKFIRST WORDADDRESSSECOND WORDADDRESSACKLSBACKLSBACKSTOPDATA(n)ACKACKDATA(n+1)DATA(n+1)SDALINEFigure 7. Page WriteThe data word address lower eight bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 256 data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten.WRITE IDENTIFICATION PAGE: The Identification Page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. It is written by issuing the Write Identification Page instruction. This instruction uses the same protocol and format as Page Write (into memory array), except for the following differences:•Device type identifier = 1011b•MSB address bits B16/B8 are don't care except for address bit B10 which must be "0".LSB address bits B7/B0 define the byte address inside the Identification page.If the Identification page is locked, the data bytes transferred during the Write Identification Page instruction are not acknowledged (NoAck).ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue.5. Read OperationsRead operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read.CURRENT ADDRESS READ:The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 8).ST A R TDEVICEADDRESSREADMSBLSBR/WACKSTOPDATANOACKSDALINEFigure 8. Current Address ReadRANDOM READ:A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 9)STA R TDEVICEADDRESSWRITEMSBLSBR/WACK1st,2nd WORDADDRESSACKLSBSTOPDATA(n)DEVICEADDRESSSTARTREADACKNOACK DUMMY WRITESDALINEFigure 9. Random ReadSEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. The sequential read operation is terminated when the microcontroller does not respond with a "0" but does generate a following stop condition (see Figure 10).DEVICE ADDRESS READR/WACKACKACKACKSTOP DATA(n)DATA(n+1)DATA(n+2)DATA(n+x)NOACKSDALINEFigure 10. Sequential ReadREAD IDENTIFICATION PAGE: The Identification Page (256 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode.The Identification Page can be read by issuing an Read Identification Page instruction. This instruction uses the same protocol and format as the Random Address Read (from memory array) with device type identifier defined as 1011b. The MSB address bits B16/B8 are don't care, the LSB address bits B7/B0 define the byte address inside the Identification Page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the Identification Page from location 10d, the number of bytes should be less than or equal to 246, as the ID page boundary is 256 bytes)LOCK IDENTIFICATION PAGE: The Lock Identification Page instruction (Lock ID) permanently locks the Identification page in Read-only mode. The Lock ID instruction is similar to Byte Write (into memory array) with the following specific conditions:Device type identifier = 1011bAddress bit B10 must be ‘1’; all other address bits are don't careThe data byte must be equal to the binary value xxxx xx1x, where x is don't careElectrical CharacteristicsAbsolute Maximum Stress Ratings：⚫DC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.5V⚫Input / Output Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND-0.3V to VCC+0.3V⚫Operating Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40℃ to +85℃⚫Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65℃ to +150℃⚫Electrostatic pulse (Human Body model) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8000VComments：Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.DC Electrical CharacteristicsApplicable over recommended operating range from: TA = -40℃to +85℃, VCC = +2.0V to +5.5V (unless otherwise noted)Parameter Symbol Min Typ Max Unit Condition Supply Voltage V CC1 2.0- 5.5V-Supply Current VCC=5.0V I CC1-0.260.5mA READ at 400KHZSupply Current VCC=5.0V I CC2-0.280.5mA WRITE at 400KHZSupply Current VCC=5.0V I SB1-0.030.5μA V IN=V CC or V SSInput Leakage Current I L1-0.10 1.0μA V IN=V CC or V SSOutput Leakage Current I LO-0.05 1.0μA V OUT=V CC or V SSInput Low Level V IL1-0.3-V CC×0.3V V CC=1.7V to 5.5VInput High Level V IH1V CC×0.7-V CC+0.3V V CC=1.7V to 5.5VOutput Low Level VCC=1.7V V OL1--0.2V I OL=2.1mAOutput Low Level VCC=5.0V V OL2--0.4V I OL=3.0mATable 3Pin CapacitanceParameter Symbol Min Typ Max Unit ConditionInput/Output Capacitance(SDA)C I/O--8pF V IO=0VInput Capacitance(A1,A2,SCL)C IN--6pF V IN=0VTable 4AC Electrical CharacteristicsApplicable over recommended operating range from TA = -40℃ to +85℃, VCC = +2.0V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted)Min Typ Max Min Typ Max Clock Frequency,SCL f SCL --400--1000KHZ Clock Pulse Width Low t LOW 1.3--0.5--μs Clock Pulse Width High t HIGH 0.6--0.26--μs Noise Suppression Time t I --50--50ns Clock Low to Data Out Valid t AA --0.9--0.45μs Time the bus must be free before a new transmission can start t BUF 1.3--0.5--μs Start Hold Time t HD:STA 0.6--0.25--μs Start Setup Time t SU:STA 0.6--0.25--μs Data In Hold Time t HD:DAT 0--0--μs Data in Setup Time t SU:DAT 100--100--ns Input Rise Time(1)t R --0.3--0.12μs Input Fall Time(1)t F --0.3--0.12μs Stop Setup Time t Su:STO 0.6--0.25--μs Data Out Hold Time t DH 50--50--ns Write Cycle Time t WR - 3.55- 3.55ms 5.0V,25℃,Byte Mode(1)Endurance4M--4M--Write CycleParameterSymbol 2.0V ≤V CC ﹤2.5V 2.5V ≤V CC ﹤5.5V UnitsNotes:1. This parameter is characterized and is not 100% tested.2. AC measurement conditions: RL (connects to VCC): 1.3 kInput pulse voltages: 0.3 VCC to 0.7 VCC Input rise and fall time: 50 nsInput and output timing reference voltages: 0.5 VCCThe value of RL should be concerned according to the actual loading on the user's system.Table 5Bus TimingSCLSDA_INSDA_OUTt SU.STAt HD.STAt LOW t Ft HIGHt LOWt HD.DATt SU.DATt Rt SU.STOt BUFt DHt AAFigure 11. SCL: Serial Clock, SDA: Serial Data I/OWrite Cycle TimingtWR(1)ACKSTOP CONDITIONSTART CONDITIONSCLSDAWord nFigure 12. SCL: Serial Clock, SDA: Serial Data I/ONotes:The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.Package InformationPDIP Outline Dimensionsb2eLAA2ceA E1COMMON DIMENSIONS (Unit of Measure=mm)SYMBOL MIN NOM MAX A 3.60 3.80 4.00A2 3.20 3.30 3.40b 0.44-0.53b2c 0.24-0.32D 9.059.259.45E1 6.156.35 6.55e eA eB 7.62-9.30L2.54BSC 7.62BSC1.52BSC3.00BSCeBDEBe A A1DE1LΦSYMBOL MIN NOM MAXA 1.35- 1.75A10.10-0.23 B0.39-0.48 C0.21-0.26D 4.70 4.90 5.10E1 3.70 3.90 4.10E 5.80 6.00 6.20eL0.50-0.80Φ0"-8"1.27BSCCOMMON DIMENSIONS(Unit of Measure=mm)CE1E Top ViewD ebA1A Side ViewL1LEnd ViewSYMBOL MIN NOM MAXD 2.90 3.00 3.10E 6.20 6.40 6.60E1 4.30 4.40 4.50A-- 1.20A10.05-0.15b0.21-0.30eL0.450.600.75L10.65BSC1.00REFCOMMON DIMENSIONSUnit of Measure=mmPIN 1 DOT BY MARKINGTOP VIEWb eLD2E2ED A3AA1PIN #1 IDENTIFICATIONCHAMFERPKG REF MIN NOM MAX A 0.500.550.60A10.00-0.05A3D 1.95 2.00 2.05E 2.95 3.00 3.05b 0.200.250.30L 0.200.300.40D2 1.25 1.40 1.50E2 1.15 1.30 1.40eCOMMON DIMENSION(MM)UT:ULTRA THIN 0.15REF0.50BSCBOTTOM VIEWSIDE VIEWWLCSPEG GA2A A1be1FFe 2eSYMBOL MIN NOM MAX A 0.4250.4650.505A10.1700.1900.210A20.2550.2750.295D 1.944 1.964 1.984E 1.4801.500 1.520e e1e2e3b F 0.5290.5490.569G0.2300.2500.2700.500BSC 0.500BSC 1.000BSC 0.270BSC 0.866BSC DMarking DiagramSOPBL24CM1ASSSSSPSSSSS : Lot IDTSSOPBL24CM1ASSSSSSSSSS : Lot IDUDFNBLFAYYWWYY: yearWW :weekWLCSPAYWY:The last digits of the yearW:week code.Y1...345 (90)Year2011...201320142015 (20192020)W A…Y Z a…y zWeek1...252627 (5152)Ordering InformationBL 24C M1 A-PA R CFeatureS: Standard (default, Pb Free RoHS Std.)C: Green (Halogen Free)Packing typeR: Tape and ReelT: TubePackage TypePA: SOP-8LSF: TSSOP-8LNT: UDFN-8LCS: WLCSPDA: PDIP-8LGenerationA: A VersionDensityM1: 1MbitProduct Family24C: IIC Interface EEPROMRevision historyVersion 1.00 BL24CM1AInitial versionVersion 1.01 BL24CM1AAdd WLCSP and UDFN Package informationVersion 1.02 BL24CM1AUpdate the Package Information。

24AA256T-ESN资料

© 2007 Microchip Technology Inc.DS21930B-page 124AA00/24LC00/24C00 24AA01/24LC01B 24AA014/24LC01424C01C 24AA02/24LC02B 24C02C24AA024/24LC024 24AA025/24LC02524AA04/24LC04B 24AA08/24LC08B 24AA16/24LC16B 24AA32A/24LC32A 24AA64/24LC64/24FC6424AA128/24LC128/24FC12824AA256/24LC256/24FC256 24AA512/24LC512/24FC512Features:•128-bit through 512 Kbit devices•Single supply with operation down to 1.7V for 24AAXX devices•Low-power CMOS technology:-1mA active current, typical-1μA standby current, typical (I-temp)•2-wire serial interface bus, I 2C™ compatible •Schmitt Trigger inputs for noise suppression •Output slope control to eliminate ground bounce •100kHz (1.7V) and 400kHz (≥ 2.5V) compatibility • 1 MHz for 24FCXX products•Self-timed write cycle (including auto-erase)•Page write buffer•Hardware write-protect available on most devices •Factory programming (QTP) available •ESD protection > 4,000V • 1 million erase/write cycles •Data retention > 200 years•8-lead PDIP , SOIC, TSSOP and MSOP packages •5-lead SOT-23 package (most 1-16 Kbit devices)•8-lead 2x3mm and 5x6mm DFN packages available•Pb-free and RoHS compliant•Available for extended temperature ranges:-Industrial (I): -40°C to +85°C -Automotive (E): -40°C to +125°CDescription:The Microchip Technology Inc. 24CXX, 24LCXX,24AAXX and 24FCXX (24XX*) devices are a family of 128-bit through 512 Kbit Electrically Erased PROMs.The devices are organized in blocks of x8-bit memory with 2-wire serial interfaces. Low-voltage design permits operation down to 1.7V (for 24AAXX devices),with standby and active currents of only 1 μA and 1mA, respectively. Devices 1 Kbit and larger have page write capability. Parts having functional address lines allow connection of up to 8 devices on the same bus.The 24XX family is available in the standard 8-pin PDIP , surface mount SOIC, TSSOP and MSOP pack-ages. Most 128-bit through 16 Kbit devices are also available in the 5-lead SOT-23 package. DFN packages (2x3mm or 5x6mm) are also available. All packages are Pb-free (Matte Tin) finish.*24XX is used in this document as a generic part number for 24 series devices in this data sheet.24XX64, for example, represents all voltages of the 64Kbit device.Package Types (1)A0A1A2V SS12348765V CC WP (3)SCL SDAPDIP/SOICA0A1A2V SS12348765V CC WP (3)SCL SDA TSSOP/MSOP (2)1543SCL V SS SDAV CCNC 2SOT-23-5(24XX00)SOT-23-51543SCL V SS SDAWPV CC 2(all except 24XX00)A0A1A2V SS WP (3)SCL SDA56784321V CC DFNNote 1:Pins A0, A1, A2 and WP are not used by some devices (no internal connections). See Table 1-1,Device Selection Table, for details.2:Pins A0 and A1 are no-connects for the 24XX128and 24XX256 MSOP devices.3:Pin 7 is “not used” for 24XX00, 24XX025 and 24C01C.I 2C ™ Serial EEPROM Family Data Sheet24AAXX/24LCXX/24FCXXDS21930B-page 2© 2007 Microchip Technology Inc.TABLE 1-1:DEVICE SELECTION TABLEPart Number V CC RangeMax. Clock FrequencyPage SizeWrite-Protect SchemeFunctional Address PinsTemp. RangePackages (5)128-bit devices 24AA00 1.7-5.5V 400 kHz (1)—NoneNoneI P , SN, ST, OT, MC24LC00 2.5-5.5V 400 kHz (1)I 24C00 4.5-5.5V400 kHzI, E1 Kb devices 24AA01 1.7-5.5V 400 kHz (2)8 bytes Entire Array None I P , SN, ST, MS, OT, MC24LC01B 2.5-5.5V 400 kHz I, E 24AA014 1.7-5.5V 400 kHz (2)16 bytes Entire Array A0, A1, A2I P , SN, ST, MS, MC 24LC014 2.5-5.5V400 kHzI 24C01C 4.5V-5.5V 400 kHz16 bytesNoneA0, A1, A2I, EP , SN, ST, MC 2 Kb devices 24AA02 1.7-5.5V 400 kHz (2)8 bytes Entire Array None I P , SN, ST, MS, OT, MC24LC02B 2.5-5.5V 400 kHz I, E 24AA024 1.7-5.5V 400 kHz (2)16 bytes Entire Array A0, A1, A2I P , SN, ST, MS, MC 24LC024 2.5-5.5V 400 kHz I 24AA025 1.7-5.5V 400 kHz (2)16 bytes None A0, A1, A2I P , SN, ST,MS, MC 24LC025 2.5-5.5V 400 kHz I 24C02C 4.5-5.5V400 kHz16 bytesUpper Half of ArrayA0, A1, A2I, EP , SN, ST, MC 4 Kb devices 24AA04 1.7-5.5V 400 kHz (2)16 bytesEntire ArrayNoneI P , SN, ST, MS, OT, MC24LC04B 2.5-5.5V400 kHzI, E8 Kb devices 24AA08 1.7-5.5V 400 kHz (2)16 bytesEntire ArrayNoneI P , SN, ST, MS, OT, MC24LC08B 2.5-5.5V400 kHzI, E16 Kb devices 24AA16 1.7-5.5V 400 kHz (2)16 bytesEntire ArrayNoneI P , SN, ST, MS, OT, MC24LC16B 2.5-5.5V400 kHzI, E32 Kb devices 24AA32A 1.7-5.5V 400 kHz (2)32 bytesEntire ArrayA0, A1, A2I P , SN, SM, ST, MS, MC24LC32A 2.5-5.5V400 kHzI, E64 Kb devices 24AA64 1.7-5.5V 400 kHz (2)32 bytesEntire ArrayA0, A1, A2I P , SN, SM, ST, MS, MC24LC64 2.5-5.5V 400 kHz I, E 24FC641.7-5.5V1 MHz (3)INote 1:100 kHz for V CC <4.5V.2:100 kHz for V CC <2.5V.3:400 kHz for V CC <2.5V.4:Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package.5:P = 8-PDIP , SN = 8-SOIC (3.90 mm JEDEC), ST = 8-TSSOP , OT = 5 or 6-SOT23, MC = 2x3mm DFN,MS = 8-MSOP , SM = 8-SOIC (200 mil EIAJ), MF = 5x6mm DFN.© 2007 Microchip Technology Inc.DS21930B-page 324AAXX/24LCXX/24FCXX128 Kb devices 24AA128 1.7-5.5V 400 kHz (2)64 bytesEntire ArrayA0, A1, A2(4)I P , SN, SM, ST, MS, MF, ST1424LC128 2.5-5.5V 400 kHz I, E 24FC128 1.7-5.5V1 MHz (3)I256 Kb devices 24AA256 1.7-5.5V 400 kHz (2)64 bytesEntire ArrayA0, A1, A2(4)I P , SN, SM, ST, MS, MF, ST1424LC256 2.5-5.5V 400 kHz I, E 24FC256 1.7-5.5V1 MHz (3)I512 Kb devices 24AA512 1.7-5.5V 400 kHz (2)128 bytesEntire ArrayA0, A1, A2IP , SM, MF, ST1424LC512 2.5-5.5V400 kHzI, E 24FC5121.7-5.5V (3) 1 MHzITABLE 1-1:DEVICE SELECTION TABLE (CONTINUED)Part Number V CC RangeMax. Clock FrequencyPage SizeWrite-Protect SchemeFunctional Address PinsTemp. RangePackages (5)Note 1:100 kHz for V CC <4.5V.2:100 kHz for V CC <2.5V.3:400 kHz for V CC <2.5V.4:Pins A0 and A1 are no-connects for the 24XX128 and 24XX256 in the MSOP package.5:P = 8-PDIP , SN = 8-SOIC (3.90 mm JEDEC), ST = 8-TSSOP , OT = 5 or 6-SOT23, MC = 2x3mm DFN,MS = 8-MSOP , SM = 8-SOIC (200 mil EIAJ), MF = 5x6mm DFN.24AAXX/24LCXX/24FCXXDS21930B-page 4© 2007 Microchip Technology Inc.2.0ELECTRICAL CHARACTERISTICSAbsolute Maximum Ratings (†)V CC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. V SS .........................................................................................................-0.6V to V CC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥4kVTABLE 2-1:DC CHARACTERISTICS† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.DC CHARACTERISTICS Electrical Characteristics:Industrial (I):V CC = +1.7V to 5.5V T A = -40°C to +85°C Automotive (E):V CC = +2.5V to 5.5V T A = -40°C to 125°CParam.No.Sym.CharacteristicMin.Max.Units ConditionsD1—A0, A1, A2, SCL, SDA and WP pins:————D2V IH High-level input voltage 0.7 V CC—V —D3V IL Low-level input voltage—0.3 V CC 0.2 V CCV V V CC ≥ 2.5V V CC < 2.5V D4V HYS Hysteresis of Schmitt Trigger inputs (SDA, SCL pins)0.05 V CC —V (Note 1)D5V OL Low-level output voltage —0.40V I OL = 3.0mA @ V CC = 2.5V D6I LI Input leakage current —±1μA V IN = V SS or V CC D7I LO Output leakage current —±1μA V OUT = V SS or V CC D8C IN , C OUTPin capacitance (all inputs/outputs)—10pF V CC = 5.0V (Note 1)T A = 25°C, F CLK = 1MHz D9I CC Read Operating current—4001μA mA 24XX128, 256, 512: V CC = 5.5V, SCL = 400 kHzAll except 24XX128, 256, 512: V CC = 5.5V, SCL = 400 kHz I CC Write—35mA mA V CC = 5.5V, All except 24XX512V CC = 5.5V, 24XX512D10I CCSStandby current—1μAT A = -40°C to +85°CSCL = SDA = V CC = 5.5V A0, A1, A2, WP = V SS or V CC —5μAT A = -40°C to 125°CSCL = SDA = V CC = 5.5V A0, A1, A2, WP = V SS or V CC —50μA24C01C and 24C02C only SCL = SDA = V CC = 5.5V A0, A1, A2, WP = V SS or V CCNote 1:This parameter is periodically sampled and not 100% tested.24AAXX/24LCXX/24FCXX TABLE 2-2:AC CHARACTERISTICS – ALL EXCEPT 24XX00, 24C01CAND 24C02CAC CHARACTERISTICS Electrical Characteristics:Industrial (I):V CC = +1.7V to 5.5V T A = -40°C to +85°C Automotive (E):V CC = +2.5V to 5.5V T A = -40°C to 125°CParam.No.Sym.Characteristic Min.Max.Units Conditions1F CLK Clock frequency————1004004001000kHz 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX2T HIGH Clock high time4000600600500————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX3T LOW Clock low time470013001300500————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX4T R SDA and SCL rise time(Note1)———1000300300ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC≤ 5.5V 24FCXXX5T F SDA and SCL fall time(Note1)——300100ns All except 24FCXXX1.7V ≤ V CC≤ 5.5V 24FCXXX6T HD:STA Start condition hold time4000600600250————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX7T SU:STA Start condition setup time4700600600250————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX8T HD:DAT Data input hold time0—ns(Note2)9T SU:DAT Data input setup time250100100———ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC≤ 5.5V 24FCXXX10T SU:STO Stop condition setup time4000600600250————ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC<2.5V 24FCXXX2.5V ≤ V CC≤ 5.5V 24FCXXX11T SU:WP WP setup time4000600600———ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC≤ 5.5V 24FCXXX12T HD:WP WP hold time470013001300———ns 1.7V ≤ V CC< 2.5V2.5V ≤ V CC≤ 5.5V1.7V ≤ V CC≤ 5.5V 24FCXXXNote1:Not 100% tested. C B = total capacitance of one bus line in pF.2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3:This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site:.4:24FCXXX denotes the 24FC64, 24FC128, 24FC256 and 24FC512 devices.© 2007 Microchip Technology Inc.DS21930B-page 524AAXX/24LCXX/24FCXXDS21930B-page 6© 2007 Microchip Technology Inc.13T AAOutput valid from clock (Note 2)————3500900900400ns1.7V ≤ V CC <2.5V 2.5V ≤ V CC ≤ 5.5V1.7V ≤ V CC <2.5V 24FCXXX 2.5V ≤ V CC ≤ 5.5V 24FCXXX 14T BUFBus free time: Time the bus must be free before a new transmission can start 470013001300500————ns1.7V ≤ V CC <2.5V 2.5V ≤ V CC ≤ 5.5V1.7V ≤ V CC <2.5V 24FCXXX 2.5V ≤ V CC ≤ 5.5V 24FCXXX 15T OF Output fall time from V IH minimum to V IL maximum C B ≤ 100pF10 + 0.1C B250250nsAll except 24FCXXX (Note 1)24FCXXX (Note 1)16T SP Input filter spike suppression (SDA and SCL pins)—50ns All except 24FCXXX (Note 1)17T WC Write cycle time (byte or page)—5ms18—Endurance1,000,000—cycles 25°C (Note 3)TABLE 2-2:AC CHARACTERISTICS – ALL EXCEPT 24XX00, 24C01C AND 24C02C (CONTINUED)AC CHARACTERISTICS Electrical Characteristics:Industrial (I):V CC = +1.7V to 5.5V T A = -40°C to +85°C Automotive (E):V CC = +2.5V to 5.5V T A = -40°C to 125°CParam.No.Sym.CharacteristicMin.Max.Units ConditionsNote 1:Not 100% tested. C B = total capacitance of one bus line in pF.2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3:This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which can be obtained from Microchip’s web site:.4:24FCXXX denotes the 24FC64, 24FC128, 24FC256 and 24FC512 devices.24AAXX/24LCXX/24FCXX TABLE 2-3:AC CHARACTERISTICS – 24XX00, 24C01C AND 24C02CAll Parameters apply across all recommended operating ranges unless otherwise noted Industrial (I):T A = -40°C to +85°C, V CC = 1.7V to 5.5V Automotive (E):T A = -40°C to +125°C, V CC = 4.5V to 5.5VParameter Symbol Min.Max.Units ConditionsClock frequency F CLK———100100400kHz 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VClock high time T HIGH40004000600———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VClock low time T LOW470047001300———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VSDA and SCL rise time (Note1)T R———10001000300ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VSDA and SCL fall time T F—300ns(Note1)Start condition hold time T HD:STA40004000600———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VStart condition setup time T SU:STA47004700600———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VData input hold time T HD:DAT0—ns(Note2)Data input setup time T SU:DAT250250100———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VStop condition setup time T SU:STO40004000600———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VOutput valid from clock (Note2)T AA———35003500900ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VBus free time: Time the bus must be free before a new transmis-sion can start T BUF470047001300———ns 4.5V ≤ Vcc ≤ 5.5V (E Temp range)1.7V ≤ Vcc ≤ 4.5V4.5V ≤ Vcc ≤5.5VOutput fall time from V IH minimum to V IL maximum T OF20+0.1CB250ns(Note1), CB ≤ 100 pFInput filter spike suppression(SDA and SCL pins)T SP—50ns(Note1)Write cycle time T WC—41.5ms24XX0024C01C, 24C02CEndurance1,000,000—cycles(Note3)Note1:Not 100% tested. C B = total capacitance of one bus line in pF.2:As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.3:This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained at .© 2007 Microchip Technology Inc.DS21930B-page 724AAXX/24LCXX/24FCXXDS21930B-page 8© 2007 Microchip Technology Inc.FIGURE 2-1:BUS TIMING DATA(unprotected)(protected)SCL SDA INSDA OUTWP 57616328913D441011121424AAXX/24LCXX/24FCXX3.0PIN DESCRIPTIONSThe descriptions of the pins are listed in Table3-1.TABLE 3-1:PIN FUNCTION TABLE3.1A0, A1, A2 Chip Address Inputs The A0, A1 and A2 pins are not used by the 24XX01 through 24XX16 devices.The A0, A1 and A2 inputs are used by the 24C01C, 24C02C, 24XX014, 24XX024, 24XX025 and the 24XX32 through 24XX512 for multiple device opera-tions. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true.For the 24XX128 and 24XX256 in the MSOP package only, pins A0 and A1 are not connected.Up to eight devices (two for the 24XX128 and 24XX256 MSOP package) may be connected to the same bus by using different Chip Select bit combinations.In most applications, the chip address inputs A0, A1 and A2 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’before normal device operation can proceed.3.2Serial Data (SDA)This is a bidirectional pin used to transfer addresses and data into and out of the device. It is an open drain terminal. Therefore, the SDA bus requires a pull-up resistor to V CC (typical 10kΩ for 100kHz, 2kΩ for 400kHz and1MHz).For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions.3.3Serial Clock (SCL)This input is used to synchronize the data transfer to and from the device.3.4Write-Protect (WP)This pin must be connected to either V SS or V CC. If tied to V SS, write operations are enabled. If tied to V CC, write operations are inhibited but read operations are not affected. See Table1-1 for the write-protect scheme of each device.3.5Power Supply (V CC)A V CC threshold detect circuit is employed which disables the internal erase/write logic if V CC is below 1.5V at nominal conditions. For the 24C00, 24C01C and 24C02C devices, the erase/write logic is disabled below 3.8V at nominal conditions.Pin Name8-PinPDIP andSOIC8-PinTSSOP andMSOP5-Pin SOT-2324XX005-Pin SOT-23All except24XX0014-PinTSSOP8-Pin5x6 DFN and2x3 DFNFunctionA011(1)——11User configurable Chip Select(3) A122(1)——22User configurable Chip Select(3) A233——63User configurable Chip Select(3) V SS442274GroundSDA553385Serial DataSCL661196Serial Clock(NC)——4—3, 4, 5,10, 11, 12—Not ConnectedWP7(2)7(2)—5137Write-Protect InputV CC8854148Power SupplyNote1:Pins 1 and 2 are not connected for the 24XX128 and 24XX256 MSOP packages.2:Pin 7 is not used for 24XX00, 24XX025 and 24C01C.3:Pins A0, A1 and A2 are not used by some devices (no internal connections). See Table1-1 for details.© 2007 Microchip Technology Inc.DS21930B-page 924AAXX/24LCXX/24FCXXDS21930B-page 10© 2007 Microchip Technology Inc.4.0FUNCTIONAL DESCRIPTIONEach 24XX device supports a bidirectional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a master device which gener-ates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XX works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated.Block DiagramHV GeneratorEEPROM Array Page Latches*YDECXDECSense Amp.R/W ControlM emory C ontrol L ogicI/O C ontrol L ogic I/OA0*A1*A2*SDASCLV CC V SSWP** A0, A1, A2, WP and page latches are not used by some devices.See Table 1-1, Device Selection Table, for details.5.0BUS CHARACTERISTICSThe following bus protocol has been defined:•Data transfer may be initiated only when the busis not busy.•During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure5-1).5.1Bus Not Busy (A)Both data and clock lines remain high.5.2Start Data Transfer (B)A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition.5.3Stop Data Transfer (C)A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition.5.4Data Valid (D)The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal.The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data.Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between Start and Stop conditions is determined by the master device.5.5AcknowledgeEach receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit.The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end-of-data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave.In this case, the slave (24XX) will leave the data line high to enable the master to generate the Stop condition (Figure 5-2).FIGURE 5-1:DATA TRANSFER SEQUENCE ON THE SERIAL BUSFIGURE 5-2:ACKNOWLEDGE TIMINGNote:During a write cycle, the 24XX will not acknowledge commands.SCLSDA(A)(B)(D)(D)(A)(C)Start ConditionAddress or AcknowledgeValid Data Allowed to ChangeStop ConditionSCL 987654321123Transmitter must release the SDA line at this point,allowing the Receiver to pull the SDA line low to acknowledge the previous eight bits of data.Receiver must release the SDA line at this point so the Transmitter can continue sending data.Data from transmitterSDA AcknowledgebitData from transmitter5.6Device Addressing For Devices Without Functional Address PinsA control byte is the first byte received following the Start condition from the master device (Figure 5-3).The control byte begins with a four-bit control code. For the 24XX, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the block-select bits (B2, B1, B0). They are used by the master device to select which of the 256-word blocks of memory are to be accessed. These bits are in effect the three Most Significant bits of the word address. Note that B2, B1 and B0 are “don’t care” for the 24XX00, the 24XX01 and 24XX02. B2 and B1 are “don’t care” for the 24XX04. B2 is “don’t care” for the 24XX08.The last bit of the control byte defines the operation to be performed. When set to ‘1’, a read operation is selected. When set to ‘0’ a write operation is selected.Following the Start condition, the 24XX monitors the SDA bus. Upon receiving a ‘1010’ code, the block Acknowledge signal on the SDA line. The address byte follows the acknowledge.FIGURE 5-3:CONTROL AND ADDRESS BYTE ASSIGNMENTS FOR DEVICES WITHOUT ADDRESS PINSS 1010x x x R/W ACK S 1010x x x R/W ACK S 1010x x x R/W ACK S 1010x xB0R/W ACK S 1010xB1B0R/W ACK S11B2B1B0R/WACK24XX0124XX0224XX0424XX0824XX016x = “don’t care” bitAcknowledge Control CodeStart bitControl ByteBlock Select bitsAddress Byte24XX00Read/Write bit (read = 1, write = 0)x x x x A3..A0x A6.....A0A7......A0A7......A0A7......A0A7......A0bit5.7Device Addressing For Devices With Functional Address PinsA control byte is the first byte received following the Start condition from the master device (Figure 5-4).The control byte begins with a 4-bit control code. For the 24XX, this is set as ‘1010’ binary for read and write operations. The next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24XX devices on the same bus and are used to select which device is accessed.The Chip Select bits in the control byte must corre-spond to the logic levels on the corresponding A2, A1and A0 pins for the device to respond. These bits are,in effect, the three Most Significant bits of the word address.For 24XX128 and 24XX256 in the MSOP package, the A0 and A1 pins are not connected. During device addressing, the A0 and A1 Chip Select bits (Figure 5-4)should be set to ‘0’. Only two 24XX128 or 24XX256MSOP packages can be connected to the same bus.The last bit of the control byte defines the operation to be performed. When set to a ‘1’, a read operation is selected. When set to a ‘0’, a write operation is selected.For higher density devices (24XX32 through 24XX512), the next two bytes received define the address of the first data byte. Depending on the prod-uct density, not all bits in the address high byte are used. A15, A14, A13 and A12 are “don’t care” for 24XX32. A15, A14 and A13 are “don’t care” for 24XX64. A15 and A14 are “don’t care” for 24XX128.A15 is “don’t care” for 24XX256. All address bits are used for the 24XX512. The upper address bits are transferred first, followed by the Less Significant bits.Following the Start condition, the 24XX monitors the SDA bus. Upon receiving a ‘1010’ code, appropriate device select bits and the R/W bit, the slave device out-puts an Acknowledge signal on the SDA line. The address byte(s) follow the acknowledge.FIGURE 5-4:CONTROL AND ADDRESS BYTE ASSIGNMENTS FOR DEVICES WITH ADDRESS PINSS 1010A2A1A0R/W ACK S 1010A2A1A0R/W ACK S 1010A2A1A0R/W ACK S 1010A2A1A0R/W ACK S110A2A1A0R/W ACK24XX6424XX12824XX25624XX512x = “don’t care” bitAcknowledgeControl Code Start bitControl ByteChip Select bits*Address High Byte24XX32Read/Write bitx x x x A11A10A9A8x x xA12A11A10A9A8x xA13A12A11A10A9A8xA14A13A12A11A10A9A8A15A14A13A12A11A10A9A8bitS 1010A2A1A0R/W ACK S 1010A2A1A0R/W ACK S11A2A1A0R/WACKx A6.....A0A7......A0A7......A024XX024/02524C02C 24C01C Address ByteA7......A0A7......A0A7......A0A7......A0A7......A0Address Low Byte* Chip Select bits A1 and A0 must be set to ‘0’ for 24XX128/256 devices in the MSOP package.Control Byte(Read = 1, Write = 0)。

2400数字万用表中文说明书(吉时利)

Keithley 2400 Source Meter•电压源、电流源、电压表、电流表四合一新型仪器，适用于快速直流测试•可选高电压型(1100V)、大电流型(3A) 或大电流脉冲型(10A) 电源／测量•最大功率：20W (2400和2410)，60W (2420)，100W (2425/2430 直流模式)，1kW (2430 脉冲模式)•五位半数字电表, 0.012%准确度•可作六线式奥姆测量•程控电流／电压，并可设定箝制准位•最快速度可达1000点／秒(GPIB接口)•内建快速「通过／失效」比较器，适用于自动化质量管理•数字I/O可直接与其它仪器沟通•IEEE-488和RS-232界面•除量测电压、电流外，并可直接量测电阻、功率、百分率、补偿电阻（Offset Compensated Ω）、变阻器α值（Varistor α）、电压系数，如需做接触检测（ContactCheck），可选用2400C 系列1美商吉時利儀器股份有限公司台灣分公司Keithley 2400系列(2400,2410,2420,2430)多功能电源电表简易操作手册一、功能：•电压源、电流源、电压表、电流表四合一新型仪器，适用于快速直流测试•可选高电压型(1100V)、大电流型(3A) 或大电流脉冲型(10A) 电源／测量•最大功率：20W (2400和2410)，60W (2420)，100W (2430 直流模式)，1kW (2430 脉冲模式)•五位半电表, 0.012%准确度•可作六线式奥姆测量•程控电流／电压，并可设定箝制准位•最快速度可达1000点／秒(GPIB接口)•内建快速「通过／失效」比较器，适用于自动化质量管理•数字I/O可直接与其它仪器沟通•IEEE-488和RS-232界面•除量测电压、电流外，并可直接量测电阻、功率、百分率、补偿电阻（Offset Compensated Ω）、变阻器α值（Varistor α）、电压系数（V oltage Coefficient）二、面板简介：123.456 uA( 量測值) ON（輸出開/關）Vsrc: +00.0000V （電源輸出值）Cmpl:105.000uA（箝位值）图2-1 2400屏幕显示图2美商吉時利儀器股份有限公司台灣分公司屏幕显示：如图2-1所示，屏幕左上方所显示为「量测值」，右上方为「输出开/关」显示，左下方为「电源输出值」，右下方为「箝位值」显示。

Belden 24 AWG 双绞线 PVC 保护胶电缆说明书

Page 2 of 2
12-30-2012
Color WHITE/RED & RED/WHITE BLUE/WHITE & WHITE/BLUE BLUE/WHITE & WHITE/BLUE BLUE/WHITE & WHITE/BLUE BLUE/RED & RED/BLUE
Notes
Item Desc CAT5 1PR XCONN REEL CAT5 1PR X-CONN KOC CAT5 1PR X-CONN KOC CAT5 1PR X-CONN REEL CAT5 1PR X-CONN REEL
CA Prop 65 (CJ for Wire & Cable):
Yes
MII Order #39 (China RoHS):
Yes
Other Specification:
Meets Category 5 NEXT performance requirements as specified by TIA/EIA 568 B-2
All sales of Belden products are subject to Belden's standard terms and conditions of sale. Belden believes this product to be in compliance with EU RoHS (Directive 2002/95/EC, 27-Jan-2003). Material manufactured prior to the compliance date may be in stock at Belden facilities and in our Distributor’s inventory. The information provided in this Product Disclosure, and the identification of materials listed as reportable or restricted within the Product Disclosure, is correct to the best of Belden’s knowledge, information, and belief at the date of its publication. The information provided in this Product Disclosure is designed only as a general guide for the safe handling, storage, and any other operation of the product itself or the one that it becomes a part of. This Product Disclosure is not to be considered a warranty or quality specification. Regulatory information is for guidance purposes only. Product users are responsible for determining the applicability of legislation and regulations based on their individual usage of the product.

华师一附中2024届高三《导数的应用——不等式恒成立大题》答案

一轮复习补充作业3：导数的应用——不等式恒成立大题1．（1）()()2()2(2)122x x x xf x e ae a e e a '=++−=++−1︒当20a −≥即2a ≥时，()0f x '>恒成立，()f x ∴在(,)−∞+∞上单调递增2︒当20a −<即2a <时，当()0f x '=时，2ln2a x −=，()0f x ∴'>时，2ln 2ax −>；()0f x '<时，2ln2a x −<，()f x ∴在2,ln 2a −⎛⎫−∞ ⎪⎝⎭上单调递减，2ln ,2a −⎛⎫+∞ ⎪⎝⎭上单调递增综上所述：2a ≥时，()f x 在(,)−∞+∞上单调递增；2a <时，()f x 在2,ln2a −⎛⎫−∞ ⎪⎝⎭上单调递减，2ln ,2a −⎛⎫+∞ ⎪⎝⎭上单调递增（2）1︒当2a =时，22()202xx af x ee −=+>=恒成立，2a ∴= 2︒当2a >时，当302(2)a x a −<<−时，232()(2)1(2)122x x a af x e ae a x a a x a −=++−<++−<+−=，此时a 无解.3︒当2a <时，由（1）知()f x 在2,ln2a −⎛⎫−∞ ⎪⎝⎭上单调递减，2ln,2a −⎛⎫+∞ ⎪⎝⎭上单调递增， 222222()ln (2)ln22222a a a a a f x f a a −−−−−⎛⎫⎛⎫⎛⎫∴≥=++−> ⎪ ⎪ ⎪⎝⎭⎝⎭⎝⎭，整理得4ln(2)4ln 20a a −−+> 记()4ln(2)4ln 2,2g a a a a =−−+<.则46()1022ag a a a−'=+=>−−恒成立，故()g x 在(,2)−∞上单调递增，(0)0g =，()4ln(2)4ln 20(0)g a a a g ∴=−−+>=，02a ∴<<。

电度表铭牌内容的含义

电度表铭牌内容的含义在电度表的铭牌上咱们可以看到以下一些名词：单相、三相、有功、无功等。

铭牌上还标有注册型号：如DDS×××，第一个D是“电能表”的拼音字头，第二个D 是“单相”的拼音字头，S是“静止式(俗称电子式)”英文static的字头。

“×××”代表不同企业生产的不同型式的电表。

我国采用220V的电压制式，交流电的频率是50Hz。

应特别关注标识的电流值：如5(20)A是指大体电流为5A，最大电流为20A。

超负荷用电是不安全的，是引发火灾的隐患。

铭牌上还标有①或②的标志，①代表电能表的准确度为1%，或称1级表；②代表电能表的准确度为2%，或称2级表。

铭牌上还标有产品采用的标准代号、制造厂、商标和出厂编号等。

电度表型号是用字母和数字的排列来表示的，内容如下：类别代号+组别代号+设计序号+派生号。

如我们常用的家用单相电度表：DD862-4型、DDS97l型、DDSY97l型等。

1、类别代号: D--电度表2、组别代号表示相线：D--单相；S--三相三线；T--三相四线。

表示用途的分类：D--多功能；S--电子式；X--无功；Y--预付费；F--复费率。

3、设计序号用阿拉伯数字表示，每个制造厂的设计序号不同，如长纱希麦特电子科技发展有限公司设计生产的电度表产品备案的序列号为971，正泰公司的为666等。

综合上面几点：DD--表示单相电度表：如DD971型DD862型DS--表示三相三线有功电度表：如DS862，DS97l型DT--表示三相四线有功电度表：如DT862、DT971型DX--表示无功电度表：如DX97l、DX864型DDS--表示单相电子式电度表：如DDS97l型D丅S--表示三相四线电子式有功电度表：如DTS97l型DDSY--表示单相电子式预付费电度表：如DDSY97l型DTSF--表示三相四线电子式复费率有功电度表：如DTSF97l型DSSD--表示三相三线多功能电度表：如DSSD97l型关于电度表的话题--电度表的分类电度表是测量电能的专用仪表，是电能计量最基础的设备，普遍用于发电、供电和用电的各个环节，是咱们生活中不可缺少的计量仪表，下面介绍电度表的分类、型号及标牌标志符号的含义。