ST33F1M

EDES Accelerator
NESCRYPT
Code/ Data Signature
MPU
ST ROM Firewall Internal Bus (APB/AHB)
NESCRYPT RAM
CRC Module
Clock Generator Module
Three 16-bit timers
SWP with RAM Buffer
■ ARM® SecurCore® SC300™ 32-bit RISC core ■ Up to 30 Kbytes of User RAM ■ Up to 1280 Kbytes of User Flash memory with
OTP area: – 10-year data retention – 100,000 Erase/Write cycles – Page granularity of 256 bytes – Block granularity: 1 Kbyte – 256 Bytes of OTP for User – Page Erase time 5 ms – Block Erase 1 Kbyte in 15 ms – Programming performance up to 10 µs/byte
The ST33F family operates in the –25 to +85°C temperature range and 1.8V, 3V and 5V supply voltage ranges. A comprehensive range of power-saving modes enables the design of efficient low-power applications.
Security Administrator
True Random Number Gene-
rator
CLK
SWIO RESET Vcc GND
SPI Slave
IART with RAM Buffer
2 I/Os
Ai15206
Note:
1.1
SWP interface not available on SC33F devices.
ST33F1M, Sx33F768 Sx33F640, Sx33F512, SC33F384
Smartcard MCU with 32-bit ARM® SecurCore® SC300™ CPU and high-density Flash memory
Data Brief
Features
Hardware features
Three general purpose 16-bit timers are available; one configurable as a watchdog.
The ST33F1M* features hardware accelerators for advanced cryptographic functions. The EDES peripheral provides a secure DES (Data Encryption Standard) algorithm implementation, while the NESCRYPT crypto-processor efficiently supports the public key algorithm.
cryptography algorithm
Development environment
■ Software development and firmware generation are supported by a comprehensive set of development tools dedicated to software design and validation: – C Compiler, Simulator and Emulator
Software development tools description
Dedicated SecurCore® SC300™ software development tools are provided by ARM and Keil. This includes the Instruction Set Simulator (ISS) and C compiler. The documentation is available on the ARM and Keil web sites.
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Doc ID 18396
ST33F1M, Sx33F768, Sx33F640, Sx33F512, SC33F384 Figure 1. ST33F1M* block diagram
DescripLeabharlann ionSecurCore® SC300™ CPU Core
RAM
Flash memory
ST ROM
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1
Description
1
Description
ST33F1M, Sx33F768, Sx33F640, Sx33F512, SC33F384
The ST33F1M* is a serial access microcontroller designed for secure mobile applications that incorporates the most recent generation of ARM processors for embedded secure systems. Its SecurCore® SC300™ 32-bit RISC core is built on the Cortex™ M3 core with additional security features to help to protect against advanced forms of attacks.
The ST33F1M* also offers a serial communication interface fully compatible with the ISO/IEC 7816-3 standard (T=0, T=1) and an optional single-wire protocol (SWP) interface for communication with a near field communication (NFC) router in SIM/NFC applications.
Part number Flash memory size
ST33F1M ST33F768 SC33F768 ST33F640 SC33F640
1280 Kbytes 768 Kbytes 640 Kbytes
ST33F512 SC33F512 SC33F384
512 Kbytes 384 Kbytes
Applications
ST33F1M*(a) major applications include: ■ Mobile communications (GSM, 3G and CDMA) ■ Java Card™ applications ■ Multimedia
Table 1. Device summary
Cadenced at 22.5 MHz, the SC300™ core brings great performance and excellent code density thanks to the Thumb®-2 instruction set.
The high-speed embedded Flash memory introduces more flexibility to the system.
Moreover, STMicroelectronics provides: ● A time-accurate hardware emulator controlled by the Keil debugger and the ST
development environment. ● A complete product simulator based on Keil’s ISS simulator for the SecurCore®
An SPI Slave interface is also available for communication in non-SIM applications. Note that this interface is not available when ISO/IEC 7816 communication is required.
SWP
Yes Yes No Yes No Yes No No
a. ST33F1M* is a generic term that refers to all devices summarized Table 1.
January 2011
Doc ID 18396 Rev 1
For further information contact your local STMicroelectronics sales office.
in Chained mode – Flash Erase / Write protection software
programmable on 128 Kbyte Sectors ■ Asynchronous receiver transmitter supporting
ISO/IEC 7816-3 T=0 and T=1 protocols (Slave mode supported) ■ Optional Single Wire Protocol (SWP) Interface for communications with NFC router ■ Serial peripheral interface (SPI) slave interface ■ Three 16-bit timers with interrupt capability including one 16-bit timer with watchdog capability ■ 1.8 V, 3 V and 5 V supply voltage ranges ■ External clock frequency from 1 up to 10 MHz ■ Current consumption compatible with GSM and ETSI specifications ■ High performance provided by: – CPU clock frequency up to 22.5 MHz – External clock multiplier (2x, 3x, and 4x) ■ Power-saving standby state ■ Contact assignment compatible with ISO/IEC 7816-2 ■ ESD protection greater than 4 kV (HBM)