STATISTICAL CLOCK CYCLE COMPUTATION
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专利名称：STATISTICAL CLOCK CYCLE COMPUTATION 发明人：Nathan BUCK,Brian DREIBELBIS,John P.
DUBUQUE,Eric A. FOREMAN,James C.
GREGERSON,Peter A. HABITZ,Jeffrey G.
HEMMETT,Debjit SINHA,Natesan
VENKATESWARAN,Chandramouli
VISWESWARIAH,Michael H. WOOD,Vladimir
ZOLOTOV
申请号：US13311832
申请日：20111206
公开号：US20130145333A1
公开日：
20130606
专利内容由知识产权出版社提供专利附图：
摘要：Systems and methods for statistical clock cycle computation and closing timing of an integrated circuit design to a maximum clock cycle or period. The method includes loading a design and timing model for at least one circuit path of an integrated circuit or a region of the integrated circuit into a computing device. The method further includes performing a statistical static timing analysis (SSTA) of the at least one circuit path using the loaded design and timing model to obtain slack canonical data. The method further includes calculating a maximum circuit clock cycle for the integrated circuit or the specified region of the integrated circuit in linear canonical form based upon the slack canonical data obtained from the SSTA.
申请人：Nathan BUCK,Brian DREIBELBIS,John P. DUBUQUE,Eric A. FOREMAN,James C. GREGERSON,Peter A. HABITZ,Jeffrey G. HEMMETT,Debjit SINHA,Natesan VENKATESWARAN,Chandramouli VISWESWARIAH,Michael H. WOOD,Vladimir ZOLOTOV 地址：Underhill VT US,Underhill VT US,Jericho VT US,Fairfax VT US,Hyde Park NY US,Hinesburg VT US,St. George VT US,Wappingers Falls NY US,Hopewell Junction NY
US,Croton-on-Hudson NY US,Hopewell Junction NY US,Putnam Valley NY US
国籍：US,US,US,US,US,US,US,US,US,US,US,US 更多信息请下载全文后查看。