FPGA可编程逻辑器件芯片EP2SGX60DF780C4中文规格书
FPGA可编程逻辑器件芯片EP3SL70F780C4中文规格书
•Encrypted transistor and logic cell library models •Encrypted input or output buffer circuit models for single-ended and differential I/O •Single-ended and differential sample SPICE decks •User guide describing the model usageThe HSPICE models provide options to simulate buffer behavior for following I/O feature:•RS OCT with and without calibration •RT OCT with calibration •Internal weak pull-up •Open drain •Bus-hold5.1.20.2. Net Length ReportsThe net length information consists of the package trace delay information from die pad to package pin. Each pin in an FPGA package has its own net length information.This information is important for you to perform board trace compensation to optimize the channel-to-channel skew on your board design.You can obtain the net length reports for Intel Agilex devices from the Board Design Guidelines Solutions Center under Tools, Models, and Libraries .Related InformationBoard Design Guidelines Solution Center: Tools, Models, and Libraries Download center for net length reports for Intel FPGA devices5.2. Intel Agilex LVDS SERDES Design Guidelines5.2.1. Use PLLs in Integer PLL Mode for LVDSEach I/O sub-bank has its own PLL (I/O PLL) to drive the SERDES channels. These I/O PLLs operate in integer mode only.5.2.2. Use High-Speed Clock from PLL to Clock SERDES OnlyThe high-speed clock generated from the PLL is intended to clock the SERDES circuitry only. Do not use the high-speed clock to drive other logic because the allowed frequency to drive the core logic is restricted by the PLL F OUT specification.For more information about the F OUT specification, refer to the Intel Agilex Device Data Sheet .5.I/O and LVDS SERDES Design GuidelinesUG-20214 | 2021.04.05Send Feedback5.2.3. Pin Placement for Differential ChannelsEach GPIO sub-bank contains its own PLL. A PLL can drive all receiver and transmitter channels in the same sub-bank. However , the individual PLL cannot drive receiver and transmitter channels in another I/O sub-bank. You must use the dedicated clock pins to drive the LVDS PLLs.The pin index number 0-47 and pin index number 48-95 from device pin out files are respectively assigned to bottom sub-bank and top sub-bank in a single GPIO bank.Refer to External Memory Interface Pin Placement Requirements for more information about the sub-bank arrangement for each I/O bank.PLLs Driving DPA-Enabled Differential Receiver ChannelsFor differential receivers, the PLL can drive all channels in the same I/O sub-bank but cannot drive across banks.Each differential receiver in an I/O bank has a dedicated DPA circuit to align the phase of the clock to the data phase of its associated channel.DPA usage adds some constraints to the placement of high-speed differential receiver channels. The Intel Quartus Prime compiler automatically checks the design and issues error messages if there are placement guidelines violations. Adhere to the guidelines to ensure proper high-speed I/O operation.Related InformationExternal Memory Interface Pin Placement Requirements on page 1225.2.4. SERDES Pin Pairs for Soft-CDR ModeYou can use only specific SERDES pin pairs in soft-CDR mode. Refer to the pinout file of each device to determine the SERDES pin pairs that support the soft-CDR mode.5.2.5. Placing LVDS Transmitters and Receivers in the Same I/O BankIf you want to place both LVDS transmitter and receiver interfaces in the same I/O bank, you can use an external PLL.5.2.5.1. Using an External PLL•To use an external PLL, in the LVDS SERDES IP parameter editor , turn on the Use external PLL option.•You can generate two instances of the LVDS SERDES IP—a receiver and a transmitter .•In each instance, you can use up to the following number of channels:—12 transmitters —12 DPA or non-DPA receivers —8 soft-CDR receivers5.I/O and LVDS SERDES Design GuidelinesUG-20214 | 2021.04.05Send Feedback6.Troubleshooting GuidelinesGPIO Debug GuidelinesThe following table lists the failure symptoms and the associated debug actions that you can take to identify the failure areas when designing GPIO systems with Intel Agilex devices. These debug guidelines are just initial debug actions and do not necessarily resolve the failures in your designs.Table 72.GPIO Debug Guidelines Failure SymptomsRecommended Debug Actions 1.2 V LVCMOS output at the entire bank does not reach 1.2V •Check the power-up and power-down sequences of each voltage rail with respect to time.•Compare the power sequences as per recommendation in the Intel Agilex Power Management User Guide.•Verify the VCCIO_PIO voltage signal is 1.2 v.Intel Quartus Prime software shows an error messages to indicate incorrect I/O settings for V CCIO during design compilation.Error message example: Illegal constraint of I/O bank to the location <I/O bank>.•Select the I/O pins specified in the error message and check the I/O settings for the pins.Intel Quartus Prime software shows illegal I/O error message during design compilation.Error message example: Programmable VOD option is set to 1 for pin <pin_name>, but setting is not supported by <I/O standard>.•Select the I/O pins specified in the error message and set the pins to the correct I/O function. Refer to the device pin-outs file for more information about the pin functions.Unable to configure a pin as an open-drain output pin.•Make sure the pin is set to the correct voltage specification per the device data sheet.•To ensure the pin is correctly set to open-drain output,check the compilation report or the resource property editor .Unable to configure a pin to use the bus-hold feature.•Make sure the pin is not set to programmable pull-up resistor . The bus-hold feature is not available when the pin is set to programmable pull-up resistor .High-Speed SERDES I/O Debug GuidelinesThe following table lists the failure symptoms and the associated debug actions that you can take to identify the failure areas when designing high-speed SERDES systems with Intel Agilex devices. These debug guidelines are just initial debug actions and do not necessarily resolve the failures in your designs.UG-20214 | 2021.04.05Send FeedbackISO 9001:2015Registered。
FPGA可编程逻辑器件芯片EP2SGX60EF1152C5中文规格书
Introduction●8B/10B encoder and decoder perform 8-bit to 10-bit encodingand 10-bit to 8-bit decoding●Phase compensation FIFO buffer performs clock domaintranslation between the transceiver block and the logic array●Receiver FIFO resynchronizes the received data with the localreference clock●Channel aligner compliant with XAUIf Certain transceiver blocks can be bypassed. Refer to the Stratix II GXArchitecture chapter in volume 1 of the Stratix II GX Device Handbook formore details.Table1–1 lists the Stratix II GX device features.Table1–1.Stratix II GX Device Features (Part 1 of2)Feature EP2SGX30C/D EP2SGX60C/D/E EP2SGX90E/F EP2SGX130/G C D C D E E F GALMs13,55224,17636,38453,016 Equivalent LEs33,88060,44090,960132,540 Transceiverchannels484812121620Transceiver data rate600 Mbps to6.375Gbps 600 Mbps to 6.375Gbps600 Mbps to6.375 Gbps600 Mbps to6.375 GbpsSource-synchronousreceive channels (1)31313142475973Source-synchronoustransmit channels29292942455971M512 RAM blocks(32×18bits)202329488699M4K RAM blocks(128×36bits)144255408609M-RAM blocks(4K×144 bits)1246 Total RAM bits1,369,7282,544,1924,520,4486,747,840 Embeddedmultipliers (18×18)64144192252 DSP blocks16364863 PLLs444888 Maximum user I/Opins361364364534558650734This module detects word boundaries for the 8B/10B-based protocols, SONET, 16-bit, and 20-bit proprietary protocols. This module is also used to align to specific programmable patterns in PRBS7/23 test mode. Pattern DetectionThe programmable pattern detection logic can be programmed to align word boundaries using a single 7-, 8-, 10-, 16-, 20, or 32-bit pattern. The pattern detector can either do an exact match, or match the exact pattern and the complement of a given pattern. Once the programmed pattern is found, the data stream is aligned to have the pattern on the LSB portion of the data output bus.XAUI, GIGE, PCI Express, and Serial RapidIO standards have embedded state machines for symbol boundary synchronization. These standards use K28.5 as their 10-bit programmed comma pattern. Each of these standards uses different algorithms before signaling symbol boundary acquisition to the FPGA.The pattern detection logic searches from the LSB to the most significant bit (MSB). If multiple patterns are found within the search window, the pattern in the lower portion of the data stream (corresponding to the pattern received earlier) is aligned and the rest of the matching patterns are ignored.Once a pattern is detected and the data bus is aligned, the word boundary is locked. The two detection status signals (rx_syncstatus andrx_patterndetect) indicate that an alignment is complete.Figure2–18 is a block diagram of the word aligner.Figure2–18.Word AlignerAdaptive Logic ModulesFigure2–44.Example of a 3-Bit Add Utilizing Shared Arithmetic ModeShared Arithmetic ChainIn addition to the dedicated carry chain routing, the shared arithmeticchain available in shared arithmetic mode allows the ALM to implementa three-input add, which significantly reduces the resources necessary toimplement large adder trees or correlator functions. The sharedarithmetic chains can begin in either the first or fifth ALM in a LAB. TheQuartus II Compiler automatically links LABs to create shared arithmeticchains longer than 16 (8ALMs in arithmetic or shared arithmetic mode).For enhanced fitting, a long shared arithmetic chain runs vertically。
FPGA可编程逻辑器件芯片EP1S20F780C5中文规格书
dataa datab datac datad
Six-Input LUT
(Function0)
datae1 dataf1
Six-Input LUT
(Function1)
combout0 combout1
In a sparsely used device, functions that could be placed into one ALM may be implemented in separate ALMs. The Quartus II Compiler spreads a design out to achieve the best possible performance. As a device begins to fill up, the Quartus II software automatically utilizes the full potential of the Stratix II ALM. The Quartus II Compiler automatically searches for functions of common inputs or completely independent functions to be placed into one ALM and to make efficient use of the device resources. In addition, you can manually control resource usage by setting location assignments.
FPGA可编程逻辑器件芯片EP3SE260H780C4N中文规格书
Tables 4–98 through 4–105 show the maximum DCD in absolutionderivation for different I/O standards on Stratix II GX devices. Examplesare also provided that show how to calculate DCD as a percentage.Here is an example for calculating the DCD as a percentage for anon-DDIO output on a row I/O on a -3 device:If the non-DDIO output I/O standard is SSTL-2 Class II, the maximumDCD is 95ps (see Table 4–99). If the clock frequency is 267MHz, the clockperiod T is:T = 1/ f = 1 / 267MHz = 3.745ns = 3,745psTo calculate the DCD as a percentage:(T/2 – DCD) / T = (3,745ps/2 – 95ps) / 3,745ps = 47.5% (for lowboundary)(T/2 + DCD) / T = (3,745ps/2 + 95ps) / 3,745ps = 52.5% (for highboundary)Table 4–98.Maximum DCD for Non-DDIO Output on Row I/O PinsRow I/O Output StandardMaximum DCD (ps) for Non-DDIO Output -3 Devices -4 and -5 Devices Unit 3.3-V LVTTTL245275ps 3.3-V LVCMOS125155ps 2.5 V105135ps 1.8 V180180ps 1.5-V LVCMOS165195ps SSTL-2 Class I115145ps SSTL-2 Class II95125ps SSTL-18 Class I5585ps 1.8-V HSTL Class I80100ps 1.5-V HSTL Class I85115ps LVDS 5580psTable4–100.Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -3 Devices Note(1)Maximum DCD (ps) for Row DDIO Output I/OStandardInput I/O Standard (No PLL in Clock Path)Unit TTL/CMOS SSTL-2SSTL/HSTL LVDS3.3 and2.5 V1.8 and1.5 V2.5 V1.8 and1.5 V3.3 V3.3-V LVTTL260380145145110ps 3.3-V LVCMOS21033010010065ps 2.5 V195315858575ps 1.8 V1502658585120ps 1.5-V LVCMOS255370140140105ps SSTL-2 Class I175295656570ps SSTL-2 Class II170290606075ps SSTL-18 Class I155275555090ps 1.8-V HSTL Class I150270606095ps 1.5-V HSTL Class I150270555590ps LVDS180180180180180psTherefore, the DCD percentage for the output clock is from 48.4% to51.6%.Table4–101.Maximum DCD for DDIO Output on Row I/O Pins Without PLL in the Clock Path for -4 and -5 Devices Note(1)Maximum DCD (ps) for Row DDIO Output I/OStandardInput I/O Standard (No PLL in the Clock Path)Unit TTL/CMOS SSTL-2SSTL/HSTL LVDS3.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 3.3V3.3-V LVTTL440495170160105ps 3.3-V LVCMOS39045012011075ps 2.5 V3754301059590ps 1.8 V32538590100135ps 1.5-V LVCMOS430490160155100ps SSTL-2 Class I355410857585ps SSTL-2 Class II350405807090ps SSTL-18 Class I3353906565105ps 1.8-V HSTL Class I3303856070110ps 1.5-V HSTL Class I3303906070105ps LVDS180180180180180ps(1)Table4–101 assumes the input clock has zero DCD.Table4–102.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3 Devices (Part 1 of2)Note(1)Maximum DCD (ps) for DDIO Column Output I/OStandardInput IO Standard (No PLL in the Clock Path)Unit TTL/CMOS SSTL-2SSTL/HSTL HSTL123.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 1.2V3.3-V LVTTL260380145145145ps 3.3-V LVCMOS210330100100100ps 2.5 V195315858585ps 1.8 V150265858585ps 1.5-V LVCMOS255370140140140ps SSTL-2 Class I175295656565ps SSTL-2 Class II170290606060ps SSTL-18 Class I155275555050psSSTL-18 Class II140260707070ps 1.8-V HSTL Class I150270606060ps 1.8-V HSTL Class II150270606060ps 1.5-V HSTL Class I150270555555ps 1.5-V HSTL Class II125240858585ps 1.2-V HSTL240360155155155ps LVPECL 180180180180180ps(1)Table 4–102 assumes the input clock has zero DCD.Table 4–103.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -4 and -5 Devices Note (1)Maximum DCD (ps) forDDIO Column Output I/OStandardInput IO Standard (No PLL in the Clock Path)Unit TTL/CMOS SSTL-2SSTL/HSTL 3.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 3.3-V LVTTL440495170160ps 3.3-V LVCMOS390450120110ps 2.5 V37543010595ps 1.8 V32538590100ps 1.5-V LVCMOS430490160155ps SSTL-2 Class I3554108575ps SSTL-2 Class II3504058070ps SSTL-18 Class I3353906565ps SSTL-18 Class II3203757080ps 1.8-V HSTL Class I3303856070ps 1.8-V HSTL Class II3303856070ps 1.5-V HSTL Class I3303906070ps 1.5-V HSTL Class II33036090100ps LVPECL180180180180ps (1)Table 4–103 assumes the input clock has zero DCD.Table 4–102.Maximum DCD for DDIO Output on Column I/O Pins Without PLL in the Clock Path for -3 Devices (Part 2 of 2) Note (1)Maximum DCD (ps) forDDIO Column Output I/OStandardInput IO Standard (No PLL in the Clock Path)Unit TTL/CMOS SSTL-2SSTL/HSTL HSTL123.3/2.5V 1.8/1.5V 2.5V 1.8/1.5V 1.2V。
FPGA可编程逻辑器件芯片EP2SGX60DF780C5中文规格书
PLL SpecificationsPLLSpecificationsf See the DC & Switching Characteristics chapter in volume 1 of theStratix II GX Device Handbook (or the Stratix II Device Handbook) forinformation about PLL timing specificationsClocking Stratix II and Stratix II GX devices provide a hierarchical clock structureand multiple PLLs with advanced features. The large number of clockingresources in combination with the clock synthesis precision provided byenhanced and fast PLLs provides a complete clock-management solution.Global and Hierarchical ClockingStratix II and Stratix II GX devices provide 16 dedicated global clocknetworks and 32 regional clock networks. These clocks are organized intoa hierarchical clock structure that allows for 24 unique clock sources perdevice quadrant with low skew and delay. This hierarchical clockingscheme provides up to 48 unique clock domains within the entireStratix II or Stratix II GX device. Table1–17 lists the clock resourcesavailable on Stratix II devices.There are 16 dedicated clock pins (CLK[15..0]) on Stratix II andStratix II GX devices to drive either the global or regional clock networks.Four clock pins drive each side of the Stratix II device, as shown inFigures1–39and 1–40. Enhanced and fast PLL outputs can also drive theglobal and regional clock networks.Table1–17.Clock Resource Availability in Stratix II and Stratix II GX Devices(Part 1 of2)Description Stratix II Device Availability Stratix II GX Device Availability Number of clock input pins24 12Number of global clock networks1616Number of regional clocknetworks3232Global clock input sources Clock input pins, PLL outputs, logicarray Clock input pins, PLL outputs, logic array, inter-transceiver clocksRegional clock input sources Clock input pins, PLL outputs, logicarray Clock input pins, PLL outputs, logic array, inter-transceiver clocksNumber of unique clock sources in a quadrant 24 (16 global clocks and 8 regionalclocks)24 (16 GCLK and 8 RCLK clocks)Number of unique clock sources in the entire device 48 (16 global clocks and 32 regionalclocks)48 (16 GCLK and 32 RCLK clocks)ClockingTables1–20 and 1–21 show which PLLs are available in each Stratix II andStratix II GX device, respectively, and which input clock pin drives whichPLLs.Table1–20.Stratix II Device PLLs and PLL Clock Pin Drivers(Part 1 of2)Input PinAll Devices EP2S60 to EP2S180 Devices Fast PLLsEnhancedPLLsFast PLLsEnhancedPLLs 123456789101112CLK0v v v(1)v (1)CLK1(2)v v v(1)v (1)CLK2v v v(1)v (1)CLK3(2)v v v(1)v (1)CLK4v v CLK5v v CLK6v v CLK7v v CLK8v v v(1)v (1)CLK9 (2)v v v(1)v (1)CLK10v v v(1)v (1)CLK11 (2)v v v(1)v (1)CLK12v vCLK13v vCLK14v vCLK15v vPLL5_FB vPLL6_FB vPLL11_FB vPLL12_FB v PLL_ENA v v v v v v v v v v v v FPLL7CLK(2)vFPLL8CLK(2)vFPLL9CLK(2)vDocument Revision HistoryContents Stratix II Device Handbook, Volume2ClockingTables1–23 and 1–24 show the global and regional clocks that the PLLoutputs drive.Table1–23.Stratix II Global and Regional Clock Outputs From PLLs(Part 1 of3)Clock NetworkPLL Number and TypeEP2S15 through EP2S30 Devices EP2S60 through EP2S180 Devices Fast PLLsEnhancedPLLsFast PLLsEnhancedPLLs 123456789101112GCLK0v v v vGCLK1v v v vGCLK2v v v vGCLK3v v v vGCLK4v v GCLK5v v GCLK6v v GCLK7v v GCLK8v v v vGCLK9v v v vGCLK10v v v vGCLK11v v v vGCLK12v vGCLK13v vGCLK14v vGCLK15v vRCLK0v v vRCLK1v v vRCLK2v v vRCLK3v v vRCLK4v v vRCLK5v v vRCLK6v v vRCLK7v v vRCLK8v v RCLK9v v。
FPGA可编程逻辑器件芯片EP3SL50F780C4N中文规格书
Stratix III Device Handbook, Volume 2Electrical CharacteristicsThis chapter describes the electrical characteristics, switching characteristics, and I/O timing for Stratix ®III devices. Electrical characteristics include operating conditions and power consumption. Switching characteristics include core performance specifications and periphery performance. A glossary is also included for your reference.Operating ConditionsWhen Stratix III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and reliability of Stratix III devices, system designers must consider the operating requirements described in this chapter.Stratix III devices are offered in both commercial and industrial grades. Commercial devices are offered in –2 (fastest), –3, –4, and –4L speed grades. Industrial devices are offered only in –3, –4, and –4L speed grades.1In this chapter, a prefix associated with the operating temperature range is attached to the speed grades; commercial with a “C” prefix and industrial with an “I” prefix. For example, commercial devices are indicated as C2, C3, C4, and C4L per respective speed grades. Industrial devices are indicated as I3, I4, and I4L.Absolute Maximum RatingsAbsolute maximum ratings define the maximum operating conditions for Stratix III devices. The values are based on experiments conducted with the device and theoretical modeling of breakdown and damage mechanisms. The functionaloperation of the device is not implied at these conditions. Conditions beyond those listed in Table 1–1 may cause permanent damage to the device. Additionally, device operation at the absolute maximum ratings for extended periods may have adverse effects on the device.Table 1–1.Absolute Maximum Ratings for Stratix III Devices (Note 1)(Part 1 of 2)SymbolParameterMinimum Maximum Unit V CCL Selectable core voltage power supply -0.5 1.65V V CC I/O registers power supply-0.5 1.65V V CCD_PLL Phase-locked loop (PLL) digital power supply -0.5 1.65V V CCA_PLL PLL analog power supply-0.5 3.75V V CCPT Programmable power technology power supply -0.5 3.75V V CCPGM Configuration pins power supply -0.5 3.9V V CCPD I/O pre-driver power supply -0.5 3.9V V CCIOI/O power supply-0.53.9VSIII52001-2.3Chapter 1:Stratix III Device Datasheet: DC and Switching CharacteristicsElectrical CharacteristicsStratix III Device Handbook, Volume 2V CC_CLKIN Differential clock input power supply (top and bottom I/O banks only)-0.5 3.75V V CCBAT Battery back-up power supply for design security volatile key register -0.5 3.75V V I DC Input voltage-0.5 4.0V T J Operating junction temperature -55125°C I OUT DC output current, per pin -2540mA T STGStorage temperature (No bias)-65150°CTable 1–1.Absolute Maximum Ratings for Stratix III Devices (Note 1)(Part 2 of 2)Symbol ParameterMinimum Maximum UnitChapter 1:Stratix III Device Datasheet: DC and Switching Characteristics Electrical CharacteristicsStratix III Device Handbook, Volume 2Table 1–2.Maximum Allowed Overshoot During TransitionsSymbolParameterConditionOvershoot Duration as a % ofHigh TimeUnit Vi (AC)AC Input Voltage (1)4100.000%4.0579.330%4.146.270%4.1527.030%4.215.800%4.259.240%4.3 5.410%4.353.160%4.4 1.850%4.45 1.080%4.50.630%4.550.370%4.60.220%4.650.130%4.70.074%4.750.043%4.80.025%4.850.015%Chapter 1:Stratix III Device Datasheet: DC and Switching CharacteristicsElectrical CharacteristicsStratix III Device Handbook, Volume 2V CCPGMConfiguration pins power supply, 3.3 V— 3.135 3.3 3.465V Configuration pins power supply, 3.0 V — 2.853 3.15V Configuration pins power supply, 2.5 V — 2.375 2.5 2.625V Configuration pins power supply, 1.8 V — 1.71 1.8 1.89V V CCPD (1)I/O pre-driver power supply, 3.3 V— 3.135 3.3 3.465V I/O pre-driver power supply, 3.0 V — 2.85 3 3.15V I/O pre-driver power supply, 2.5 V — 2.375 2.5 2.625V V CCIOI/O power supply, 3.3 V — 3.135 3.3 3.465V I/O power supply, 3.0 V— 2.85 3 3.15V I/O power supply, 2.5 V — 2.375 2.5 2.625V I/O power supply, 1.8 V — 1.71 1.8 1.89V I/O power supply, 1.5 V — 1.425 1.5 1.575V I/O power supply, 1.2 V— 1.14 1.2 1.26V V CC_CLKIN Differential clock input power supply (top and bottom I/O banks only)— 2.375 2.5 2.625V V CCBAT (3)Battery back-up power supply for design security volatile key register — 1.0— 3.3V V I DC Input voltage —-0.3— 3.6V V OOutput voltage—0—V CCIO V T J Operating junction temperatureFor commercialuse 0—85°C For industrial use (2)-40—100°C t RAMPPower Supply Ramptime (For V CCPT )Normal POR (PORSEL=0)50 µs — 5 ms —Fast POR (PORSEL=1)50 µs — 5 ms —Power Supply Ramptime (For all power supplies except V CCPT )Normal POR (PORSEL=0)50 µs —100 ms —Fast POR (PORSEL=1)50 µs—12 ms—Notes to Table 1–3:(1)V CCPD is 2.5, 3.0, or 3.3V. For a 3.3-V I/O standard, V CCPD =3.3 V. For a 3.0-V I/O standard, V CCPD = 3.0 V. For a 2.5-V or lower I/O standard,V CCPD =2.5V.(2)For the EP3SL340, EP3SE260, and EP3SL200 devices in the I4L ordering code, the industrial junction temperature range is from 0° C to100° C, regardless of supply voltage.(3)Altera recommends a 3.0-V nominal battery voltage when connecting V CCBAT to a battery for volatile key backup. If you do not use the volatilesecurity key, you may connect the V CCBAT to either GND or a 3.0-V power supply.Table 1–3.Recommended Operating Conditions for Stratix III Devices (Part 2 of 2)SymbolParameterConditionsMinimum Typical Maximum UnitChapter 1:Stratix III Device Datasheet: DC and Switching Characteristics Electrical CharacteristicsStratix III Device Handbook, Volume 2Parameter Symbol Conditions V CCIOUnit1.2V 1.5V 1.8V2.5V3.0V/3.3V MinMaxMinMaxMinMaxMinMaxMinMaxLow sustaining current I SUSL V IN >V IL (maximum)22.5 —25.0 —30.0 —50.0 —70.0 —µA High sustaining current I SUSH V IN <V IH (minimum)-22.5 —-25.0 —-30.0 —-50.0 —-70.0 —µA Low overdrive currentI ODL0V <V IN <V CCIO—120—160—200—300—500µA。
FPGA可编程逻辑器件芯片EP2S60F1020C4中文规格书
Table 4–96 shows the maximum output clock toggle rate for Stratix II GXdevice series-terminated dedicated clock pins.SSTL-2 Class IOCT_50_OHMS 600 500 500 MHz SSTL-2 Class IIOCT_25_OHMS 600 550 500 MHz SSTL-18 Class I OCT_50_OHMS 590 400 350 MHz 1.5-V HSTLClass IOCT_50_OHMS 600 550 500 MHz 1.8-V HSTLClass IOCT_50_OHMS 650 600 600 MHz DifferentialSSTL-2 Class IOCT_50_OHMS 600 500 500 MHz DifferentialSSTL-2 Class II OCT_25_OHMS 600550 500 MHz Differential SSTL-18 Class I OCT_50_OHMS 590400 350 MHz Differential HSTL-18 Class I OCT_50_OHMS 650600600MHz Differential HSTL-15 Class IOCT_50_OHMS600550500Table 4–95.Stratix II GX Maximum Output Clock Rate for Row Pins (Series Termination)(Part 2 of 2)I/O StandardDrive Strength -3 Speed Grade -4 Speed Grade -5 Speed Grade Unit Table 4–96.Stratix II GX Maximum Output Clock Rate for Dedicated Clock Pins (Series Termination)(Part 1 of 2)I/O StandardDrive Strength -3 Speed Grade -4 Speed Grade -5 Speed Grade Unit LVTTLOCT_25_OHMS 400 400 350 MHz OCT_50_OHMS 400 400 350 MHz LVCMOSOCT_25_OHMS 350 350 300 MHz OCT_50_OHMS 350 350 300 MHz 2.5 VOCT_25_OHMS 350 350 300 MHz OCT_50_OHMS 350 350 300 MHz 1.8 VOCT_25_OHMS 700 550 450 MHz OCT_50_OHMS 700 550 450 MHz 1.5 VOCT_50_OHMS 550 450 400 MHz SSTL-2 Class IOCT_50_OHMS 600 500 500 MHz SSTL-2 Class II OCT_25_OHMS 600550 500 MHz SSTL-18 Class I OCT_50_OHMS450 400 350 MHzSSTL-18 Class II 8mA173206206---155********mA150160160---14016016018mA120130130---11013013020mA109127127---941271272.5-V SSTL-2Class I8mA 36468068036468068035068068012mA 1632072071632072071882072072.5-V SSTL-2Class II 16mA 1181471471181471479414714720mA 99122122---8712212224mA 91116116---851161161.8-V SSTL-18 Class I 4mA 4585705704585705705055705706mA 3053803803053803803363803808mA 22528228222528228224828228210mA 16722022016722022019022022012mA 129175175---1481751751.8-V SSTL-18 Class II 8mA 173206206---155********mA 150160160---14016016018mA 120130130---11013013020mA 109127127---941271271.8-V HSTL Class I 4mA 2452822822452822822292822826mA 1641881881641881881531881888mA 12314014012314014011414014010mA 11012412411012412410812412412mA 97110110971101101041101101.8-V HSTL Class II 16mA 101104104---9910410418mA 98102102---9310210220mA 939999---8899991.5-V HSTL Class I 4mA 1681961961681961961881961966mA 1121311311121311311251311318mA 84999984999995999910mA 879898---90989812mA 869898---879898Table 4–97.Maximum Output Clock Toggle Rate Derating Factors (Part 3 of 5)I/O Standard DriveStrength Maximum Output Clock Toggle Rate Derating Factors (ps/pF)Column I/O PinsRow I/O Pins Dedicated Clock Outputs -3-4-5-3-4-5-3-4-51.5-V HSTL Class II 16mA 95101101---96101101 18mA 95100100---101100100 20mA 94101101---1041011012.5-V differential SSTL Class II (3)8mA 364680680---350680680 12mA 163207207---188207207 16mA 118147147---94147147 20mA 99122122---87122122 24mA91116116---851161161.8-V differential SSTL Class I (3)4mA 458570570---505570570 6mA 305380380---336380380 8mA 225282282---248282282 10mA 167220220---190220220 12mA 129175175---1481751751.8-V differential SSTL Class II (3)8mA 173206206---155206206 16mA 150160160---140160160 18mA 120130130---110130130 20mA 109127127---941271271.8-V differential HSTL Class I (3)4mA 245282282---229282282 6mA 164188188---153188188 8mA 123140140---114140140 10mA 110124124---108124124 12mA 97110110---1041101101.8-V differential HSTL Class II (3)16mA 101104104---99104104 18mA 98102102---93102102 20mA 939999---8899991.5-V differential HSTL Class I (3)4mA 168196196---188196196 6mA 112131131---125131131 8mA 849999---959999 10mA 879898---909898 12mA 869898---879898Table4–97.Maximum Output Clock Toggle Rate Derating Factors (Part 4 of5)I/O StandardDriveStrengthMaximum Output Clock Toggle Rate Derating Factors (ps/pF) Column I/O Pins Row I/O PinsDedicated ClockOutputs -3-4-5-3-4-5-3-4-5。
FPGA可编程逻辑器件芯片EP2S60F484I4中文规格书
Tables 5–77 through 5–79 show the I/O toggle rates for Stratix II devices.
Table 5–77. Maximum Input Toggle Rate on Stratix II Devices (Part 1 of 2)
Parameter
tP I tP C O U T tP I tP C O U T tP I tP C O U T tP I tP C O U T tP I tP C O U T
Minimum Timing Industrial Commercial
-3 Speed Grade (1)
-3 Speed Grade (2)
-4 Speed Grade
-5 Speed Grade
Column I/O Pins (MHz) Row I/O Pins (MHz)
-3 -4
-5
-3 -4
-5
500 500 450 500 500 450
500 500 450 500 500 450
500 500 450 500 500 450
500 500 450 500 500 450
500 500 450 500 500 450
Input I/O Standard
LVTTL 2.5-V LVTTL/CMOS 1.8-V LVTTL/CMOS 1.5-V LVTTL/CMOS LVCMOS SSTL-2 Class I SSTL-2 Class II SSTL-18 Class I SSTL-18 Class II 1.5-V HSTL Class I 1.5-V HSTL Class II 1.8-V HSTL Class I
FPGA可编程逻辑器件芯片EP2S130F780C4N中文规格书
Stratix II Architecture Figure2–56.DQS Phase-Shift Circuitry Notes(1), (2), (3), (4)Notes to Figure2–56:(1)There are up to 18 pairs of DQS and DQSn pins available on the top or the bottom of the Stratix II device. There areup to 10 pairs on the right side and 8 pairs on the left side of the DQS phase-shift circuitry.(2)The t module represents the DQS logic block.(3)Clock pins CLK[15..12]p feed the phase-shift circuitry on the top of the device and clock pins CLK[7..4]p feedthe phase circuitry on the bottom of the device. You can also use a PLL clock output as a reference clock to the phase-shift circuitry.(4)You can only use PLL 5 to feed the DQS phase-shift circuitry on the top of the device and PLL 6 to feed the DQSphase-shift circuitry on the bottom of the device.These dedicated circuits combined with enhanced PLL clocking andphase-shift ability provide a complete hardware solution for interfacingto high-speed memory.f For more information on external memory interfaces, refer to theExternal Memory Interfaces in Stratix II & Stratix II GX Devices chapter involume 2 of the Stratix II Device Handbook or the Stratix II GX DeviceHandbook.Programmable Drive StrengthThe output buffer for each Stratix II device I/O pin has a programmabledrive strength control for certain I/O standards. The LVTTL, LVCMOS,SSTL, and HSTL standards have several levels of drive strength that theuser can control. The default setting used in the Quartus II software is themaximum current strength setting that is used to achieve maximum I/Operformance. For all I/O standards, the minimum setting is the lowestdrive strength that guarantees the I OH/I OL of the standard. Usingminimum settings provides signal slew rate control to reduce systemnoise and signal overshoot.High-Speed Differential I/O with DPA SupportHigh-Speed Differential I/O with DPA SupportStratix II devices contain dedicated circuitry for supporting differential standards at speeds up to 1 Gbps. The LVDS and HyperTransport differential I/O standards are supported in the Stratix II device. In addition, the LVPECL I/O standard is supported on input and output clock pins on the top and bottom I/O banks.The high-speed differential I/O circuitry supports the following high speed I/O interconnect standards and applications:■SPI-4 Phase 2 (POS-PHY Level 4)■SFI-4■Parallel RapidIO■HyperTransport technologyThere are four dedicated high-speed PLLs in the EP2S15 to EP2S30 devices and eight dedicated high-speed PLLs in the EP2S60 to EP2S180 devices to multiply reference clocks and drive high-speed differential SERDES channels.Tables 2–21 through 2–26 show the number of channels that each fast PLL can clock in each of the Stratix II devices. In Tables 2–21 through 2–26 the first row for each transmitter or receiver provides the number of channels driven directly by the PLL. The second row below it shows the maximum channels a PLL can drive if cross bank channels are used from theadjacent center PLL. For example, in the 484-pin FineLine BGA EP2S15Non-Stratix II VCC = 3.3 Vv (1)v (2)v (3)Level shifter required Level shifter required VCC = 2.5 V v (1), (4)v (2)v (3)Level shifter required Level shifter required VCC = 1.8 V v (1), (4)v (2), (5)v Level shifter requiredLevel shifter requiredVCC = 1.5 Vv (1), (4)v (2), (5)v (6)v vNotes to Table 2–20:(1)The TDO output buffer meets V OH (MIN) = 2.4 V .(2)The TDO output buffer meets V OH (MIN) = 2.0 V .(3)An external 250- pull-up resistor is not required, but recommended if signal levels on the board are not optimal.(4)Input buffer must be 3.3-V tolerant.(5)Input buffer must be 2.5-V tolerant.(6)Input buffer must be 1.8-V tolerant.Table 2–20.Supported TDO/TDI Voltage Combinations (Part 2 of 2)DeviceTDI InputBuffer Power Stratix II TDO V C C I O Voltage Level in I/O Bank 4VC C I O = 3.3 V V C C I O = 2.5 V V C C I O = 1.8 V V C C I O = 1.5 V V C C I O = 1.2 VDocumentRevision HistoryTable2–27 shows the revision history for this chapter.Table2–27.Document Revision History (Part 1 of2)Date andDocumentVersionChanges Made Summary of Changes May 2007, v4.3Updated “Clock Control Block” section.—Updated note in the “Clock Control Block” section.—Deleted Tables 2-11 and 2-12.—Updated notes to:●Figure2–41●Figure2–42●Figure2–43●Figure2–45—Updated notes to Table2–18.—Moved Document Revision History to end of the chapter.—August 2006,v4.2Updated Table2–18 with note.—April 2006, v4.1●Updated T able2–13.●Removed Note 2 from T able2–16.●Updated “On-Chip Termination” section and T able2–19 toinclude parallel termination with calibration information.●Added new “On-Chip Parallel Termination with Calibration”section.●Updated Figure2–44.●Added parallel on-chip terminationdescription andspecification.●Changed RCLKnames to match theQuartus II software inT able2–13.December2005, v4.0Updated “Clock Control Block” section.—July 2005, v3.1●Updated HyperT ransport technology information in Table2–18.●Updated HyperT ransport technology information inFigure2–57.●Added information on the asynchronous clear signal.—May 2005, v3.0●Updated “Functional Description” section.●Updated T able2–3.●Updated “Clock Control Block” section.●Updated T ables2–17 through 2–19.●Updated T ables2–20 through 2–22.●Updated Figure2–57.—March 2005, 2.1●Updated “Functional Description” section.●Updated T able2–3.—。
FPGA可编程逻辑器件芯片EP2SGX30DF780C5N中文规格书
Adaptive Logic ModulesOne ALM contains two programmable registers. Each register has data,clock, clock enable, synchronous and asynchronous clear, asynchronousload data, and synchronous and asynchronous load/preset inputs.Global signals, general-purpose I/O pins, or any internal logic can drivethe register’s clock and clear control signals. Either general-purpose I/Opins or internal logic can drive the clock enable, preset, asynchronousload, and asynchronous load data. The asynchronous load data inputcomes from the datae or dataf input of the ALM, which are the sameinputs that can be used for register packing. For combinational functions,the register is bypassed and the output of the LUT drives directly to theoutputs of the ALM.Each ALM has two sets of outputs that drive the local, row, and columnrouting resources. The LUT, adder, or register output can drive theseoutput drivers independently (see Figure2–36). For each set of outputdrivers, two ALM outputs can drive column, row, or direct link routingconnections, and one of these ALM outputs can also drive localinterconnect resources. This allows the LUT or adder to drive one outputwhile the register drives another output. This feature, called registerpacking, improves device utilization because the device can use theregister and the combinational logic for unrelated functions. Anotherspecial packing mode allows the register output to feed back into the LUTof the same ALM so that the register is packed with its own fan-out LUT.This feature provides another mechanism for improved fitting. The ALMcan also drive out registered and unregistered versions of the LUT oradder output.f See the Stratix II Performance and Logic Efficiency Analysis White Paper formore information on the efficiencies of the Stratix II GX ALM andcomparisons with previous architectures.ALM Operating ModesThe Stratix II GX ALM can operate in one of the following modes:■Normal mode■Extended LUT mode■Arithmetic mode■Shared arithmetic modeEach mode uses ALM resources differently. Each mode has 11 availableinputs to the ALM (see Figure2–35)—the eight data inputs from the LABlocal interconnect; carry-in from the previous ALM or LAB; the sharedarithmetic chain connection from the previous ALM or LAB; and theregister chain connection—are directed to different destinations toimplement the desired logic function. LAB-wide signals provide clock,Clear and Preset Logic ControlLAB-wide signals control the logic for the register’s clear and load/preset signals. The ALM directly supports an asynchronous clear and preset function. The register preset is achieved through the asynchronous load of a logic high. The direct asynchronous preset does not require a NOT gate push-back technique. Stratix II GX devices support simultaneous asynchronous load/preset and clear signals. An asynchronous clear signal takes precedence if both signals are asserted simultaneously. Each LAB supports up to two clears and one load/preset signal.In addition to the clear and load/preset ports, Stratix II GX devices provide a device-wide reset pin (DEV_CLRn) that resets all registers in the device. An option set before compilation in the Quartus II software controls this pin. This device-wide reset overrides all other control signals.MultiTrack Interconnect In the Stratix II GX architecture, the MultiTrack interconnect structure with DirectDrive technology provides connections between ALMs, TriMatrix memory, DSP blocks, and device I/O pins. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity. The Quartus II Compiler automatically places critical design paths on faster interconnects to improve design performance. DirectDrive technology is a deterministic routing technology that ensures identical routing resource usage for any function regardless of placement in the device. The MultiTrack interconnect and DirectDrive technology simplify the integration stage of block-based designing by eliminating the re-optimization cycles that typically follow design changes and additions.The MultiTrack interconnect consists of row and column interconnects that span fixed distances. A routing structure with fixed length resources for all devices allows predictable and repeatable performance when migrating through different device densities. Dedicated row interconnects route signals to and from LABs, DSP blocks, and TriMatrix memory in the same row.These row resources include:■Direct link interconnects between LABs and adjacent blocks■R4 interconnects traversing four blocks to the right or left■R24 row interconnects for high-speed access across the length of the deviceMultiTrack InterconnectThe direct link interconnect allows a LAB, DSP block, or TriMatrixmemory block to drive into the local interconnect of its left and rightneighbors and then back into itself, providing fast communicationbetween adjacent LABs and/or blocks without using row interconnectresources.The R4 interconnects span four LABs, three LABs and one M512 RAMblock, two LABs and one M4K RAM block, or two LABs and one DSPblock to the right or left of a source LAB. These resources are used for fastrow connections in a four-LAB region. Every LAB has its own set of R4interconnects to drive either left or right. Figure2–46 shows R4interconnect connections from a LAB.R4 interconnects can drive and be driven by DSP blocks and RAM blocksand row IOEs. For LAB interfacing, a primary LAB or LAB neighbor candrive a given R4 interconnect. For R4 interconnects that drive to the right,the primary LAB and right neighbor can drive onto the interconnect. ForR4 interconnects that drive to the left, the primary LAB and its leftneighbor can drive onto the interconnect. R4 interconnects can driveother R4 interconnects to extend the range of LABs they can drive. R4interconnects can also drive C4 and C16 interconnects for connectionsfrom one row to another. Additionally, R4 interconnects can drive R24interconnects.Figure2–46.R4 Interconnect Connections Notes(1), (2), (3)Notes to Figure2–46:(1)C4 and C16 interconnects can drive R4 interconnects.(2)This pattern is repeated for every LAB in the LAB row.(3)The LABs in Figure2–46 show the 16 possible logical outputs per LAB.。
FPGA可编程逻辑器件芯片EP2SGX30DF780I4中文规格书
Logic Array BlocksApplications and Protocols Supported with Stratix II GX DevicesEach Stratix II GX transceiver block is designed to operate at any serial bitrate from 600 Mbps to 6.375 Gbps per channel. The wide data rate rangeallows Stratix II GX transceivers to support a wide variety of standardsand protocols, such as PCI Express, GIGE, SONET/SDH, SDI, OIF-CEI,and XAUI. Stratix II GX devices are ideal for many high-speedcommunication applications, such as high-speed backplanes,chip-to-chip bridges, and high-speed serial communications links.Example Applications Support for Stratix II GXStratix II GX devices can be used for many applications, including:■Traffic management with various levels of quality of service (QoS)and integrated serial backplane interconnect■Multi-port single-protocol switching (for example, PCI Express,GIGE, XAUI switch, or SONET/SDH)Logic Array Blocks Each logic array block (LAB) consists of eight adaptive logic modules (ALMs), carry chains, shared arithmetic chains, LAB control signals, local interconnects, and register chain connection lines. The local interconnect transfers signals between ALMs in the same LAB. Register chain connections transfer the output of an ALM register to the adjacent ALM register in a LAB. The Quartus II Compiler places associated logic in a LAB or adjacent LABs, allowing the use of local, shared arithmetic chain, and register chain connections for performance and area efficiency. Table2–17 shows Stratix II GX device resources. Figure2–32 shows the Stratix II GX LAB structure.Table2–17.Stratix II GX Device ResourcesDeviceM512 RAMColumns/BlocksM4K RAMColumns/BlocksM-RAMBlocksDSP BlockColumns/BlocksLABColumnsLAB RowsEP2SGX306/2024/14412/164936 EP2SGX607/3295/25523/366251 EP2SGX908/4886/40843/487168 EP2SGX1309/6997/60963/638187Adaptive Logic ModulesFigure2–41.ALM in Arithmetic ModeWhile operating in arithmetic mode, the ALM can support simultaneoususe of the adder’s carry output along with combinational logic outputs.In this operation, the adder output is ignored. This usage of the adderwith the combinational logic output provides resource savings of up to50% for functions that can use this ability. An example of suchfunctionality is a conditional operation, such as the one shown inFigure2–42. The equation for this example is:R = (X < Y) ? Y : XTo implement this function, the adder is used to subtract ‘Y’ from ‘X’. If‘X’ is less than ‘Y’, the carry_out signal will be ‘1’. The carry_outsignal is fed to an adder where it drives out to the LAB local interconnect.It then feeds to the LAB-wide syncload signal. When asserted,syncload selects the syncdata input. In this case, the data ‘Y’ drivesthe syncdata inputs to the registers. If ‘X’ is greater than or equal to ‘Y’,the syncload signal is de-asserted and ‘X’ drives the data port of theregisters.Figure2–42.Conditional Operation ExampleThe arithmetic mode also offers clock enable, counter enable, synchronous up and down control, add and subtract control, synchronous clear, synchronous load. The LAB local interconnect data inputs generate the clock enable, counter enable, synchronous up and down and add and subtract control signals. These control signals may be used for the inputs that are shared between the four LUTs in the ALM. The synchronous clear and synchronous load options are LAB-wide signals that affect all registers in the LAB. The Quartus II software automatically places any registers that are not used by the counter into other LABs.。
FPGA可编程逻辑器件芯片EP2SGX30DF780C4中文规格书
SignalTap II Embedded Logic Analyzerf For more information on JTAG, see the following documents:■The IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing for Stratix II &Stratix II GX Devices chapter of the Stratix II Device Handbook,Volume2 or the Stratix II GX Device Handbook, Volume 2■Jam Programming & Test Language SpecificationSignalTap II Embedded Logic Analyzer Stratix II devices feature the SignalTap II embedded logic analyzer, which monitors design operation over a period of time through the IEEE Std.1149.1 (JTAG) circuitry. You can analyze internal logic at speed without bringing internal signals to the I/O pins. This feature is particularly important for advanced packages, such as FineLine BGA®packages, because it can be difficult to add a connection to a pin during the debugging process after a board is designed and manufactured.Configuration The logic, circuitry, and interconnects in the Stratix II architecture areconfigured with CMOS SRAM elements. Altera® FPGA devices arereconfigurable and every device is tested with a high coverageproduction test program so you do not have to perform fault testing andcan instead focus on simulation and design verification.Stratix II devices are configured at system power-up with data stored inan Altera configuration device or provided by an external controller (e.g.,a MAX®II device or microprocessor). Stratix II devices can be configuredusing the fast passive parallel (FPP), active serial (AS), passive serial (PS),passive parallel asynchronous (PPA), and JTAG configuration schemes.The Stratix II device’s optimized interface allows microprocessors toconfigure it serially or in parallel, and synchronously or asynchronously.The interface also enables microprocessors to treat Stratix II devices asmemory and configure them by writing to a virtual memory location,making reconfiguration easy.In addition to the number of configuration methods supported, Stratix IIdevices also offer the design security, decompression, and remote systemupgrade features. The design security feature, using configurationbitstream encryption and AES technology, provides a mechanism toprotect your designs. The decompression feature allows Stratix II FPGAsto receive a compressed configuration bitstream and decompress thisdata in real-time, reducing storage requirements and configuration time.The remote system upgrade feature allows real-time system upgradesfrom remote locations of your Stratix II designs. For more information,see “Configuration Schemes” on page3–7.Configuration & TestingOperating ModesThe Stratix II architecture uses SRAM configuration elements that require configuration data to be loaded each time the circuit powers up. The process of physically loading the SRAM data into the device is called configuration. During initialization, which occurs immediately after configuration, the device resets registers, enables I/O pins, and begins to operate as a logic device. The I/O pins are tri-stated during power-up, and before and during configuration. Together, the configuration and initialization processes are called command mode. Normal device operation is called user mode.SRAM configuration elements allow Stratix II devices to be reconfigured in-circuit by loading new configuration data into the device. With real-time reconfiguration, the device is forced into command mode with a device pin. The configuration process loads different configuration data, reinitializes the device, and resumes user-mode operation. You can perform in-field upgrades by distributing new configuration files either within the system or remotely.PORSEL is a dedicated input pin used to select POR delay times of 12 ms or 100 ms during power-up. When the PORSEL pin is connected to ground, the POR time is 100 ms; when the PORSEL pin is connected to V CC, the POR time is 12 ms.The nIO PULLUP pin is a dedicated input that chooses whether the internal pull-ups on the user I/O pins and dual-purpose configuration I/O pins (nCSO, ASDO, DATA[7..0], nWS, nRS, RDYnBSY, nCS, CS, RUnLU, PGM[2..0], CLKUSR, INIT_DONE, DEV_OE, DEV_CLR) are on or off before and during configuration. A logic high (1.5, 1.8, 2.5, 3.3 V) turns off the weak internal pull-ups, while a logic low turns them on.Stratix II devices also offer a new power supply, V CCPD, which must be connected to 3.3 V in order to power the 3.3-V/2.5-V buffer available on the configuration input pins and JTAG pins. V CCPD applies to all the JTAG input pins (TCK, TMS, TDI, and TRST) and the configuration input pins when VCCSEL is connected to ground. See Table3–4 for more information on the pins affected by VCCSEL.The VCCSEL pin allows the V CCIO setting (of the banks where the configuration inputs reside) to be independent of the voltage required by the configuration inputs. Therefore, when selecting the V CCIO, the V IL and V IH levels driven to the configuration inputs do not have to be a concern.Document Revision HistoryTable5–12.LVPECL SpecificationsSymbol Parameter Conditions Minimum Typical Maximum Unit V CCIO (1)I/O supply voltage 3.135 3.300 3.465V V ID Input differential voltage3006001,000mV swing (single-ended)V ICM Input common mode voltage 1.0 2.5V V OD Output differential voltageR L = 100 Ω525970mV (single-ended)R L = 100 Ω1,6502,250mV V OCM Output common modevoltage90100110ΩR L Receiver differential inputresistorNote to Table5–12:(1)The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by V CCINT, not V CCIO.The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clockoutput/feedback operation, VCC_PLL_OUT should be connected to 3.3 V.Table5–13.HyperTransport Technology SpecificationsSymbol Parameter Conditions Minimum Typical Maximum Unit2.375 2.500 2.625V V CCIO I/O supply voltage for left andright I/O banks (1, 2, 5, and 6)R L = 100 Ω300600900mV V ID Input differential voltage swing(single-ended)V ICM Input common mode voltage R L = 100 Ω385600845mV V OD Output differential voltageR L = 100 Ω400600820mV (single-ended)ΔV OD Change in V OD between highR L = 100 Ω75mV and lowV OCM Output common mode voltage R L = 100 Ω440600780mV ΔV OCM Change in V OCM between highR L = 100 Ω50mV and lowR L Receiver differential input90100110ΩresistorTable5–14.3.3-V PCI Specifications(Part 1 of2)Symbol Parameter Conditions Minimum Typical Maximum Unit V CCIO Output supply voltage 3.0 3.3 3.6V V IH High-level input voltage0.5 × V CCIO V CCIO + 0.5V。
FPGA可编程逻辑器件芯片EP2SGX60CF780C4N中文规格书
Chapter 4:TriMatrix Embedded Memory Blocks in Stratix III DevicesClocking ModesClocking ModesStratix III TriMatrix memory blocks support the following clocking modes:■Independent■Input/output■Read/write■Single clock1Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This applies to both read and write operations.1Altera recommends using a memory block clock that comes through global clock routing from an on-chip PLL set to 50% output duty cycle to achieve the maximummemory block performance. Use Quartus II to report timing for this and othermemory block clocking schemes.f For more information refer to the Stratix III Device Family Errata Sheet.Table4–9 shows the clocking mode versus memory mode support matrix.Table4–9.Stratix III TriMatrix Memory Clock ModesIndependent Clock ModeStratix III TriMatrix memory blocks can implement independent clock mode for truedual-port memories. In this mode, a separate clock is available for each port (A andB). Clock A controls all registers on the port A side, while clock B controls all registerson the port B side. Each port also supports independent clock enables for port A andport B registers. Asynchronous clears are supported only for output latches andoutput registers on both ports.Input/Output Clock ModeStratix III TriMatrix memory blocks can implement input/output clock mode for trueand simple dual-port memories. In this mode, an input clock controls all registersrelated to the data input to the memory block, including data, address, byte-enables,read enables, and write enables. An output clock controls the data output registers.Asynchronous clears are available on output latches and output registers only.Chapter 4:TriMatrix Embedded Memory Blocks in Stratix III DevicesDesign ConsiderationsRead/Write Clock ModeStratix III TriMatrix memory blocks can implement read/write clock mode for simpledual-port memories. In this mode, a write clock controls the data-input,write-address, and write-enable registers. Similarly, a read clock control thedata-output, read-address, and read-enable registers. The memory blocks supportindependent clock enables for both the read and write clocks. Asynchronous clearsare available on data output latches and registers only.When using read/write mode, if you perform a simultaneous read/write to the sameaddress location, the output read data will be unknown. If you require the output datato be a known value in this case, use either single-clock mode or input/output clockmode and choose the appropriate read-during-write behavior in the Megawizard.Single Clock ModeStratix III TriMatrix memory blocks can implement single-clock mode for truedual-port, simple dual-port, and single-port memories. In this mode, a single clock,together with a clock enable, is used to control all registers of the memory block.Asynchronous clears are available on output latches and output registers only.Design ConsiderationsThis section describes guidelines for designing with TriMatrix memory blocks.Selecting TriMatrix Memory BlocksThe Quartus II software automatically partitions user-defined memory intoembedded memory blocks by taking into account both speed and size constraintsplaced on your design. For example, the Quartus II software may spread out amemory across multiple memory blocks when resources are available to increase theperformance of the design. You can manually assign the memory to a specific blocksize via the RAM MegaWizard Plug-In Manager.MLABs can implement single-port SRAM through emulation via the Quartus IIsoftware. Emulation results in minimal additional logic resources being used. Becauseof the dual-purpose architecture of the MLAB, it only has data input registers andoutput registers in the block. MLABs gain input address registers and additionaloptional data output registers from adjacent ALMs by using register packing.f For more information about register packing, refer to the Logic Array Blocks andAdaptive Logic Modules in Stratix III Devices chapter in volume 1 of the Stratix III DeviceHandbook.Conflict ResolutionWhen using the memory blocks in true dual-port mode, it is possible to attempt twowrite operations to the same memory location (address). Since no conflict resolutioncircuitry is built into the memory blocks, this results in unknown data being written tothat location. Therefore, you must implement conflict resolution logic external to thememory block to avoid address conflicts.xxiv List of TablesSection I: Device CoreRevision HistoryChapter 5:DSP Blocks in Stratix III DevicesOperational Mode DescriptionsThe second-stage and output registers are triggered by the positive edge of the clocksignal and are cleared on power up. The following DSP block signals control theoutput registers within the DSP block:■clock[3..0]■ena[3..0]■aclr[3..0]Operational Mode DescriptionsThe various modes of operation are discussed below.Independent Multiplier ModesIn independent input and output multiplier mode, the DSP block performs individualmultiplication operations for general-purpose multipliers.9-, 12-, and 18-Bit MultiplierYou can configure each DSP block multiplier for 9-, 12-, or 18-bit multiplication. Asingle DSP block can support up to eight individual 9×9 multipliers, six 12×12multipliers, or up to four individual 18×18 multipliers. For operand widths up to9bits, a 9×9 multiplier is implemented. For operand widths from 10 to 12 bits, a12×12 multiplier is implemented, and for operand widths from 13 to 18 bits, an18×18 multiplier is implemented. This is done by the Quartus II software byzero-padding the LSBs. Figure5–8, Figure5–9, and Figure5–10 show the DSP block inthe independent multiplier operation mode.Figure5–8.18-Bit Independent Multiplier Mode for Half-DSP Blockwresult_0[ ]data bdata b。
FPGA可编程逻辑器件芯片EP3SL200H780C4中文规格书
Table 5–30. Series On-Chip Termination Specification for Top & Bottom I/O Banks (Part 2 of 2) Notes (1), 2
Symbol
Description
Conditions
Timing Model
Internal Timing Parameters
See Tables 5–37 through 5–42 for internal timing parameters.
Table 5–37. LE_FF Internal Timing Microparameters
Symbol
Internal series termination without calibration (25- setting)
Internal series termination with calibration (50- setting)
Internal series termination without calibration (50- setting)
number is the minimum timing parameter for commercial devices.
Stratix II Device Handbook, Volume 1
Timing Model
Clock Network Skew Adders
The Quartus II software models skew within dedicated clock networks such as global and regional clocks. Therefore, intra-clock network skew adder is not specified. Table 5–68 specifies the clock skew between any two clock networks driving registers in the IOE.
FPGA可编程逻辑器件芯片EP1AGX60DF780C6N中文规格书
System Reset and BootingThese functions are:•BFROM_MEMBOOT discussed in “Flash Boot Modes” on page17-62 and “SDRAM Boot Mode” on page17-66•BFROM_TWIBOOT discussed in “TWI Master Boot Mode” onpage17-77•BFROM_SPIBOOT discussed in “SPI Master Boot Modes” onpage17-69•BFROM_OTPBOOT discussed in “OTP Boot Mode” on page17-85•BFROM_NANDBOOT discussed in “NAND Flash Boot Mode” on page17-88The user application, the boot manager application, or an initcode can call these functions to load the requested boot data. Using the BFLAG_RETURN flag the user can control whether the routine simply returns to the calling function or executes the loaded application immediately.These ROM functions expect the start address of the requested bootstream as an argument. For BFROM_MEMBOOT, this is a Blackfin memory address, for BFROM_TWIBOOT and BFROM_SPIBOOT it is a serial address. The SPI function can also accept the code for the GPIO pin that controls the device select strobe of the SPI memory.ADSP-BF54x Blackfin Processor Hardware ReferenceSpecific Boot ModesADSP-BF54x Blackfin Processor Hardware ReferenceFigure 17-17 on page 17-73 shows the initial signaling when a 24-bit addressable SPI memory is connected in SPI master boot mode. After RESET releases and preboot has processed relevant OTP pages, a 0x03 com-mand is transmitted to the MOSI output, followed by a number of 0x00 bytes. The 24-bit addressable memory device returns a first data byte at the fourth zero byte. Then, the device detection has completed and the boot kernel re-issues a 0x00 address to load the boot stream.Figure 17-16. SPI Device Detection Principle。
FPGA可编程逻辑器件芯片EP2SGX60CF780I4N中文规格书
Chapter 1:Stratix III Device Data Sheet: DC and Switching Characteristics Electrical CharacteristicsStratix III Device Handbook, Volume 2Table 1–9 lists OCT variation with temperature and voltage after power-upcalibration. Use Table 1–9 and Equation 1–1 to determine OCT variation without re-calibration.Table 1–8.Stratix III On-Chip Termination Resistance Tolerance SpecificationSymbol Description Conditions Resistance Tolerance UnitC2C3, I3C4, I4R OCT_UNCALInternal series termination without calibration—25-Ω R S 3.3/3.0/2.5Internal series termination without calibration (25-Ω setting)V CCIO = 3.3/3.0/2.5 V ±30±40±40%25-Ω R S 1.8/1.5Internal series termination without calibration (25-Ω setting)V CCIO = 1.8/1.5 V ±30±50±50%25-Ω R S 1.2Internal series termination without calibration (25-Ω setting)V CCIO = 1.2 V ±35±60±60%50-Ω R S 3.3/3.0/2.5Internal series termination without calibration (50-Ω setting)V CCIO = 3.3/3.0/2.5 V ±30±40±40%50-Ω R S 1.8/1.5Internal series termination without calibration (50-Ω setting)V CCIO = 1.8/1.5 V ±30±50±50%50-Ω R S 1.2Internal series termination without calibration (50-Ω setting)V CCIO = 1.2 V±35±60±60%Equation 1–1.OCT Variation Without Re-Calibration (Note 1)Notes to Equation 1–1:(1)R OCT value calculated from Equation 1–1 shows the range of OCT resistance with the variation of temperature andV CCIO .(2)R SCAL is the OCT resistance value at power-up.(3)∆T is the variation of temperature with respect to the temperature at power-up.(4)∆V is the variation of voltage with respect to the V CCIO at power-up.(5)dR/dT is the percentage change of R SCAL with temperature.(6)dR/dV is the percentage change of R SCAL with voltage.R OCT R SCAL 1dR dT ------∆T ⨯〈〉dR dV ------∆V ⨯〈〉±+⎝⎭⎛⎫=Table 1–9.On-Chip Termination Variation after Power-up Calibration (Part 1 of 2) (Note 1)SymbolDescriptionV CCIO (V)Commercial Typical Unit dR/dVOCT variation with voltage without re-calibration30.029%/mV 2.50.036%/mV 1.80.065%/mV 1.50.104%/mV 1.20.177%/mVChapter 1:Stratix III Device Data Sheet: DC and Switching CharacteristicsElectrical CharacteristicsStratix III Device Handbook, Volume 2Pin CapacitanceTable 1–10 shows the Stratix III device family pin capacitance. Hot-SocketingTable 1–11 lists the hot-socketing specifications for Stratix III devices.Internal Weak Pull-Up ResistorTable 1–12 lists the weak pull-up resistor values for Stratix III devices.dR/dTOCT variation with temperature without re-calibration30.294%/°C2.50.301%/°C 1.80.355%/°C 1.50.344%/°C 1.20.348%/°C Note to Table 1–9:(1)Valid for V CCIO range of ±5% and temperature range of 0° to 85° C.Table 1–9.On-Chip Termination Variation after Power-up Calibration (Part 2 of 2) (Note 1)SymbolDescriptionV CCIO (V)Commercial Typical UnitTable 1–10.Stratix III Device CapacitanceSymbol ParameterTypical Unit C IOTB Input capacitance on top/bottom I/O pins 4pF C IOLR Input capacitance on left/right I/O pins 4pF C CLKTB Input capacitance on top/bottom non-dedicated clock input pins4pF C CLKLR Input capacitance on left/right non-dedicatedclock input pins4pF C OUTFBInput capacitance on dual-purpose clock output/feedback pins5pF C CLK1, C CLK3, C CLK8, and C CLK10Input capacitance for dedicated clock inputpins2pFTable 1–11.Stratix III Hot-Socketing SpecificationsSymbol Parameter Maximum I IOPIN (DC)DC current per I/O pin 300 μA I IOPIN (AC)AC current per I/O pin8 mA for ≤ 10 nsChapter 1:Stratix III Device Data Sheet: DC and Switching CharacteristicsI/O TimingStratix III Device Handbook, Volume 2Chapter 1:Stratix III Device Data Sheet: DC and Switching CharacteristicsI/O TimingStratix III Device Handbook, Volume 2。
FPGA可编程逻辑器件芯片EP2S90F780C5中文规格书
TransceiversThe rx_syncstatus signal is not available in bit-slipping mode.Channel AlignerThe channel aligner is available only in XAUI mode and aligns the signalsof all four channels within a transceiver. The channel aligner follows theIEEE802.3ae, clause 48 specification for channel bonding.The channel aligner is a 16-word FIFO buffer with a state machinecontrolling the channel bonding process. The state machine looks for an/A/ (/K28.3/) in each channel, and aligns all the /A/ code groups in thetransceiver. When four columns of /A/ (denoted by //A//) aredetected, the rx_channelaligned signal goes high, signifying that allthe channels in the transceiver have been aligned. The reception of fourconsecutive misaligned /A/ code groups restarts the channel alignmentsequence and sends the rx_channelaligned signal low.Figure2–19 shows misaligned channels before the channel aligner andthe aligned channels after the channel aligner.Figure2–19.Before and After the Channel AlignerStratix II GX ArchitectureRate MatcherRate matcher is available in Basic, PCI Express, XAUI, and GIGE modes and consists of a 20-word deep FIFO buffer and a FIFO controller. Figure2–20 shows the implementation of the rate matcher in the Stratix II GX device.Figure2–20.Rate MatcherIn a multi-crystal environment, the rate matcher compensates for up to a ±300-PPM difference between the source and receiver clocks. Table2–8 shows the standards supported and the PPM for the rate matcher tolerance.Table2–8.Rate Matcher PPM Support Note(1)Standard PPMXAUI±100PCI Express (PIPE)±300GIGE±100Basic Double-Width±300Note to Table2–8:(1)Refer to the Stratix II GX Transceiver User Guide for the Altera®-defined scheme. Basic ModeIn Basic mode, you can program the skip and control pattern for rate matching. In single-width Basic mode, there is no restriction on the deletion of a skip character in a cluster. The rate matcher deletes the skip characters as long as they are available. For insertion, the rate matcher inserts skip characters such that the number of skip characters at the output of rate matcher does not exceed five. In double-width mode, the rate matcher deletes skip character when they appear as pairs in the upper and lower bytes. There are no restrictions on the number of skip characters that are deleted. The rate matcher inserts skip characters as pairs.TransceiversGIGE ModeIn GIGE mode, the rate matcher adheres to the specifications in clause36of the IEEE 802.3 documentation for idle additions or removals. The ratematcher performs clock compensation only on /I2/ ordered sets,composed of a /K28.5/+ followed by a /D16.2/-. The rate matcher doesnot perform clock compensation on any other ordered set combinations.An /I2/ is added or deleted automatically based on the number of wordsin the FIFO buffer. A K28.4 is given at the control and data ports when theFIFO buffer is in an overflow or underflow condition.XAUI ModeIn XAUI mode, the rate matcher adheres to clause 48 of the IEEE 802.3aespecification for clock rate compensation. The rate matcher performsclock compensation on columns of /R/ (/K28.0/), denoted by //R//.An //R// is added or deleted automatically based on the number ofwords in the FIFO buffer.PCI Express ModePCI Express mode operates at a data rate of 2.5 Gbps, and supports lanewidths of ×1, ×2, ×4, and ×8. The rate matcher can support up to±300-PPM differences between the upstream transmitter and thereceiver. The rate matcher looks for the skip ordered sets (SOS), whichusually consist of a /K28.5/ comma followed by three /K28.0/ skipcharacters. The rate matcher deletes or inserts skip characters whennecessary to prevent the rate matching FIFO buffer from overflowing orunderflowing.The Stratix II GX rate matcher in PCI Express mode has FIFO overflowand underflow protection. In the event of a FIFO overflow, the ratematcher deletes any data after the overflow condition to prevent FIFOpointer corruption until the rate matcher is not full. In an underflowcondition, the rate matcher inserts 9'h1FE (/K30.7/) until the FIFO is notempty. These measures ensure that the FIFO can gracefully exit theoverflow and underflow condition without requiring a FIFO reset.8B/10B DecoderThe 8B/10B decoder (Figure2–21) is part of the Stratix II GX transceiverdigital blocks (PCS) and lies in the receiver path between the rate matcherand the byte deserializer blocks. The 8B/10B decoder operates insingle-width and double-width modes, and can be bypassed if the8B/10B decoding is not necessary. In single-width mode, the 8B/10Bdecoder restores the 8-bit data + 1-bit control identifier from the 10-bitcode. In double-width mode, there are two 8B/10B decoders in parallel,which restores the 16-bit (2 × 8-bit) data + 2-bit (2 × 1-bit) control identifierfrom the 20-bit (2 × 10-bit) code. This 8B/10B decoder conforms to theIEEE 802.3 1998 edition standards.。
FPGA可编程逻辑器件芯片EP2AGX260EF29C4N中文规格书
DMC P ROGRAMMING M ODELa)Enter into self-refreshb)Change the clock frequency, as requiredc)Wait for DLL lockd)Exit self refreshe)Write new control register valuesf)Set init bit in DMC_CTL register and poll the MEMINITDONE and DLLCALDONE bits within theDMC_STAT registerg)Write to the DMC_DLLCTL register.Note that for cases where the DDR2 interface has already been initialized (whether it is via an XML file loaded in during a debug session, or through code executed during the booting process), the user needs to perform second-time initialization as described above.Saving Power with the DMCThis section discusses the suggested flow to enter and exit DDR self-refresh before and after the processor enters the HIBERNATE state.For this procedure, the system is in normal operation and the EXT_WAKE signal is high.1.Put the SDRAM in self-refresh mode by setting the DMC_CTL.SRREQ bit.S TEP R ESULT:The DDR goes through the self-refresh entry sequence and enters the Self Refresh state.S TEP R ESULT:The DMC_STAT.SRACK bit is set.S TEP R ESULT:The CKE pin is driven low by the controller when the DDR has entered Self-Refresh.2.Read the DMC_DLLCTL register to get the current DLL tap and calibration settings. This can be used laterto quickly lock and start normal DDR operation. The values read are stored in the DPM registers.3.Initialize the Power-On Reset Delay register to the appropriate values to count off the time requiredfor core V DD to reach a safe value when exiting the Hibernate state.4.Enter the Hibernate state by following the procedure detailed in the DPM chapter. Hibernate is indi-cated by the EXT_WAKE signal going low.5.When EXT_WAKE goes low, the part enters Hibernate state and remains here until brought out by thisstate through SYS_PWRGD pin/counter expiry.6.When a wake-up event occurs, first the EXT_WAKE signal goes high.A DDITIONAL I NFORMATION:When core V DD power reaches a proper value, the Core domain logic is reset.The DDR controller drives the input of the CKE pad low. When this counter reaches 0 a CounterADSP-BF60X DMC R EGISTER D ESCRIPTIONS11:9 (R/W)RDTOWR Read-to-Write Cycle.The DMC_CTL.RDTOWR bits select the number of cycles that the DMCadds when a write operation follows a read operation. Note thatvalues 101 through 111 are reserved.00 Cycles Added1 1 Cycle Added2 2 Cycles Added3 3 Cycles Added4 4 Cycles Added8 (R/W)ADDRMODE Addressing (Page/Bank) Mode.The DMC_CTL.ADDRMODE bit selects whether the DMC uses page orbank interleaving for addressing. When using page interleaving, thebank address bits follow the most significant column address bits.When using bank interleaving, the bank address bits follow the mostsignificant row address bits.0Bank Interleaving1Page Interleaving6 (R/W)PREC Precharge.The DMC_CTL.PREC bit enables pre-charge, which closes DRAM rowsimmediately after access. When disabled, all accesses result in therespective DRAM rows remaining open, until the DMC needs toclose them.0No Effect1Enable Precharge5 (R/W)DPDREQ Deep Power Down Request.The DMC_CTL.DPDREQ bit enables deep powerdown mode if lowpower DMC operation is enabled (DMC_CTL.LPDDR =1}). When theprocessor does not require the data stored in SDRAM (assume resetstate of SDRAM), the DMC may put the SDRAM in deep powerdownmode. When the DMC is in deep powerdown, any data accessescause the DMC to generate a bus error.0Disable Deep Powerdown1Enable Deep PowerdownTable 11-3:DMC_CTL Register Fields (Continued)Bit No.(Access)Bit Name Description/EnumerationD YNAMIC M EMORY C ONTROLLER (DMC)F UNCTIONAL D ESCRIPTION•Sends and receives data to/from the protocol controller.•Creates suitable read/write response and sends read data back to the system crossbar bus.The system crossbar slave interface supports the following:•all burst lengths (1 – 16)•incremental and wrap bursts•data transfer sizes of 8, 16 or 32-bits•arrival of write data before write address•generation of error responses which includes–any access to un-implemented region of the external memory space–any access when the SDRAM is in self-refresh, power-down or deep power down (in case of LPDDR)–any access when the direct command interface is in operationRead/Write Command and Data BuffersThe system crossbar interface comprises of a four deep read command buffer and a four deep writecommand buffer. Up to four write commands and four read commands can be waiting for access to the SDRAM. The system crossbar write buffer is 32 deep. It can support write data interleaving of two. The system crossbar read buffer is 32 deep.Peripheral Bus Slave InterfaceThe peripheral bus slave interface connects the dynamic memory controller to the peripheral bus and provides a host controller with access to the registers. The peripheral bus slave interface supports the following features:•read and write word accesses•32-bit data bus•Ability to extend a transfer using PREADY•Generation of PSLVERR when unimplemented registers are accessed or when read-only registers are written.Architectural ConceptsThe following sections provide information on the architecture of the interface.。
FPGA可编程逻辑器件芯片EP4SGX360KF43C4中文规格书
Configuring Stratix II and Stratix II GX Devices Data is continuously clocked into the target device until CONF_DONE goes high. The CONF_DONE pin goes high one byte early in parallel configuration (FPP and PPA) modes. The last byte is required for serial configuration (AS and PS) modes. After the device has received the next to last byte of the configuration data successfully, it releases theopen-drain CONF_DONE pin, which is pulled high by an external 10-kΩpull-up resistor. A low-to-high transition on CONF_DONE indicates configuration is complete and initialization of the device can begin. The CONF_DONE pin must have an external 10-kΩ pull-up resistor in order for the device to initialize.In Stratix II and Stratix II GX devices, the initialization clock source is either the internal oscillator (typically 10MHz) or the optional CLKUSR pin. By default, the internal oscillator is the clock source for initialization. If the internal oscillator is used, the Stratix II or Stratix II GX device provides itself with enough clock cycles for proper initialization. Therefore, if the internal oscillator is the initialization clock source, sending the entire configuration file to the device is sufficient to configure and initialize the device. Driving DCLK to the device after configuration is complete does not affect device operation.You can also synchronize initialization of multiple devices or to delay initialization with the CLKUSR option. The Enable user-supplied start-up clock (CLKUSR) option can be turned on in the Quartus II software from the General tab of the Device & Pin Options dialog box. Supplying a clock on CLKUSR does not affect the configuration process. TheCONF_DONE pin goes high one byte early in parallel configuration (FPP and PPA) modes. The last byte is required for serial configuration (AS and PS) modes. After the CONF_DONE pin transitions high, CLKUSR is enabled after the time specified as t CD2CU. After this time period elapses, Stratix II and Stratix II GX devices require 299 clock cycles to initialize properly and enter user mode. Stratix II and Stratix II GX devices support a CLKUSR f MAX of 100MHz.An optional INIT_DONE pin is available, which signals the end of initialization and the start of user-mode with a low-to-high transition. This Enable INIT_DONE Output option is available in the Quartus II software from the General tab of the Device & Pin Options dialog box. If the INIT_DONE pin is used, it is high because of an external 10-kΩpull-up resistor when nCONFIG is low and during the beginning of configuration. Once the option bit to enable INIT_DONE is programmed into the device (during the first frame of configuration data), theINIT_DONE pin goes low. When initialization is complete, theINIT_DONE pin is released and pulled high. The MAX II device must be able to detect this low-to-high transition, which signals the device hasStratix II Device Handbook, Volume2Fast Passive Parallel Configurationentered user mode. When initialization is complete, the device enters usermode. In user-mode, the user I/O pins no longer have weak pull-upresistors and function as assigned in your design.To ensure DCLK and DATA[7..0] are not left floating at the end ofconfiguration, the MAX II device must drive them either high or low,whichever is convenient on your board. The DATA[7..0] pins areavailable as user I/O pins after configuration. When you select the FPPscheme in the Quartus II software, as a default, these I/O pins aretri-stated in user mode. To change this default option in the Quartus IIsoftware, select the Pins tab of the Device & Pin Options dialog box.The configuration clock (DCLK) speed must be below the specifiedfrequency to ensure correct configuration. No maximum DCLK periodexists, which means you can pause configuration by halting DCLK for anindefinite amount of time.1If you are using the Stratix II or Stratix II GX decompressionand/or design security feature and need to stop DCLK, it canonly be stopped three clock cycles after the last data byte waslatched into the Stratix II or Stratix II GX device.By stopping DCLK, the configuration circuit allows enough clock cycles toprocess the last byte of latched configuration data. When the clockrestarts, the MAX II device must provide data on the DATA[7..0] pinsprior to sending the first DCLK rising edge.If an error occurs during configuration, the device drives its nSTATUS pinlow, resetting itself internally. The low signal on the nSTATUS pin alsoalerts the MAX II device that there is an error. If the Auto-restartconfiguration after error option (available in the Quartus II softwarefrom the General tab of the Device & Pin Options (dialog box) is turnedon, the device releases nSTATUS after a reset time-out period (maximumof 100µs). After nSTATUS is released and pulled high by a pull-upresistor, the MAX II device can try to reconfigure the target devicewithout needing to pulse nCONFIG low. If this option is turned off, theMAX II device must generate a low-to-high transition (with a low pulseof at least 2µs) on nCONFIG to restart the configuration process.The MAX II device can also monitor the CONF_DONE and INIT_DONEpins to ensure successful configuration. The CONF_DONE pin must bemonitored by the MAX II device to detect errors and determine whenprogramming completes. If all configuration data is sent, but theCONF_DONE or INIT_DONE signals have not gone high, the MAX IIdevice will reconfigure the target device.Stratix II Device Handbook, Volume2Configuring Stratix II and Stratix II GX Devices1If the optional CLKUSR pin is used and nCONFIG is pulled lowto restart configuration during device initialization, you need toensure CLKUSR continues toggling during the time nSTATUS islow (maximum of 100µs).When the device is in user-mode, initiating a reconfiguration is done bytransitioning the nCONFIG pin low-to-high. The nCONFIG pin should below for at least 2µs. When nCONFIG is pulled low, the device also pullsnSTATUS and CONF_DONE low and all I/O pins are tri-stated. OncenCONFIG returns to a logic high level and nSTATUS is released by thedevice, reconfiguration begins.Figure7–4 shows how to configure multiple devices using a MAX IIdevice. This circuit is similar to the FPP configuration circuit for a singledevice, except the Stratix II or Stratix II GX devices are cascaded formulti-device configuration.Figure7–4.Multi-Device FPP Configuration Using an External HostNote to Figure7–4:(1)The pull-up resistor should be connected to a supply that provides an acceptable input signal for all devices in thechain. V CC should be high enough to meet the V IH specification of the I/O standard on the device and the external host.In multi-device FPP configuration, the first device’s nCE pin is connectedto GND while its nCEO pin is connected to nCE of the next device in thechain. The last device’s nCE input comes from the previous device, whileits nCEO pin is left floating. After the first device completes configurationin a multi-device configuration chain, its nCEO pin drives low to activatethe second device’s nCE pin, which prompts the second device to beginconfiguration. The second device in the chain begins configuration withinone clock cycle; therefore, the transfer of data destinations is transparentto the MAX II device. All other configuration pins (nCONFIG, nSTATUS,DCLK, DATA[7..0], and CONF_DONE) are connected to every device inStratix II Device Handbook, Volume2。
FPGA可编程逻辑器件芯片EP3SL70F780C4N中文规格书
•fp32_adder_inexact•fp32_adder_overflow•fp32_adder_underflowFigure 34.Sum of Two FP16 Multiplication with FP32 Addition Modefp32_adder_invalidfp32_adder_inexactfp32_adder_overflowfp32_adder_underflow*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.fp16_adder_zero(extended format)3.2.2.4. Sum of Two FP16 Multiplication with Accumulation ModeThis mode performs a summation of two half-precision multiplication and accumulatethe value into single-precision format:fp32_result(t) = [fp16_mult_top_a(t) * fp16_mult_top_b(t)] + [fp16_mult_bot_a(t) *fp16_mult_bot_b(t)] + fp32_result(t-1)The following are exception flags supported in flushed and bfloat16 formats:•fp16_mult_top_invalid•fp16_mult_top_inexact•fp16_mult_top_overflow•fp16_mult_top_underflow•fp16_mult_bot_invalid•fp16_mult_bot_inexact•fp16_mult_bot_overflow•fp16_mult_bot_underflow•fp16_adder_invalid•fp16_adder_inexact•fp16_adder_overflow•fp16_adder_underflow•fp32_adder_invalid3.Intel Agilex Variable Precision DSP Blocks Operational ModesUG-20213 | 2021.02.05Send Feedback•fp32_adder_inexact•fp32_adder_overflow•fp32_adder_underflowThe following are exception flags supported in extended format:•fp16_mult_top_invalid•fp16_mult_top_inexact•fp16_mult_top_infinite•fp16_mult_top_zero•fp16_mult_bot_invalid•fp16_mult_bot_inexact•fp16_mult_bot_infinite•fp16_mult_bot_zero•fp16_adder_invalid•fp16_adder_inexact•fp16_adder_infinite•fp16_adder_zero•fp32_adder_invalid•fp32_adder_inexact•fp32_adder_overflow•fp32_adder_underflowFigure 35.Sum of Two FP16 Multiplication with Accumulation Mode*This block diagram shows the functional representation of the DSP block. The pipeline registers are embedded within the various circuits of the DSP block.fp32_adder_invalid fp32_adder_inexact fp32_adder_overflow fp32_adder_underflowfp16_adder_zero(extended format)3.Intel Agilex Variable Precision DSP Blocks Operational ModesUG-20213 | 2021.02.05Send Feedback3.2.2.5. FP16 Vector One ModeThis mode performs a summation of two half-precision multiplications with the chainininput from the previous variable DSP Block. The output is a single-precision floating-point value which is fed into chainout.Table 19.Equations Applied to FP16 Vector One ModeChainin Parameter Vector One with Floating-pointAddition Vector One with Floating-pointSubtractionDisable fp32_result = (fp16_mult_top_a *fp16_mult_top_b) + (fp16_mult_bot_a*fp16_mult_bot_b)fp32_chainout = fp32_adder_a fp32_result = (fp16_mult_top_a *fp16_mult_top_b) - (fp16_mult_bot_a *fp16_mult_bot_b)fp32_chainout = fp32_adder_aEnable fp32_result = (fp16_mult_top_a *fp16_mult_top_b) + (fp16_mult_bot_a*fp16_mult_bot_b) + fp32_chaininfp32_chainout = fp32_adder_a fp32_result = (fp16_mult_top_a *fp16_mult_top_b) - (fp16_mult_bot_a *fp16_mult_bot_b) - fp32_chaininfp32_chainout = fp32_adder_aThe following are exception flags supported in flushed and bfloat16 formats:•fp16_mult_top_invalid•fp16_mult_top_inexact•fp16_mult_top_overflow•fp16_mult_top_underflow•fp16_mult_bot_invalid•fp16_mult_bot_inexact•fp16_mult_bot_overflow•fp16_mult_bot_underflow•fp16_adder_invalid•fp16_adder_inexact•fp16_adder_overflow•fp16_adder_underflow•fp32_adder_invalid•fp32_adder_inexact•fp32_adder_overflow•fp32_adder_underflowThe following are exception flags supported in extended format:•fp16_mult_top_invalid•fp16_mult_top_inexact•fp16_mult_top_infinite•fp16_mult_top_zero•fp16_mult_bot_invalid•fp16_mult_bot_inexact3.Intel Agilex Variable Precision DSP Blocks Operational ModesUG-20213 | 2021.02.05Send Feedback。
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MultiTrack InterconnectC16 column interconnects span a length of 16 LABs and provide the fastest resource for long column connections between LABs, TriMatrix memory blocks, DSP blocks, and IOEs. C16 interconnects can crossM-RAM blocks and also drive to row and column interconnects at every fourth LAB. C16 interconnects drive LAB local interconnects via C4 and R4 interconnects and do not drive LAB local interconnects directly. All embedded blocks communicate with the logic array similar toLAB-to-LAB interfaces. Each block (that is, TriMatrix memory and DSP blocks) connects to row and column interconnects and has localinterconnect regions driven by row and column interconnects. These blocks also have direct link interconnects for fast connections to and from a neighboring LAB. All blocks are fed by the row LAB clocks,labclk[5..0].Table 2–18 shows the Stratix II GX device’s routing scheme.Table 2–18. Stratix II GX Device Routing Scheme (Part 1 of 2)SourceDestinationS h a r e d A r i t h m e t i c C h a i nC a r r y C h a i nR e g i s t e r C h a i nL o c a l I n t e r c o n n e c tD i r e c t L i n k I n t e r c o n n e c t R 4 I n t e r c o n n e c tR 24 I n t e r c o n n e c tC 4 I n t e r c o n n e c tC 16 I n t e r c o n n e c tA L MM 512 R A M B l o c kM 4K R A M B l o c kM -R A M B l o c kD S P B l o c k sC o l u m n I O ER o w I O EShared arithmetic chain v Carry chain v Register chain vLocal interconnect v v v v v v vDirect link interconnect v R4 interconnect v v v v v R24 interconnect v v v v C4 interconnect vvv C16 interconnect v v v vALMv v v v v vv M512 RAM block v v v v M4K RAM block v v vv M-RAM block v v v vDSP blocksv vvStratix II GX ArchitectureTriMatrix MemoryTriMatrix memory consists of three types of RAM blocks: M512, M4K, and M-RAM. Although these memory blocks are different, they can all implement various types of memory with or without parity, including true dual-port, simple dual-port, and single-port RAM, ROM, and FIFO buffers. Table 2–19 shows the size and features of the different RAM blocks.Column IOE v v vRow IOEv v v vTable 2–18. Stratix II GX Device Routing Scheme (Part 2 of 2)SourceDestinationS h a r e d A r i t h m e t i c C h a i nC a r r y C h a i nR e g i s t e r C h a i nL o c a l I n t e r c o n n e c tD i r e c t L i n k I n t e r c o n n e c t R 4 I n t e r c o n n e c tR 24 I n t e r c o n n e c tC 4 I n t e r c o n n e c tC 16 I n t e r c o n n e c tA L MM 512 R A M B l o c kM 4K R A M B l o c kM -R A M B l o c kD S P B l o c k sC o l u m n I O ER o w I O ETable 2–19.TriMatrix Memory Features (Part 1 of 2)Memory FeatureM512 RAM Block (32×18 Bits)M4K RAM Block (128×36 Bits)M-RAM Block (4K ×144Bits)Maximum performance 500 MHz550 MHz420 MHzT rue dual-port memory vv Simple dual-port memory v v v Single-port memory v v vShift register v v ROM v v (1)FIFO buffer v v v Pack mode v v Byte enablev v v Address clock enable v v Parity bits v v v Mixed clock mode v v vMemory initialization (.mif )vvTriMatrix MemorySimilar to all RAM blocks, M-RAM blocks can have different clocks ontheir inputs and outputs. Either of the two clocks feeding the block canclock M-RAM block registers (renwe, address, byte enable, datain,and output registers). The output register can be bypassed. The sixlabclk signals or local interconnect can drive the control signals for theA andB ports of the M-RAM block. ALMs can also control the clock_a,clock_b, renwe_a, renwe_b, clr_a, clr_b, clocken_a, andclocken_b signals, as shown in Figure2–53.Figure2–53.M-RAM Block Control SignalsThe R4, R24, C4, and direct link interconnects from adjacent LABs oneither the right or left side drive the M-RAM block local interconnect. Upto 16 direct link input connections to the M-RAM block are possible fromthe left adjacent LABs and another 16 possible from the right adjacentLAB. M-RAM block outputs can also connect to left and right LABsthrough direct link interconnect. Figure2–54 shows an example floorplanfor the EP2SGX130 device and the location of the M-RAM interfaces.Figures2–55 and 2–56 show the interface between the M-RAM block andthe logic array.PLLs and Clock NetworksStratix II GX Architecture。