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33399中文资料

Document Number: MC33399Rev. 8.0, 10/2006Freescale Semiconductor Advance Information* This document contains certain information on a new product.Specifications and information herein are subject to change without notice.© Freescale Semiconductor, Inc., 2006. All rights reserved.Local Interconnect Network (LIN) Physical Interface•••± 5•30 k Ω••••••• Figure 1. 33399 Simplified Application Diagram33399Analog Integrated Circuit Device Data33399INTERNAL BLOCK DIAGRAMINTERNAL BLOCK DIAGRAMFigure 2. 33399 Simplified Internal Block DiagramV REF ReceiverINF ENRXDTXD GNDLIN30 k ΩVSUPDriverWAKE Wake-Up V REG ControlBiasProtectionLogicAnalog Integrated Circuit Device Data 33399PIN CONNECTIONSPIN CONNECTIONSFigure 3. 33399 8-SOICN Pin ConnectionsTable 1. 8-SOICN Pin DefinitionsA functional description of each pin can be found in the Functional Pin Description section beginning on page 10.Pin Pin Name Formal Name Definition1RXDData Output MCU interface that reports the state of the LIN bus voltage. 2EN Enable Control Controls the operation mode of the interface.3WAKEWake Input High voltage input used to wake up the device from the Sleep mode.4TXDData Input MCU interface that controls the state of the LIN output.5GNDGround Device ground pin.6LIN LIN Bus Bidirectional pin that represents the single-wire bus transmitter and receiver.7VSUPPower Supply Device power supply pin.8INHInhibit OutputControls an external switchable voltage regulator having an inhibit input.12345678RXD EN WAKE TXDINH V SUP LIN GNDAnalog Integrated Circuit Device Data33399ELECTRICAL CHARACTERISTICS MAXIMUM RATINGSELECTRICAL CHARACTERISTICSMAXIMUM RATINGSTable 2. Maximum RatingsAll voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.RatingSymbolValueUnitELECTRICAL RATINGS Power Supply Voltage Continuous Supply Voltage Transient Voltage (Load Dump)V SUP2740VWAKE DC and Transient Voltage (Through a 33 k Ω Serial Resistor)V WAKE - 18 to 40V Logic Voltage (RXD, TXD, EN Pins)V LOG - 0.3 to 5.5V LIN Pin DC VoltageTransient (Coupled Through 1.0 nF Capacitor)V BUS- 18 to 40- 150 to 100V INH Voltage / C urrent DC VoltageV INH - 0.3 to V SUP + 0.3V ESD Voltage, Human Body Model (1)All PinsLIN Bus Pin with Respect to Ground V E SD1± 4000± 5000VESD Voltage, Machine Model All PinsV E SD2± 200VTHERMAL RATINGS Operating Temperature Ambient JunctionT A T J - 40 to 125- 40 to 150°CStorage TemperatureT STG - 55 to 165°C Thermal Resistance , Junction to AmbientR θJA 150°C/W Peak Package Reflow Temperature During Reflow (2), (3)T PPRT Note 3.°C Thermal ShutdownT SHUT 150 to 200°C Thermal Shutdown HysteresisT HYST8.0 to 20°C Notes1.ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, R ZAP = 1500 Ω), ESD2 testing is performed inaccordance with the Machine Model (C ZAP = 220 pF, R ZAP = 0 Ω).2.Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.3.Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL),Go to , search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.Analog Integrated Circuit Device Data 33399ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSTable 3. Static Electrical CharacteristicsCharacteristics noted under conditions 7.0 V ≤ V SUP ≤ 18 V, -40°C ≤ T A ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitVSUP PIN (DEVICE POWER SUPPLY)Supply Voltage Range V SUP7.013.518V Supply Current in Sleep Mode V LIN > V SUP - 0.5 V, V SUP < 14 V 14 V < V SUP < 18 V I S1I S2——20—50150µASupply Current in Normal Mode Recessive StateDominant State, Total Bus Load > 500 ΩI S(REC)I S(DOM)———— 2.03.0mASupply Undervoltage Threshold V SUP_UV5.56.46.8VRXD OUTPUT PIN (LOGIC)Low-Level Output Voltage I IN ≤ 1.5 mAV OL0.0—0.9VHigh-Level Output Voltage I OUT ≤ 250 µΑV OH3.75—5.25V TXD INPUT PIN (LOGIC)Low-Level Input Voltage V IL —— 1.5V High-Level Input VoltageV IH 3.5——V Input Voltage Threshold Hysteresis V INHYST 100550800mV Pullup Current Source1.0 V < V TXD < 4.0 V, V EN = 5.0 V I PU- 50—- 25µAEN INPUT PIN (LOGIC)Low-Level Input Voltage V IL —— 1.5V High-Level Input VoltageV IH 3.5——V Input Voltage Threshold Hysteresis V INHYST100480800mV EN Low-Level Input Current V IN = 1.0 VI IL5.02030µAHigh-Level Input Current V IN = 4.0 V I IH—2040µAPulldown Current 1.0 V < EN < 4.0 VI PD—20—µAAnalog Integrated Circuit Device Data33399ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSLIN PIN (VOLTAGE EXPRESSED VERSUS VSUP VOLTAGE)Low-Level Bus Voltage (Dominant State) TXD LOW, V LIN = 40 mAV DOM0.0—1.4VHigh-Level Voltage (Recessive State) TXD HIGH, I OUT = 1.0 µA V REC0.85 V SUP——V Internal Pullup Resistor to VSUP (4)- 40°C ≤ T A ≤ 70°C 70°C < T A ≤ 125°C R PU203530494760k ΩCurrent Limitation TXD LOW, V LIN = V SUP I L IM50150200mALeakage Current to GNDRecessive State, V SUP - 0.3 V ≤ V LIN ≤ V SUP (4)V SUP Disconnected, -18 V ≤ V LIN ≤ 18 V (Excluding Internal Pullup Source)V SUP Disconnected, V LIN = -18 V (Including Internal Pullup Source)V SUP Disconnected, V LIN = +18 V (Including Internal Pullup Source)I L EAK0.0- 40————- 600151040——µALIN Receiver, Low-Level Input Voltage TXD HIGH, RXD LOWV L INL0 V SUP—0.4 V SUPVLIN Receiver, High-Level Input Voltage TXD HIGH, RXD HIGH V L INH0.6 V SUP—V SUPVLIN Receiver Threshold Center (V LINH - V LINL ) / 2V L INTH—V SUP /2—VLIN Receiver Input Voltage Hysteresis V LINH - V LINLV L INHYS0.05 V SUP—0.15 V SUPVLIN Wake-Up Threshold Voltage V L INWU 3.54.56.0VINH OUTPUT PINHigh-Level Voltage (Normal Mode)V WUH V SUP - 0.8—V SUPV Leakage Current (Sleep Mode)0 < V INH < V SUP I L EAK—5.0µAWAKE INPUT PINTypical Wake-Up Threshold (EN = 0 V, 7.0 V ≤ V SUP ≤ 18 V) (5)HIGH-to-LOW Transition LOW-to-HIGH Transition V WUTH0.3 V SUP 0.4 V SUP 0.43 V SUP 0.55 V SUP 0.55 V SUP 0.65 V SUP VWake-Up Threshold Hysteresis V WUHYS 0.1 V SUP0.16 V SUP0.2 V SUPV WAKE Input Current V WAKE ≤ 14 V V WAKE > 14 VI W U——1.0—5.0100µA Notes4. A diode structure is inserted with the pullup resistor to avoid parasitic current path from LIN to V SUP .5.When V SUP is greater than 18 V, the wake-up voltage thresholds remain identical to the wake-up thresholds at 18 V. Table 3. Static Electrical Characteristics (continued)Characteristics noted under conditions 7.0 V ≤ V SUP ≤ 18 V, -40°C ≤ T A ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitAnalog Integrated Circuit Device Data 33399ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSTable 4. Dynamic Electrical CharacteristicsCharacteristics noted under conditions 7.0 V ≤ V SUP ≤ 18 V, -40°C ≤ T A ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitDIGITAL INTERFACE TIMING LIN Slew Rate (6) , (7)Falling Edge Rising Edget FALL t R ISE 0.750.75 2.02.0 3.03.0V/µsLIN Rise/Fall Symmetry (t RISE - t FALL )t S YM- 2.0—2.0µs Driver Propagation Delay (8) , (9) TXD LOW-to-LIN LOW TXD HIGH-to-LIN HIGH t TXDLINL t TXDLINH0.00.0——4.04.0µs Receiver Propagation Delay (9) ,(10) LIN LOW to RXD LOW LIN HIGH to RXD HIGHt RXDLINL t R XDLINH2.02.0 4.04.0 6.06.0µsReceiver Propagation Delay Symmetry t R ECSYM - 2.0— 2.0µs Transmitter Propagation Delay Symmetry t T RSYM - 2.0—2.0µs Propagation Delay (11)LIN Bus Wake-Up to INH HIGHt P ROP WL4570130µsNotess6.Measured between 20 and 80 percent of bus signal for 10 V < V SUP < 18 V. Between 30 and 70 percent of signal for7.0 V < V SUP < 10 V. 7.See Figure 5, page 8.8.t T XDLINL is measured from TXD (HIGH-to-LOW) and LIN (V REC - 0.2 V). t T XDLINH is measured from TXD (LOW-to-HIGH) and LIN (V DOM + 0.2 V).9.See Figure 4, page 8.10.Measured between LIN receiver thresholds and RXD pin.11.See Figure 6, page 8.Analog Integrated Circuit Device Data33399ELECTRICAL CHARACTERISTICS TIMING DIAGRAMSTIMING DIAGRAMSFigure 4. Normal Mode Bus Timing CharacteristicsFigure 5. LIN Rise and Fall Time Figure 6. LIN Bus Wake-UpTXDRXDLINV REC Dominant Statet TXDLINLt TXDLINHRecessive StateRecessive State 0.4 V SUP0.6 V SUPt RXDLINH t RXDLINLV DOM + 0.2VV REC - 0.2VV DOM t FALLt RISE0.2 V SUP0.8 V SUP0.8 V SUP0.2 V SUPINHLINV SUPDominant StateRecessive State 0.4 V SUPt PROP WLAnalog Integrated Circuit Device Data 33399FUNCTIONAL DIAGRAMSTIMING DIAGRAMSFUNCTIONAL DIAGRAMSFigure 7. LIN Wake-Up with INH Option Figure 8. LIN Wake-Up from Wake-Up SwitchFigure 9. LIN Wake-Up with MCU in Stop ModeLIN BusINH Bus Wake-Up Filtering Time (t PROG WL)Voltage Off StateOn StateNode in Sleep StateNode in Regulator Wake-Up Time DelayLow or FloatingHighMCU Startup Time DelayENEN HighOperation RegulatorWAKEINH Voltage Off StateOn StateNode in Sleep StateNode in Regulator Wake-Up Time DelayHighMCU Startup Time DelayENEN HighOperation State ChangeRegulatorLow or FloatingWAKE Filtering TimeLIN BusIRQWake-Up Filtering Time (t PROG WL)Voltage RegOn StateMCU in Stop ModeNode In OperationHighLow MCU Stop Mode Recovery/Startup Time DelayEN StateEN HighHighWake-Up from Stop ModeINHLow or Floating High(previous Wake-Up)I/O(2)High Impedance / I/O in Input State LowAnalog Integrated Circuit Device Data33399FUNCTIONAL DESCRIPTION TIMING DIAGRAMSFUNCTIONAL DESCRIPTIONINTRODUCTIONThe 33399 is a Physical Layer component dedicated to automotive LIN sub-bus applications.The 33399 features include speed communication from 1.0 kbps to 20 kbps, up to 60 kbps for Programming Mode, and active bus waveshaping to minimize radiated emission.The device offers three different wake-up capabilities: wake-up from LIN bus, wake-up from the MCU command, and dedicated high voltage wake-up input.The INH output may be used to control an external voltage regulator.FUNCTIONAL PIN DESCRIPTIONPOWER SUPPLY PIN (VSUP)The V SUP power supply pin is connected to a batterythrough a serial diode for reverse battery protection. The DC operating voltage is from 7.0 V to 27 V. This pin sustains standard automotive voltage conditions such as 27 V DC during jump-start conditions and 40 V during load dump. To avoid a false bus message, an undervoltage reset circuitry disables the transmission path (from TXD to LIN) when V SUP falls below 7.0 V. Supply current in the Sleep mode is typically 20 µA.GROUND PIN (GND)In case of a ground disconnection at the module level, the 33399 does not have significant current consumption on the LIN bus pin when in the recessive state. (Less than 100 µA is sourced from LIN bus pin, which creates 100 mV drop voltage from the 1.0 k Ω LIN bus pullup resistor.) For the dominant state, the pullup resistor should always be active. The 33399 handles a ground shift up to 3.0 V when V SUP > 9.0 V. Below 9.0 V V SUP , a ground shift can reduce V SUP value below the minimum V SUP operation of 7.0 V.LIN BUS PIN (LIN)The LIN bus pin represents the single-wire bus transmitter and receiver.Transmitter CharacteristicsThe LIN driver is a low-side MOSFET with internal current limitation and thermal shutdown. An internal pullup resistor with a serial diode structure is integrated so no external pullup components are required for the application in a slave node. An additional pullup resistor of 1.0 k Ω must be added when the device is used in the master node.Voltage can go from - 18 V to 40 V without current other than the pullup resistance. The LIN pin exhibits no reverse current from the LIN bus line to V SUP , even in the event of GND shift or V PWR disconnection. LIN thresholds are compatible with the LIN protocol specification.The fall time from recessive to dominant and the rise time from dominant to recessive are controlled to typically 2.0 V/µs. The symmetry between rise and fall time is also guaranteed.When going from dominant to recessive, the busimpedance parasitic capacitor must be charged up to V SUP.This charge-up is achieved by the total system pullup current resistors. In order to guarantee that the rise time is within specification, maximum bus capacitance should not exceed 10 nF with bus total pullup resistance less than 1.0 k Ω.Receiver CharacteristicsThe receiver thresholds are ratiometric with the device supply pin. Typical threshold is 50%, with a hysteresis between 5% and 10% of V SUP .DATA INPUT PIN (TXD)The TXD input pin is the MCU interface that controls the state of the LIN output. When TXD is LOW, LIN output is LOW; when TXD is HIGH, the LIN output transistor is turned OFF.This pin has an internal 5.0 V internal pullup currentsource to set the bus in a recessive state in case the MCU is not able to control it; for instance, during system power-up/power-down. During the Sleep mode, the pullup current source is turned OFF.DATA OUTPUT PIN (RXD)The RXD output pin is the MCU interface that reports the state of the LIN bus voltage. LIN HIGH (recessive) is reported by a high level on RXD; LIN LOW (dominant) is reported by a low voltage on RXD. RXD output structure is a CMOS-type push-pull output stage.ENABLE INPUT PIN (EN)The EN pin controls the operation mode of the interface. If EN = logic [1], the interface is in normal mode, with thetransmission path from TXD to LIN and from LIN to RXD both active. If EN = logic [0], the device is in Sleep mode or low power mode, and no transmission is possible.In Sleep mode, the LIN bus pin is held at V SUP through the bus pullup resistors and pullup current sources. The device can transmit only after being awakened. Refer to the INHIBIT OUTPUT PIN (INH) description on page 11.During Sleep mode, the device is still supplied from the battery voltage (through V SUP pin). Supply current is 20 µA typical. Setting the EN pin to LOW will turn the INH to high impedance. The EN pin has an internal 20 µA pulldown current source to ensure the device is in Sleep mode if EN floats.Analog Integrated Circuit Device Data 33399FUNCTIONAL DESCRIPTIONTIMING DIAGRAMSINHIBIT OUTPUT PIN (INH)The INH pin controls an external switchable voltageregulator having an inhibit input. This pin is a high-side switch structure to V SUP . When the device is in the Normal mode, the inhibit high-side switch is turned ON and the external voltage regulator is activated. When the device is in Sleep mode, the inhibit switch is turned OFF and disables the voltage regulator (if this feature is used).A wake-up event on the LIN bus line will switch the INH pin to V SUP level. Wake-up output current capability is limited to 280 µA. INH can also drive an external MOSFET connected to an MCU IRQ or XIRQ input to generate an interrupt. See the typical application illustrated in Figure 13, page 15.WAKE INPUT PIN (WAKE)The WAKE pin is a high-voltage input used to wake up the device from Sleep mode. WAKE is usually connected to an external switch in the application. The typical WAKE thresholds are V SUP / 2.The WAKE pin has a special design structure and allows wake-up from both HIGH-to-LOW or LOW-to-HIGHtransitions. When entering the Sleep mode, the LIN monitors the state of the WAKE pin and stores it as a reference state. The opposite state of this reference state will be the wake-up event used by the device to re-enter Normal mode.An internal filter is implemented (50 µs typical filtering time delay). The WAKE pin input structure exhibits a highimpedance with extremely low input current when voltage at this pin is below 14 V. When voltage at the WAKE pinexceeds 14 V, input current starts to sink into the device. A series resistor should be inserted in order to limit the input current, mainly during transient pulses. Recommended resistor value is 33 k Ω.Important The WAKE pin should not be left open. If the wake-up function is not used, WAKE should be connected to GND to avoid false wake-up.Analog Integrated Circuit Device Data33399FUNCTIONAL DEVICE OPERATION OPERATIONAL MODESFUNCTIONAL DEVICE OPERATIONOPERATIONAL MODESAs described below and depicted in Figure 10 and Table 5 on page 13, the 33399 has two operational modes, normal and sleep, and one transitional mode, Awake.NORMAL MODEThis is the normal transmitting and receiving mode. All features are available.SLEEP MODEIn this mode the transmission path is disabled and the device is in low power mode. Supply current from V SUP is 20 µA typical. Wake-up can occur from LIN bus activity, as well as from node internal wake-up through the EN pin and the WAKE input pin.DEVICE POWER-UP (AWAKE TRANSITIONAL MODE)At system power-up (V SUP rises from zero), the 33399 automatically switches into the “Awake ” mode (refer toFigure 10 below and Table 5 on page 13. It switches the INH pin in HIGH state to V SUP level. The microcontroller of the application then confirms the Normal mode by setting the EN pin HIGH.DEVICE WAKE-UP EVENTSThe device can be awakened from Sleep mode by three wake-up events:•LIN bus activity•Internal node wake-up (EN pin)•Wake-up from WAKE pinFigures 7, 8, and 9 on page 9 show device application circuit and detail of wake-up operations.Wake-Up from LIN Bus (Awake Transitional Mode)A wake-up from the LIN pin switching from recessive to dominant state (switch from V SUP to GND) can occur. This is achieved by a node sending a wake-up frame on the bus. This condition internally wakes up the interface, which switches the INH pin to a HIGH level to enable the voltage regulator. The device switches into the Awake mode. The microcontroller and the complete application power up. The microcontroller must switch the EN pin to a HIGH level to allow the device to leave the Awake mode and turn it into Normal mode in order to allow communication on the bus.Wake-Up from Internal Node Activity (Normal Mode)The application can internally wake up. In this case the microcontroller of the application sets the EN pin in the HIGH state. The device switches into Normal mode.Wake-Up from WAKE Pin (Awake Transitional Mode)The application can wake up with the activation of an external switch. Refer to Table 1, 8-SOICN Pin Definitions on page 3.Figure 10. Operational and Transitional Modes State DiagramPower-Up/SleepAwakeNormal EN LOWLIN Bus or WAKE PinEN HIGHWake-UpEN HIGH (Local Wake-Up Event)1.0 to 20kbpsV PWR > 7.0VNote Refer to Table 5 for explanation.V PWR < 7.0VV PWR < 7.0VV PWR < 7.0VDownAnalog Integrated Circuit Device Data 33399FUNCTIONAL DEVICE OPERATIONPROTECTION AND DIAGNOSIS FEATURESPROTECTION AND DIAGNOSIS FEATURESELECTROSTATIC DISCHARGE (ESD)The 33399 has two Human Body Model ESD values. All pins can handle ± 4.0 kV. The LIN bus pin, with respect to ground, can handle ± 5.0 kV.ELECTROMAGNETIC COMPATIBILITYRADIATED EMISSION ON LIN BUS OUTPUT LINERadiated emission level on the LIN bus output line is internally limited and reduced by active slew rate control of the output bus driver. Figure 11 shows the results in the frequency range 100 kHz to 2.0 MHz.ELECTROMAGNETIC IMMUNITY (EMI)On the LIN bus pin, the 33399 offers high EMI level from external disturbance occurring at the LIN bus pin in order to guarantee communication during external disturbance.On the WAKE input pin, an internal filter is implemented to reduce false wake-up during external disturbance.NOISE FILTERINGNoise filtering is used to protect the electronic module against illegal wake-up spikes on the bus. Integrated receiver filters suppress any high-frequency (HF) noise induced into the bus wires. The cut-off frequency of these filters is a compromise between propagation delay and HF suppression.Figure 11. Radiated Emission in Normal ModeTable 5. Explanation of Operational and Transitional Modes State DiagramOperational/ Transitional LININH EN TXD RXDSleep Mode Recessive state, driver off. 20 µA pullup current source.LOW LOW X High impedance.Awake Recessive state, driver off. HIGH LOW XLOW.Normal ModeDriver active. 30 k Ω pullup active.HIGHHIGHLOW to drive LIN bus in dominant.HIGH to drive LIN bus in recessive.Report LIN bus level: • LOW LIN bus dominant • HIGH LIN bus recessiveX = Don’t care.Analog Integrated Circuit Device Data33399TYPICAL APPLICATIONSTYPICAL APPLICATIONSThe 33399 can be configured in several applications. Figures 12 and 13 show slave and master node applications. An additional pullup resistor of 1.0 k Ω in series with a diode must be added when the device is used in the master node.Figure 12. Slave Node Typical Application with WAKE Input Switch and INH(Switchable 5.0 V Regulator)Actuator SCIMCUDriverM12V5.0VINH5.0 VL I N B u sV REGI/OV DD External SwitchRXDTXDENLINVSUPV REF LogicGNDDriverReceiverBias INHProtectionWake-Up WAKE30k Ω33399V PWRRegulator Regulator ControlAnalog Integrated Circuit Device Data 33399TYPICAL APPLICATIONSFigure 13. Master Node Typical Device Application with MCU Wake-Up from Stop Mode(Non-Switchable 5.0 V Regulator, MCU Stop Mode)Actuator SCIMCU DriverM5.0 VL I N B u sMaster Node PullupIRQ5.0VI/O V DD I/O(2)RXDTXDENLINVSUPV REF LogicGNDDriverReceiverBiasINHProtectionWAKE30k Ω1.0k Ω33399V PWRExternal Switch12V5.0VRegulator Wake-Up Regulator ControlREFERENCE DOCUMENTSREFERENCE DOCUMENTSTable 6. Reference DocumentsTitle LIterature Order Number Local Interconnect Network (LIN) Physical Interface: Difference Between MC33399 and MC33661EB21533399Analog Integrated Circuit Device DataAnalog Integrated Circuit Device Data 33399PACKAGINGPACKAGE DIMENSIONSPACKAGINGPACKAGE DIMENSIONSImportant For the most current revision of the package, visit and do a keyword search on the 98Adrawing number below.8-PIN SOIC NARROW BODYPLASTIC PACKAGE 98ASB42564B ISSUE UAnalog Integrated Circuit Device Data33399REVISION HISTORYREVISION HISTORYREVISIONDATE DESCRIPTION OF CHANGES7.07/2006•Implemented Revision History page •Added Pb-Free suffix code EF•Added EPP ordering part number MCZ33399EF/R2•Adjusted to the Freescale prevailing form and style8.010/2006•Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from MAXIMUM RATINGS on page 4. Added note with instructions to obtain this information from .MC33399Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may beprovided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended orunauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.© Freescale Semiconductor, Inc., 2006. All rights reserved.RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-freecounterparts. For further information, see or contact your Freescale sales representative.For information on Freescale’s Environmental Products program, go to /epp .How to Reach Us:Home Page:Web Support:/support USA/Europe or Locations Not Listed:Freescale Semiconductor, Inc.Technical Information Center, EL5162100 East Elliot Road Tempe, Arizona 85284+1-800-521-6274 or +/supportEurope, Middle East, and Africa:Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 781829 Muenchen, Germany +44 1296 380 456 (English)+46 8 52200080 (English)+49 89 92103 559 (German)+33 1 69 35 48 48 (French)/supportJapan:Freescale Semiconductor Japan Ltd. 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ER9.5-2.5-5-3C92-S中文资料

PRODUCT STATUS DEFINITIONS
STATUS Prototype Design-in Preferred Support
INDICATION
DEFINITION
These are products that have been made as development samples for the purposes of technical evaluation only. The data for these types is provisional and is subject to change. These products are recommended for new designs.
TYPE NUMBER
ER9.5/2.5/5-3C92-S ER9.5/2.5/5-3C93-S ER9.5/2.5/5-3C94-A63-S ER9.5/2.5/5-3C94-A100-S ER9.5/2.5/5-3C94-A160-S ER9.5/2.5/5-3C94-S ER9.5/2.5/5-3C96-S ER9.5/2.5/5-3F3-A63-S ER9.5/2.5/5-3F3-A100-S ER9.5/2.5/5-3F3-A160-S ER9.5/2.5/5-3F3-S ER9.5/2.5/5-3F35-S ER9.5/2.5/5-3F4-A40-S ER9.5/2.5/5-3F4-A63-S ER9.5/2.5/5-3F4-A100-S ER9.5/2.5/5-3F4-S ER9.5/2.5/5-3F45-S
B (mT) at
CORE LOSS (W) at
GRADE
3C92 3C93 3C94 3C96 3F3 3F35 3F4 3F45

MC33399中文资料

Description
VSUP pin (Device power supply) Nominal DC Voltage Range Supply Current in Sleep Mode
Supply Current in Sleep Mode and Vsup>14V Supply Current in Normal Mode Supply Current in Normal Mode
• Speed Communication from 1 to 20Kb/s • Nominal Operation from VSUP 8 to 18V DC • Fully Functional up to 27V DC battery voltage. • 40V maximum Voltage during Load Dump • Handle from +40V to -18V DC voltage at LIN pin • Gnd disconnection fail safe at module level • An Unpowered Node does not disturb the network • GND Shift Operation at system level • Two Operation Modes: Normal and Sleep Mode • Very Low Standby Current during Sleep Mode 20uA • Wake-up Capability from LIN bus, MCU command and dedicated high voltage wake up input (interface to external switch) • Interface to MCU with CMOS compatible I/O pins • Control of External Voltage Regulator • LIN bus Threshold Voltage fully Compatible with LIN protocol specification • Bus slew rate control according to LIN protocol specification recommendations (2V/us typ.) • Internal pull up resistor • Handle Automotive Transients per ISO9137 Specification • ESD 4KV on LIN bus Pin • High EMC Immunity

车辆运行安全监控系统建设要求

车辆运行安全监控系统建设要求徐占山，张项（中国铁路济南局集团有限公司车辆部，济南250001）[摘要] 车辆运行安全监控系统（5T 系统）是保障铁路运输安全的重要铁路行车安全监测设备，其建设要求涉及房建、电力、通信、信息、车辆、工务等多个专业。

本文对分散在若干规章、标准、文件中的车辆运行安全监控系统建设要求，从探测站，检测、监测和复示站，维修工区，机房设施，检修通道，电磁防护，传输通道，供电，UPS ，消防设施等9个方面进行了梳理并结合现场需求进行了优化，在近年的新改建铁路工程实践中取得了较好的效果，降低了建设难度，减少了工程返工，提高了建设质量。

[关键词] 工程建设；车辆运行安全监控系统；5T 系统1 前言车辆运行安全监控系统（下称5T 系统）[1]，是保障铁路运输安全的重要铁路行车安全监测设备[2]，包括车辆轴温智能探测系统（THDS ）、铁道车辆运行品质轨旁动态监测系统（TPDS ）、铁道车辆滚动轴承故障轨旁声学诊断系统（TADS ）、货车故障轨旁图像检测系统（TFDS ）、铁道客车故障轨旁图像检测系统（TVDS ）、动车组运行故障图像检测系统（TEDS ）、客车运行安全监控系统（TCDS ）等子系统，由各级联网服务器和监测、检测（对TEDS 和TVDS 也称监控中心）、复示终端、探测站设备及机房、供电、通道、网络设备等配套设施组成[1]，使用声学、光学、力学、电磁和图像等高性能传感器检测运行车辆（动车组）的载重、轮轨冲击、部件状态和轴承温度、内部缺陷等安全信息，采用信息化、智能化、网络化技术，全天候自动采集、传输、存贮、识别、报警运行中的动车组和客货车辆故障[3]，点线成网、跟踪运行、局间互控，实现铁路车辆（动车组）运用质量在线监测，及时消除铁路安全隐患，为铁路车辆装备修程修制改革和铁路行车安全保障提供重要信息支撑[4]。

新建铁路须设计5T 系统并应与铁路主体工程同时投产[3]。

探测站是5T 系统信息采集源点和施工维修上道作业重点，分散布局在铁路沿线，如图1至图4所示，其中THDS 探测站间距30km 左右，TFDS 、TPDS 、TADS 探测站间距分别在300km 、400km 、500km左右[4]，TCDS 设置在客车技术整备所，TVDS 和TEDS 设置在国铁集团、集团公司规划地点；各级联网服务器和监测、检测、复示终端是处理5T 信息的大脑，分别提供国铁集团、铁路局集团公司、车辆（动车）段和列检等各级应用；通道网络为5T 系统信息传输提供通路；机房、电力为5T 系统设备运行提供环境和动力保障。

Air King 5-Speed Table Fan User Manual

DOUBLE BLADEWHOLE ROOM STAND FANHSF1640 SeriesA001819R128SEP17Honeywell is a trademark of Honeywell International Inc., used under license by Helen of Troy Limited. Honeywell International Inc. makes no representation or warranties with respect to this product.© 2018 All rights reserved. Kaz USA, Inc., a Helen of Troy Company Marlborough, MA 01752Imported and Distributed by: Kaz Canada Inc., a Helen of Troy Company 6700 Century Avenue, Suite 210, Mississauga, Ontario L5N 6A4Contact us at 1-800-477-0457 or /fansHoneywell est une marque de commerce de Honeywell International, Inc. qu’utilise Helen of Troy Limited sous licence. Honeywell International Inc. ne fait aucune assertion et n’offre aucune garantie en ce qui concerne ce produit.© 2018 Tous droits réservés. Kaz USA, Inc., a Helen of Troy Company Marlborough, MA 01752Importé et distribué par : Kaz Canada Inc., a Helen of Troy Company 6700 Century Avenue, Suite 210, Mississauga, Ontario L5N 6A4Pour nous joindre : Composez le 1 800 477-0457 ou visitez notre site Web à /fans For Responsible recycling, please visit: Honeywell es una marca registrada de Honeywell International Inc., utilizada bajo licencia por Helen of Troy Limited. Honeywell International Inc. no hace ninguna representación o garantía con respecto a este producto.© 2018 Todos los derechos reservados. Kaz USA, Inc., una Empresa de Helen of Troy Marlborough, MA 01752Importado y Distribuido por: Kaz Canada Inc., una Empresa de Helen of Troy 6700 Century Avenue, Suite 210, Mississauga, Ontario L5N 6A4Contáctenos en el 1-800-477-0457 o /fans Para reciclar responsablemente, por favor visite:。

2985中文资料

8-CHANNEL SOURCE DRIVER Recommended for applications requiring separate logic and load grounds, load supply voltages to 30 V, and load currents to 250 mA, the UDN2985A source driver is used as an interface between standard low-power digital logic and LEDs, relays, and solenoids. The outputs feature saturated transistors for low collector-emitter saturation voltages.The UDN2985A driver is for use with 5 V logic systems: TTL, Schottky TTL, DTL, and CMOS. This device has a minimum output breakdown rating of 30 V with a minimum output sustaining voltage of 15 V. The output is switched on by an active-high input level.Under normal operating conditions, this device can source up to 120 mA for each of the eight outputs at an ambient temperature of 75°C and a supply voltage of 15 V. It incorporates input current-limiting resistors and output transient-suppression diodes.The UDN2985A source driver is supplied in an 18-pin dual in-line package. All inputs are on one side of the package, output pins on the other, to simplify printed wiring board layout.Always order by complete part number:UDN2985A.Dwg. No. DS-1013FEATURESI TTL, DTL, or CMOS Compatible Inputs I 250 mA Output Source Current Capability I Output Transient-Suppression DiodesI 30 V Minimum Output Breakdown Voltage I Low Output-Saturation VoltagePARTIAL SCHEMATIC DIAGRAM 1 of 8 DRIVERS Data Sheet29310.2A†298529858-CHANNELSOURCE DRIVER115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000 LimitsCharacteristics Symbol Test Conditions Min.Typ.Max. Units Output Leakage Current I CEX V IN = 0.4 V, V OUT = 0 V —<-1.0-100µA Output Sustaining Voltage V CE(sus)l OUT = -120 mA, L = 3 mH 15——V Output Saturation VoltageV CE(SAT)V IN = 2.4, l OUT = -60 mA —0.8 1.1V V IN = 2.4, l OUT = -120 mA—0.9 1.2V Input Current VoltageI IN(ON)V IN = 2.4 V —90225µA V IN = 5.0 V—280650µA I IN(OFF)V IN = 0.4 V—1015µA Supply Current I S V S = 30 V, V IN = 2.4 V —1015mA (outputs open)Clamp Diode I R V R = 30 V, T A = 70°C —<1.050µA Leakage Current Clamp Diode V F I F = 120 mA— 1.1 2.0V Foward Voltage Turn-On Delay t ON —0.5 1.0µs Turn-Off Delayt OFF—5.010µsELECTRICAL CHARACTERISTICS at T A = 25°C, V S = 30 V (unless otherwise noted).COMMON-CATHODE LED DRIVERNOTE: Negative current is defined as coming out of (sourcing) the specified device pin.Dwg. No. DS-1014Copyright © 1984, 2000 Allegro MicroSystems, Inc.29858-CHANNEL SOURCE DRIVERNOTES:1.Exact body and lead configuration at vendor’s option within limits shown.2.Lead spacing tolerance is non-cumulative.3.Lead thickness is measured at seating plane or below.4.Supplied in standard sticks/tubes of 21 devices.Dimensions in Inches(controlling dimensions)Dimensions in Millimeters(for reference only)Dwg. MA-001-18A in181910Dwg. MA-001-18A mm191029858-CHANNELSOURCE DRIVER115 Northeast Cutoff, Box 15036Worcester, Massachusetts 01615-0036 (508) 853-5000POWER SOURCE DRIVERSIN ORDER OF 1) OUTPUT CURRENT, 2) OUTPUT VOLTAGE, 3) NUMBER OF DRIVERSOutput Ratings *FeaturesSerial Latched Diode Saturated Internal mA V #Input Drivers Clamp Outputs ProtectionPart Number †-2560 8–X –––58156010X X active pull-down ––5810-F and 6809/106012XX active pull-down ––5811 and 68116020X X active pull-down ––5812-F and 68126032X X active pull-down ––5818-F and 681885 8–––––6118-120-25 8––X X –258530 8––X X –298550 8X X X X –5895-35035 8––X –X 298750 8––X ––2981 and 298250 8X X X ––5891-50 8––X ––258080 8––X ––2983 and 298480 8X X X ––5890-80 8––X ––2588-50061–––MO SFET X 2525 and 253562–––MOSFET X 2526 and 2536-4000604––X ––2944*Current is maximum specified test condition, voltage is maximum rating. See specification for sustaining voltage limits orover-current protection voltage limits.†Complete part number includes additional characters to indicate operating temperature range and package style.The products described here are manufactured under one or more U.S. patents or U.S. patents pending.Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, ormanufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.Allegro products are not authorized for use as critical components in life-support devices or systems without express written approval.The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsi-bility for its use; nor for any infringement of patents or other rights of third parties which may result from its use.。

33389资料

Document Number: MC33389Rev. 5.0, 3/2007Freescale Semiconductor Advance Information* This document contains certain information on a new product.Specifications and information herein are subject to change without notice.© Freescale Semiconductor, Inc., 2007. All rights reserved.System Basis Chip with Low Speed Fault Tolerant CANThe 33389 is a monolithic integrated circuit combining manyfunctions frequently used by automotive Engine Control Units (ECUs). It incorporates a low speed fault tolerant CAN transceiver.Features•Dual Low Drop Voltage Regulators, with Respectively 100 mA and 200 mA Current Capabilities, Current Limitation, and Over Temperature Detection with Pre-warning • 5.0 V Output Voltage for V1 Regulator•Three Operational Modes (Normal, Stand-by, and Sleep Modes) Separated from the CAN Interface Operating Modes•Low Speed 125 kBaud Fault Tolerant CAN Interface, Compatible with 33388 Stand Alone Physical Interface •V1 Regulator Monitoring and Reset Function•Three External High Voltage Wake-Up Inputs, Associated with V3 V BAT Switch•100 mA Output Current Capability for V3 V BAT Switch Allowing Drive of External Switches or Relays•Low Stand-by and Sleep Current Consumption•V BAT Monitoring and V BAT Failure Detection Capabilities •DC Operating Voltage up to 27 V •40 V Maximum Transient Voltage•Programmable Software Window Watchdog and Reset•Wake-Up Capabilities (CAN Interface, Local Programmable Cycle Wake•INterface with the MCU through the SPI•Pb-Free Packaging Designated by Suffix Codes VW and EGFigure 1. 33389 Simplified Application DiagramSYSTEM BASIS CHIP33389ORDERING INFORMATIONDevice Temperature Range (T A )PackageMC33389CDH/R2-40 to 125°CHSOP-20MC33389CVW/R2MC33389CDW/R2SO-28MC33389DDW/R2Analog Integrated Circuit Device Data33389DEVICE VARIATIONSDEVICE VARIATIONSTable 1. Device VariationsFreescale Part No.V1 UndervoltageMC33389CDH MC33389CVW MC33389CDW In V1 undervoltage condition, device remains in permanent reset state until V1 returns to normal conditions. V1 is protected by overcurrent and overtemperature functions.MC33389DDWThe sole difference between the C version and the D version is V1 Reset Threshold. Reference V1 Reset Threshold on V1 on page 9.INTERNAL BLOCK DIAGRAMINTERNAL BLOCK DIAGRAMFigure 2. 33389 Simplified Internal Block Diagram33389 Analog Integrated Circuit Device DataAnalog Integrated Circuit Device Data33389PIN CONNECTIONSPIN CONNECTIONSFigure 3. 33389 Pin ConnectionsTable 1. 33389 Pin Definitions: HSOSP 20-LeadA functional description of each pin can be found in the Functional Pin Description section beginning on page 17.Pin NumberPin NameFormal Name Definition1TX Transmitter DataTransmitter input of the LS CAN interface2V1Voltage Regulator One This 5.0 V pin is a 3% low drop voltage regulator dedicated to the microcontroller supply.3RX Receiver DataReceiver output of the LS CAN interface 4RST Reset This is an Input/Output pin.5INT Interrupt Output This output is asserted LOW when an enabled interrupt condition occurs.6MISO Master In/Slave Out This pin is the tri-state output from the shift register. 7MOSI Master Out/Slave In This pin is for the input of serial instruction data. 8SCLK System Clock This pin clocks the internal shift registers.9CS Chip Select This pin communicates with the system MCU and enables SPI communication.10 - 12L0 - L2Level 0 - 2 inputs(L0: L2)Input interfaces to external circuitry. Levels at these pins can be read by SPI and input can be used as programmable wake-up input in Sleep or Stop mode.13RTH RTH Pin for the connection of the bus termination to CANH 14CANLCAN Low CAN low input/output15GND Ground This pin is the ground of the integrated circuit.16CANH CAN HighCAN high input/output17V2Voltage Regulator Two This 5.0 V pin is a low drop voltage regulator dedicated to the peripherals supply.18RTL RTL Pin for the connection of the bus termination to CANL 19VBAT Voltage Battery This pin is voltage supply from the battery.20V3Voltage RegulatorThreeThis pin is a 10 Ω switch to V BAT , used to supply external contacts or relays.Analog Integrated Circuit Device Data 33389PIN CONNECTIONSTable 2. 33389 Pin Definitions: SOICW 28-LeadA functional description of each pin can be found in the Functional Pin Description section beginning on page 17.Pin NumberPin Name Formal Name Definition1TXTransmitter Data Transmitter input of the LS CAN interface2V1Voltage Regulator OneThis 5.0 V pin is a 3% low drop voltage regulator dedicated to the microcontroller supply.3RXReceiver Data Receiver output of the LS CAN interface 4RST Reset This is an Input/Output pin.5INT Interrupt This output is asserted LOW when an enabled interrupt condition occurs.6 -9 20 - 23GND GroundThese device ground pins are internally connected to the package lead frame to provide a 33389-to-PCB thermal path.10MISO Master In/Slave OutThis pin is the tri-state output from the shift register. 11MOSIMaster Out/Slave In This pin is for the input of serial instruction data. 12SCLKSystem Clock This pin clocks the internal shift registers.13CS Chip Select This pin communicates with the system MCU and enables SPI communication.14, 15, 16L0: L2Wake-up Input (L0: L2)Input interfaces to external circuitry. Levels at these pins can be read by SPI and input can be used as programmable wake-up input in Sleep or Stop mode.17NCNo Connect This pin does not connect.18RTH Thermal Resistance High Pin for the connection of the bus termination to CANH 19CANLCAN Low CAN low input/output 24CANHCAN High CAN high input/output25V2Voltage Regulator TwoThis 5.0 V pin is a low drop voltage regulator dedicated to the peripherals supply.26RTL Thermal Resistance LowPin for the connection of the bus termination to CANL 27VBAT Voltage Battery This pin is voltage supply from the battery.28V3Voltage Regulator ThreeThis pin is a 10 Ω switch to V BAT , used to supply external contacts or relays.Analog Integrated Circuit Device Data33389ELECTRICAL CHARACTERISTICS MAXIMUM RATINGSELECTRICAL CHARACTERISTICSMAXIMUM RATINGSTable 3. Maximum RatingsAll voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.RatingsSymbol Value UnitELECTRICAL RATINGS DC Voltage at VBAT Pin V BAT -0.3 to 27V Transient Voltage at VBAT Pint < 500 ms (load dump)V BAT 40V DC Voltage at Pins CANH and CANL V BAT -20 to 27V Transient Voltage at Pins CANH and CANL 0.0 < V2 < 5.5, V BAT > 0.0, t < 500 msV BAT-40 to 40VCoupled Transient Voltage at Pins CANH and CANLWith 100 Ω Termination Resistors, Coupled Through 1.0 nF (1)V BAT-100 to 100 VDC Voltage at Pins V1 and V2V BAT -0.3 to 6.0V DC Current at Output Pins RX, MISO, RST, INT V BAT -20 to 20mA DC Voltage at Input Pins TX, MOSI, CS, RST V BAT -0.3 to 6.0V DC Voltage at Pins L0, L1, L20.0 < V BAT < 40 V V BAT-0.3 to 40VCurrent at Pins L0, L1, L2V BAT -15mA Transient Current at Pin V3V BAT -30 to 20mA DC Voltage at pins RTH and RTLV BAT -0.3 to 40V ESD Voltage on any Pin (HBM 100 pF, 1.5 K)V BAT -2.0 to 2.0kV ESD Voltage on L0, L1, L2, CANH, CANL, VBAT V BAT -2.0 to 2.0kV ESD Voltage on any Pin (MM 200 pF, 0 Ω)V BAT-150 to 150VTHERMAL RATINGSOperating Junction Temperature T J -40 to 150°C Ambient Temperature T A -40 to 125°C Storage TemperatureT S-55 to 165°CNotes1.Pulses 1, 2, 3a, and 3b according to ISO7637.Analog Integrated Circuit Device Data 33389ELECTRICAL CHARACTERISTICSMAXIMUM RATINGSTHERMAL RESISTANCERTH, RTL Termination ResistanceR RTHRTL 500 to 16 kΩJunction to Heatsink Thermal Resistance for HSOP-2033% Power on V1, 66% on V2 (including CAN) (2) R AJC3.1°C/WJunction to Pin Thermal Resistance for SO-28WD (3) R AS/P 17°C/W Thermal Shutdown TemperatureT SD 165°C Peak Package Reflow Temperature During Reflow (4), (5)T PPRTNote 5°CNotes2.Refer to thermal management in device description section.3.Refer to thermal management in device section. Ground pins 6, 7, 8, 9, 20, 21, 22, and 23 of SO28WB package.4.Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits maycause malfunction or permanent damage to the device.5.Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package ReflowTemperature and Moisture Sensitivity Levels (MSL),Go to , search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.Table 3. Maximum Ratings (continued)All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent damage to the device.RatingsSymbolValueUnitAnalog Integrated Circuit Device Data33389ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSTable 4. Static Electrical CharacteristicsCharacteristics noted under conditions V BAT , - 40°C ≤ T A ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbol Min Typ Max UnitPOWER INPUT (VBAT)Nominal VBAT Operating Range V BAT 5.5—18V Functional VBAT Operating Range V BAT 5.5—27V V BAT Threshold for BAT FAIL Flag BAT FAIL2.0— 4.0V Delay for Signalling BAT FAIL TFAIL—150400µs Overvoltage V BAT Threshold BAT HIGH 182022V Delay for Setting BAT HIGH Flag T HIGH 4.01850µs Supply Current in Sleep ModeForced Wake-Up and Cyclic Sense Disabled V BAT = 12 V, T J = 25°C to 150°C I SLEEP1—75125µASupply Current in Sleep ModeForced Wake-Up and Cyclic Sense Disabled V BAT = 12 V, T J = -40°C to 25°C I SLEEP2——210µASupply Current in Sleep ModeForced Wake-Up and Cyclic Sense Enabled V BAT = 12 V, T J = 25°C to 150°C I SLEEP3—105155µASupply Current in Sleep ModeForced Wake-Up and Cyclic Sense Enabled V BAT = 12 V, T J = -40°C to 25°C I SLEEP4——250µASupply Current in Sleep ModeForced Wake-Up and Cyclic Sense Disabled V BAT = 12 V, T J = 25°C to 150°C I SLEEP5——300µASupply Current in Stand-by Mode I STB2—0.5 1.0mA Supply Current in Normal Mode Normal Mode with I(V1) = 1 I(V2) = 0Bus in Recessive State I NREC—3.57.0mAPOWER OUTPUT V1 Output Voltage 0 mA < I OUT < 100 mA 5.5 V < V BAT < 27 V V1NOM4.855.05.15VV1 Output Voltage I OUT =< 100 mA 27 V < V BAT < 40 V V14.85.05.2VV1 Drop Voltage I OUT =< 100 mA (6)V1DROP —0.350.5VNotes6.Measured when V1 has dropped 100mV below its nominal valueAnalog Integrated Circuit Device Data 33389ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSPOWER OUTPUT (CONTINUED) V1 Output Current Limitation V1NOM - 100 mVI1MAX130170200mAV1 Overtemperature Shut OFF Threshold Junction TemperatureTV1H 160—190°CV1 Pre-Warning Temperature Threshold Junction TemperatureTV1L 130—160°CV1 Temperature Threshold Difference TV1H-TV1L20—40°C V1 Reset Threshold on V15.5 V < V BAT < 27 V (C Version)(D Version)VR1 4.1V2 - 0.4 4.3V1 - 0.284.8V1 - 0.1VV1 Reset Active V1 RangeV1R 1.0VR1—V V1 Reverse Current from V1 to V BAT and GND V1 = 4.9 V, 0 < V BAT < 4.9 V IREV——1.0mAV2 Output Voltage0 mA < I OUT < 200 mA 5.5 V < V BAT < 40 V V2NOM 4.75 5.0 5.25 VV2 Drop Voltage I OUT = 200 mA (7)V2DROP —0.2 0.5VV2 Drop Voltage I OUT = 20 mA (7)V2DROP —0.050.15VV2 Output Current Limitation V2NOM -100 mVI1MAX220280350mAV2 Threshold on V2 to Report V2 OFF V2 Nominal V R24.14.554.75VV R2 Delay TimeV R220—70µs V2 Overtemperature Pre-Warning Threshold V2 Junction TemperatureT V2L130—160°CV2 Overtemperature Switch-OFF Threshold V2 Junction Temperature T V2H155—185°CV2 Line Regulation 9.0 V < V BAT < 16.5V2LR1-15—+15mVV2 Load Regulation 4.0 mA < I LOAD < 200 mA V2LR2-75—+75mVV2 Line Ripple Rejection 100 Hz, 1.0 V PP on V BAT (8)V2LRR3055—dBNotes7.Measured when V1 has dropped 100mV below its nominal value 8.Guaranteed by design; however, it is not production testedTable 4. Static Electrical Characteristics (continued)Characteristics noted under conditions V BAT , - 40°C ≤ T A ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbol Min Typ Max UnitAnalog Integrated Circuit Device Data33389ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSPOWER OUTPUT (CONTINUED) V2 Percentage Difference V2-V1V BAT > 9.0, I V1 = 20 mA, I V2 = 40 mA V2V2-V1-3.0—3.0%V3 High Level Voltage DropI V3 = -50 mA, 9.0 V < V BAT < 40 V V3DROP—0.41.0VV3 High Level Voltage DropI V3 = -50 mA, 6.0 V < V BAT < 9.0 V V3DROP——1.5VV3 Leakage Output Limitation 5.5 V < V BAT < 27 V I3LIM100150250mAV3 Leakage Current V3 = 0 (V3 OFF)I3LEAK——15µAV3 Overtemperature Detection Junction TemperatureT V3155—185°CV3 Voltage with -30 mA (negative current for Relay Switch OFF) No Functional Error Allowed for t < 100 msV V30.3—0.5VCAN Transceiver V2 for Forced Bus Stand-by Mode (Fail Safe) VRC2 3.0 3.9 4.7V CANH/L Differential Receiver, Threshold VoltageV CANTH -3.2—-2.5V CANH/L Differential Receiver, Dominant to Recessive Threshold (Bus Failures 1, 2, and 5)V CANDRTH-3.2—-2.5VCANH Recessive Output Voltage TX = High, R(RTH) < 4.0 k V CANH——0.2VCANL Recessive Output Voltage TX = High, R(RTH) < 4.0 k V CANLV2-0.2——VCANH Output Voltage, DominantTX = 0 V, BusNormal Mode, I CANH = - 40 mA V CANHV2-1.4——VCANL Output Voltage, DominantTX = 0 V, Bus Normal Mode, I CANL = - 40 mA V CANL——1.4VCANH Output Current Limit (V CANH = 0.0 V, TX = 0)I CANH5075100mACANL Output Current Limit (V CANL = 14 V, TX = 0)I CANL5095130mADetection Threshold for Short Circuit to Battery Voltage Bus Normal ModeV CANH -V CANL7.37.98.9VDetection Threshold for Short Circuit to Battery Voltage Bus Stand-by ModeV CANHV BAT /2+3—V BAT /2+5VCANH Output Current, Failure 3Bus Stand-by Mode V CANH = 12 V I CANHF3—5.010µACANL Output Current, Failure 4Bus Stand-by Mode, V CANL = 0.0 V, V BAT = 12 VI CANLF4—0.02.0µATable 4. Static Electrical Characteristics (continued)Characteristics noted under conditions V BAT , - 40°C ≤ T A ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSPOWER OUTPUT (CONTINUED)CANL Wake-Up Voltage ThresholdBus Stand-by ModeV WAKEL 2.5 3.3 3.9VCANH Wake-Up Voltage ThresholdBus Stand-by ModeV WAKEH 1.2 2.0 2.7VWake-Up Threshold Difference V WAKEL -V WAKEH0.2——V CANH Single Ended Receiver ThresholdFailures 4, 6, and 7V CANH 1.5 1.85 2.15VCANL Single Ended Receiver ThresholdFailures 3 and 8V CANL 2.8 3.05 3.4VCANL Pull-Up CurrentBus Normal ModeI CANLPU457590µACANH Pull Down CurrentBus Normal ModeI CANLPD457590µA Receiver Differential Input Impedance CANH/CANL R DIFF100—180kΩDifferential Receiver Common Mode Voltage Range V COM-8.0—8.0V RTL to V2 Switch on ResistanceI OUT < -10 mA, Bus Normal Operating ModeR RTL102570ΩRTL to Battery Switch Series ResistanceBus Stand-by ModeR RTL8.012.520kΩRTH to Ground Switch on ResistanceI OUT < 10 mA, All ModesR RTH—2570ΩCONTROL INTERFACEHigh Level Input Voltage VIH0.7 V1—V1 + 0.3 V VCS Threshold for SPI Wake-UpSBC in Sleep Mode, V1 < 1.5 VV CSTH— 2.2—VCS Filter Time for SPI Wake-UpSBC in Sleep Mode, V1 < 1.0 Vt CSFT—— 3.0µsLow Level Input Voltage VIL-0.3—0.3 V1V High Level Input Current on CSV I = 4.0 VI CSH-100—-20µALow Level Input Current on CSV I = 1.0 VI CSL-100—-20µATX High Level Input CurrentV I = 4.0 VI TXH-200-80-25µATX Low Level Input CurrentV I = 1.0 VI TXL-800-320-100µASI, SCLK Input Current0 < V IN < V1I SISLK-10—+10µATable 4. Static Electrical Characteristics (continued)Characteristics noted under conditions V BAT, -40°C ≤ T A ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.Characteristic Symbol Min Typ Max UnitELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSCONTROL INTERFACE (CONTINUED)RX, INT, MISO High Level Output Voltage I 0 = -250 µAV OHV1 - 0.9—V1VRX, INT, MISO Low Level Output Voltage I 0 = -1.5 mAV OL0.0—0.9VRX, INT, MISO Tri-Stated SO Output Current 0 V < V SO < V1I Z-2.0—+2.0µARST High Level Input Voltage V IH 0.7 V1—V1 + 0.3 V —RST Low Level Input Voltage V IL -0.3—-0.3 V1V RST High Level Output Current 10.0 < V OUT < 0.5 V1I RSTH1-50-30-10µARST High Level Output Current 20.5 < V OUT < V1I RSTH2—-300—µARST Low Level Output Voltage (I 0 = 1.5 mA)1.0 V < V BAT < 27 VV RST0.0—0.9VLX/Wake-Up Positive Switching Threshold 6.0 V <V BAT < 16 VV WUP3.03.74.5VLX/Wake-Up Negative Switching Threshold 6.0 V <V BAT < 16 V V WUN2.53.03.8VLX/Wake-Up Hysteresis 6.0 V <V BAT < 16 VV HYS—700—mALX/Wake-Up Leakage Current 0 < V WU < V BAT I LXWU -5.0—+5.0µA LX Input Current at 40 VV IN—350600µATable 4. Static Electrical Characteristics (continued)Characteristics noted under conditions V BAT , - 40°C ≤ T A ≤ 125°C unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSTable 5. Dynamic Electrical CharacteristicsCharacteristics noted under conditions 7.0 V ≤ V SUP≤ 18 V, - 40°C ≤ T A ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.Characteristic Symbol Min Typ Max Unit MICROCONTROLLER INTERFACEAC CANL/CANH Slew Rates, Rising or Falling Edges, TX from Recessive toDominant StateC LOAD - 10 nF, 133 Ω Termination Resistorst CANRD 3.5 5.010V/µsAC CANL/CANH Slew Rates, Rising or Falling Edges, TX from Dominant toRecessive StateC LOAD - 10 nF, 133 Ω Termination Resistorst CANDR 2.0 3.510V/µsAC Propagation Delay TX to RX LowC LOAD - 10 nF, 133 Ω Termination Resistorst DH— 1.2 2.0µsAC Propagation Delay TX to RX HighC LOAD - 10 nF, 133 Ω Termination Resistorst DL— 2.0 3.0µsWake-Up Filter Time tWUFT8.02038µs RST Duration after V1 High t RES— 1.0—ms SCLK Clock Period t PSCLK500——ns SCLK Clock High Time t WSCLKH175——ns SCLK Clock Low Time t WSCLKL175——ns Falling Edge of CS to Rising Edge of SCLK t LEAD25050—ns Falling Edge of SCLK to Rising Edge of CS t LEAD25050—nsSI to Falling Edge of SCLK t SISU12525—ns Falling Edge of SCLK to SI t SI(HOLD)12525—nsSO Rise Time (C L = 200 pF)t RSO—2575nsSO Fall Time (C L = 200 pF)t FSO—2575ns SI, CS, SCLK Incoming Signal Rise Time t RSI——200ns SI, CS, SCLK Incoming Signal Fall Time t FSI——200—Time from Falling Edge of CS to SOLow Impedance High Impedance t SO(EN)t SO(DIS)——200200nsTime from Rising Edge of SCLK to SO Data Valid0.2 V1 or V2 < SO > 0.8 V1 or V2, C L = 200 pFt VALID—50125—Running Mode Oscillator Tolerance (Normal Request, Normal and Stand-byModes (9))RMOT-12—+12%Software Watchdog Timing 1 (9)tSW1 4.4 5.0 5.6msSoftware Watchdog Timing 2 (9)tSW28.81011.2msSoftware Watchdog Timing 3 (9)tSW317.62022.4msSoftware Watchdog Timing 4 (9)tSW4283236ms Notes9.Software watchdog timing accuracy is based on the running mode oscillator toleranceELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSMICROCONTROLLER INTERFACE (CONTINUED)Software Watchdog Timing 5 (10)t SW544.85158ms Software Watchdog Timing 6 (10)t SW6657483ms Software Watchdog Timing 7 (10)t SW788100112ms Software Watchdog Timing 8 (10).t SW8167190213ms Sleep Mode Oscillator Tolerance (10)SMOT -30—+30%Cyclic Sense/FWU Timing 1 Sleep Mode (10)t CY122.43246.6ms Cyclic Sense/FWU Timing 2 Sleep Mode (10)t CY244.86483.2ms Cyclic Sense/FWU Timing 3 Sleep Mode (10)t CY389.6128166.4ms Cyclic Sense/FWU Timing 4 Sleep Mode (10)t CY4179256333ms Cyclic Sense/FWU Timing 5 Sleep Mode (10)t CY5358512665ms Cyclic Sense/FWU Timing 6 Sleep Mode (10).t CY671710241331ms Cyclic Sense/FWU Timing 7 Sleep Mode (10) t CY7143420482662ms Cyclic Sense/FWU Timing 8 Sleep Mode (10)t CY85734819210650ms Ground Shift Threshold 1 (11)CAN Transceiver Active in Two Wire Operation GS1-1.0-0.7-0.3VGround Shift Threshold 2 (11)CAN Transceiver Active in Two Wire Operation GS2-1.5-1.2-0.8VGround Shift Threshold 3 (11)CAN Transceiver Active in Two Wire Operation GS3-2.0-1.7-1.3VGround Shift Threshold 4 (11)CAN Transceiver Active in Two Wire Operation GS4-2.6-2.2-1.7VBUS TRANSMITTERAC Minimum Dominant Time for Wake-Up on CANL or CANH Bus Stand-by Mode, V BAT = 12 V t WAKE4.0—40µsAC Failure 3 Detection Time Bus Normal Mode t AC3D10—60µsAC Failure 3 Recovery Time Bus Normal Mode t AC3R10—60µsAC Failure 6 Detection Time Bus Normal Mode t AC6D50—400µsAC Failure 6 Recovery Time Bus Normal Modet AC6R150—1000µsAC Failure 4, 7, and 8 Detection Time Bus Normal Modet AC478D0.75—4.0msNotes10.Cyclic sense and forced wake-up timing accuracy are based on the Sleep mode oscillator tolerance.11.No overlap between two adjacent thresholds.Table 5. Dynamic Electrical Characteristics (continued)Characteristics noted under conditions 7.0 V ≤ V SUP ≤ 18 V, - 40°C ≤ T A ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSBUS TRANSMITTER (CONTINUED)AC Failure 4, 7, and 8 Recovery Time Bus Normal Modet AC478R10—60µsAC Failure 3, 4, and 7 Detection Time Bus Stand-by Mode, V BAT = 12 V t AC347D0.8—8.0msAC Failure 3, 4 and 7 Recovery Time Bus Stand-by Mode, V BAT = 12 Vt AC347R—2.5—msAC Edge Count Difference Between CANH/CANL for Failures 1, 2, 5 Detection Bus Normal ModeCAN 125D—3.0——AC Edge Count Difference Between CANH/CANL for Failures 1, 2, 5 Recovery Bus Normal ModeCAN 125R—3.0——TX Permanent Dominant Timer Disable Time Bus Normal and Failure Modes t TXD0.75—4.0msPOWER INPUT TIMING V1 Reset Delay Time t D 2.0—20µs V1 Line Regulation9.0 V < V BAT < 16.5, I LOAD = 10 mA t D -152.0+15mVV1 Line Regulation5.5 V < V BAT < 27 V I LOAD = 10 mA t D -5010+50mVV1 Load Regulation1.0 mA < I LOAD < 100 mA t D -50—+50mVV1 Line Ripple Rejection100 Hz, 1.0 V PP on V BAT = 12 V, I LOAD = 100 mA (12)t D 3055—dBV1 Line Transient ResponseV BAT from 12 V to 40 V in 1.0 µs, (10 µF, ESR = 3 Ω)t D —27—mVV1 Load Transient ResponseI LOAD from 10 µA to 100 mA in 1.0 µs (CLOAD = 10 µF, ESR = 3 Ω) (13)t D —400—mVV1 Load Transient ResponseI LOAD from 10 µA to 100 mA in 1.0 µs (CLOAD = 10 µF, ESR= 0.1 Ω)t D—16—mVNotes12.Guaranteed by design. Not production tested.13.This condition does not produce a resetTable 5. Dynamic Electrical Characteristics (continued)Characteristics noted under conditions 7.0 V ≤ V SUP ≤ 18 V, - 40°C ≤ T A ≤ 125°C, GND = 0 V unless otherwise noted. Typical values noted reflect the approximate parameter means at T A = 25°C under nominal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitELECTRICAL CHARACTERISTICS TIMING DIAGRAMSTIMING DIAGRAMSFigure 4. Input Timing Switch CharacteristicsSISCLKCSDon’t Care Don’t CareDon’t CareValidValidt LEAD t WSCLKH t WSCLKLt R t F t LAGt SISUt SI(HOLD)FUNCTIONAL DESCRIPTIONINTRODUCTION FUNCTIONAL DESCRIPTIONINTRODUCTIONThe System Basis Chip (SBC) is an integrated circuit dedicated to car body applications. It includes three main blocks:1. A dual voltage regulator2.Reset, watchdog, wake-up inputs, cyclic wake-up3.CAN low speed fault tolerant physical interfaceSuppliesTwo low drop regulators and one switch to V BAT are provided to supply the ECU microcontroller or peripherals, with independent control and monitoring through SPI.FUNCTIONAL PIN DESCRIPTIONTRANSMIT AND RECEIVE DATA (TX AND RX) The RX and TX pins (receive data and transmit data pins, respectively) are connected to a microcontroller’s CAN protocol handler. TX is an input and controls the CANH and CANL line state (dominant when TX is LOW, recessive when TX is HIGH). RX is an output and reports the bus state.VOLTAGE REGULATOR ONE AND TWO(V1 AND V2)The V1 pin is a 3% low drop voltage regulator dedicated to the microcontroller supply (nominal 5V supply).The V2 pin is a low drop voltage regulator dedicated to the peripherals supply (nominal 5V supply).RESET (RST)The RST (reset) pin is an input/output pin. The typical reset duration from SBC to microcontroller is 1ms. If longer times are required, an external capacitor can be used. SBC provides two RST output pull-up currents. A typical 30µA pull up when Vreset is below 2.5V and a 300uA pull up when reset voltage is higher than 2.5V. RST is also an input for the SBC. It means the MC33389 is forced to Normal Request mode after RST is released by the microcontroller INTERRUPT (INT)The Interrupt pin INT is an output that is set LOW when an interrupt occurs. INT is enabled using the Interrupt Register (INTR). When an interrupt occurs, INT stays LOW until the interrupt source is cleared.INT output also reports a wake-up event.GROUND (GND)This pin is the ground of the integrated circuit.MASTER IN/ SLAVE OUT (MISO)MISO is the Master In Slave Out pin of the serial peripheral interface. Data is sent from the SBC to the microcontroller through the MISO pin.MASTER OUT/ SLAVE IN (MOSI)MOSI is the Master Out Slave In pin of the serial peripheral interface. Control data from a microcontroller is received through this pin.SYSTEM CLOCK (SCLK)This pin clocks the internal shift registers for SPI communication.CHIP SELECT (CS)CS is the Chip Select pin of the serial peripheral interface (SPI). When this pin is LOW, the SPI port of the device is selected.LEVEL 0-2 INPUTS (L0: L2)The L0: L2 pins can be connected to contact switches or the output of other ICs for external inputs. The input states can be read by the SPI. These inputs can be used as wake-up events for the SBC.NO CONNECT (NC)No pin connection.TERMINATION RESISTANCE (HIGH AND LOW?) (RTH AND RTL)External CAN bus high and low termination resistance pins are connected to these pins.CAN HIGH AND CAN LOW OUTPUTS(CANH AND CANL)The CAN High and CAN Low pins are the interfaces to the CAN bus lines. They are controlled by TX input level, and the state of CANH and CANL is reported through RX output. VOLTAGE BATTERY (VBAT)This pin is the voltage supply from the battery.VOLTAGE REGULATOR THREE (V3)This pin is a 10 Ω switch to VBAT, which is used to supply external contacts or relays.。

39352-00中文资料

FEATURES AND SPECIFICATIONS3.50mm (.138") Pitch Beau ® Eurostyle ® 35 SeriesPluggable Terminal Blocks3.50mm (.138") Pluggable Terminal Blocks for Higher Density Applications3.50mm (.138") terminal blocks have gained wide spread market acceptance and continue to grow in popularity as the terminal block of choice as more and more high density I/O applications are released. The compact size makes it the perfect choice for low-level signal, I/O daughter cards and also where PCB real estate is limited.Features and Beneﬁts■ 30% density advantage over traditional 5.00mm (.197") terminal blocks■Headers have been designed to withstand surface mount re-ﬂow soldering processes, eliminating the need for secondary wave soldering operations and reducing assembly time■ Rising cage clamp termination provides a gas-tight connection without strand damage or intermittence ■ Polarization and keying features prevent mis-mating■Optional retention screws and inserts secure plug to header in vibration-susceptible applications where the possibility of accidental disconnection exists ■Additional options available: imprinting, Gold-plating and color options including green, orange and blueReplace XX with circuit size 02 through 20Series No.Order No.Description 3935139351-00XX Plug3935239352-00XX Plug with Retention Screws3935339353-00XX Vertical Header3935439354-00XX Vertical Header with Retention Inserts3935539355-00XX Right Angle Header3935639356-00XXRight Angle Header with Retention InsertsORDERING INFORMATIONSpeciﬁcationsReference Information Packaging: Box UL File No.: E48521Guide No.: XCFR2UL for Canada File No: E48521Guide No.: XCFR8Electrical Voltage: 300V Current: 10.0AContact Resistance: 1 milliohm max.Dielectric Withstanding Voltage: 3500V DC min.Insulation Resistance: 5000 Gigohms min.Physical Housing:Header – Black, Nylon 4/6, UL 94V-0 Plug – Black, Polyamide 4/6 Contacts:Header – BrassPlug – Beryllium Copper Plating: TinWire Range: 16 to 24 AWG (1.0 to 0.2mm2 )Operating Temperature: +140°C元器件交易网3.50mm (.138") PitchBeau® Eurostyle®35 SeriesPluggable Terminal Blocks APPLICATIONS■Process Controls ■Motors and Drives ■Motion Control■Factory Automation ■Instrumentation ■Security, Alarm and Surveillance ■Signal Conditioning■Scales and Weighing Equipment ■Switching EquipmentAmericas Headquarters Lisle, Illinois 60532 U.S.A. 1-800-78MOLEX amerinfo@ Far East North HeadquartersYamato, Kanagawa, Japan81-462-65-2324feninfo@Far East South HeadquartersJurong, Singapore65-6-268-6868fesinfo@European HeadquartersMunich, Germany49-89-413092-0eurinfo@Corporate Headquarters2222 Wellington Ct.Lisle, IL 60532 U.S.A.630-969-4550Fax:630-969-1352 Visit our Web site at /product/tblocks.htmlOrder No. USA-198 Rev. 1Printed in USA/7.5K/JI/JI/2004.03©2004, Molex 元器件交易网。

AO4459中文资料

AO4459中⽂资料SymbolTyp Max 33406275R θJL 1824Maximum Junction-to-Lead CSteady-State°C/WThermal Characteristics ParameterUnits Maximum Junction-to-AmbientAt ≤ 10s R θJA °C/W Maximum Junction-to-Ambient ASteady-State °C/W AO4459AO4459SymbolMin TypMaxUnits BV DSS -30V -1T J =55°C-5I GSS ±100nA V GS(th)-1.5-1.85-2.5V I D(ON)-30A 3846T J =125°C53685872m ?g FS 11S V SD -0.78-1V I S-3.5A C iss 668830pF C oss 126pF C rss 92pF R g69?Q g (10V)12.716nC Q g (4.5V) 6.4nC Q gs 2nC Q gd 4nC t D(on)7.7ns t r 6.8ns t D(off)20ns t f 10ns t rr 2230ns Q rr15nCTHIS PRODUCT HAS BEEN DESIGNED AND QUALIFIED FOR THE CONSUMER MARKET. APPLICATIONS OR USES AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS ARE NOT AUTHORIZED. AOS DOES NOT ASSUME ANY LIABILITY ARISING OUT OF SUCH APPLICATIONS OR USES OF ITS PRODUCTS. AOS RESERVES THE RIGHT TO IMPROVE PRODUCT DESIGN,FUNCTIONS AND RELIABILITY WITHOUT NOTICE.DYNAMIC PARAMETERS Maximum Body-Diode Continuous CurrentGate resistanceV GS =0V, V DS =0V, f=1MHzV GS =0V, V DS =-15V, f=1MHz Input Capacitance Output Capacitance Turn-On Rise Time Turn-Off DelayTime V GS =-10V, V DS =-15V, R L =2.5?, R GEN =3?Turn-Off Fall TimeTurn-On DelayTime SWITCHING PARAMETERSTotal Gate Charge (4.5V)Gate Source Charge Gate Drain Charge Total Gate Charge (10V)V GS =-10V, V DS =-15V, I D =-6.5Am ?V GS =-4.5V, I D =-5AI S =-1A,V GS =0V V DS =-5V, I D =-6.5AR DS(ON)Static Drain-Source On-ResistanceForward TransconductanceDiode Forward VoltageI DSS µA Gate Threshold Voltage V DS =V GS I D =-250µA V DS =-24V, V GS =0VV DS =0V, V GS =±20V Zero Gate Voltage Drain Current Gate-Body leakage current Electrical Characteristics (T J =25°C unless otherwise noted)STATIC PARAMETERS ParameterConditions Body Diode Reverse Recovery Time Body Diode Reverse Recovery ChargeI F =-6.5A, dI/dt=100A/µsDrain-Source Breakdown Voltage On state drain currentI D =-250µA, V GS =0V V GS =-10V, V DS =-5V V GS =-10V, I D =-6.5AReverse Transfer Capacitance I F =-6.5A, dI/dt=100A/µs A: The value of R θJA is measured with the device mounted on 1in 2FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The value in any a given application depends on the user's specific board design. The current rating is based on the t ≤ 10s thermal resistance rating.B: Repetitive rating, pulse width limited by junction temperature.C. The R θJA is the sum of the thermal impedence from junction to lead R θJL and lead to ambient.D. The static characteristics in Figures 1 to 6 are obtained using < 300µs pulses, duty cycle 0.5% max.E. These tests are performed with the device mounted on 1 in 2FR-4 board with 2oz. Copper, in a still air environment with T A =25°C. The SOA curve provides a single pulse rating. Rev0 Sept 2006AO4459AO4459。

M393T5166AZA-CC中文资料

DDR2 Registered SDRAM MODULE 240pin Registered Module based on 1Gb A-die72-bit ECCINFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,AND IS SUBJECT TO CHANGE WITHOUT NOTICE.NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDEDON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.1. For updates or additional information about Samsung products, contact your nearest Samsung office.2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similarapplications where Product failure couldresult in loss of life or personal or physical harm, or any military ordefense application, or any governmental procurement to which special terms or provisions may apply.* Samsung Electronics reserves the right to change products or specification without notice.Table of Contents1.0 DDR2 Registered DIMM Ordering Information (4)2.0 Features (4)3.0 Address Configuration (4)4.0 Pin Configurations (Front side/Back side) (5)5.0 Pin Description (6)6.0 Input/Output Function Description (7)7.0 Functional Block Diagram (8)7.1 1GB, 128Mx72 Module (M393T2863AZ3/M393T2863AZA) (8)7.2 2GB, 256Mx72 Module (M393T5663AZ3/M393T5663AZA) (9)7.3 2GB, 256Mx72 Module (M393T5660AZ3/M393T5660AZA) (10)7.4 4GB, 512Mx72 Module (M393T5168AZ0/M393T5166AZA) (11)8.0 Absolute Maximum DC Ratings (12)9.0 AC & DC Operating Conditions (12)9.1 Operating Temperature Condition (13)9.2 Input DC Logic Level (13)9.3 Input AC Logic Level (13)9.4 AC Input Test Conditions (13)10.0 IDD Specification Parameters Definition (14)11.0 Operating Current Table(1-1) (15)11.1 M393T2863AZ3/M393T2863AZA : 1GB(128Mx8 *9) Module (15)11.2 M393T5663AZ3/M393T5663AZA : 2GB(128Mx8 *18) Module (15)11.3 M393T5660AZ3/M393T5660AZA : 2GB(256Mx4 *18) Module (16)11.4 M393T5168AZ0/M393T5166AZA : 4GB(st.512Mx4 *18) Module (16)12.0 Input/Output Capacitance (17)13.0 Electrical Characteristics & AC Timing for DDR2-667/533/400 (18)13.1 Refresh Parameters by Device Density (18)13.2 Speed Bins and CL, tRCD, tRP, tRC and tRAS for Corresponding Bin (18)13.3 Timing Parameters by Speed Grade (18)14.0 Physical Dimensions (20)14.1 128Mbx8 based 128Mx72 Module(1 Rank) (M393T2863AZ3/M393T2863AZA) (20)14.2 128Mbx8/256Mbx4 based 256Mx72 Module(2/1 Ranks)(M393T5663AZ3/M393T5663AZA/ M393T5660AZ3/M393T5660AZA) (21)14.3 st.512Mbx4 based 512Mx72 Module(2 Ranks) (M393T5168AZ0/M393T5166AZA) (22)15.0 240 Pin DDR2 Registered DIMM Clock Topology (23)Revision HistoryRevision Month Year History1.0July2005 - Initial Release1.1Aug.2005 - Revised IDD Current Values1.2Sep.2005 - Revised the Ordering InformationDDR2 Registered DIMM Ordering InformationPart Number Density Organization Component Composition Number of Rank Parity Register Height M393T2863AZ3-CD5/CC1GB128Mx72128Mx8(K4T1G084QA)*9EA1X30mm M393T2863AZA-CE6/D5/CC1GB128Mx72128Mx8(K4T1G084QA)*9EA1O30mm M393T5663AZ3-CD5/CC2GB256Mx72128Mx8(K4T1G084QA)*18EA2X30mm M393T5663AZA-CE6/D5/CC2GB256Mx72128Mx8(K4T1G084QA)*18EA2O30mm M393T5660AZ3-CD5/CC2GB256Mx72256Mx4(K4T1G044QA)*18EA1X30mm M393T5660AZA-CE6/D5/CC2GB256Mx72256Mx4(K4T1G044QA)*18EA1O30mm M393T5168AZ0-CD5/CC4GB512Mx72st.512Mx4(K4T2G064QA)*18EA2X30mm M393T5166AZA-CE6/D5/CC4GB512Mx72st.512Mx4(K4T2G264QA)*18EA2O30mm Note: “Z” of Part number(11th digit) stand for Lead-free products.Note: “3” of Part number(12th digit) stand for Dummy Pad PCB products.Note: "A" of Part number(12th digit) stand for Parity Register products.Features•Performance rangeE6(DDR2-667)D5(DDR2-533)CC(DDR2-400)UnitSpeed@CL3400400400MbpsSpeed@CL4533533400MbpsSpeed@CL5667533-MbpsCL-tRCD-tRP5-5-54-4-43-3-3CK•JEDEC standard 1.8V ± 0.1V Power Supply•V DDQ = 1.8V ± 0.1V•200 MHz f CK for 400Mb/sec/pin, 267MHz f CK for 533Mb/sec/pin, 333MHz f CK for 667Mb/sec/pin•8Banks•Posted CAS•Programmable CAS Latency: 3, 4, 5•Programmable Additive Latency: 0, 1 , 2 , 3 and 4•Write Latency(WL) = Read Latency(RL) -1•Burst Length: 4 , 8(Interleave/nibble sequential)•Programmable Sequential / Interleave Burst Mode•Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)•Off-Chip Driver(OCD) Impedance Adjustment•On Die Termination with selectable values(50/75/150 ohms or disable)•PASR(Partial Array Self Refresh)•Average Refresh Period 7.8us at lower than a T CASE 85°C, 3.9us at 85°C < T CASE < 95 °C- support High Temperature Self-Refresh rate enable feature•Serial presence detect with EEPROM•DDR2 SDRAM Package: 68ball FBGA - 256Mx4/128Mx8, 56ball BGA - st.512Mbx4•All of Lead-free products are compliant for RoHSNote: For detailed DDR2 SDRAM operation, please refer to Samsung’s Device operation & Timing diagram..Address ConfigurationOrganization Row Address Column Address Bank Address Auto Precharge 256Mx4(1Gb) based Module A0-A13A0-A9, A11BA0-BA2A10128Mx8(1Gb) based Module A0-A13A0-A9BA0-BA2A10NC = No Connect, RFU = Reserved for Future Use1. RESET (Pin 18) is connected to both OE of PLL and Reset of register.2. The Test pin (Pin 102) is reserved for bus analysis probes and is not connected on normal memory modules (DIMMs)3. NC/Err_Out ( Pin 55) and NC/Par_In (Pin 68) are for optional function to check address and command parity.4. CKE1,S1 Pin is used for double side Registered DIMM.Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back Pin Front Pin Back 1V REF 121V SS 31DQ19151V SS 61A4181V DDQ 91V SS 211DM5/DQS142V SS 122DQ432V SS 152DQ2862V DDQ 182A392DQS5212NC/DQS143DQ0123DQ533DQ24153DQ2963A2183A193DQS5213V SS 4DQ1124V SS 34DQ25154V SS 64V DD184V DD94V SS 214DQ465V SS 125DM0/DQS935V SS 155DM3/DQS12KEY95DQ42215DQ476DQS0126NC/DQS936DQS3156NC/DQS1265V SS 185CK096DQ43216V SS 7DQS0127V SS 37DQS3157V SS 66V SS 186CK097V SS 217DQ528V SS 128DQ638V SS 158DQ3067V DD 187V DD 98DQ48218DQ539DQ2129DQ739DQ26159DQ3168NC/Par_In 188A099DQ49219V SS 10DQ3130V SS 40DQ27160V SS 69V DD 189V DD 100V SS 220RFU 11V SS 131DQ1241V SS 161CB470A10/AP 190BA1101SA2221RFU 12DQ8132DQ1342CB0162CB571BA0191V DDQ 102NC(TEST)222V SS 13DQ9133V SS 43CB1163V SS 72V DDQ 192RAS 103V SS 223DM6/DQS1514V SS 134DM1/DQS1044V SS 164DM8/DQS1773WE 193S0104DQS6224NC/DQS1515DQS1135NC/DQS1045DQS8165NC/DQS1774CAS 194V DDQ 105DQS6225V SS 16DQS1136V SS 46DQS8166V SS 75V DDQ 195ODT0106V SS 226DQ5417V SS 137RFU 47V SS 167CB676S14196A13107DQ50227DQ5518RESET 138RFU 48CB2168CB777ODT1197V DD 108DQ51228V SS 19NC 139V SS 49CB3169V SS 78V DDQ 198V SS 109V SS 229DQ6020V SS 140DQ1450V SS 170V DDQ 79V SS 199DQ36110DQ56230DQ6121DQ10141DQ1551V DDQ 171CKE1480DQ32200DQ37111DQ57231V SS 22DQ11142V SS 52CKE0172V DD 81DQ33201V SS 112V SS 232DM7/DQS1623V SS 143DQ2053V DD 173NC 82V SS 202DM4/DQS13113DQS7233NC/DQS1624DQ16144DQ2154BA2174NC 83DQS4203NC/DQS13114DQS7234V SS 25DQ17145V SS 55NC/Err_Out 175V DDQ 84DQS4204V SS 115V SS 235DQ6226V SS 146DM2/DQS1156V DDQ 176A1285V SS 205DQ38116DQ58236DQ6327DQS2147NC/DQS1157A11177A986DQ34206DQ39117DQ59237V SS 28DQS2148V SS 58A7178V DD 87DQ35207V SS 118V SS 238VDDSPD 29V SS 149DQ2259V DD 179A888V SS 208DQ44119SDA 239SA030DQ18150DQ2360A5180A689DQ40209DQ45120SCL240SA190DQ41210V SS Pin Configurations (Front side/Back side)* The VDD and VDDQ pins are tied to the single power-plane on PCB.Pin Name DescriptionPin Name Description CK0Clock Inputs, positive line ODT0~ODT1On die termination CK0Clock inputs, negative line DQ0~DQ63Data Input/OutputCKE0, CKE1Clock Enables CB0~CB7Data check bits Input/Output RAS Row Address Strobe DQS0~DQS8Data strobesCAS Column Address Strobe DQS0~DQS8Data strobes, negative line WE Write Enable DM(0~8), DQS(9~17)Data Masks / Data strobes (Read)S0, S1Chip Selects DQS9~DQS17Data strobes (Read), negative line A0~A9, A11~A13Address InputsRFU Reserved for Future Use A10/AP Address Input/Autoprecharge NC No ConnectBA0~BA2DDR2 SDRAM Bank AddressTEST Memory bus test tool(Not Connect and Not Useable on DIMMs)SCL Serial Presence Detect (SPD) Clock Input V DD Core Power SDA SPD Data Input/Output V DDQ I/O Power SA0~SA2SPD addressV SS GroundPar_In Parity bit for the Address and Control bus V REF Input/Output Reference Err_Out Parity error found in the Address and Control bus V DDSPDSPD PowerRESETRegister and PLL control pinPin DescriptionSymbol Type DescriptionCK0Input Positive line of the differential pair of system clock inputs that drives input to the on-DIMM PLL.CK0Input Negative line of the differential pair of system clock inputs that drives the input to the on-DIMM PLL.CKE0~CKE1Input Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode.S0~S1Input Enables the associated SDRAM command decoder when low and disables decoder when high. When decoder is dis-abled, new commands are ignored but previous operations continue.These input signals also disable all outputs (except CKE and ODT) of the register(s) on the DIMM when both inputs are high.ODT0~ODT1Input I/O bus impedance control signals.RAS, CAS, WE Input When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM.V REF Supply Reference voltage for SSTL_18 inputsV DDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity BA0~BA2Input Selects which SDRAM bank of eight is activated.A0~A9,A10/APA11~A13Input During a Bank Activate command cycle, Address defines the row address.During a Read or Write command cycle, Address defines the column address. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0, BA1, BA2 defines the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge com-mand cycle, AP is used in conjunction with BA0, BA1, BA2 to control which bank(s) to precharge. If AP is high, all banks will be precharged regardless of the state of BA0 or BA1 or BA2. If AP is low, BA0 and BA1 and BA2 are used to define which bank to precharge.DQ0~63,CB0~CB7In/Out Data and Check Bit Input/Output pinsDM0~DM8Input Masks write data when high, issued concurrently with input data. Both DM and DQ have a write latency of one clock once the write command is registered into the SDRAM.V DD, V SS Supply Power and ground for the DDR SDRAM input buffers and core logicDQS0~DQS17In/Out Positive line of the differential data strobe for input and output data.DQS0~DQS17In/Out Negative line of the differential data strobe for input and output data.SA0~SA2Input These signals are tied at the system planar to either V SS or V DDSPD to configure the serial SPD EEPROM address range.SDA In/Out This bidirectional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DDSPD to act as a pullup.SCL Input This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DDSPD to act as a pullup.V DDSPD Supply Serial EEPROM positive power supply (wired to a separate power pin at the connector which supports from 1.7 Volt to 3.6 Volt operation).RESET Input The RESET pin is connected to the RST pin on the register and to the OE pin on the PLL. When low, all register outputs will be driven low and the PLL clocks to the DRAMs and register(s) will be set to low level (The PLL will remain synchro-nized with the input clock )Par_In Input Parity bit for the Address and Control bus. ( “1 “ : Odd, “0 “ : Even) Err_Out Input Parity error found in the Address and Control busTEST In/Out Used by memory bus analysis tools (unused on memory DIMMs) Input/Output Function Description(populated as 1 rank of x8 DDR2 SDRAMs)1GB, 128Mx72 Module (M393T2863AZ3/M393T2863AZA)RS0DQS0DQS0DM0/DQS9NC/DQS9DM/ RDQS NU/RDQSCS DQS DQSDQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D0DQS1DQS1DM1/DQS10 NC/DQS10DM/ RDQS NU/RDQSCS DQS DQSDQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D1DQS2DQS2DM2/DQS11 NC/DQS11DM/ RDQS NU/RDQSCS DQS DQSDQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D2DQS3DQS3DM3/DQS12 NC/DQS12DM/ RDQS NU/RDQSCS DQS DQSDQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D3DQS8DQS8DM8/DQS17 NC/DQS17DM/ RDQS NU/RDQSCS DQS DQSCB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D8DQS4DQS4DM4/DQS13NC/DQS13DM/RDQSNU/RDQSCS DQS DQSDQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D4DQS5DQS5DM5/DQS14NC/DQS14DM/RDQSNU/RDQSCS DQS DQSDQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D5DQS6DQS6DM6/DQS15NC/DQS15DM/RDQSNU/RDQSCS DQS DQSDQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D6DQS7DQS7DM7/DQS16NC/DQS16DM/RDQSNU/RDQSCS DQS DQSDQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D7A0Serial PDA1A2SA0SA1SA2SCL SDAV SS D0 - D8V DD/V DDQ D0 - D8D0 - D8VREFV DDSPD Serial PDWPNotes :1. DQ-to-I/O wiring may be changed within a byte.2. DQ/DQS/DM/CKE/S relationships must be maintained as shown.3. Unless otherwise noted, resister values are 22 Ohms1:1REGISTERRSTS0*BA0-BA2A0-A13RASCASWECKE0ODT0RESETPCK7PCK7RSO-> CS : DDR2 SDRAMs D0-D8RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D8RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D8RRAS -> RAS : DDR2 SDRAMs D0-D8RCAS -> CAS : DDR2 SDRAMs D0-D8RWE -> WE : DDR2 SDRAMs D0-D8RCKE0 -> CKE : DDR2 SDRAMs D0-D8RODT0 -> ODT0 : DDR2 SDRAMs D0-D8PLLOECK0CK0RESETPCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8PCK7 -> CK : RegisterPCK7 -> CK : Register* S0 connects to DCS and VDD connects to CSR on the register.Functional Block DiagramSignals for Address and Command Parity Function (M393T2863AZA)V SSV SS PAR_IN C0C1PPOQERR Err_Out RegisterPAR_IN100K ohmsThe resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs"RS0DQS0DQS0DM0/DQS9NC/DQS9DM/RDQS NU/RDQSCS DQS DQSDQ0DQ1DQ2DQ3DQ4DQ5DQ6DQ7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D0DQS1DQS1DM1/DQS10NC/DQS10DM/RDQS NU/RDQSCS DQS DQSDQ8DQ9DQ10DQ11DQ12DQ13DQ14DQ15I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D1DQS2DQS2DM2/DQS11NC/DQS11DM/RDQS NU/RDQSCS DQS DQSDQ16DQ17DQ18DQ19DQ20DQ21DQ22DQ23I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D2DQS3DQS3DM3/DQS12NC/DQS12DM/RDQS NU/RDQSCS DQS DQSDQ24DQ25DQ26DQ27DQ28DQ29DQ30DQ31I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D3DQS8DQS8DM8/DQS17NC/DQS17DM/RDQS NU/RDQSCS DQS DQSCB0CB1CB2CB3CB4CB5CB6CB7I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D8DQS4DQS4DM4/DQS13NC/DQS13DM/RDQS NU/RDQSCS DQS DQSDQ32DQ33DQ34DQ35DQ36DQ37DQ38DQ39I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D4DQS5DQS5DM5/DQS14NC/DQS14DM/RDQS NU/RDQSCS DQS DQSDQ40DQ41DQ42DQ43DQ44DQ45DQ46DQ47I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D5DQS6DQS6DM6/DQS15NC/DQS15DM/RDQS NU/RDQSCS DQS DQSDQ48DQ49DQ50DQ51DQ52DQ53DQ54DQ55I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D6DQS7DQS7DM7/DQS16NC/DQS16DM/RDQS NU/RDQSCS DQS DQSDQ56DQ57DQ58DQ59DQ60DQ61DQ62DQ63I/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D7DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D9DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D10DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D11DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D12DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D17DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D13DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D14DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D15DM/RDQS NU/RDQSCS DQS DQSI/O 0I/O 1I/O 2I/O 3I/O 4I/O 5I/O 6I/O 7D16RS1A0Serial PDA1A2SA0SA1SA2SCLSDAV SSD0 - D17V DD /V DDQ D0 - D17D0 - D17VREF V DDSPDSerial PD WP Notes :1. DQ-to-I/O wiring may be changed per nibble.2. Unless otherwise noted, resister values are 22 Ohms3. RS0 and RS1 alternate between the back and front sides of the DIMM1:2R E G I S T E RRSTS1*BA0-BA2A0-A13RAS CAS WE CKE0CKE1RESET**PCK7**PCK7**RS1-> CS : DDR2 SDRAMs D9-D17RBA0-RBA2 -> BA0-BA2: DDR2 SDRAMs D0-D17RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17RRAS -> RAS : DDR2 SDRAMs D0-D17RCAS -> CAS : DDR2 SDRAMs D0-D17RWE -> WE : DDR2 SDRAMs D0-D17RCKE0 -> CKE : DDR2 SDRAMs D0-D8RCKE1 -> CKE : DDR2 SDRAMs D9-D17P L LOECK0CK0RESETPCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D17PCK7 -> CK : Register PCK7 -> CK : RegisterODT0ODT1RODT0 -> ODT0 : DDR2 SDRAMs D0-D8RODT1 -> ODT1 : DDR2 SDRAMs D9-D17S0*RSO-> CS : DDR2 SDRAMs D0-D8(populated as 2 rank of x8 DDR2 SDRAMs)2GB, 256Mx72 Module (M393T5663AZ3/M393T5663AZA)* S0 connects to DCS and S0 connects to CSR on a Register,S1 connects to DCS and S0 connects to CSR on another Register.** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.Signals for Address and Command Parity Function (M393T5663AZA)V SS V DDPAR_IN C0C1PPO QERRRegister APAR_IN 100K ohmsThe resistors on Par_In, A13, A14, A15, BA2 and the signal line of Err_Out refer to the section: "Register Options for Unused Address inputs"V DD V DDC0C1PPO QERRErr_OutRegister BPAR_INVSSRS0DQS0DQS0DM CS DQS DQSDQ0 DQ1 DQ2 DQ3I/O 0I/O 1I/O 2I/O 3D0DM0/DQS9NC/DQS9DM CS DQS DQSDQ4DQ5DQ6DQ7I/O 0I/O 1I/O 2I/O 3D9DQS1DQS1DM CS DQS DQSDQ8 DQ9 DQ10 DQ11I/O 0I/O 1I/O 2I/O 3D1DM1/DQS10NC/DQS10DM CS DQS DQSDQ12DQ13DQ14DQ15I/O 0I/O 1I/O 2I/O 3D10DQS2DQS2DM CS DQS DQSDQ16 DQ17 DQ18 DQ19I/O 0I/O 1I/O 2I/O 3D2DM2/DQS11NC/DQS11DM CS DQS DQSDQ20DQ21DQ22DQ23I/O 0I/O 1I/O 2I/O 3D11DQS3DQS3DM CS DQS DQSDQ24 DQ25 DQ26 DQ27I/O 0I/O 1I/O 2I/O 3D3DM3/DQS12NC/DQS12DM CS DQS DQSDQ28DQ29DQ30DQ31I/O 0I/O 1I/O 2I/O 3D12DQS5DQS5DM CS DQS DQSDQ40 DQ41 DQ42 DQ43I/O 0I/O 1I/O 2I/O 3D5DM5/DQS14NC/DQS14DM CS DQS DQSDQ44DQ45DQ46DQ47I/O 0I/O 1I/O 2I/O 3D14DQS4DQS4DM CS DQS DQSDQ32 DQ33 DQ34 DQ35I/O 0I/O 1I/O 2I/O 3D4DM4/DQS13NC/DQS13DM CS DQS DQSDQ36DQ37DQ38DQ39I/O 0I/O 1I/O 2I/O 3D13DQS6DQS6DM CS DQS DQSDQ48 DQ49 DQ50 DQ51I/O 0I/O 1I/O 2I/O 3D6DM6/DQS15NC/DQS15DM CS DQS DQSDQ52DQ53DQ54DQ55I/O 0I/O 1I/O 2I/O 3D15DQS8DQS8DM CS DQS DQSCB0 CB1 CB2 CB3I/O 0I/O 1I/O 2I/O 3D8DM8/DQS17NC/DQS17DM CS DQS DQSCB4CB5CB6CB7I/O 0I/O 1I/O 2I/O 3D17DQS7DQS7DM CS DQS DQSDQ56 DQ57 DQ58 DQ59I/O 0I/O 1I/O 2I/O 3D7DM7DQS16NC/DQS16DM CS DQS DQSDQ60DQ61DQ62DQ63I/O 0I/O 1I/O 2I/O 3D16A0Serial PDA1A2SA0SA1SA2SCL SDAV SS D0 - D17V DD/V DDQ D0 - D17D0 - D17VREFV DDSPD Serial PDWPNotes :1. DQ-to-I/O wiring may be changed per nibble.2. Unless otherwise noted, resister values are 22 Ohms 1:2REGISTERRSTS0*BA0-BA2A0-A13RASCASWECKE0ODT0RESET**PCK7** PCK7**RSO-> CS : DDR2 SDRAMs D0-D17RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D17RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D17RRAS -> RAS : DDR2 SDRAMs D0-D17RCAS -> CAS : DDR2 SDRAMs D0-D17RWE -> WE : DDR2 SDRAMs D0-D17RCKE0 -> CKE : DDR2 SDRAMs D0-D17RODT0 -> ODT0 : DDR2 SDRAMs D0-D17PLLOECK0CK0RESETPCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D8PCK7 -> CK : RegisterPCK7 -> CK : Register(populated as 1 rank of x4 DDR2 SDRAMs)2GB, 256Mx72 Module (M393T5660AZ3/M393T5660AZA)* S0 connects to DCS of Register1, CSR of Register2. CSR of reg-ister 1 and DCS of register 2 connects to VDD.** RESET, PCK7 and PCK7 connects to both Registers. Other sig-nals connect to one of two Registers.Signals for Address and Command Parity Function (M393T5660AZA)V SSV DDPAR_INC0C1PPOQERRRegister APAR_IN100K ohmsThe resistors on Par_In, A13, A14, A15, BA2 and thesignal line of Err_Out refer to the section: "RegisterOptions for Unused Address inputs"V DDV DDC0C1PPOQERR Err_OutRegister BPAR_IN(populated as 2 rank of x4 DDR2 SDRAMs)A0Serial PDA1A2SA0SA1SA2SCLSDAV SSD0 - D35V DD /V DDQ D0 - D35D0 - D35VREF V DDSPDSerial PD WP P L LOECK0CK0RESET PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35PCK0-PCK6, PCK8, PCK9 -> CK : DDR2 SDRAMs D0-D35PCK7 -> CK : Register PCK7 -> CK : Register1:2R E G I S T E RRSTS1*BA0-BA2A0-A13RAS CAS WE CKE0CKE1RESET**PCK7**PCK7**RS1-> CS : DDR2 SDRAMs D18-D35RBA0-RBA2 -> BA0-BA2 : DDR2 SDRAMs D0-D35RA0-RA13 -> A0-A13 : DDR2 SDRAMs D0-D35RRAS -> RAS : DDR2 SDRAMs D0-D35RCAS -> CAS : DDR2 SDRAMs D0-D35RWE -> WE : DDR2 SDRAMs D0-D35RCKE0 -> CKE : DDR2 SDRAMs D0-D17RCKE1 -> CKE : DDR2 SDRAMs D18-D35ODT0ODT1RODT0 -> ODT0 : DDR2 SDRAMs D0-D17RODT1 -> ODT1 : DDR2 SDRAMs D18-D35S0*RSO-> CS : DDR2 SDRAMs D0-D174GB, 512Mx72 Module (M393T5168AZ0/M393T5166AZA)* S0 connects to DCS and S0 connects to CSR on a Register,S1 connects to DCS and S0 connects to CSR on another Register.** RESET, PCK7 and PCK7 connects to both Registers. Other signals connect to one of two Registers.VSS RS0DQS0DQS0DMCSDQS DQSDQ0DQ1DQ2DQ3I/O 0I/O 1I/O 2I/O 3D0DM0/DQS9NC/DQS9DMCSDQS DQSDQ4DQ5DQ6DQ7I/O 0I/O 1I/O 2I/O 3D9DQS1DQS1DM CS DQS DQS DQ8DQ9DQ10DQ11I/O 0I/O 1I/O 2I/O 3D1DM1/DQS10NC/DQS10DM CS DQS DQS DQ12DQ13DQ14DQ15I/O 0I/O 1I/O 2I/O 3D10DQS2DQS2DM CS DQS DQS DQ16DQ17DQ18DQ19I/O 0I/O 1I/O 2I/O 3D2DM2/DQS11NC/DQS11DM CS DQS DQS DQ20DQ21DQ22DQ23I/O 0I/O 1I/O 2I/O 3D11DQS3DQS3DM CS DQS DQS DQ24DQ25DQ26DQ27I/O 0I/O 1I/O 2I/O 3D3DM3/DQS12NC/DQS12DM CS DQS DQS DQ28DQ29DQ30DQ31I/O 0I/O 1I/O 2I/O 3D12DQS5DQS5DM CS DQS DQS DQ40DQ41DQ42DQ43I/O 0I/O 1I/O 2I/O 3D5DM5/DQS14NC/DQS14DM CS DQS DQS DQ44DQ45DQ46DQ47I/O 0I/O 1I/O 2I/O 3D14DQS4DQS4DM CS DQS DQS DQ32DQ33DQ34DQ35I/O 0I/O 1I/O 2I/O 3D4DM4/DQS13NC/DQS13DM CS DQS DQS DQ36DQ37DQ38DQ39I/O 0I/O 1I/O 2I/O 3D13DQS6DQS6DM CS DQS DQS DQ48DQ49DQ50DQ51I/O 0I/O 1I/O 2I/O 3D6DM6/DQS15NC/DQS15DM CS DQS DQS DQ52DQ53DQ54DQ55I/O 0I/O 1I/O 2I/O 3D15DQS8DQS8DM CS DQS DQS CB0CB1CB2CB3I/O 0I/O 1I/O 2I/O 3D8DM8/DQS17NC/DQS17DM CS DQS DQS CB4CB5CB6CB7I/O 0I/O 1I/O 2I/O 3D17DQS7DQS7DM CS DQS DQS DQ56DQ57DQ58DQ59I/O 0I/O 1I/O 2I/O 3D7DM7DQS16NC/DQS16DM CS DQS DQS DQ60DQ61DQ62DQ63I/O 0I/O 1I/O 2I/O 3D16DM/CSDQS DQSI/O 0I/O 1I/O 2I/O 3D18DM/CS DQS DQS I/O 0I/O 1I/O 2I/O 3D19DM/CS DQS DQS I/O 0I/O 1I/O 2I/O 3D20DM CS DQS DQS I/O 0I/O 1I/O 2I/O 3D21DM CS DQS DQS I/O 0I/O 1I/O 2I/O 3D23DM CS DQS DQS I/O 0I/O 1I/O 2I/O 3D22DM CS DQS DQS I/O 0I/O 1I/O 2I/O 3D24DM CS DQS DQS I/O 0I/O 1I/O 2I/O 3D26DM CS DQS DQS I/O 0I/O 1I/O 2I/O 3D25DMCSDQS DQSI/O 0I/O 1I/O 2I/O 3D27DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D28DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D29DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D30DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D32DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D31DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D33DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D35DM CS DQS DQSI/O 0I/O 1I/O 2I/O 3D34RS1Signals for Address and Command The resistors on Par_In, A13, A14, A15, BA2and the signal line of Err_Out refer to the sec-tion: "Register Options for Unused Address inputs"PAR_INErr_Out100K ohmsV SS V DDC0C1PPO QERRRegister A1PAR_INV DD V DDC0C1PPO QERRRegister B1PAR_INV SS V DDC0C1PPO QERRRegister A2PAR_INV DD V DDC0C1PPO QERRRegister B2PAR_INParity Function (M393T5166AZA)Register A1 and A2 share the a part of Add/Cmd input signal set.Register B1 and B2 share the rest part of Add/Cmd input signal set.Recommended DC Operating Conditions (SSTL - 1.8)Note : There is no specific device V DD supply voltage requirement for SSTL-1.8 compliance. However under all conditions V DDQ must be less than or equalto V DD .1. The value of V REF may be selected by the user to provide optimum noise margin in the system. Typically the value of V REF is expected to be about 0.5 x V DDQ of the transmitting device and V REF is expected to track variations in V DDQ .2. Peak to peak AC noise on V REF may not exceed +/-2% V REF (DC).3. V TT of transmitting device must track V REF of receiving device.4. AC parameters are measured with V DD , V DDQ and V DDL tied together.Symbol ParameterRatingUnits NotesMin.Typ. Max.V DD Supply Voltage 1.7 1.8 1.9V V DDL Supply Voltage for DLL 1.7 1.8 1.9V 4V DDQ Supply Voltage for Output 1.7 1.8 1.9V 4V REF Input Reference Voltage 0.49*V DDQ 0.50*V DDQ0.51*V DDQ mV 1,2V TTTermination VoltageV REF -0.04V REFV REF +0.04V3 Note :1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51-2standard.Symbol ParameterRating Units Notes V DD Voltage on V DD pin relative to V SS - 1.0 V ~ 2.3 V V 1V DDQ Voltage on V DDQ pin relative to V SS - 0.5 V ~ 2.3 V V 1V DDL Voltage on V DDL pin relative to V SS - 0.5 V ~ 2.3 V V 1V IN, V OUT Voltage on any pin relative to V SS - 0.5 V ~ 2.3 V V1T STGStorage Temperature-55 to +100°C 1, 2AC & DC Operating ConditionsAbsolute Maximum DC Ratings。

5TTP中文资料

0.492
0.64
5.25
5.81
0.79
5TT (P) 1
-R
1A
0.270
0.52
8.63
9.6
0.85
5TT (P) 1.25 -R 1.25A
0.206
0.44
13.1
14.6
0.91
5TT (P) 1.5 -R
1.5A
0.140
0.39
18.3
20.5
0.96
5TT (P) 1.6 -R
1.6A
Far East Office Bel Fuse Ltd. 8F/8 Luk Hop Street San Po Kong Kowloon, Hong Kong Tel: 852-2328-5515 Fax: 852-2352-3706
European Office Bel Fuse Europe Ltd. Preston Technology Management Centre Marsh Lane, Preston PR1 8UD Lancashire, U.K Tel: 44-1772-556601 Fax: 44-1772-888366
0.120
0.37
19.7
22.2
0.97
5TT (P) 2
-R
2A
0.080
0.32
29.9
33.7
1.03
5TT (P) 2.5 -R
2.5A
0.060
0.27
45.2
51.3
1.10
5TT (P) 3
-R
3A
0.043
0.23
55.6
63.3

中外不锈钢耐热钢和特殊合金钢牌号对照

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93 00123;!436-"91@9 53>(3< 99 95 96 0123/!435-"5 3123;!439-"5,4 0123;!439-"5,4 00123/!435-"5 *00123?!436-"5. 0123;!43>-"7 L 53?
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2294351资料

Extract from the onlinecatalogFLKMS-D25 SUB/B (1-25)Order No.: 2294351The illustration shows version FLKMS-D37 SUB/S (1-37)http://eshop.phoenixcontact.de/phoenix/treeViewClick.do?UID=2294351VARIOFACE module, with screw connection and D-Subminiaturesocket strip, for mounting on NS 35/7.5 or NS 32, 25-pos.http://Please note that the data givenhere has been taken from theonline catalog. For comprehensiveinformation and data, please referto the user documentation. TheGeneral Terms and Conditions ofUse apply to Internet downloads. Technical dataGeneral dataNominal voltage U N125 V AC/DCMax. current carrying capacity per branch 2.5 ANumber of positions25Length77 mmWidth67.5 mmHeight72 mmStatus display NoAmbient temperature (operation)-20 °C ... 50 °C Ambient temperature (storage/transport)-20 °C ... 70 °CTest voltage800 V (50 Hz, 1 min.) Mounting position AnyStandards/regulations IEC 60664DIN EN 50178IEC 62103 Pollution degree2Surge voltage category IIConnection dataConnection 1PCB connection Connection in acc. with standard IEC / ENType of connection Screw connection Conductor cross section solid min.0.2 mm2 Conductor cross section solid max. 4 mm2Conductor cross section stranded min.0.2 mm2 Conductor cross section stranded max. 2.5 mm2 Conductor cross section AWG/kcmil min.24Conductor cross section AWG/kcmil max12Stripping length8 mmScrew thread M 3Connection 2D-SUB connection Type of connection PluggableNumber of positions25Certificates / ApprovalsApproval logorequested approbationsCertification GOSTAccessoriesItem Designation DescriptionCable/conductor2302434CABLE D-SUB-S-S-S/.../.../...Shielded round cable, assembled with two D-SUB maleconnectors, variable cable length2302340CABLE D-SUB-S/.../.../...Shielded round cable, assembled with one D-SUB male and onefemale connector, variable cable length2302120CABLE-D25SUB/B/S/ 50/KONFEK/S Round shielded cable set, with 25-pos. D-SUB female and male connectors, cable length: 0.5 m2302133CABLE-D25SUB/B/S/100/KONFEK/S Round shielded cable set, with 25-pos. D-SUB female and male connectors, cable length: 1 m2302146CABLE-D25SUB/B/S/150/KONFEK/S Round shielded cable set, with 25-pos. D-SUB female and male connectors, cable length: 1.5 m2302159CABLE-D25SUB/B/S/200/KONFEK/S Round shielded cable set, with 25-pos. D-SUB female and male connectors, cable length: 2 m2302162CABLE-D25SUB/B/S/300/KONFEK/S Round shielded cable set, with 25-pos. D-SUB female and male connectors, cable length: 3 m2302175CABLE-D25SUB/B/S/400/KONFEK/S Round shielded cable set, with 25-pos. D-SUB female and male connectors, cable length: 4 m2302188CABLE-D25SUB/B/S/600/KONFEK/S Round shielded cable set, with 25-pos. D-SUB female and male connectors, cable length: 6 mDrawings Schematic diagramAddressPHOENIX CONTACT GmbH & Co. KGFlachsmarktstr. 832825 Blomberg,GermanyPhone +49 5235 3 00Fax +49 5235 3 41200http://www.phoenixcontact.de© 2008 Phoenix ContactTechnical modifications reserved;。

关于发电抽汽对生产成本影响的测算

发电车间抽汽对生产成本影响的测算2013年冬季发电车间降成本任务完成较好，现根据2013年11月份、12月份、2014年1月份、2月份和3月份运行情况，对整个采暖季抽汽成本以及影响发电的成本进行核算。

汽轮机工业抽汽的主要工艺流程为：锅炉产生的主蒸汽（9.0MPa，540℃）进入汽轮机冲动转子做功，汽轮机转子带动发电机转子做切割磁感线运动，从而产生电能。

其中一部分蒸汽在汽轮机前几级做完功后，被抽出供暖，其余蒸汽进入汽轮机后几级继续做功发电。

2013年11月份和12月份、2014年1月份、2月份和3月份运行情况如表1所示。

（一）2013年冬季抽汽成本测算现以2014年1月份为例，对发电车间抽汽成本进行测算：2014年1月份发电车间汽轮机运行情况如下：汽轮机电负荷为23.844MW/台，总抽汽量为33395t，主蒸汽用量为170378t。

1、计算原理：通过能量转换，把1t 抽汽转换成焓值相等的主蒸汽，通过1月份汽轮机运行汽耗，计算抽1t抽汽损失的发电量，从而计算1t抽汽的成本。

2、计算依据：蒸汽焓值的计算及转换。

焓值定义：蒸汽的热力学能与推动功之和，即蒸汽的有用功。

以下的蒸汽焓值是利用“FORM张学超焓值计算软件”得出。

汽轮机总抽汽量33395t，抽汽压力为0.8MPa，抽汽温度为200℃，抽汽焓值为2899.37kJ/kg；主蒸汽压力为9MPa，温度为530℃，蒸汽焓值为3462.45 kJ/kg。

因此，通过能量守恒1t抽汽可以兑换为2899.37kJ/kg÷3462.45 kJ/kg＝0.84t主蒸汽，本月产生的33395t抽汽可兑换为33395t×0.84t/t＝28051.8t主蒸汽。

1月份发电平均汽耗为170378t（1月份主蒸汽总产量）÷35479200kW.h（1月份总发电量）＝0.0048t/kW.h，将本月产生的33395t 抽汽兑换成发电量为（33395t×0.84t/t）÷0.0048t/kW.h＝5844125kW.h，由以上计算可知：1t抽汽等价于5844125kW.h÷33395t＝175kW.h/t的发电量。

五吨叉车技术数据(台励福

供应南通台励福5吨叉车，内燃引擎式，柴油/汽油•上一件•下一件商品价格：询问最新价格供货总量：5台•发货地点：江苏南通崇川区•想了解产品详情，请•和我联系•或•查看联系方式••••分享o QQ空间o新浪微薄o淘江湖o人人网o旺旺/QQ•收藏商品•详细信息•订购说明•联系方式是否提供加工定制：是额定起重量：5000（kg）类型：燃料叉车型号：FD50/FG50 货叉长度：1220（mm）载重量：5000（kg）货叉最低位：0（mm）行走方式：内燃式叉车工业车辆：内燃叉车特种行业：叉车品牌：台励福制造厂：台励福型号：FD50/FG50载荷重量：5000Kg载荷中心：600mm动力形式：柴油/汽油驾驭形式：坐式轮胎类型：充气胎车轮（x驱动轮）数量：2X/2(前/后）最大货叉高度：3000mm货叉尺寸：1220*150*60mm门架倾角（前/后）：6-12后悬：540mm叉距宽（外）：1310mm全宽：1450mm门架高度（货叉落地）：2190mm车顶护驾高：2250mm最小回转半径（外侧）：3050mm最大高度：4220mm前悬：570mm货叉架高：1220mm全车长：4530mm行驶速度：（全负荷/无负荷）：20/22km/h 上升速度：（全负荷/无负荷）：400/500mm/s 下降速度：（全负荷/无负荷）：400/400mm/s 最大牵引力（全负荷）：33203N最大爬坡能力（全负荷/空负荷）：23/19%叉车总重：6700kg轮胎数量（前/后）：2/2前轮尺寸：300-15-20P.R后轮尺寸：7.0-12-12P.R轴距：2200mm轮距（前/后）：1150/1190mm距地面高度最低点：140mm距地面高度车中心：230mm刹车操作方式：脚制动油压式刹车刹车手刹车制动方式：手制动机械式刹车发动机：潍柴4105，可选进口发动机传动系统：自动排挡系统/手动排挡系统伺服压力：160kg/cm2。

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Document Number: MC33395Rev 4.0, 2/2007Freescale Semiconductor Technical Data* This document contains certain information on a new product.Specifications and information herein are subject to change without notice.© Freescale Semiconductor, Inc., 2007. All rights reserved.Three-Phase Gate Driver ICThe 33395 simplifies the design of high-power BLDC motor control design by combining the gate drive, charge pump, current sense, and protection circuitry necessary to drive a three-phase bridge configuration of six N-channel power MOSFETs. Mode logic is incorporated to route a pulse width modulation (PWM) or acomplementary PWM output signal to either low-side or high-side•••••••••• Figure 1. 33395 Simplified Application DiagramTHREE-PHASE GATE DRIVER IC33395 33395TAnalog Integrated Circuit Device Data33395INTERNAL BLOCK DIAGRAMINTERNAL BLOCK DIAGRAMFigure 2. 33395 Simplified Internal Block DiagramLow Reset Overvoltage Osc.Charge PumpDrive Limiting Gate Drive Circuits Control Logic Shutdown CP1H CP1L CP2H CP2L CPRESVGDH GDH1GDH2GDH3SRC1SRC2SRC3GDL1GDL2GDL3VIGNPVIGN VDD+ISENS -ISENSMODE0MODE1PWM HSE1HSE2HSE3LSE1LSE2LSE3AGND PGNDLow Overvoltage ChargeDrive LimitingGate Control Overtemperature+-LHLogicDrive CircuitsShutdownVoltage ResetShutdownTESTAnalog Integrated Circuit Device Data 33395PIN CONNECTIONSPIN CONNECTIONSFigure 3. 33395 Pin ConnectionsTable 1. 33395 Pin DefinitionsA functional description of each pin can be found in the Functional Pin Description section beginning on page 9.Pin NumberPin Name Pin FunctionFormal Name Definition1CP2H Charge Pump Cap High potential pin connection for secondary charge pump capacitor 2CPRES Input Charge Pump Reserve Cap Input from external reservoir capacitor for charge pump 3VIGN Input Input Voltage Input from ignition level supply voltage for power functions4VGDH Output High-Side GateVoltage Output full-time gate drive for auxiliary high-side power MOSFET switch 5VIGNP Input Input Voltage Protected Input from protected ignition level supply for power functions 6 SRC1Sensor High-Side Sense Sense for high-side source voltage, phase 17GDH1Output Gate Drive High Output for gate high-side, phase 18GDL1Output Output for Gate Output for gate drive low-side, phase 19SRC2Sensor High-Side Sense Sense for high-side source voltage, phase 210GDH2Output Gate Drive High Output for gate high-side, phase 211 GDL2Output Output for Gate Output for gate drive low-side, phase 212 SRC3Sensor High-Side Sense Sense for high-side source voltage, phase 313GDH3Output Gate Drive High Output for gate drive high-side, phase 314GDL3Output Gate Drive Low Output for gate drive low-side, phase 315PGND Ground Power Ground Ground pins for power functions16Test N/A Test Pin This should be connected to ground or left open 17-ISENS Input IS Minus Inverting input for current limit comparator 18+ISENS Input IS Plus Non-inverting input for current limit comparator 19AGND Ground Analog Ground Ground pin for logic functions 20VDD Power Logic Supply VoltageSupply voltage for logic functions21PWMInput Pulse Width Modulator Input for pulse width modulated driver duty cycleAnalog Integrated Circuit Device Data33395PIN CONNECTIONS22MODE1 Input Mode Control Bit 1Input for mode control selection 23MODE0Input Mode Control Bit 0Input for mode control selection 24HSE3Input High-Side Enable Input for high-side enable logic, phase 3 25HSE2Input High-Side Enable Input for high-side enable logic, phase 226HSE1Input High-Side Enable Input for high-side enable logic, phase 127 LSE3Input Low-Side Enable Input for low-side enable logic, phase 328 LSE2Input Low-Side Enable Input for low-side enable logic, phase 229LSE1Input Low-Side Enable Input for low-side enable logic, phase 130CP1L Input External Pump Capacitor Input from external pump capacitor for charge pump and secondary pins 31CP1H Input External Pump Capacitor Input from external pump capacitor for charge pump and secondary pins 32CP2LInputCharge Pump CapacitorInput from external reservoir, external pump capacitors for charge pump, and secondary pinsTable 1. 33395 Pin Definitions (continued)A functional description of each pin can be found in the Functional Pin Description section beginning on page 9.Pin NumberPin Name Pin FunctionFormal Name DefinitionAnalog Integrated Circuit Device Data 33395ELECTRICAL CHARACTERISTICSMAXIMUM RATINGSELECTRICAL CHARACTERISTICSMAXIMUM RATINGSTable 2. Maximum RatingsAll voltages are with respect to ground unless otherwise noted.RatingSymbol Value Unit VIGN Supply Voltage V IGN -15.5 to 40VDC VIGNP Load Dump SurvivalV IGNPLD-0.3 to 65VDC VDD Logic Supply Voltage (Fail Safe)V DD -0.3 to 7.0VDC Logic Input Voltage (LSEn, HSEn, PWM, and MODEn)V IN 0.3 to 7.0VDC Start Up Current V IGNP I VIGNSTARTUP100mA ESD Voltage (1)Human Body Model Machine Model V ESD1V ESD2±500±200VStorage TemperatureT STG -65 to 160°C Operating Ambient Temperature T A -40 to 125°C Operating Case Temperature T C -40 to 125°C Maximum Junction Temperature T J 150°C Power Dissipation (T A = 25°C)P D 1.5W Peak Package Reflow Temperature During Reflow (2), (3)T PPRT Note 3°C Thermal Resistance, Junction-to-AmbientR ΘJA65°C/ WNotes1.ESD1 testing is performed in accordance with the Human Body Model (C ZAP = 100 pF, R ZAP = 1500 Ω), ESD2 testing is performed inaccordance with the Machine Model (C ZAP = 200 pF, R ZAP = 0 Ω).2.Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause malfunction or permanent damage to the device.3.Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow Temperature and Moisture Sensitivity Levels (MSL),Go to , search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.Analog Integrated Circuit Device Data33395ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSTable 3. Static Electrical CharacteristicsCharacteristics noted under conditions -40°C ≤ T A ≤ 125°C, 5.5 V ≤ V IGNP ≤ 24 V unless otherwise noted. Typical values reflect approximate parameter mean at T A = 25°C under normal conditions unless otherwise noted.CharacteristicSymbol Min Typ Max UnitPOWER INPUTV IGN Current @ 5.5 V – 24 V, V DD = 5.5 V I IGN –0.2 1.0mA V IGNP Current @ 5.5 V – 24 V, V DD = 5.5 V I IGNP ––100mA V IGNP Overvoltage Shutdown V IGNP SD253336.5V V IGNP VoltageV IGNP5.5–24V V DD Current @ 5.5 VDC, 5.5 V ≤ V IGNP ≤ 24 V IV DD– 1.8 4.0mA V DD Low-Voltage Reset Level V DD(RESET)2.53.24.0V V DD One-Time Fuse (Logic Supply)–7.0––VINPUT / O UTPUTInput Current at V DD = 5.5 VLSEn, HSEn, PWM, and MODEn = 3.0 V I IN5.01225µAInput Threshold at V DD = 5.5 V LSEn, HSEn, PWM, and MODEn (4)V TH1.02.03.0V V SCRn Source Sense Voltage SRC1, SRC2, SRC3V SCRn-0.3V IGNP 24VComparator Input Offset Voltage V INP(OFFSET) 5.01420mV Comparator Input Bias Current V INP(BIAS)-500-170500nA Comparator Input Offset Current I INP(OFFSET)-300-3.0300nA Common Mode Voltage (5)V CMR 0–V DD - 2.0V DC Comparator Differential Input Voltage (5)V INPdiff -V DD–+V DDV Charge Pump Voltage V IGN (6)V IGNP = 5.5 V, I C RES = 1.0 mA V IGNP = 9.0 V, I C RES = 1.0 mA V IGNP = 12 V, I C RES = 5.0 mA V IGNP = 24 V, I C RES = 1.0 mA V IGNP = 24 V, I C RES = 5.0 mAV CRES - V IGNP4.04.04.58.04.56.07.51016121818181818VV GDH Output Voltage with GDHn in ON State V IGNP = 5.5 V, I GDHn = 1.0 mA V IGNP = 12 V, I GDHn = 5.0 mA V IGNP = 24 V, I GDHn = 5.0 mAV GDHn(on ) - V SRCn4.04.04.55.29.011181818VV GDH Output Voltage with GDHn in OFF State V IGNP = SRCn = 14 V, I GDHn = 1.0 mAV GDHn(off )-1.00.61.0VNotes4.Logic inputs LSEn, HSEn, PWM, and MODEn have internal 20 µA internal sinks.5.Guaranteed by design and characterization. Not production tested.6.The Charge Pump has a positive temperature coefficient. Therefore the Min’s occur at -40°C, Typ’s at 25°C, and Max’s at 125°C.Analog Integrated Circuit Device Data 33395ELECTRICAL CHARACTERISTICSSTATIC ELECTRICAL CHARACTERISTICSINPUT / O UTPUT (CONTINUED)V GDL Low-Side Output Voltage GDHn in ON State V IGNP = 5.5 V, I GDLn = 1.0 mA V IGNP = 12 V, I GDLn = 5.0 mA V IGNP = 24 V, I GDLn = 0.0 mA V IGNP = 24 V, I GDLn = 5.0 mA V GDL(on )5.08.08.08.08.014171618181919VV GDL Output Voltage GDHn in OFF State V IGNP = 14 V, I GDLn = 1.0 mA V GDL(off)-1.00.3 1.0V Thermal Shutdown (7)T LIM 160–190°CNotes7.Guaranteed by design and characterization. Not production tested.Table 3. Static Electrical Characteristics (continued)Characteristics noted under conditions -40°C ≤ T A ≤ 125°C, 5.5 V ≤ V IGNP ≤ 24 V unless otherwise noted. Typical values reflect approximate parameter mean at T A = 25°C under normal conditions unless otherwise noted.CharacteristicSymbolMinTypMaxUnitAnalog Integrated Circuit Device Data33395ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSDYNAMIC ELECTRICAL CHARACTERISTICSTIMING DIAGRAMFigure 4. Shoot-Through SuppressionTable 4. Dynamic Electrical CharacteristicsCharacteristics noted under conditions -40°C ≤ T A ≤ 125°C, 5.5 V ≤ V IGNP ≤ 24 V unless otherwise noted. Typical values reflect approximate parameter mean at T A = 25°C under normal conditions unless otherwise noted.CharacteristicSymbol MinTypMaxUnit High-Side (GDHn) and Low-Side Drivers (GDHn) Rise Time (25% to 75%), C ISS Value = 2000 pF (8)t R H–0.351.5µsHigh-Side (GDHn) and Low-Side Drivers (GDHn) Fall Time (75% to 25%), C ISS Value = 2000 pF (8)t FH–0.251.5µsShoot-Through Suppression Time Delay (33395) (8), (9)3339533395Tt D1, t D21.00.2 3.00.65 5.51.0µsCurrent Limit Time Delay (10)t I LIMDELAY 1.52.85.0µsNotes8.See Figure 4, page 8.9.Shoot-Through Suppression Time Delay is provided to prevent directly connected high- and low-side MOSFETs from being onsimultaneously.10.Current Limit Time Delay: The internal comparator places the device in the current limit mode when the comparator output goes LOWand sets an internal logic bit. This takes a finite amount of time and is stated as the Current Limit Time Delay.1007525010075250t RH t FHt FLt RLTIMEG D L n , G a t e V (%)G D H n S R C n (%)t D2t D1Analog Integrated Circuit Device Data 33395FUNCTIONAL DESCRIPTIONINTRODUCTIONFUNCTIONAL DESCRIPTIONINTRODUCTIONThe 33395 and 33395T devices are designed to provide the necessary drive and control signal buffering and amplification to enable a DSP or MCU to control a three-phase array of power MOSFETs such as would be required to energize the windings of powerful brushless DC (BLDC)motors. It contains built-in charge pump circuitry so that the MOSFET array may consist entirely of N-ChannelMOSFETs. It also contains feedback sensing circuitry and control circuitry to provide a robust overall motor control design.FUNCTIONAL PIN DESCRIPTIONCHARGE PUMP CAPACITOR (CP2H)High potential pin connection for secondary charge pump capacitorCHARGE PUMP RESERVE CAPACITOR (CPRES)Input from external reservoir capacitor for charge pumpINPUT VOLTAGE (VIGN)Input from ignition level supply voltage for power functionsHIGH-SIDE GATE VOLTAGE (VGDH)Output full-time gate drive for auxiliary high-side power MOSFET switchINPUT VOLTAGE PROTECTED (VIGNP)Input from protected ignition level supply for power functionsHIGH-SIDE SENSE (SRC1, SRC2, SRC3)Sense for high-side source voltage, phase 1/2/3GATE DRIVE HIGH (GDH1, GDH2, GDH3)Output for gate high-side, phase 1/2/3OUTPUT FOR GATE (GDL1, GDL2, GDL3)Output for gate drive low-side, phase 1POWER GROUND (PGND)Ground pins for power functionsTEST PIN (TEST)This should be connected to ground or left openIS MINUS (-ISENS)Inverting input for current limit comparatorIS PLUS (+ISENS)Non-Inverting input for current limit comparatorANALOG GROUND (AGND)Ground pin for logic functionsLOGIC SUPPLY VOLTAGE (VDD)Supply voltage for logic functionsPULSE WIDTH MODULATOR (PWM)Input for pulse width modulated driver duty cycleMODE CONTROL BIT 1 (MODE1)Input for mode control selectionMODE CONTROL BIT 0 (MODE0)Input for mode control selectionHIGH-SIDE ENABLE (HSE3, HSE2, HSE1)Input for high-side enable logic, phase 1/2/3LOW-SIDE ENABLE (LSE3, LSE2, LSE1)Input for low-side enable logic, phase 1/2/3EXTERNAL PUMP CAPACITOR (CP1L, CP1H)Input from external pump capacitor for charge pump and secondary pinsCHARGE PUMP CAPACITOR (CP2L)Input from external reservoir, external pump capacitors for charge pump, and secondary pinsAnalog Integrated Circuit Device Data33395FUNCTIONAL DESCRIPTIONFUNCTIONAL INTERNAL BLOCK DESCRIPTIONFUNCTIONAL INTERNAL BLOCK DESCRIPTIONGATE DRIVE CIRCUITSThe gate drive outputs (GDH1, GDH2, etc.) supply the peak currents required to turn ON and hold ON theMOSFETs, as well as turn OFF and hold OFF the MOSFETs.CHARGE PUMPThe current capability of the charge pump is sufficient to supply the gate drive circuit’s demands when PWMing at up to 28 kHz. Two external charge pump capacitors and a reservoir capacitor are required to complete the charge pump’s circuitry.Charge reservoir capacitance is a function of the total MOSFET gate charge (Q G ) gate drive voltage level relative to the source (V GS ) and the allowable sag of the drive level during the turn-on interval (V SAG ). C RES can be expressed by the following formula:For example, for Q G = 60 nC, V GS = 14 V, V SAG = 0.2 V:Proper charge pump capacitance is required to maintain, and provide for, adequate gate drive during high demand turn-ON intervals. Use the following formula to determine values for C P1 and C P2:For example, for the above determination of C RES = 0.15 µF:By averaging these two values, the proper C P n value can be determined:C P1 and C P2 =(0.0075 µF + 0.015 µF) ÷ 2 = 0.01 µFTHERMAL SHUTDOWN FUNCTIONThe device has internal temperature sensing circuitry which activates a protective shutdown function should the die reach excessively elevated temperatures. This function effectively limits power dissipation and thus protects the device.OVERVOLTAGE SHUTDOWN FUNCTIONWhen the supply voltage (V IGN ) exceeds the specified over- voltage shutdown level, the part will automatically shut down to protect both internal circuits as well as the load. Operation will resume upon return of V IGN to normal operating levels.LOW VOLTAGE RESET FUNCTIONWhen the logic supply voltage (V DD ) drops below the minimum voltage level or when the part is initially powered up, this function will turn OFF and hold OFF the external MOSFETs until the voltage increases above the minimum voltage level required for normal operation.CONTROL LOGICThe control logic block controls when the low-side and high-side drivers are enabled. The logic implements the Truth Table found in the specification and monitors the M0, M1, PWM, CL, OT, OV, LSE, and HSE pins. Note that the drivers are enabled 3 µs after the PWM edge. During complimentary chop mode the high-side and low-side drives are alternatively enabled and disabled during the PWM cycle. To prevent shoot-through current, the high-side drive turn-on is delayed by t D1, and the low-side drive turn on is delayed by t D2 (see Figure 4, page 8).Note that the drivers are disabled during anovertemperature or overvoltage fault. A flip-flop keeps the drive off until the following PWM cycle. This prevents erratic operation during fault conditions. The current limit circuit also uses a flip-flop for latching the drive off until the following PWM cycle.Note PWM must be toggled after POR, Thermal Limit, or overvoltage faults to re-enable the gate drivers.VGDHThe VGDH pin is used to provide a gate drive signal to areverse battery protection MOSFET. If reverse batteryprotection is desired, V IGN would be applied to the source of an external MOSFET, and the drain of the MOSFET would then deliver a "protected" supply voltage (V IGNP ) to the three phase array of external MOSFETs as well as the supply voltage to the V IGNP pin of the IC.In a reverse polarity event (e.g., an erroneous installation of the system battery), the V GDH signal will not be supplied to the external protection MOSFET, and the MOSFET will remain off and thus prevent reverse polarity from being applied to the load and the VIGNP supply pin of the IC.HIGH-SIDE GATE DRIVE CIRCUITSOutputs GDH1, GDH2, and GDH3 provide the elevated drive voltage to the high-side external MOSFETs (HS1, HS2, and HS3; see Figure 5, page 13). These gate drive outputs supply the peak currents required to turn ON and hold ON the high-side MOSFETs, as well as turn OFF the MOSFETs. These gate drive circuits are powered from an internal charge pump, and therefore compensate for voltage dropped across the load that is reflected to the source-gate circuits of the high-side MOSFETs.LOW-SIDE GATE DRIVE CIRCUITSOutputs GDL1, GDL2, and GDL3 provide the drive voltage to the low-side external MOSFETs (LS1, LS2, and LS3; seeC RES =Q G x V GS2 x V GS x V SAG - V SAG 2C RES =(60 nC) x (14 V)2 x (14 V) x (0.2 V) - (0.2)= 0.15 µFC RES20< C P1 = C P2 <10C RES0.15 µF 20= 0.075 µF, lower limit; and100.15 µF = .015 µF, upper limAnalog Integrated Circuit Device Data 33395FUNCTIONAL DESCRIPTIONFUNCTIONAL INTERNAL BLOCK DESCRIPTIONFigure 5). These gate drive outputs supply the peak currents required to turn ON and hold ON the low-side MOSFETs, as well as turn OFF the MOSFETs.V DD FUSEThe V DD supply of the 33395 IC has an internal fuse, which will blow and set all outputs of the device to OFF, if the V DD voltage exceeds that stated in the maximum rating section of the data sheet. When this fuse blows, the device is permanently disabled.I SENS INPUTSThe +I sens and -I sens pins are inputs to the internalcurrent sense comparator. In a typical application, these would receive a a low-pass filtered voltage derived from a current sense resistor placed in series with the ground return of the three-phase output bridge. When triggered by the comparator, the CL (current limit) bit of the internal error register is set, and the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3), are controlled such that current will cease flowing through the load (refer to Table 5, Truth Table, page 12).OVERTEMPERATURE AND OVERVOLTAGE SHUTDOWN CIRCUITSInternal monitoring is provided for both over temperature conditions and over voltage conditions. When any of these conditions presents itself to the IC, the correspondinginternally set bits of the error register are set, and the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3), are controlled such that current will cease flowing through the load (refer to Table 5).LSE AND HSE INPUT CIRCUITSThe low-side enable input pins (LSE1, LSE2, LSE3) and high-side enable input pins (HSE1, HSE2, HSE3) form the input pairs (HSE1 and LSE1, HSE2 and LSE2, HSE3 and LSE3) which set the logic states of the output gate drive pairs (i.e., GDH1 and GDL1, GDH2 and GDL2, GDH3 and GDL3) in accordance with the logic set forth in the Truth Table(page 12). Typically these inputs are supplied from an MCU or DSP to provide the phasing of the currents applied to a brushless dc motor's stator coils via the output MOSFET pairs.PWM INPUTThe pulse width modulation input provides a single input pin to accomplish PWM modulation of the output pairs in accordance with the states of the Mode 0 and Mode 1 inputs as set forth in the Truth Table (page 12).MODE SELECTION INPUTSThe mode selection inputs (Mode 0 and Mode 1)determine the PWM implementation of the output pairs in accordance with the logic set forth in the Truth Table(page 12). PWMing can thus be set to occur either on the high-side MOSFETs or the low-side MOSFETs, or can be setto occur on both the high-side and low-side MOSFETs as "complementary chopping".TEST PINThis pin should be grounded or left floating (i.e., do not connect it to the printed circuit board). It is used by the automated test equipment to verify proper operation of the internal overtemperature shut down circuitry. This pin is susceptible to latch-up and therefore may cause erroneous operation or device failure if connected to external circuitry.Analog Integrated Circuit Device Data33395FUNCTIONAL DEVICE OPERATION OPERATIONAL MODESFUNCTIONAL DEVICE OPERATIONOPERATIONAL MODESTable 5. Truth TableThe logic state of each output pair, GDLn and GDHn (n = 1, 2, 3), is a function of its corresponding input pair, LSEn and HSEn (n = 1, 2, 3), along with the logic states of the MODEn and PWM inputs and the internally set overtemperature shutdown (OT), overvoltage (OV), and current limit (CL) bits provided in this table.NORMAL OPERATIONSwitching Modes Internally Set Bits Input Pairs(e.g., LSE2 and HSE2)Output Pairs(e.g., GDL2 and GDH2)MODE1MODE0OT OV CL LSEn HSEn GDLn GDHn 0000000000000001010000010PWM 00000011000100000000100001010100010PWM PWM 01000110010000000010000010PWM 1000010101000011001100000001100001PWM PWM 1100010101111FAULT MODE OPERATIONSwitching Modes Internally Set Bits Input Pairs(e.g., LSE2 and HSE2)Output Pairs(e.g., GDL2 and GDH2)MODE1MODE0OT OV CL LSEn HSEn GDLn GDHn 000010000000010101000011000000011100010010000010010101010011001010011100100010000100010100100011010100011100110010000110010110110011010110011100x x x 1x x x 00xx 1xxxxAnalog Integrated Circuit Device Data 33395TYPICAL APPLICATIONS OPERATIONAL MODESTYPICAL APPLICATIONSFigure 5. Typical Application DiagramLSE3LSE2LSE1CP1LCP1H CP2L HSE2HSE1AGND VDD PWM MODE1MODE0HSE3-ISENS+ISENS SRC1VIGNPVGDH VIGN CPRES CP2H GDL1GDH1GDL3GDH3SRC3GDL2GDH2SRC2TESTPGND 6543218714131211109161527282930313225261920212223241718 MCU+-T O M O T O RLS3LS2LS1HS1HS2HS3R S E N S E5.0V 12V++Analog Integrated Circuit Device Data33395PACKAGINGPACKAGE DIMENSIONSPACKAGINGPACKAGE DIMENSIONSFor the most current package revision, visit and perform a keyword search using the 98ARH99137A listed below.DWB SUFFIXEW SUFFIX (PB-FREE)32-PINPLASTIC PACKAGE 98ARH99137A ISSUE ANOTES:1.ALL DIMENSIONS ARE IN MILLIMETERS.2.DIMENSIONING AND TOLERANCING PER ASMEY14.5M, 1994.3.DATUMS B AND C TO BE DETERMINED AT THEPLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY .4.THIS DIMENSION DOES NOT INCLUDE MOLDFLASH, PROTRUSION OR GATE BURRS. MOLD FLASH, PROTRUSION OR GATE BURRS SHALL NOT EXCEED 0.15 MM PER SIDE. THISDIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY .5.THIS DIMENSION DOES NOT INCLUDEINTERLEAD FLASH OR PROTRUSIONS.INTERLEAD FLASH AND PROTRUSIONS SHALL NOT EXCEED 0.25 MM PER SIDE. THISDIMENSION IS DETERMINED AT THE PLANE WHERE THE BOTTOM OF THE LEADS EXIT THE PLASTIC BODY .6.THIS DIMENSION DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.4 MM PER SIDE. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEENPROTRUSION AND ADJACENT LEAD SHALL NOT LESS THAN 0.07 MM.7.EXACT SHAPE OF EACH CORNER IS OPTIONAL.8.THESE DIMENSIONS APPLY TO THE FLATSECTION OF THE LEAD BETWEEN 0.10 MM AND 0.3 MM FROM THE LEAD TIP .9.THE PACKAGE TOP MAY BE SMALLER THAN THEPACKAGE BOTTOM. THIS DIMENSION ISDETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTER-LEAD FLASH, BUT INCLUDING ANYMISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY .C L10.97.411617320.10A2.35SEATINGPLANE0.9SECTION B-B0.65R0.08 MIN B APIN 1 IDSECTION A-A ROTATED 90 CLOCKWISE °8950.13MC AMBAC 7.611.19410.35.15A32X30X2.650.3A 2X 16 TIPSB CB0.290.130.50°8°0°0.25GAUGE PLANEMINAnalog Integrated Circuit Device Data 33395REVISION HISTORYREVISION HISTORYREVISIONDATE DESCRIPTION OF CHANGES 3.07/2005•Implemented Revision History page •Converted to Freescale format •Added Pin Definitions4.02/2007•Updated Freescale data sheet form and style•Added MCZ33395EW/R2 to the Ordering Information block•Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter and added notes (2) and (3) to Maximum Ratings on page 5MC33395Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. 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