Laboratory_03_for_AC-DC_Converter[1]
MPLAB Code Configurator X2C Scope 库版本 2.0.0 发布说明书
Release Notes for MPLAB® Code ConfiguratorX2Cscope Library v2.0.01What is MPLAB Code Configurator X2C Scope LibraryX2CScope is a lightweight firmware-based debugging tool, and it is running on the target MCU parallelto the application. It is a runtime online debugging tool that works in RUN and DEBUGGING mode. X2CScopeis for generic use in any application and perfectly fits motor control applications.For more information, please visit https://x2cscope.github.io/2System Requirements1.MPLAB X 6.00 (or higher)2.XC16 1.50 (or higher)3.XC32 2.10 (or higher)4.MCC5.1.0 (or higher)5.MCC X2C Library v2.0.03Installing MPLAB® Code Configurator X2Cscope LibraryBasic steps for installing MPLAB® Code Configurator needs to be installed as below.To install the MPLAB® Code Configurator v5.1.0 or later Plugin1.In the MPLAB® X IDE, select Plugins from the Tools menu2.Select the Available Plugins tab3.Check the box for the MPLAB® Code Configurator v4, and click on InstallTo install and load different library version when connected to internet1.Open MPLAB® Code Configurator2.In the Versions tab under PIC24\dsPIC33\PIC32MM MCUs or X2Cscope will find the multiplelibrary version (loaded version is indicated by the green dot)3.Right Click on the required version of the library as specified in System Requirements and select Markfor load4.Click on Load Selected Libraries button to load the libraryTo install the X2Cscope Library when not connected to internet1.In the MPLAB® X IDE, select Options from the Tools menu2.Select Plugins tab3.Click on Install Library4.Add the required version(s) of the library as specified in the System Requirements.4What’s New•Migrated X2C Scope library to MCC version 5.1.0•X2C Scope library support in MCC melody.5Supported DevicesThe X2Cscope library supports the following device families.1.dsPIC33EP512GP506 (/dsPIC33EP512GP506)2.dsPIC33EV256GM106(/dsPIC33EV256GM106)3.dsPIC33EV256GM006(/dsPIC33EV256GM006)4.dsPIC33EP128GS806 (/dsPIC33EP128GS806)5.dsPIC33EP64GS506 (/dsPIC33EP64GS506)6.dsPIC33EP512GM710(/dsPIC33EP512GM710)7.dsPIC33CH128MP508 anddsPIC33CH128MP508S1(/dsPIC33CH128MP508)8.dsPIC33CK256MP508 (/dsPIC33CK256MP508)9.dsPIC33CH512MP508 anddsPIC33CH512MP508S1(https:///dsPIC33CH512MP508)10.dsPIC33CK64MP105(https:///dsPIC33CK64MP105)6 Device Support List☑ : The X2Cscope is supported for the device.7 Customer Support7.1 Microchip Web SiteMicrochip provides online support via our web site at . This web site is used to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information:•Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software •General Technical Support – Frequently Asked Questions (FAQs), technical support requests, online discussion groups/forums (), Microchip consultant program member listing •Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors, and factory representatives8.2Additional SupportUsers of Microchip products can receive assistance through several channels:•Distributor or Representative•Local Sales Office•Field Application Engineering (FAE)•Technical SupportCustomers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is available on our web site.Technical support is available through the web site at: 。
Silicon Laboratories C8051F380 1 2 3 4 5 6 7 C USB
-10 位 ADC(仅 C8051F380/1/2/3/C)•高达 500ksps•内建模拟多路复用器,单端和差分模式•VREF 来自外部引脚、内部参考或 V DD•内建温度传感器•外部转换启动输入选项-两个比较器-内部参考电压(仅 C8051F380/1/2/3/C)-掉电检测器和上电复位电路USB 功能控制器-符合 USB 规格 2.0-全速 (12Mbps) 或低速 (1.5Mbps) 运行-集成时钟恢复;全速或低速无需外部晶体-支持八个灵活的终端-1kB USB 缓冲存储器-集成收发器;无需外部电阻片上调试-片上调试电路提供全速、非侵入式的系统内调试(无需仿真器)-提供断点、单步执行、检查/修改内存和寄存器-比使用 ICE 芯片、目标仿真头和仿真插座的仿真系统有更优越的性能电源电压输入: 2.7 至 5.25V-使用片内稳压器时,支持的电压范围为 2.7~5.25V -流水线指令体系结构;70% 指令的执行时间为 1 个或2个系统时钟-高达 48 MIPS 的操作-扩展的中断处理程序内存-4352 或 2304字节 RAM-64、32 或 16kB 闪存;可在系统内编程的 512 字节扇区数字外围设备-40/25 个端口 I/O;全部能承受 5V 高灌电流-硬件增强型SPI™、两个 I2C/SMBus™ 和两个增强型UART 串口-六个通用 16 位计数器/定时器-16 位可编程计数器阵列 (PCA),有五个采集/比较模块-外部存储器接口 (EMIF)时钟源-内部振荡器:启用时钟恢复时精度为 ±0.25%。
支持所有USB 和 UART 模式-外部振荡器:晶体、RC、C 或时钟(1 或 2 引脚模式)-低频 (80kHz) 内部振荡器-在运行中可切换时钟源封装-48 引脚 TQFP (C8051F380/2/4/6)-32 引脚 LQFP (C8051F381/3/5/7/C)-5x5mm 32 引脚 QFN (C8051F381/3/5/7/C)温度范围: –40 至 +85°CC8051F380/1/2/3/4/5/6/7/CC8051F380/1/2/3/4/5/6/7/CTable of Contents1. System Overview (16)2. C8051F34x Compatibility (20)2.1. Hardware Incompatibilities (21)3. Pinout and Package Definitions (22)4. Typical Connection Diagrams (34)4.1. Power (34)4.2. USB (36)4.3. Voltage Reference (VREF) (36)5. Electrical Characteristics (37)5.1. Absolute Maximum Specifications (37)5.2. Electrical Characteristics (38)6. 10-Bit ADC (ADC0, C8051F380/1/2/3/C only) (46)6.1. Output Code Formatting (47)6.3. Modes of Operation (50)6.3.1. Starting a Conversion (50)6.3.2. Tracking Modes (51)6.3.3. Settling Time Requirements (52)6.4. Programmable Window Detector (56)6.4.1. Window Detector Example (58)6.5. ADC0 Analog Multiplexer (C8051F380/1/2/3/C only) (59)7. Voltage Reference Options (62)8. Comparator0 and Comparator1 (64)8.1. Comparator Multiplexers (71)9. Voltage Regulators (REG0 and REG1) (74)9.1. Voltage Regulator (REG0) (74)9.1.1. Regulator Mode Selection (74)9.1.2. VBUS Detection (74)9.2. Voltage Regulator (REG1) (74)10. Power Management Modes (76)10.1. Idle Mode (76)10.2. Stop Mode (77)10.3. Suspend Mode (77)11. CIP-51 Microcontroller (79)11.1. Instruction Set (80)11.1.1. Instruction and CPU Timing (80)11.2. CIP-51 Register Descriptions (85)12. Prefetch Engine (88)13. Memory Organization (89)13.1. Program Memory (91)13.2. Data Memory (91)13.3. General Purpose Registers (92)13.4. Bit Addressable Locations (92)13.5. Stack (92)C8051F380/1/2/3/4/5/6/7/C14. External Data Memory Interface and On-Chip XRAM (93)14.1. Accessing XRAM (93)14.1.1. 16-Bit MOVX Example (93)14.1.2. 8-Bit MOVX Example (93)14.2. Accessing USB FIFO Space (94)14.3. Configuring the External Memory Interface (95)14.4. Port Configuration (95)14.5. Multiplexed and Non-multiplexed Selection (98)14.5.1. Multiplexed Configuration (98)14.5.2. Non-multiplexed Configuration (98)14.6. Memory Mode Selection (100)14.6.1. Internal XRAM Only (100)14.6.2. Split Mode without Bank Select (100)14.6.3. Split Mode with Bank Select (101)14.6.4. External Only (101)14.7. Timing (102)14.7.1. Non-multiplexed Mode (104)14.7.1.1. 16-bit MOVX: EMI0CF[4:2] = 101, 110, or 111 (104)14.7.1.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 101 or 111 (105)14.7.1.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 110 (106)14.7.2. Multiplexed Mode (107)14.7.2.1. 16-bit MOVX: EMI0CF[4:2] = 001, 010, or 011 (107)14.7.2.2. 8-bit MOVX without Bank Select: EMI0CF[4:2] = 001 or 011 (108)14.7.2.3. 8-bit MOVX with Bank Select: EMI0CF[4:2] = 010 (109)15. Special Function Registers (111)15.1. 13.1. SFR Paging (111)16. Interrupts (118)16.1. MCU Interrupt Sources and Vectors (119)16.1.1. Interrupt Priorities (119)16.1.2. Interrupt Latency (119)16.2. Interrupt Register Descriptions (119)16.3. INT0 and INT1 External Interrupt Sources (127)17. Reset Sources (129)17.1. Power-On Reset (130)17.2. Power-Fail Reset / VDD Monitor (131)17.3. External Reset (132)17.4. Missing Clock Detector Reset (132)17.5. Comparator0 Reset (132)17.6. PCA Watchdog Timer Reset (133)17.7. Flash Error Reset (133)17.8. Software Reset (133)17.9. USB Reset (133)18. Flash Memory (135)18.1. Programming The Flash Memory (135)18.1.1. Flash Lock and Key Functions (135)C8051F380/1/2/3/4/5/6/7/C18.1.2. Flash Erase Procedure (135)18.1.3. Flash Write Procedure (136)18.2. Non-Volatile Data Storage (137)18.3. Security Options (137)19. Oscillators and Clock Selection (142)19.1. System Clock Selection (143)19.2. USB Clock Selection (143)19.3. Programmable Internal High-Frequency (H-F) Oscillator (145)19.3.1. Internal Oscillator Suspend Mode (145)19.4. Clock Multiplier (147)19.5. Programmable Internal Low-Frequency (L-F) Oscillator (148)19.5.1. Calibrating the Internal L-F Oscillator (148)19.6. External Oscillator Drive Circuit (149)19.6.1. External Crystal Mode (149)19.6.2. External RC Example (151)19.6.3. External Capacitor Example (151)20. Port Input/Output (153)20.1. Priority Crossbar Decoder (154)20.2. Port I/O Initialization (158)20.3. General Purpose Port I/O (161)21. Universal Serial Bus Controller (USB0) (172)21.1. Endpoint Addressing (172)21.2. USB Transceiver (173)21.3. USB Register Access (175)21.4. USB Clock Configuration (179)21.5. FIFO Management (181)21.5.1. FIFO Split Mode (181)21.5.2. FIFO Double Buffering (182)21.5.1. FIFO Access (182)21.6. Function Addressing (183)21.7. Function Configuration and Control (183)21.8. Interrupts (186)21.9. The Serial Interface Engine (193)21.10. Endpoint0 (193)21.10.1. Endpoint0 SETUP Transactions (193)21.10.2. Endpoint0 IN Transactions (193)21.10.3. Endpoint0 OUT Transactions (194)21.11. Configuring Endpoints1-3 (196)21.12. Controlling Endpoints1-3 IN (197)21.12.1. Endpoints1-3 IN Interrupt or Bulk Mode (197)21.12.2. Endpoints1-3 IN Isochronous Mode (198)21.13. Controlling Endpoints1-3 OUT (201)21.13.1. Endpoints1-3 OUT Interrupt or Bulk Mode (201)21.13.2. Endpoints1-3 OUT Isochronous Mode (201)22. SMBus0 and SMBus1 (I2C Compatible) (205)C8051F380/1/2/3/4/5/6/7/C22.1. Supporting Documents (206)22.2. SMBus Configuration (206)22.3. SMBus Operation (206)22.3.1. Transmitter Vs. Receiver (207)22.3.2. Arbitration (207)22.3.3. Clock Low Extension (207)22.3.4. SCL Low Timeout (207)22.3.5. SCL High (SMBus Free) Timeout (208)22.4. Using the SMBus (208)22.4.1. SMBus Configuration Register (208)22.4.2. SMBus Timing Control Register (210)22.4.3. SMBnCN Control Register (214)22.4.3.1. Software ACK Generation (214)22.4.3.2. Hardware ACK Generation (214)22.4.4. Hardware Slave Address Recognition (217)22.4.5. Data Register (221)22.5. SMBus Transfer Modes (223)22.5.1. Write Sequence (Master) (223)22.5.2. Read Sequence (Master) (224)22.5.3. Write Sequence (Slave) (225)22.5.4. Read Sequence (Slave) (226)22.6. SMBus Status Decoding (226)23. UART0 (232)23.1. Enhanced Baud Rate Generation (233)23.2. Operational Modes (234)23.2.1. 8-Bit UART (234)23.2.2. 9-Bit UART (235)23.3. Multiprocessor Communications (236)24. UART1 (240)24.1. Baud Rate Generator (241)24.2. Data Format (242)24.3. Configuration and Operation (243)24.3.1. Data Transmission (243)24.3.2. Data Reception (243)24.3.3. Multiprocessor Communications (244)25. Enhanced Serial Peripheral Interface (SPI0) (250)25.1. Signal Descriptions (251)25.1.1. Master Out, Slave In (MOSI) (251)25.1.2. Master In, Slave Out (MISO) (251)25.1.3. Serial Clock (SCK) (251)25.1.4. Slave Select (NSS) (251)25.2. SPI0 Master Mode Operation (251)25.3. SPI0 Slave Mode Operation (253)25.4. SPI0 Interrupt Sources (254)25.5. Serial Clock Phase and Polarity (254)25.6. SPI Special Function Registers (256)26. Timers (263)26.1. Timer 0 and Timer 1 (266)26.1.1. Mode 0: 13-bit Counter/Timer (266)26.1.2. Mode 1: 16-bit Counter/Timer (267)26.1.3. Mode 2: 8-bit Counter/Timer with Auto-Reload (267)26.1.4. Mode 3: Two 8-bit Counter/Timers (Timer 0 Only) (268)26.2. Timer 2 (274)26.2.1. 16-bit Timer with Auto-Reload (274)26.2.2. 8-bit Timers with Auto-Reload (275)26.2.3. Timer 2 Capture Modes: USB Start-of-Frame or LFO Falling Edge (275)26.3. Timer 3 (281)26.3.1. 16-bit Timer with Auto-Reload (281)26.3.2. 8-bit Timers with Auto-Reload (282)26.3.3. Timer 3 Capture Modes: USB Start-of-Frame or LFO Falling Edge (282)26.4. Timer 4 (288)26.4.1. 16-bit Timer with Auto-Reload (288)26.4.2. 8-bit Timers with Auto-Reload (289)26.5. Timer 5 (293)26.5.1. 16-bit Timer with Auto-Reload (293)26.5.2. 8-bit Timers with Auto-Reload (294)27. Programmable Counter Array (298)27.1. PCA Counter/Timer (299)27.2. PCA0 Interrupt Sources (300)27.3. Capture/Compare Modules (301)27.3.1. Edge-triggered Capture Mode (302)27.3.2. Software Timer (Compare) Mode (303)27.3.3. High-Speed Output Mode (304)27.3.4. Frequency Output Mode (305)27.3.5. 8-bit Pulse Width Modulator Mode (306)27.3.6. 16-Bit Pulse Width Modulator Mode (307)27.4. Watchdog Timer Mode (308)27.4.1. Watchdog Timer Operation (308)27.4.2. Watchdog Timer Usage (309)27.5. Register Descriptions for PCA0 (311)28. C2 Interface (316)28.1. C2 Interface Registers (316)28.2. C2 Pin Sharing (319)Document Change List (320)Contact Information (321)List of FiguresFigure1.1. C8051F380/2/4/6 Block Diagram (18)Figure1.2. C8051F381/3/5/7/C Block Diagram (19)Figure3.1. TQFP-48 Pinout Diagram (Top View) (25)Figure3.2. TQFP-48 Package Diagram (26)Figure3.3. TQFP-48 Recommended PCB Land Pattern (27)Figure3.4. LQFP-32 Pinout Diagram (Top View) (28)Figure3.5. LQFP-32 Package Diagram (29)Figure3.6. LQFP-32 Recommended PCB Land Pattern (30)Figure3.7. QFN-32 Pinout Diagram (Top View) (31)Figure3.8. QFN-32 Package Drawing (32)Figure3.9. QFN-32 Recommended PCB Land Pattern (33)Figure4.1. Connection Diagram with Voltage Regulator Used and No USB (34)Figure4.2. Connection Diagram with Voltage Regulator Not Used and No USB (34)Figure4.3. Connection Diagram with Voltage Regulator Used and USB Connected (Bus-Powered) (35)Figure4.4. Connection Diagram with Voltage Regulator Used and USB Connected (Self-Powered) (35)Figure4.5. Connection Diagram for USB Pins (36)Figure4.6. Connection Diagram for Internal Voltage Reference (36)Figure6.1. ADC0 Functional Block Diagram (46)Figure6.2. Typical Temperature Sensor Transfer Function (48)Figure6.3. Temperature Sensor Error with 1-Point Calibration (49)Figure6.4. 10-Bit ADC Track and Conversion Example Timing (51)Figure6.5. ADC0 Equivalent Input Circuits (52)Figure6.6. ADC Window Compare Example: Right-Justified Data (58)Figure6.7. ADC Window Compare Example: Left-Justified Data (58)Figure7.1. Voltage Reference Functional Block Diagram (62)Figure8.1. Comparator0 Functional Block Diagram (64)Figure8.2. Comparator1 Functional Block Diagram (65)Figure8.3. Comparator Hysteresis Plot (66)Figure8.4. Comparator Input Multiplexer Block Diagram (71)Figure11.1. CIP-51 Block Diagram (79)Figure13.1. On-Chip Memory Map for 64kB Devices (C8051F380/1/4/5) (89)Figure13.2. On-Chip Memory Map for 32kB Devices (C8051F382/3/6/7) (90)Figure13.3. On-Chip Memory Map for 16kB Devices (C8051F38C) (91)Figure14.1. USB FIFO Space and XRAM Memory Map with USBFAE set to ‘1’ (94)Figure14.2. Multiplexed Configuration Example (98)Figure14.3. Non-multiplexed Configuration Example (99)Figure14.4. EMIF Operating Modes (100)Figure14.5. Non-Multiplexed 16-bit MOVX Timing (104)Figure14.6. Non-multiplexed 8-bit MOVX without Bank Select Timing (105)Figure14.7. Non-multiplexed 8-bit MOVX with Bank Select Timing (106)Figure14.8. Multiplexed 16-bit MOVX Timing (107)C8051F380/1/2/3/4/5/6/7/CFigure14.9. Multiplexed 8-bit MOVX without Bank Select Timing (108)Figure14.10. Multiplexed 8-bit MOVX with Bank Select Timing (109)Figure17.1. Reset Sources (129)Figure17.2. Power-On and VDD Monitor Reset Timing (130)Figure18.1. Flash Program Memory Map and Security Byte (137)Figure19.1. Oscillator Options (142)Figure19.2. External Crystal Example (150)Figure20.1. Port I/O Functional Block Diagram (Port 0 through Port 3) (153)Figure20.2. Port I/O Cell Block Diagram (154)Figure20.3. Peripheral Availability on Port I/O Pins (155)Figure20.4. Crossbar Priority Decoder in Example Configuration(No Pins Skipped) (156)Figure20.5. Crossbar Priority Decoder in Example Configuration (3 Pins Skipped) (157)Figure21.1. USB0 Block Diagram (172)Figure21.2. USB0 Register Access Scheme (175)Figure21.3. USB FIFO Allocation (181)Figure22.1. SMBus Block Diagram (205)Figure22.2. Typical SMBus Configuration (206)Figure22.3. SMBus Transaction (207)Figure22.4. Typical SMBus SCL Generation (209)Figure22.5. Typical Master Write Sequence (223)Figure22.6. Typical Master Read Sequence (224)Figure22.7. Typical Slave Write Sequence (225)Figure22.8. Typical Slave Read Sequence (226)Figure23.1. UART0 Block Diagram (232)Figure23.2. UART0 Baud Rate Logic (233)Figure23.3. UART Interconnect Diagram (234)Figure23.4. 8-Bit UART Timing Diagram (234)Figure23.5. 9-Bit UART Timing Diagram (235)Figure23.6. UART Multi-Processor Mode Interconnect Diagram (236)Figure24.1. UART1 Block Diagram (240)Figure24.2. UART1 Timing Without Parity or Extra Bit (242)Figure24.3. UART1 Timing With Parity (242)Figure24.4. UART1 Timing With Extra Bit (242)Figure24.5. Typical UART Interconnect Diagram (243)Figure24.6. UART Multi-Processor Mode Interconnect Diagram (244)Figure25.1. SPI Block Diagram (250)Figure25.2. Multiple-Master Mode Connection Diagram (252)Figure25.3. 3-Wire Single Master and 3-Wire Single Slave Mode Connection Diagram (252)Figure25.4. 4-Wire Single Master Mode and 4-Wire Slave Mode Connection Diagram (253)Figure25.5. Master Mode Data/Clock Timing (255)Figure25.6. Slave Mode Data/Clock Timing (CKPHA = 0) (255)C8051F380/1/2/3/4/5/6/7/C Figure25.7. Slave Mode Data/Clock Timing (CKPHA = 1) (256)Figure25.8. SPI Master Timing (CKPHA = 0) (260)Figure25.9. SPI Master Timing (CKPHA = 1) (260)Figure25.10. SPI Slave Timing (CKPHA = 0) (261)Figure25.11. SPI Slave Timing (CKPHA = 1) (261)Figure26.1. T0 Mode 0 Block Diagram (267)Figure26.2. T0 Mode 2 Block Diagram (268)Figure26.3. T0 Mode 3 Block Diagram (269)Figure26.4. Timer 2 16-Bit Mode Block Diagram (274)Figure26.5. Timer 2 8-Bit Mode Block Diagram (275)Figure26.6. Timer2 Capture Mode (T2SPLIT = 0) (276)Figure26.7. Timer2 Capture Mode (T2SPLIT = 0) (277)Figure26.8. Timer 3 16-Bit Mode Block Diagram (281)Figure26.9. Timer 3 8-Bit Mode Block Diagram (282)Figure26.10. Timer3 Capture Mode (T3SPLIT = 0) (283)Figure26.11. Timer3 Capture Mode (T3SPLIT = 0) (284)Figure26.12. Timer 4 16-Bit Mode Block Diagram (288)Figure26.13. Timer 4 8-Bit Mode Block Diagram (289)Figure26.14. Timer 5 16-Bit Mode Block Diagram (293)Figure26.15. Timer 5 8-Bit Mode Block Diagram (294)Figure27.1. PCA Block Diagram (298)Figure27.2. PCA Counter/Timer Block Diagram (299)Figure27.3. PCA Interrupt Block Diagram (300)Figure27.4. PCA Capture Mode Diagram (302)Figure27.5. PCA Software Timer Mode Diagram (303)Figure27.6. PCA High-Speed Output Mode Diagram (304)Figure27.7. PCA Frequency Output Mode (305)Figure27.8. PCA 8-Bit PWM Mode Diagram (306)Figure27.9. PCA 16-Bit PWM Mode (307)Figure27.10. PCA Module 4 with Watchdog Timer Enabled (308)Figure28.1. Typical C2 Pin Sharing (319)List of TablesTable1.1. Product Selection Guide (17)Table2.1. C8051F38x Replacement Part Numbers (20)Table3.1. Pin Definitions for the C8051F380/1/2/3/4/5/6/7/C (22)Table3.2. TQFP-48 Package Dimensions (26)Table3.3. TQFP-48 PCB Land Pattern Dimensions (27)Table3.4. LQFP-32 Package Dimensions (29)Table3.5. LQFP-32 PCB Land Pattern Dimensions (30)Table3.6. QFN-32 Package Dimensions (32)Table3.7. QFN-32 PCB Land Pattern Dimensions (33)Table5.1. Absolute Maximum Ratings (37)Table5.2. Global Electrical Characteristics (38)Table5.3. Port I/O DC Electrical Characteristics (39)Table5.4. Reset Electrical Characteristics (39)Table5.5. Internal Voltage Regulator Electrical Characteristics (40)Table5.6. Flash Electrical Characteristics (40)Table5.7. Internal High-Frequency Oscillator Electrical Characteristics (41)Table5.8. Internal Low-Frequency Oscillator Electrical Characteristics (41)Table5.9. External Oscillator Electrical Characteristics (41)Table5.10. ADC0 Electrical Characteristics (42)Table5.11. Temperature Sensor Electrical Characteristics (43)Table5.12. Voltage Reference Electrical Characteristics (43)Table5.13. Comparator Electrical Characteristics (44)Table5.14. USB Transceiver Electrical Characteristics (45)Table11.1. CIP-51 Instruction Set Summary (81)Table14.1. AC Parameters for External Memory Interface (110)Table15.1. Special Function Register (SFR) Memory Map (112)Table15.2. Special Function Registers (113)Table16.1. Interrupt Summary (120)Table21.1. Endpoint Addressing Scheme (173)Table21.2. USB0 Controller Registers (178)Table21.3. FIFO Configurations (182)Table22.1. SMBus Clock Source Selection (209)Table22.2. Minimum SDA Setup and Hold Times (210)Table22.3. Sources for Hardware Changes to SMBnCN (217)Table22.4. Hardware Address Recognition Examples (EHACK = 1) (218)Table22.5. SMBus Status Decoding: Hardware ACK Disabled (EHACK = 0) (227)Table22.6. SMBus Status Decoding: Hardware ACK Enabled (EHACK = 1) (229)Table23.1. Timer Settings for Standard Baud Rates Using Internal Oscillator (238)Table24.1. Baud Rate Generator Settings for Standard Baud Rates (241)Table25.1. SPI Slave Timing Parameters (262)Table27.1. PCA Timebase Input Options (299)Table27.2. PCA0CPM Bit Settings for PCA Capture/Compare Modules (301)Table27.3. Watchdog Timer Timeout Intervals1 (310)List of RegistersSFR Definition6.1. ADC0CF: ADC0 Configuration (53)SFR Definition6.2. ADC0H: ADC0 Data Word MSB (54)SFR Definition6.3. ADC0L: ADC0 Data Word LSB (54)SFR Definition6.4. ADC0CN: ADC0 Control (55)SFR Definition6.5. ADC0GTH: ADC0 Greater-Than Data High Byte (56)SFR Definition6.6. ADC0GTL: ADC0 Greater-Than Data Low Byte (56)SFR Definition6.7. ADC0LTH: ADC0 Less-Than Data High Byte (57)SFR Definition6.8. ADC0LTL: ADC0 Less-Than Data Low Byte (57)SFR Definition6.9. AMX0P: AMUX0 Positive Channel Select (60)SFR Definition6.10. AMX0N: AMUX0 Negative Channel Select (61)SFR Definition7.1. REF0CN: Reference Control (63)SFR Definition8.1. CPT0CN: Comparator0 Control (67)SFR Definition8.2. CPT0MD: Comparator0 Mode Selection (68)SFR Definition8.3. CPT1CN: Comparator1 Control (69)SFR Definition8.4. CPT1MD: Comparator1 Mode Selection (70)SFR Definition8.5. CPT0MX: Comparator0 MUX Selection (72)SFR Definition8.6. CPT1MX: Comparator1 MUX Selection (73)SFR Definition9.1. REG01CN: Voltage Regulator Control (75)SFR Definition10.1. PCON: Power Control (78)SFR Definition11.1. DPL: Data Pointer Low Byte (85)SFR Definition11.2. DPH: Data Pointer High Byte (85)SFR Definition11.3. SP: Stack Pointer (86)SFR Definition11.4. ACC: Accumulator (86)SFR Definition11.5. B: B Register (86)SFR Definition11.6. PSW: Program Status Word (87)SFR Definition12.1. PFE0CN: Prefetch Engine Control (88)SFR Definition14.1. EMI0CN: External Memory Interface Control (96)SFR Definition14.2. EMI0CF: External Memory Interface Configuration (97)SFR Definition14.3. EMI0TC: External Memory TIming Control (103)SFR Definition15.1. SFRPAGE: SFR Page (111)SFR Definition16.1. IE: Interrupt Enable (121)SFR Definition16.2. IP: Interrupt Priority (122)SFR Definition16.3. EIE1: Extended Interrupt Enable 1 (123)SFR Definition16.4. EIP1: Extended Interrupt Priority 1 (124)SFR Definition16.5. EIE2: Extended Interrupt Enable 2 (125)SFR Definition16.6. EIP2: Extended Interrupt Priority 2 (126)SFR Definition16.7. IT01CF: INT0/INT1 ConfigurationO (128)SFR Definition17.1. VDM0CN: VDD Monitor Control (132)SFR Definition17.2. RSTSRC: Reset Source (134)SFR Definition18.1. PSCTL: Program Store R/W Control (139)SFR Definition18.2. FLKEY: Flash Lock and Key (140)SFR Definition18.3. FLSCL: Flash Scale (141)SFR Definition19.1. CLKSEL: Clock Select (144)C8051F380/1/2/3/4/5/6/7/CSFR Definition19.2. OSCICL: Internal H-F Oscillator Calibration (145)SFR Definition19.3. OSCICN: Internal H-F Oscillator Control (146)SFR Definition19.4. CLKMUL: Clock Multiplier Control (147)SFR Definition19.5. OSCLCN: Internal L-F Oscillator Control (148)SFR Definition19.6. OSCXCN: External Oscillator Control (152)SFR Definition20.1. XBR0: Port I/O Crossbar Register 0 (159)SFR Definition20.2. XBR1: Port I/O Crossbar Register 1 (160)SFR Definition20.3. XBR2: Port I/O Crossbar Register 2 (161)SFR Definition20.4. P0: Port 0 (162)SFR Definition20.5. P0MDIN: Port 0 Input Mode (162)SFR Definition20.6. P0MDOUT: Port 0 Output Mode (163)SFR Definition20.7. P0SKIP: Port 0 Skip (163)SFR Definition20.8. P1: Port 1 (164)SFR Definition20.9. P1MDIN: Port 1 Input Mode (164)SFR Definition20.10. P1MDOUT: Port 1 Output Mode (165)SFR Definition20.11. P1SKIP: Port 1 Skip (165)SFR Definition20.12. P2: Port 2 (166)SFR Definition20.13. P2MDIN: Port 2 Input Mode (166)SFR Definition20.14. P2MDOUT: Port 2 Output Mode (167)SFR Definition20.15. P2SKIP: Port 2 Skip (167)SFR Definition20.16. P3: Port 3 (168)SFR Definition20.17. P3MDIN: Port 3 Input Mode (168)SFR Definition20.18. P3MDOUT: Port 3 Output Mode (169)SFR Definition20.19. P3SKIP: Port 3 Skip (169)SFR Definition20.20. P4: Port 4 (170)SFR Definition20.21. P4MDIN: Port 4 Input Mode (170)SFR Definition20.22. P4MDOUT: Port 4 Output Mode (171)SFR Definition21.1. USB0XCN: USB0 Transceiver Control (174)SFR Definition21.2. USB0ADR: USB0 Indirect Address (176)SFR Definition21.3. USB0DAT: USB0 Data (177)USB Register Definition21.4. INDEX: USB0 Endpoint Index (179)USB Register Definition21.5. CLKREC: Clock Recovery Control (180)USB Register Definition21.6. FIFOn: USB0 Endpoint FIFO Access (182)USB Register Definition21.7. FADDR: USB0 Function Address (183)USB Register Definition21.8. POWER: USB0 Power (185)USB Register Definition21.9. FRAMEL: USB0 Frame Number Low (186)USB Register Definition21.10. FRAMEH: USB0 Frame Number High (186)USB Register Definition21.11. IN1INT: USB0 IN Endpoint Interrupt (187)USB Register Definition21.12. OUT1INT: USB0 OUT Endpoint Interrupt (188)USB Register Definition21.13. CMINT: USB0 Common Interrupt (189)USB Register Definition21.14. IN1IE: USB0 IN Endpoint Interrupt Enable (190)USB Register Definition21.15. OUT1IE: USB0 OUT Endpoint Interrupt Enable (191)USB Register Definition21.16. CMIE: USB0 Common Interrupt Enable (192)USB Register Definition21.17. E0CSR: USB0 Endpoint0 Control (195)USB Register Definition21.18. E0CNT: USB0 Endpoint0 Data Count (196)C8051F380/1/2/3/4/5/6/7/C USB Register Definition21.19. EENABLE: USB0 Endpoint Enable (197)USB Register Definition21.20. EINCSRL: USB0 IN Endpoint Control Low (199)USB Register Definition21.21. EINCSRH: USB0 IN Endpoint Control High (200)USB Register Definition21.22. EOUTCSRL: USB0 OUT Endpoint Control Low Byte 202 USB Register Definition21.23. EOUTCSRH: USB0 OUT Endpoint Control High Byte (203)USB Register Definition21.24. EOUTCNTL: USB0 OUT Endpoint Count Low (203)USB Register Definition21.25. EOUTCNTH: USB0 OUT Endpoint Count High (204)SFR Definition22.1. SMB0CF: SMBus Clock/Configuration (211)SFR Definition22.2. SMB1CF: SMBus Clock/Configuration (212)SFR Definition22.3. SMBTC: SMBus Timing Control (213)SFR Definition22.4. SMB0CN: SMBus Control (215)SFR Definition22.5. SMB1CN: SMBus Control (216)SFR Definition22.6. SMB0ADR: SMBus0 Slave Address (218)SFR Definition22.7. SMB0ADM: SMBus0 Slave Address Mask (219)SFR Definition22.8. SMB1ADR: SMBus1 Slave Address (219)SFR Definition22.9. SMB1ADM: SMBus1 Slave Address Mask (220)SFR Definition22.10. SMB0DAT: SMBus Data (221)SFR Definition22.11. SMB1DAT: SMBus Data (222)SFR Definition23.1. SCON0: Serial Port 0 Control (237)SFR Definition23.2. SBUF0: Serial (UART0) Port Data Buffer (238)SFR Definition24.1. SCON1: UART1 Control (245)SFR Definition24.2. SMOD1: UART1 Mode (246)SFR Definition24.3. SBUF1: UART1 Data Buffer (247)SFR Definition24.4. SBCON1: UART1 Baud Rate Generator Control (248)SFR Definition24.5. SBRLH1: UART1 Baud Rate Generator High Byte (248)SFR Definition24.6. SBRLL1: UART1 Baud Rate Generator Low Byte (249)SFR Definition25.1. SPI0CFG: SPI0 Configuration (257)SFR Definition25.2. SPI0CN: SPI0 Control (258)SFR Definition25.3. SPI0CKR: SPI0 Clock Rate (259)SFR Definition25.4. SPI0DAT: SPI0 Data (259)SFR Definition26.1. CKCON: Clock Control (264)SFR Definition26.2. CKCON1: Clock Control 1 (265)SFR Definition26.3. TCON: Timer Control (270)SFR Definition26.4. TMOD: Timer Mode (271)SFR Definition26.5. TL0: Timer 0 Low Byte (272)SFR Definition26.6. TL1: Timer 1 Low Byte (272)SFR Definition26.7. TH0: Timer 0 High Byte (273)SFR Definition26.8. TH1: Timer 1 High Byte (273)SFR Definition26.9. TMR2CN: Timer 2 Control (278)SFR Definition26.10. TMR2RLL: Timer 2 Reload Register Low Byte (279)SFR Definition26.11. TMR2RLH: Timer 2 Reload Register High Byte (279)SFR Definition26.12. TMR2L: Timer 2 Low Byte (279)SFR Definition26.13. TMR2H Timer 2 High Byte (280)SFR Definition26.14. TMR3CN: Timer 3 Control (285)C8051F380/1/2/3/4/5/6/7/CSFR Definition26.15. TMR3RLL: Timer 3 Reload Register Low Byte (286)SFR Definition26.16. TMR3RLH: Timer 3 Reload Register High Byte (286)SFR Definition26.17. TMR3L: Timer 3 Low Byte (286)SFR Definition26.18. TMR3H Timer 3 High Byte (287)SFR Definition26.19. TMR4CN: Timer 4 Control (290)SFR Definition26.20. TMR4RLL: Timer 4 Reload Register Low Byte (291)SFR Definition26.21. TMR4RLH: Timer 4 Reload Register High Byte (291)SFR Definition26.22. TMR4L: Timer 4 Low Byte (291)SFR Definition26.23. TMR4H Timer 4 High Byte (292)SFR Definition26.24. TMR5CN: Timer 5 Control (295)SFR Definition26.25. TMR5RLL: Timer 5 Reload Register Low Byte (296)SFR Definition26.26. TMR5RLH: Timer 5 Reload Register High Byte (296)SFR Definition26.27. TMR5L: Timer 5 Low Byte (296)SFR Definition26.28. TMR5H Timer 5 High Byte (297)SFR Definition27.1. PCA0CN: PCA Control (311)SFR Definition27.2. PCA0MD: PCA Mode (312)SFR Definition27.3. PCA0CPMn: PCA Capture/Compare Mode (313)SFR Definition27.4. PCA0L: PCA Counter/Timer Low Byte (314)SFR Definition27.5. PCA0H: PCA Counter/Timer High Byte (314)SFR Definition27.6. PCA0CPLn: PCA Capture Module Low Byte (315)SFR Definition27.7. PCA0CPHn: PCA Capture Module High Byte (315)C2 Register Definition28.1. C2ADD: C2 Address (316)C2 Register Definition28.2. DEVICEID: C2 Device ID (317)C2 Register Definition28.3. REVID: C2 Revision ID (317)C2 Register Definition28.4. FPCTL: C2 Flash Programming Control (318)C2 Register Definition28.5. FPDAT: C2 Flash Programming Data (318)。
关于MAX6675的说明书
General DescriptionThe MAX6675 performs cold-junction compensation and digitizes the signal from a type-K thermocouple. The data is output in a 12-bit resolution, SPI-compatible, read-only format.This converter resolves temperatures to 0.25°C, allows readings as high as +1024°C, and exhibits thermocouple accuracy of 8 LSBs for temperatures ranging from 0°C to +700°C.The MAX6675 is available in a small, 8-pin SO package.Applications●Industrial ●Appliances ●HVACFeatures●Direct Digital Conversion of Type -K ThermocoupleOutput ●Cold-Junction Compensation●Simple SPI-Compatible Serial Interface ●12-Bit, 0.25°C Resolution ●Open Thermocouple DetectionPART TEMP RANGE PIN-PACKAGE MAX6675ISA-20°C to +85°C8 SOMAX6675Cold-Junction-Compensated K-Thermocouple-to-Digital Converter (0°C to +1024°C)19-2235; Rev 3; 6/21Ordering InformationEVALUATION KIT AVAILABLEClick here to ask about the production status of specific part numbers.Supply Voltage (V CC to GND) ............................... -0.3V to +6V SO, SCK, CS , T-, T+ to GND .....................-0.3V to V CC + 0.3V SO Current ....................................................................... 50mA ESD Protection (Human Body Model) .......................... ±2000V Continuous Power Dissipation (T A = +70°C)8-Pin SO (derate 5.88mW/°C above +70°C) ............. 471mW Operating Temperature Range ..........................-20°C to +85°CStorage Temperature Range ...........................-65°C to +150°C Junction Temperature .................................................... +150°C SO PackageVapor Phase (60s) . .....................................................+215°C Infrared (15s) ..............................................................+220°C Lead Temperature (soldering, 10s) ............................... +300°C(V CC = +3.0V to +5.5V, T A = -20°C to +85°C, unless otherwise noted. Typical values specified at +25°C.) (Note 1)PARAMETERSYMBOLCONDITIONSMINTYP MAX UNITSTemperature ErrorT THERMOCOUPLE = +700°C,T A = +25°C (Note 2)V CC = +3.3V -5+5LSBV CC = +5V -6+6T THERMOCOUPLE = 0°C to +700°C, T A = +25°C (Note 2)V CC = +3.3V -8+8V CC = +5V -9+9T THERMOCOUPLE = +700°Cto +1000°C, T A = +25°C (Note 2)V CC = +3.3V -17+17V CC = +5V-19+19Thermocouple Conversion Constant10.25µV/LSB Cold-JunctionCompensation Error T A = -20°C t o +85°C (Note 2)V CC = +3.3V -3.0+3.0°C V CC= +5V-3.0+3.0Resolution0.25°C Thermocouple Input Impedance 60k W Supply Voltage V CC 3.05.5V Supply CurrentI CC0.7 1.5mA Power-On Reset Threshold V CC rising12 2.5V Power-On Reset Hysteresis 50mV Conversion Time (Note 2)0.170.22sSERIAL INTERFACE Input Low Voltage V IL 0.3 x V CCV Input High Voltage V IH 0.7 x V CCV Input Leakage Current I LEAK V IN = GND or V CC±5µA Input CapacitanceC IN5pFto-Digital Converter (0°C to +1024°C)Electrical CharacteristicsStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.Absolute Maximum RatingsNote 1: All specifications are 100% tested at T A = +25°C. Specification limits over temperature (T A = T MIN to T MAX ) are guaranteedby design and characterization, not production tested.Note 2: Guaranteed by design. Not production tested.(V CC = +3.3V, T A = +25°C, unless otherwise noted.)(V CC = +3.0V to +5.5V, T A = -20°C to +85°C, unless otherwise noted. Typical values specified at +25°C.) (Note 1)PARAMETERSYMBOL CONDITIONSMIN TYPMAXUNITS Output High Voltage V OH I SOURCE = 1.6mA V CC - 0.4V Output Low Voltage V OLI SINK = 1.6mA0.4VTIMINGSerial Clock Frequency f SCL 4.3MHz SCK Pulse High Width t CH 100ns SCK Pulse Low Width t C L 100ns CSB Fall to SCK Rise t CSS C L = 10pF 100ns CSB Fall to Output Enable t DV C L = 10pF 100ns CSB Rise to Output Disable t TR C L = 10pF 100ns SCK Fall to Output Data Validt DOC L = 10pF100ns-50510-103050OUTPUT CODE ERROR vs. VOLTAGE DIFFERENTIALM A X 6675 t o c 02VOLTAGE DIFFERENTIAL (mV)O U T P U T C O D E E R R O R (L S B )1020401086420451530607590OUTPUT CODE ERROR vs. AMBIENT TEMPERATUREM A X 6675 t o c 01TEMPERATURE (°C)O U T P U T C O D E E R R O R (L S B )to-Digital Converter (0°C to +1024°C)Typical Operating CharacteristicsElectrical Characteristics (continued)Detailed DescriptionThe MAX6675 is a sophisticated thermocouple-to-digi- tal converter with a built-in 12-bit analog-to-digital con-verter (ADC). The MAX6675 also contains cold-junction compensation sensing and correction, a digital con- troller, an SPI-compatible interface, and associated control logic.The MAX6675 is designed to work in conjunction with an external microcontroller (µC) or other intelligence in ther-mostatic, process-control, or monitoring applications. Temperature ConversionThe MAX6675 includes signal-conditioning hardware to convert the thermocouple’s signal into a voltage compat-ible with the input channels of the ADC. The T+and T- inputs connect to internal circuitry that reduces the intro- duction of noise errors from the thermocouple wires. Before converting the thermoelectric voltages into equivalent temperature values, it is necessary to com-pensate for the difference between the thermocouple cold-junction side (MAX6675 ambient temperature) and a 0°C virtual reference. For a type-K thermocouple, the voltage changes by 41µV/°C, which approximates the thermocouple characteristic with the following linear equation:V OUT = (41µV / °C) x (T R - T AMB)Where:V OUT is the thermocouple output voltage (µV).T R is the temperature of the remote thermocouple junc-tion (°C).T AMB is the ambient temperature (°C).Cold-Junction CompensationThe function of the thermocouple is to sense a differ- ence in temperature between two ends of the thermo- couple wires. The thermocouple’s hot junction can be read from 0°C to +1023.75°C. The cold end (ambi-ent temperature of the board on which the MAX6675 is mounted) can only range from -20°C to +85°C. While the temperature at the cold end fluctuates, the MAX6675 continues to accurately sense the tempera- ture difference at the opposite end.The MAX6675 senses and corrects for the changes in the ambient temperature with cold-junction compen-sation. The device converts the ambient temperature reading into a voltage using a temperature-sensing diode. To make the actual thermocouple temperature measurement, the MAX6675 measures the voltage from the thermocouple’s output and from the sensing diode. The device’s internal circuitry passes the diode’s volt- age (sensing ambient temperature) and thermocouple voltage (sensing remote temperature minus ambient temperature) to the conversion function stored in the ADC to calculate the thermocouple’s hot-junction tem-perature.Optimal performance from the MAX6675 is achieved when the thermocouple cold junction and the MAX6675 are at the same temperature. Avoid placing heat-gen-erating devices or components near the MAX6675 because this may produce cold-junction-related errors. DigitizationThe ADC adds the cold-junction diode measurement with the amplified thermocouple voltage and reads out the 12-bit result onto the SO pin. A sequence of all zeros means the thermocouple reading is 0°C. A sequence of all ones means the thermocouple reading is +1023.75°C.PIN NAME FUNCTION1GND Ground2T-Alumel Lead of Type-K Thermocouple.Should be connected to ground externally. 3T+Chromel Lead of Type-K Thermocouple4V CC Positive Supply. Bypass with a 0.1µFcapacitor to GND.5SCK Serial Clock Input6CS Chip Select. Set CS low to enable the serialinterface.7SO Serial Data Output8N.C.No Connection to-Digital Converter (0°C to +1024°C)Pin DescriptionApplications InformationSerial InterfaceThe T ypical Application Circuit shows the MAX6675 interfaced with a microcontroller. In this example, the MAX6675 processes the reading from the thermocou- ple and transmits the data through a serial interface. Force CS low and apply a clock signal at SCK to read the results at SO. Forcing CS low immediately stops any conversion process. Initiate a new conversion process by forcing CS high.Force CS low to output the first bit on the SO pin. A complete serial interface read requires 16 clock cycles. Read the 16 output bits on the falling edge of the clock. The first bit, D15, is a dummy sign bit and is always zero. Bits D14–D3 contain the converted temperature in the order of MSB to LSB. Bit D2 is normally low and goes high when the thermocouple input is open. D1 is low to provide a device ID for the MAX6675 and bit D0 is three-state.Figure 1a is the serial interface protocol and Figure 1b shows the serial interface timing. Figure 2 is the SO out-put.Open ThermocoupleBit D2 is normally low and goes high if the thermocou- ple input is open. In order to allow the operation of the open thermocouple detector, T- must be grounded. Make the ground connection as close to the GND pin as possible.Noise ConsiderationsThe accuracy of the MAX6675 is susceptible to power- supply coupled noise. The effects of power-supply noise can be minimized by placing a 0.1µF ceramic bypass capacitor close to the supply pin of the device.Thermal ConsiderationsSelf-heating degrades the temperature measurement accuracy of the MAX6675 in some applications. The magnitude of the temperature errors depends on the thermal conductivity of the MAX6675 package, the mounting technique, and the effects of airflow. Use a large ground plane to improve the temperature mea- surement accuracy of the MAX6675.The accuracy of a thermocouple system can also be improved by following these precautions:●Use the largest wire possible that does not shuntheat away from the measurement area.●If small wire is required, use it only in the region ofthe measurement and use extension wire for theregion with no temperature gradient.●Avoid mechanical stress and vibration, which couldstrain the wires.●When using long thermocouple wires, use a twisted-pair extension wire.●Avoid steep temperature gradients.●Try to use the thermocouple wire well within its tem-perature rating.●Use the proper sheathing material in hostile environ-ments to protect the thermocouple wire.●Use extension wire only at low temperatures andonly in regions of small gradients.●Keep an event log and a continuous record of ther-mocouple resistance.Reducing Effects of Pick-Up NoiseThe input amplifier (A1) is a low-noise amplifier designed to enable high-precision input sensing. Keep the thermocouple and connecting wires away from elec-trical noise sources.to-Digital Converter (0°C to +1024°C)Figure 2. SO OutputFigure 1b. Serial Interface TimingFigure 1a. Serial Interface ProtocolBIT DUMMY SIGN BIT12-BITTEMPERATURE READING THERMOCOUPLEINPUTDEVICE IDSTATE Bit15141312111098765432100MSBLSBThree-stateCSSCKSOD15D14D13D12D11D10D9D8D7D6D5D4D3D2D1D0to-Digital Converter (0°C to +1024°C)PACKAGE TYPEPACKAGE CODE OUTLINE ND PATTERN NO.8 SOS8+221-004190-0096to-Digital Converter (0°C to +1024°C)Package InformationFor the latest package outline information and land patterns (footprints), go to /packages . Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.Chip InformationTRANSISTOR COUNT: 6720PROCESS: BiCMOSREVISION NUMBERREVISION DATE DESCRIPTIONPAGES CHANGED24/14Removed automotive reference136/21Updated equation in Temperature Compensation section.4Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.to-Digital Converter (0°C to +1024°C)Revision HistoryFor pricing, delivery, and ordering information, please visit Maxim Integrated’s online storefront at https:///en/storefront/storefront.html.。
FullProf 详细使用教程
New facilities concerning symmetry in FullProf
⇒ The symmetry used within FullProf is totally based in the Crystallographic Fortran 95 Modules Library (CrysFML) (Tuesday 26 ⇒ FA3-MS5, Meeting Room 11B) ⇒ These modules provide better crystallographic information to the user of the program. In particular automatic calculation of the multiplicity of each site is now performed after reading the atoms as well as the calculation of the appropriate coefficients for automatic quantitative analysis of mixture of phases. ⇒ New output files with full information of crystallographic symmetry are produced (extension: sym)
Durban, August 24, 2003
ECM-21 Software Workshop
Last minute changes in FullProf Documented in “fp2k.inf”
LD05-20BxxMU系列AC DC转换器用户说明书
5W, AC/DC converterRoHSFEATURES● Universal input: 85~264V AC/100~370VDC● AC and DC dual-use (input from the same terminal) ● High efficiency, high power density● Output short-circuit, over-current, over-voltage protection ● EN60601-1, ANSI/AAMI ES60601-1 approval (3rd edition 2xMOPP)LD05-20BxxMU series is a compact size power converter. It features universal input voltage, taking both DC and AC input voltage, low power consumption, high efficiency, high reliability, safer isolation. It offers good EMC performance, and is widely used in medical, industrial and instrumentation applications.Selection GuideRS Stock No. Part No. Output PowerNominal Output V oltageand Current (V o/Io)Efficiency (230V AC, %/Typ.)Max. Capacitive Load*(µF)1446281 LD05-20B05MU 5W 5V/1000mA 76 4000 1446282 LD05-20B12MU 12V/420mA 80 820 1446283 LD05-20B24MU5.5W24V/230mA81330Note: *Test without external circuit.Input SpecificationsItemOperating Conditions Min. Typ. Max. Unit Input V oltage Range AC input 85 -- 264 V AC DC input 100 -- 370 VDC Input frequency 47 -- 63 HzInput current115V AC -- -- 0.12 A 230V AC -- -- 0.07 Inrush current 115V AC -- 10 -- 230V AC -- 20 -- Leakage Current264V AC ----80uA Recommended external input fuse2A/250V , slow blowOutput SpecificationsItemOperating Conditions Min. Typ. Max. UnitOutput V oltage Accuracy-- ±2 -- % Line Regulation Full load -- ±0.5 -- Load Regulation 10%-100% load-- ±1 -- Ripple & Noise* 20MHz bandwidth (peak-peak value)-- 50 100 mV Temperature Coefficient -- ±0.02 -- %/℃ Stand-by Power Consumption----0.3W Short Circuit Protection Continuous, self-recovery Over-current Protection110 - 280% Io self-recoveryOver-voltage Protection LD05-20B05MU -- -- 7.5 VLD05-20B12MU -- -- 16 LD05-20B24MU-- -- 30 Min. Load0 -- -- % Hold-up Time115V AC input -- 10 -- ms 230V AC input --80--General SpecificationsItem Operating Conditions Min. Typ. Max. Unit Isolation V oltage Input-output Test time: 1min 4000 -- -- V AC Operating Temperature -25 -- +70℃Storage Temperature -40 -- +85Max. Casing Temperature -- -- +95Storage Humidity -- -- 95 %RHWelding Temperature Wave-soldering 260±5℃; time:5~10s Manual-welding 360±10℃; time:3~5sSwitching Frequency -- -- 140 kHzPower Derating -25 ~ 0℃ 1 -- -- %/℃+55 ~ +70℃ 2 -- -- %/℃Safety Standard EN60601/UL60601Safety Certification EN60601/UL60601Safety Class CLASS IIinsulation Level Primary to Secondary2xMOPPMTBF MIL-HDBK-217F@25℃ >300,000 h Physical SpecificationsCasing Material Black flame-retardant and heat-resistant plastic (UL94-V0)Package Dimensions 53.80*28.80*19.00 mmWeight 43g (Typ.)Cooling method Free air convectionEMC SpecificationsEMI CE CISPR11/EN55011 CLASS B RE CISPR11/EN55011 CLASS BEMS ESD IEC/EN61000-4-2 Contact±6KV/Air±8KV Perf. Criteria B RS IEC/EN61000-4-3 10V/m perf. Criteria AEFTIEC/EN61000-4-4 ±2KV perf. Criteria BIEC/EN61000-4-4 ±4KV (See Fig. 2 for recommended circuit) perf. Criteria B SurgeIEC/EN61000-4-5 ±1KV perf. Criteria BIEC/EN61000-4-5 ±2KV/±4KV (See Fig. 2 for recommended circuit) perf. Criteria B CS IEC/EN61000-4-6 10 Vr.m.s perf. Criteria A PFM IEC/EN61000-4-8 10A/m perf. Criteria A V oltage dips, short interruptions andvoltage variations immunityIEC/EN61000-4-11 0%-70% perf. Criteria BProduct Characteristic Curve-25 0 55 701007075O u t p u t P o w e r P e r c e n t a g e (%)Amb ie nt T e mp e ra ture ()℃T empe rature Dera ting Curve100~264VAC 120~370VDCInp ut vo lta g e:1007010085264120100370VAC VD C240340Input Volta ge De ra ting CurveAmb ie nt te m p e ra ture :25℃Inp ut Vo lta g eO u t p u t P o w e r P e r c e n t a g e (%)Note: Input voltage should be derated based on temperature derating when it is 85~100VAC/100~120VDC;This product is suitable for use in natural air cooling environments, if in a closed environment, please contact our company’s FAE.L D05-20B05MU50 55 6065 70 75 80 85 9095 100 85V110V120V220V240V264VE f f i c i e n c y (%)Input Voltage(V)E fficiency Vs Input Voltage (F ull L oad)L D05-20B05MU5055 6065 70 75 808590 10254050657590100E f f i c i e n c y (%)Output Cur r ent Per centage(%)E fficiency Vs Output L oad(Vin=230VAC)L D05-20B24MU50 556065 70 75 80 859095 100 85V110V120V220V240V264VE f f i c i e n c y (%)Input Voltage(V)E fficiency Vs Input Voltage (F ull L oad)L D05-20B24MU5055 6065 70 75 808590 10254050657590100E f f i c i e n c y (%)Output Cur r ent Per centage(%)E fficiency Vs Output L oad(Vin=230VAC)Design Reference1. T ypical application circuitAC (L )+Vo-VoA C (L )AC (N)AC(N)C 1C 2L O ADF US E AC /DCM O VN T CFig. 1: Typical application circuitModelC1(µF) C2(µF) LD05-20B05MU 1220 LD05-20B12MU 100 LD05-20B24MU47Note:Output filtering capacitor C2 is electrolytic capacitor, it is recommended to apply electrolytic capacitor with high frequency and low resistance. For capacitance and current of capacitor please refer to manufacture’s datasheet. Capacitance withstand voltage derating should be 80% or above. C1 is ceramic capacitor, which is used to filter high-frequency noise. External input NTC is recommended to use 5D-9. External input MOV is recommended to use S14K300. External input FUSE is recommended to use 2A/250V , slow blow.2. E MC solution-recommended circuitAC DCAC (N)AC (L)LCMM OVC XC Y1C Y2FUSEAC (N)AC (L)+Vo-Vo+L1C1C2R LC a n us e MO RNS UN’s FC -L X1DNT CFig 2: EMC Recommended circuit with higher requirementsElement modelRecommended valueMOV S14K300 CX 0.1µF/275V AC L1 4.7uH/2.0A CY1 1nF/400V AC CY2 1nF /400V ACNTC 5D-9LCM 2.2mH, recommended to use MORNSUN’s FL2D -10-222FUSE 2A/250V , slow blow, necessaryFC-LX1DEMC FilterDimensions and Recommended LayoutNote:1.If the product is not operated within the required load range, the product performance cannot be guaranteed to comply with all parameters in the datasheet;2.Unless otherwise specified, parameters in this datasheet were measured under the conditions of Ta = 25℃, humidity <75% with nominal input voltage andrated output load;3.All index testing methods in this datasheet are based on our Company’s corporate stan dards;4.The performance parameters of the product models listed in this manual are as above, but some parameters of non-standard model products may exceed therequirements mentioned above. Please contact our technicians directly for specific information;5.We can provide product customization service;6.Specifications are subject to change without prior notice.。
CS5532_DataSheet
Copyright ©Cirrus Logic,Inc.200278760CS5531/32/33/3416-Bit and 24-Bit ADCs with Ultra Low Noise PGIAMAR ‘02TABLE OF CONTENTS1.CHARACTERISTICS AND SPECIFICATIONS (5)ANALOG CHARACTERISTICS (5)TYPICAL RMS NOISE(NV),CS5531/32/33/34-AS (8)TYPICAL NOISE FREE RESOLUTION(BITS),CS5532/34-AS (8)TYPICAL RMS NOISE(NV),CS5532/34-BS (9)TYPICAL NOISE FREE RESOLUTION(BITS),CS5532/34-BS (9)5V DIGITAL CHARACTERISTICS (10)3V DIGITAL CHARACTERISTICS (10)DYNAMIC CHARACTERISTICS (11)ABSOLUTE MAXIMUM RATINGS (11)SWITCHING CHARACTERISTICS (12)2.GENERAL DESCRIPTION (14)2.1.Analog Input (14)2.1.1.Analog Input Span (15)2.1.2.Multiplexed Settling Limitations (15)2.1.3.Voltage Noise Density Performance (15)2.1.4.No Offset DAC (15)2.2.Overview of ADC Register Structure and Operating Modes (16)2.2.1.System Initialization (17)mand Register Quick Reference (19)mand Register Descriptions (20)2.2.4.Serial Port Interface (24)2.2.5.Reading/Writing On-Chip Registers (25)2.3.Configuration Register (25)2.3.1.Power Consumption (25)2.3.2.System Reset Sequence (25)2.3.3.Input Short (26)2.3.4.Guard Signal (26)2.3.5.Voltage Reference Select (26)2.3.6.Output Latch Pins (26)2.3.7.Offset and Gain Select (27)Contacting Cirrus Logic SupportFor a complete listing of Direct Sales,Distributor,and Sales Representative contacts,visit the Cirrus Logic web site at: /corporate/contacts/sales.cfmSPI is a registered trademark of International Business Machines Corporation.Microwire is a trademark of National Semiconductor Corporation.IMPORTANT NOTICE"Preliminary"product information describes products that are in production,but for which full characterization data is not yet available."Advance"product infor-mation describes products that are in development and subject to development changes.Cirrus Logic,Inc.and its subsidiaries("Cirrus")believe that the infor-mation contained in this document is accurate and reliable.However,the information is subject to change without notice and is provided"AS IS"without warranty of any kind(express or implied).Customers are advised to obtain the latest version of relevant information to verify,before placing orders,that information being relied on is current and complete.All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment,including those pertaining to warranty,patent infringement,and limitation of liability.No responsibility is assumed by Cirrus for the use of this information,including use of this information as the basis for manufacture or sale of any items,or for infringement of patents or other rights of third parties.This document is the property of Cirrus and by furnishing this information,Cirrus grants no license,express or implied under any patents,mask work rights,copyrights,trademarks,trade secrets or other intellectual property rights.Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus.This consent does not extend to other copying such as copying for general distribution,advertising or promotional purposes,or for creating any work for resale.An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma-terial and controlled under the"Foreign Exchange and Foreign Trade Law"is to be exported or taken out of Japan.An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC.CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH,PERSONAL INJURY,OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE("CRITICAL APPLICATIONS").CIRRUS PRODUCTS ARE NOT DESIGNED,AUTHORIZED,OR WARRANT-ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK.Cirrus Logic,Cirrus,and the Cirrus Logic logo designs are trademarks of Cirrus Logic,Inc.All other brand and product names in this document may be trade-marks or service marks of their respective owners.2.3.8.Filter Rate Select (27)2.3.9.Configuration Register Descriptions (28)2.4.Setting up the CSRs for a Measurement (29)2.4.1.Channel-Setup Register Descriptions (30)2.5.Calibration (32)2.5.1.Calibration Registers (32)2.5.2.Gain Register (32)2.5.3.Offset Register (32)2.5.4.Performing Calibrations (33)2.5.5.Self Calibration (33)2.5.6.System Calibration (34)2.5.7.Calibration Tips (34)2.5.8.Limitations in Calibration Range (35)2.6.Performing Conversions (35)2.6.1.Single Conversion Mode (35)2.6.2.Continuous Conversion Mode (36)2.6.3.Examples of Using CSRs to Perform Conversions and Calibrations (37)ing Multiple ADCs Synchronously (38)2.8.Conversion Output Coding (38)2.8.1.Conversion Data Output Descriptions (39)2.9.Digital Filter (40)2.10.Clock Generator (41)2.11.Power Supply Arrangements (41)2.12.Getting Started (45)2.13.PCB Layout (45)3.PIN DESCRIPTIONS (46)Clock Generator (46)Control Pins and Serial Data I/O (46)Measurement and Reference Inputs (47)Power Supply Connections (47)4.SPECIFICATION DEFINITIONS (48)5.ORDERING GUIDE (48)6.PACKAGE DRAWINGS (49)LIST OF FIGURESFigure1.SDI Write Timing(Not to Scale) (13)Figure2.SDO Read Timing(Not to Scale) (13)Figure3.Multiplexer Configuration (14)Figure4.Input models for AIN+and AIN-pins (15)Figure5.Measured Voltage Noise Density (15)Figure6.CS5531/32/33/34Register Diagram (16)mand and Data Word Timing (24)Figure8.Guard Signal Shielding Scheme (26)Figure9.Input Reference Model when VRS=1 (27)Figure10.Input Reference Model when VRS=0 (27)Figure11.Self Calibration of Offset (34)Figure12.Self Calibration of Gain (34)Figure13.System Calibration of Offset (34)Figure14.System Calibration of Gain (34)Figure15.Synchronizing Multiple ADCs (38)Figure16.Digital Filter Response(Word Rate=60Sps) (40)Figure17.120Sps Filter Magnitude Plot to120Hz (40)Figure18.120Sps Filter Phase Plot to120Hz (40)Figure19.Z-Transforms of Digital Filters (40)Figure20.On-chip Oscillator Model (41)Figure21.CS5532Configured with a Single+5V Supply (42)Figure22.CS5532Configured with±2.5V Analog Supplies (43)Figure23.CS5532Configured with±3V Analog Supplies (43)Figure24.CS5532Configured for Thermocouple Measurement (44)Figure25.Bridge with Series Resistors (44)LIST OF TABLESTable1.Conversion Timing for Single Mode (36)Table2.Conversion Timing for Continuous Mode (37)mand Byte Pointer (37)Table4.Output Coding for16-bit CS5531and CS5533 (39)Table5.Output Coding for24-bit CS5532and CS5534 (39)1.CHARACTERISTICS AND SPECIFICATIONSANALOG CHARACTERISTICS(VA+,VD+=5V ±5%;VREF+=5V;VA-,VREF-,DGND =0V;MCLK =4.9152MHz;OWR (Output Word Rate)=60Sps;Bipolar Mode;Gain =32)(See Notes 1and 2.)Notes: 1.Applies after system calibration at any temperature within -40°C ~+85°C.2.Specifications guaranteed by design,characterization,and/or test.LSB is 16bits for the CS5531/33andLSB is 24bits for the CS5532/34.3.This specification applies to the device only and does not include any effects by external parasiticthermocouples.The PGIA contributes 5nV of offset drift,and the modulator contributes 640/G nV of offset drift,where G is the amplifier gain setting.4.Drift over specified temperature range after calibration at power-up at 25°C.ParameterCS5531-AS/CS5533-ASUnit Min Typ Max Accuracy Linearity Error -±0.0015±0.003%FS No Missing Codes 16--Bits Bipolar Offset -±1±2LSB 16Unipolar Offset-±2±4LSB 16Offset Drift(Notes 3and 4)-640/G +5-nV/°C Bipolar Full Scale Error -±8±31ppm Unipolar Full Scale Error -±16±62ppm Full Scale Drift(Note 4)-2-ppm/°CParameterCS5532-AS/CS5534-ASCS5532-BS/CS5534-BS Unit Min Typ Max Min Typ Max Accuracy Linearity Error -±0.0015±0.003-±0.0007±0.0015%FS No Missing Codes 24--24--Bits Bipolar Offset -±16±32-±16±32LSB 24Unipolar Offset-±32±64-±32±64LSB 24Offset Drift(Notes 3and 4)-640/G +5--640/G +5-nV/°C Bipolar Full Scale Error -±8±31-±8±31ppm Unipolar Full Scale Error -±16±62-±16±62ppm Full Scale Drift(Note 4)-TBD--2-ppm/°CANALOG CHARACTERISTICS(Continued)(See Notes 1and 2.)Notes: 5.The voltage on the analog inputs is amplified by the PGIA,and becomes V CM ±Gain*(AIN+-AIN-)/2atthe differential outputs of the amplifier.In addition to the input common mode +signal requirements for the analog input pins,the differential outputs of the amplifier must remain between (VA-+0.1V)and (VA+-0.1V)to avoid saturation of the output stage.6.See the section of the data sheet which discusses input models.ParameterMinTypMaxUnitAnalog InputCommon Mode +Signal on AIN+or AIN-Bipolar/Unipolar ModeGain =1Gain =2,4,8,16,32,64(Note 5)VA-VA-+0.7--VA+VA+-1.7V V CVF Current on AIN+or AIN-Gain =1(Note 6)Gain =2,4,8,16,32,64--500500--nA pA Input Current Noise Gain =1Gain =2,4,8,16,32,64--2001--pA/√Hz pA/√Hz Input Leakage for Mux when Off (at 25°C)-10-pA Off-Channel Mux Isolation -120-dB Open Circuit Detect Current 100300-nA Common Mode Rejection dc,Gain =1dc,Gain =6450,60Hz ---90130120---dB dB dB Input Capacitance -60-pF Guard Drive Output -20-µA Voltage Reference Input Range (VREF+)-(VREF-)1 2.5(VA+)-(VA-)V CVF Current (Note 6)-500-nA Common Mode Rejection dc 50,60Hz --120120--dB dB Input Capacitance 11-22pF System Calibration Specifications Full Scale Calibration Range Bipolar/Unipolar Mode 3-110%FS Offset Calibration Range Bipolar Mode -100-100%FS Offset Calibration Range Unipolar Mode -90-90%FSANALOG CHARACTERISTICS(Continued)(See Notes 1and 2.)7.All outputs unloaded.All input CMOS levels.8.Power is specified when the instrumentation amplifier (Gain ≥2)is on.Analog supply current is reducedby approximately 1/2when the instrumentation amplifier is off (Gain =1).9.Tested with 100mV change on VA+or VA-.ParameterCS5531/32/33/34-AS CS5532/34-BS MinTypMaxMinTypMaxUnitPower SuppliesDC Power Supply Currents (Normal Mode)I A+,I A-I D+--60.581--130.5151mA mA Power ConsumptionNormal Mode (Notes 7and 8)Standby Sleep---35350045-----70450080--mW mW µW Power Supply Rejection(Note 9)dc Positive Supplies dc Negative Supply--115115----115115--dB dBTYPICAL RMS NOISE (nV),CS5531/32/33/34-AS (See notes 10,11and 12)Notes:10.Wideband noise aliased into the baseband.Referred to the input.Typical values shown for 25°C.11.For Peak-to-Peak Noise multiply by 6.6for all ranges and output rates.12.Word rates and -3dB points with FRS =0.When FRS =1,word rates and -3dB points scale by 5/6.TYPICAL NOISE FREE RESOLUTION(BITS),CS5532/34-AS (See Notes 13and 14)13.Noise Free Resolution listed is for Bipolar operation,and is calculated as LOG((Input Span)/(6.6xRMSNoise))/LOG(2)rounded to the nearest bit.For Unipolar operation,the input span is 1/2as large,so one bit is lost.The input span is calculated in the analog input span section of the data sheet.The Noise Free Resolution table is computed with a value of 1.0in the gain register.Values other than 1.0will scale the noise,and change the Noise Free Resolution accordingly.14.“Noise Free Resolution”is not the same as “Effective Resolution”.Effective Resolution is based on theRMS noise value,while Noise Free Resolution is based on a peak-to-peak noise value specified as 6.6times the RMS noise value.Effective Resolution is calculated as LOG((Input Span)/(RMS Noise))/LOG(2).Specifications are subject to change without notice.Output Word Rate (Sps)-3dB Filter Frequency (Hz)Instrumentation Amplifier Gain x64x32x16x8x4x2x17.5 1.9417171926427915515 3.882425273659111218307.7534353951841573086015.548495472118222436120316870771021673146162406211516027652710402070415048012216323039274814802950589096023022932155410602090417083401,920390344523946184036507290146003,84078013902710539010800215004300086100Output Word Rate (Sps)-3dB Filter Frequency (Hz)Instrumentation Amplifier Gain x64x32x16x8x4x2x17.5 1.941920212222222215 3.8819202121212222307.75181920212121216015.5181920202021211203117181920202020240621617171717171748012216171717171717960230151616161616161,920390151515151515153,84078013131313131313TYPICAL RMS NOISE (nV),CS5532/34-BS (See notes 15,16,17and 18)Notes:15.The -B devices provide the best noise specifications.16.Wideband noise aliased into the baseband.Referred to the input.Typical values shown for 25°C.17.For Peak-to-Peak Noise multiply by 6.6for all ranges and output rates.18.Word rates and -3dB points with FRS =0.When FRS =1,word rates and -3dB points scale by 5/6.TYPICAL NOISE FREE RESOLUTION(BITS),CS5532/34-BS (See Notes 19and 20)19.Noise Free Resolution listed is for Bipolar operation,and is calculated as LOG((Input Span)/(6.6xRMSNoise))/LOG(2)rounded to the nearest bit.For Unipolar operation,the input span is 1/2as large,so one bit is lost.The input span is calculated in the analog input span section of the data sheet.The Noise Free Resolution table is computed with a value of 1.0in the gain register.Values other than 1.0will scale the noise,and change the Noise Free Resolution accordingly.20.“Noise Free Resolution”is not the same as “Effective Resolution”.Effective Resolution is based on theRMS noise value,while Noise Free Resolution is based on a peak-to-peak noise value specified as 6.6times the RMS noise value.Effective Resolution is calculated as LOG((Input Span)/(RMS Noise))/LOG(2).Specifications are subject to change without notice.Output Word Rate (Sps)-3dB Filter Frequency (Hz)Instrumentation Amplifier Gain x64x32x16x8x4x2x17.5 1.948.59101526509915 3.88121315213770139307.751718213052991966015.524252942731402771203134364259103198392240628013626051410202050409048012211319436973014502900581096023015927452310302060411082301,920390260470912181036207230145003,84078013602690538010800215004300086000Output Word Rate (Sps)-3dB Filter Frequency (Hz)Instrumentation Amplifier Gain x64x32x16x8x4x2x17.5 1.942021222323232315 3.8820212222222222307.75192021222222226015.5192021212121211203118192021212121240621717181818181848012217171717171717960230161617171717171,920390161616161616163,840780131313131313135V DIGITAL CHARACTERISTICS (VA+,VD+=5V ±5%;VA-,DGND =0V;See Notes 2and 21.)3V DIGITAL CHARACTERISTICS (T A =25°C;VA+=5V ±5%;VD+=3.0V±10%;VA-,DGND =0V;See Notes 2and 21.)21.All measurements performed under static conditions.ParameterSymbol Min Typ Max Unit High-Level Input Voltage All Pins Except SCLKSCLK V IH 0.6VD+(VD+)-0.45--VD+VD+V Low-Level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-Level Output Voltage A0and A1,I out =-1.0mASDO,I out =-5.0mA V OH (VA+)-1.0(VD+)-1.0--V Low-Level Output Voltage A0and A1,I out =1.0mASDO,I out =5.0mAV OL --(VA-)+0.40.4V Input Leakage Current I in -±1±10µA SDO 3-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFParameterSymbol Min Typ Max Unit High-Level Input Voltage All Pins Except SCLKSCLK V IH 0.6VD+(VD+)-0.45-VD+VD+V Low-Level Input Voltage All Pins Except SCLKSCLK V IL 0.00.0-0.80.6V High-Level Output Voltage A0and A1,I out =-1.0mASDO,I out =-5.0mA V OH (VA+)-1.0(VD+)-1.0--V Low-Level Output Voltage A0and A1,I out =1.0mASDO,I out =5.0mAV OL --(VA-)+0.40.4V Input Leakage Current I in -±1±10µA SDO 3-State Leakage Current I OZ --±10µA Digital Output Pin CapacitanceC out-9-pFDYNAMIC CHARACTERISTICS22.The ADCs use a Sinc 5filter for the 3200Sps and 3840Sps output word rate (OWR)and a Sinc 5filterfollowed by a Sinc 3filter for the other OWRs.OWR sinc5refers to the 3200Sps (FRS =1)or 3840Sps (FRS =0)word rate associated with the Sinc 5filter.23.The single conversion mode only outputs fully settled conversions.See Table 1for more details aboutsingle conversion mode timing.OWR SC is used here to designate the different conversion time associated with single conversions.24.The continuous conversion mode outputs every conversion.This means that the filter’s settling timewith a full scale step input in the continuous conversion mode is dictated by the OWR.ABSOLUTE MAXIMUM RATINGS(DGND =0V;See Note 25.)Notes:25.All voltages with respect to ground.26.VA+and VA-must satisfy {(VA+)-(VA-)}≤+6.6V.27.VD+and VA-must satisfy {(VD+)-(VA-)}≤ +7.5V.28.Applies to all pins including continuous overvoltage conditions at the analog input (AIN)pins.29.Transient current of up to 100mA will not cause SCR latch-up.Maximum input current for a power supply pin is ±50mA.30.Total power dissipation,including all input currents and output currents.WARNING:Operation at or beyond these limits may result in permanent damage to the device.Normal operation is not guaranteed at these extremes.ParameterSymbol Ratio Unit Modulator Sampling Ratef s MCLK/16Sps Filter Settling Time to 1/2LSB (Full Scale Step Input)Single Conversion mode (Notes 22,23,and 24)Continuous Conversion mode,OWR <3200Sps Continuous Conversion mode,OWR ≥3200Spst s t s t s1/OWR SC5/OWR sinc5+3/OWR5/OWRs s sParameterSymbolMin Typ Max Unit DC Power Supplies(Notes 26and 27)Positive Digital Positive Analog Negative Analog VD+VA+VA--0.3-0.3+0.3---+6.0+6.0-3.75V V V Input Current,Any Pin Except Supplies (Notes 28and 29)I IN --±10mA Output Current I OUT --±25mA Power Dissipation (Note 30)PDN --500mW Analog Input Voltage VREF pins AIN PinsV INR V INA (VA-)-0.3(VA-)-0.3--(VA+)+0.3(VA+)+0.3V V Digital Input VoltageV IND -0.3-(VD+)+0.3V Ambient Operating Temperature T A -40-85°C Storage T emperature T stg-65-150°CSWITCHING CHARACTERISTICS (VA+=2.5V or 5V ±5%;VA-=-2.5V±5%or 0V;VD+=3.0V±10%or 5V ±5%;DGND =0V;Levels:Logic 0=0V,Logic 1=VD+;C L =50pF;See Figures 1and 2.)Notes:31.Device parameters are specified with a 4.9152MHz clock.32.Specified using 10%and 90%points on waveform of interest.Output loaded with 50pF.33.Oscillator start-up time varies with crystal parameters.This specification does not apply when using anexternal clock source.ParameterSymbol MinTypMaxUnitMaster Clock Frequency (Note 31)External Clock or Crystal OscillatorMCLK1 4.91525MHz Master Clock Duty Cycle 40-60%Rise Times(Note 32)Any Digital Input Except SCLKSCLKAny Digital Output t rise-----50 1.0100-µs µs ns Fall Times(Note 32)Any Digital Input Except SCLKSCLKAny Digital Output t fall-----50 1.0100-µs µs ns Start-upOscillator Start-up Time XTAL =4.9152MHz(Note 33)t ost-20-ms Serial Port Timing Serial Clock Frequency SCLK 0-2MHz Serial Clock Pulse Width High Pulse Width Lowt 1t 2250250----ns nsSDI Write TimingCS Enable to Valid Latch Clock t 350--ns Data Set-up Time prior to SCLK rising t 450--ns Data Hold Time After SCLK Rising t 5100--ns SCLK Falling Prior to CS Disable t 6100--nsSDO Read Timing CS to Data Validt 7--150ns SCLK Falling to New Data Bit t 8--150ns CS Rising to SDO Hi-Zt 9--150nsFigure1.SDI Write Timing(Not toScale)2.GENERAL DESCRIPTIONThe CS5531/32/33/34are highly integrated∆ΣAn-alog-to-Digital Converters(ADCs)which use charge-balance techniques to achieve16-bit (CS5531/33)and24-bit(CS5532/34)performance. The ADCs are optimized for measuring low-level unipolar or bipolar signals in weigh scale,process control,scientific,and medical applications.To accommodate these applications,the ADCs come as either two-channel(CS5531/32)or four-channel(CS5533/34)devices and include a very low noise chopper-stabilized programmable gain instrumentation amplifier(PGIA,6nV/√Hz@0.1 Hz)with selectable gains of1×,2×,4×,8×,16×, 32×,and64×.These ADCs also include a fourth or-der∆Σmodulator followed by a digital filter which provides twenty selectable output word rates of6.25, 7.5,12.5,15,25,30,50,60,100,120,200,240,400, 480,800,960,1600,1920,3200,and3840Samples per second(MCLK=4.9152MHz).To ease communication between the ADCs and a micro-controller,the converters include a simple three-wire serial interface which is SPI and Mi-crowire compatible with a Schmitt Trigger input on the serial clock(SCLK).2.1.Analog InputFigure3illustrates a block diagram of the CS5531/32/33/34.The front end consists of a multi-plexer,a unity gain coarse/fine charge input buffer, and a programmable gain chopper-stabilized instru-mentation amplifier.The unity gain buffer is activat-ed any time conversions are performed with a gain of one and the instrumentation amplifier is activated any time conversions are performed with gain set-tings greater than one.The unity gain buffer is designed to accommodate rail to rail input signals.The common-mode plus signal range for the unity gain buffer amplifier is VA-to VA+.Typical CVF(sampling)current for the unity gain buffer amplifier is about500nA (MCLK=4.9152MHz,see Figure4).The instrumentation amplifier is chopper-stabi-lized and operates with a chop clock frequency of MCLK/128.The CVF(sampling)current into the instrumentation amplifier is typically500pA overFigure3.Multiplexer Configuration-40°C to+85°C(MCLK=4.9152MHz).The com-mon-mode plus signal range of the instrumentation amplifier is(VA-)+0.7V to(VA+)-1.7V. Figure4illustrates the input models for the ampli-fiers.The dynamic input current for each of the pins can be determined from the models shown. Note:The C=2.5pF and C=16pF capacitors are for input current modeling only.For physicalinput capacitance see‘Input Capacitance’specification under Analog Characteristics.2.1.1.Analog Input SpanThe full scale input signal that the converter can dig-itize is a function of the gain setting and the refer-ence voltage connected between the VREF+and VREF-pins.The full scale input span of the convert-er is((VREF+)-(VREF-))/(GxA),where G is the gain of the amplifier and A is2for VRS=0,or A is 1for VRS=1.VRS is the Voltage Reference Select bit,and must be set according to the differential volt-age applied to the VREF+and VREF-pins on the part.See section2.3.5for more details.After reset,the unity gain buffer is engaged.With a 2.5V reference this would make the full scale input range default to2.5V.By activating the instrumen-tation amplifier(i.e.a gain setting other than1)and using a gain setting of32,the full scale input range can quickly be set to2.5/32or about78mV.Note that these input ranges assume the calibration regis-ters are set to their default values(i.e.Gain=1.0and Offset=0.0).2.1.2.Multiplexed Settling LimitationsThe settling performance of the CS5531/32/33/34 in multiplexed applications is affected by the sin-gle-pole low-pass filter which follows the instru-mentation amplifier(see Figure3).To achieve data sheet settling and linearity specifications,it is rec-ommended that a22nF C0G capacitor be used.Ca-pacitors as low as10nF or X7R type capacitors can also be used with some minor increase in distortion for AC signals.2.1.3.Voltage Noise Density Performance Figure5illustrates the measured voltage noise den-sity versus frequency from0.01Hz to10Hz of a CS5532-BS.The device was powered with±2.5V supplies,using120Sps OWR,the64x gain range, bipolar mode,and with the input short bit enabled.2.1.4.No Offset DACAn offset DAC was not included in the CS553X family because the high dynamic range of the con-verter eliminates the need for one.The offset regis-Figure4.Input models for AIN+and AIN-pinster can be manipulated by the user to mimic the function of a DAC if desired.2.2.Overview of ADC Register Structure and Operating ModesThe CS5531/32/33/34ADCs have an on-chip con-troller,which includes a number of user-accessible registers.The registers are used to hold offset and gain calibration results,configure the chip's operat-ing modes,hold conversion instructions,and to store conversion data words.Figure6depicts a block diagram of the on-chip controller’s internal registers.Each of the converters has32-bit registers to func-tion as offset and gain calibration registers for each channel.The converters with two channels have two offset and two gain calibration registers,the converters with four channels have four offset and four gain calibration registers.These registers hold calibration results.The contents of these registers can be read or written by the user.This allows cal-ibration data to be off-loaded into an external EE-PROM.The user can also manipulate the contents of these registers to modify the offset or the gain slope of the converter.The converters include a32-bit configuration reg-ister which is used for setting options such as the power down modes,resetting the converter,short-ing the analog inputs,and enabling diagnostic test bits like the guard signal.A group of registers,called Channel Setup Regis-ters,are used to hold pre-loaded conversion in-structions.Each channel setup register is32bits long,and holds two16-bit conversion instructions referred to as Setups.Upon power up,these regis-ters can be initialized by the system microcontrol-ler with conversion instructions.The user can then instruct the converter to perform single or multiple conversions or calibrations with the converter in the mode defined by one of these Setups.Figure6.CS5531/32/33/34Register DiagramUsing the single conversion mode,an8-bit com-mand word can be written into the serial port.The command includes pointer bits which‘point’to a 16-bit command in one of the Channel Setup Reg-isters which is to be executed.The16-bit Setups can be programmed to perform a conversion on any of the input channels of the converter.More than one of the16-bit Setups can be used for the same analog input channel.This allows the user to con-vert on the same signal with either a different con-version speed,a different gain range,or any of the other options available in the channel setup regis-ters.Alternately,the user can set up the registers to perform different conversion conditions on each of the input channels.The ADCs also include continuous conversion ca-pability.The ADCs can be instructed to continu-ously convert,referencing one16-bit command Setup.In the continuous conversions mode,the conversion data words are loaded into a shift regis-ter.The converter issues a flag on the SDO pin when a conversion cycle is completed so the user can read the register,if need be.See the section on Performing Conversions for more details.The following pages document how to initialize the converter,perform offset and gain calibrations,and how to configure the converter for the various con-version modes.Each of the bits of the configuration register and of the Channel Setup Registers is de-scribed.A list of examples follows the description section.Also the Command Register Quick Refer-ence can be used to decode all valid commands(the first8-bits into the serial port).2.2.1.System InitializationThe CS5531/32/33/34provide no power-on-reset function.To initialize the ADCs,the user must per-form a software reset by resetting the ADC’s serial port with the Serial Port Initialization sequence. This sequence resets the serial port to the command mode and is accomplished by transmitting at least 15SYNC1command bytes(0xFF hexadecimal),followed by one SYNC0command(0xFE hexa-decimal).Note that this sequence can be initiated at anytime to reinitialize the serial port.To complete the system initialization sequence,the user must also perform a system reset sequence which is as follows:Write a logic1into the RS bit of the con-figuration register.This will reset the calibration registers and other logic(but not the serial port).A valid reset will set the RV bit in the configuration register to a logic1.After writing the RS bit to a logic1,wait20microseconds,then write the RS bit back to logic0.While this involves writing an en-tire word into the configuration register,the RV bit is a read only bit,therefore a write to the configu-ration register will not overwrite the RV bit.After clearing the RS bit back to logic0,read the config-uration register to check the state of the RV bit as this indicates that a valid reset occurred.Reading the configuration register clears the RV bit back to logic0.Completing the reset cycle initializes the on-chip registers to the following states:Note:Previous datasheets stated that the RS bit would clear itself back to logic0and thereforethe user was not required to write the RS bitback to logic0.The current data sheetinstruction that requires the user to write intothe configuration register to clear the RS bithas been added to insure that the RS bit iscleared.Characterization across multiple lotsof silicon has indicated some chips do notautomatically reset the RS bit to logic0in theconfiguration register,although the resetfunction is completed.This occurs only onsmall number of chips when the VA-supply isnegative with respect to DGND.This has notcaused an operational issue for customersbecause their start-up sequence includeswriting a word(with RS=0)into theconfiguration register after performing areset.The change in the reset sequence to Configuration Register:00000000(H)Offset Registers:00000000(H)Gain Registers:01000000(H)Channel Setup Registers:00000000(H)。
Design and Control of an LCL-filter based Three-phase Active Rectifier
I. INTRODUCTION The Voltage Source Converter (VSC) may be used as an active rectifier. The advantages are the possibility of full control both of the dc voltage and of the power factor, working in rectifying and regenerating modes [1]. Moreover, the VSC based active rectifier represents an attractive solution due to the possibility to obtain sinusoidal input current with a Total Harmonic Distortion (THD) below 5 %, [2]-[5]. Unfortunately, the power devices switching frequency is generally between 2 kHz and 15 kHz and causes high order harmonics, that can disturb other EMI sensitive loads/equipment on the grid [6]. To reduce the current harmonics around the switching frequency a high value of input inductance should be selected. But for applications above several kW it becomes
zl30111中文资料_数据手册_IC数据表
1Features•Synchronizes to 8kHz, 2.048MHz, 8.192MHz or 19.44MHz input•Provides a range of clock outputs: 2.048MHz, 4.096MHz and 8.192MHz•Provides 2 styles of 8kHz framing pulses •Automatic entry and exit from freerun mode on reference fail•Provides DPLL lock and reference fail indication •DPLL bandwidth of 922Hz for all rates of input reference and 58 Hz for an 8kHz input reference •Less than 0.6 ns pp intrinsic jitter on all output clocks •20 MHz external master clock source: clock oscillator or crystal•Simple hardware control interfaceApplications•Synchronizer for POTS line cards•Rate convert NTR 8kHz or GPON physical interface clock to TDM clockDescriptionThe ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices.The ZL30111 generates TDM clock and framing signals that are phase locked to the input reference.It helps ensure system reliability by monitoring its reference for stability and by maintaining stable output clocks during short periods when the reference is unavailable.January 2007ZL30111POTS Line Card PLLData SheetFigure 1 - Functional Block DiagramReference MonitorMode ControlState Machine RST C4C8F4F8OSCoOSCi Master ClockREFLOCKDPLLC2o REF_FAIL Ordering InformationZL30111QDG 64 Pin TQFP Trays, Bake & Drypack ZL30111QDG164 Pin TQFP*Trays, Bake & Drypack *Pb Free Matte Tin -40°C to +85°CZL30111Data SheetTable of Contents1.0 Physical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41.1 Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41.2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82.1 Reference Monitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82.2 Digital Phase Lock Loop (DPLL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92.3 Frequency Synthesizers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92.4 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92.5 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93.0 DPLL Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.1 Freerun Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103.2 Normal Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104.0 Measures of Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114.1 Jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114.2 Jitter Generation (Intrinsic Jitter). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114.3 Jitter Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114.4 Lock Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115.0 Applications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125.1 Power Supply Decoupling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125.2 Master Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125.2.1 Clock Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125.2.2 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135.3 Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145.4 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146.0 Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156.1 AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156.2 Performance Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19ZL30111Data SheetList of FiguresFigure 1 - Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Pin Connections (64 pin TQFP, please see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3 - Reference Monitor Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4 - DPLL Mode Switching. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 5 - Clock Oscillator Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 6 - Power-Up Reset Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - Timing Parameter Measurement Voltage Levels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 8 - Input to Output Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 9 - Output Timing Referenced to F8o. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18ZL30111Data Sheet1.0 Physical Description1.1 Pin ConnectionsFigure 2 - Pin Connections (64 pin TQFP, please see Note 1)Note 1: The ZL30111 uses the TQFP shown in the package outline designated with the suffix QD, the ZL30111does not use the e-Pad TQFP .ZL3011134363840424446486462605856525054161412108642OSCo NC GND V DD AV DD IC NC RST NC AGNDF4/F65oV DD NC IC C 8/C 32o N C C 2o A G N DA V D DN C F 8/F 32o C 4/C 65o 1820222426303228IC OSCi A V D DA V D DA V D DA V C O R EA G N D A G N D A G N D NC NC IC IC NC REF0V C O R EL O C K G N DR E F _F A I L I C V C O R EA V C O R EG N D I C I C I C I C I C I C I CI C IC ICIC IC I C IC IC IC IC IC ICZL30111Data Sheet1.2 Pin DescriptionPin DescriptionPin # Name Description1GND Ground. 0 V.2V CORE Positive Supply Voltage. +1.8 V DC nominal.3LOCK Lock Indicator (Output). This output goes to a logic high when the PLL is frequencylocked to the selected input reference.4REF_FAIL Reference Failure Indicator (Output). A logic high at this pin indicates that the REFreference frequency is exhibiting abrupt phase or frequency changes.5IC Internal Connection. Leave unconnected.6IC Internal Connection. Leave unconnected.7IC Internal Connection. Leave unconnected.8IC Internal Connection. Leave unconnected.9IC Internal Connection. Leave unconnected.10IC Internal Connection. Connect to GND.11IC Internal Connection. Connect to GND.12V CORE Positive Supply Voltage. +1.8 V DC nominal.13GND Ground. 0 V.14AV CORE Positive Analog Supply Voltage. +1.8 V DC nominal.15IC Internal Connection. Leave unconnected.16IC Internal Connection. Connect to VDD.17IC Internal Connection. Connect to GND.18IC Internal Connection. Connect to GND.19RST Reset (Input). A logic low at this input resets the device. On power up, the RST pin must be held low for a minimum of 300ns after the power supply pins have reachedthe minimum supply voltage. When the RST pin goes high, the device will transitioninto a Reset state for 3ms. In the Reset state all clock and frame pulse outputs will beforced into high impedance.20OSCo Oscillator Master Clock (Output). For crystal operation, a 20MHz crystal is connected from this pin to OSCi. This output is not suitable for driving other devices. For clockoscillator operation, this pin must be left unconnected.21OSCi Oscillator Master Clock (Input). For crystal operation, a 20MHz crystal is connected from this pin to OSCo. For clock oscillator operation, this pin must be connected to aclock source.22IC Internal Connection. Leave unconnected.23GND Ground. 0V.24NC No internal bonding Connection. Leave unconnected.25V DD Positive Supply Voltage. +3.3 V DC nominal.26IC Internal Connection. Connect this pin to GND.ZL30111Data Sheet Pin Description (continued)Pin # Name Description27IC Internal Connection. Connect this pin to GND.28IC Internal Connection. Connect this pin to GND.29AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.30NC No internal bonding Connection. Leave unconnected.31NC No internal bonding Connection. Leave unconnected.32IC Internal Connection. Leave unconnected.33AGND Analog Ground. 0 V34AGND Analog Ground. 0 V35AV CORE Positive Analog Supply Voltage. +1.8 V DC nominal.36AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.37AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.38NC No internal bonding Connection. Leave unconnected.39NC No internal bonding Connection. Leave unconnected.40AGND Analog Ground.0V41AGND Analog Ground.0V42C4Clock 4.096MHz (Output). This output is used for ST-BUS operation at 2.048Mbps or4.096Mbps.43C8Clock 8.192MHz (Output). This output is used for ST-BUS and GCI operation at8.192Mbps.44AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.45AV DD Positive Analog Supply Voltage. +3.3 V DC nominal.46C2o Clock 2.048MHz (Output). This output is used for standard E1 interface timing.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.47IC Internal Connection. Leave unconnected.48F8Frame Pulse (Output). This is an 8kHz 122ns active high framing pulse, which marks the beginning of a frame.This clock output pad includes a Schmitt input which serves as a PLL feedback path;proper transmission-line termination should be applied to maintain reflections belowSchmitt trigger levels.49F4Frame Pulse ST-BUS 2.048Mbps (Output). This output is an 8kHz 244ns active low framing pulse, which marks the beginning of an ST-BUS frame. This is typically used forST-BUS operation at 2.048Mbps and 4.096Mbps.50IC Internal Connection. Leave unconnected.51AGND Analog Ground.0VZL30111Data Sheet Pin Description (continued)Pin # Name Description52IC Internal Connection. Connect this pin to GND.53IC Internal Connection. Leave unconnected.54NC No internal bonding Connection. Leave unconnected.55REF Reference (Input). This is the input reference sources used for synchronization. One of four possible frequencies may be used: 8kHz, 2.048MHz, 8.192MHz or 19.44 MHz.This pin is internally pulled down to GND.56NC No internal bonding Connection. Leave unconnected.57IC Internal Connection. Leave unconnected.58NC No internal bonding Connection. Leave unconnected.59IC Internal Connection. Connect this pin to GND.60IC Internal Connection. Connect this pin to VDD.61V DD Positive Supply Voltage. +3.3 V DC nominal.62NC No internal bonding Connection. Leave unconnected.63IC Internal Connection. Connect this pin to GND.64IC Internal Connection. Connect this pin to VDD.ZL30111Data Sheet2.0 Functional DescriptionThe ZL30111 POTS line card PLL contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SLIC/CODEC devices. Figure 1 is a functional block diagram which is described in the following sections.2.1 Reference MonitorThe input reference is monitored by two reference monitor blocks. The block diagram of reference monitoring is shown in Figure 3. The reference frequency is detected and the clock is continuously monitored for two independent criteria that indicate abnormal behavior of the reference signal, for example; loss of clock or excessive level of frequency error. To ensure proper operation of the reference monitor circuit, the minimum input pulse width restriction of 15nsec must be observed. •Reference Frequency Detector (RFD): This detector determines whether the frequency of the reference clock is 8kHz, 2.048MHz, 8.192MHz or 19.44MHz and provides this information to the various monitor circuits and the phase detector circuit of the DPLL.•Coarse Frequency Monitor (CFM): This circuit monitors the reference frequency over intervals of approximately 30µs to quickly detect large frequency changes.•Single Cycle Monitor (SCM): This detector checks the period of a single clock cycle to detect large phase hits or the complete loss of the clock.Figure 3 - Reference Monitor CircuitExceeding the thresholds of any of the monitors forces the corresponding REF_FAIL pin to go high. The single cycle and coarse frequency failure flags force the DPLL into FreeRun mode.Reference FrequencyDetectorSingle Cycle MonitorCoarse FrequencyMonitorREFORMode select state machineDPLL in FreeRun ModeREF_FAILZL30111Data Sheet2.2 Digital Phase Lock Loop (DPLL)The DPLL of the ZL30111 consists of a phase detector, a loop filter and a digitally controlled oscillator.Phase Detector - the phase detector compares the input reference signal to the feedback signal and provides an error signal corresponding to the phase difference between the two.Loop Filter - the loop filter is similar to a first order low pass filter with a bandwidth of 922Hz. For stability reasons, the loop filter bandwidth for an 8kHz reference is limited to a maximum of 58Hz.Digitally Controlled Oscillator (DCO) - the DCO receives the filtered signal from the Loop Filter, and based on its value, generates a corresponding digital output signal. The synchronization method of the DCO is dependent on the state of the ZL30111.In Normal Mode, the DCO provides an output signal which is frequency and phase locked to the selected input reference signal.In Freerun Mode, the DCO is free running with an accuracy equal to the accuracy of the OSCi 20MHz source. Lock Indicator - the lock detector monitors if the output value of the phase detector is within the phase-lock-window for a certain time. The selected phase-lock-window guarantees the stable operation of the LOCK pin with maximum network jitter and wander on the reference input. If the DPLL goes into FreeRun mode, the LOCK pin will initially stay high for 0.1s. If at that point the DPLL is still in FreeRun mode, the LOCK pin will go low. In Freerun mode the LOCK pin will go low immediately.2.3 Frequency SynthesizersThe output of the DCO is used by the frequency synthesizer to generate the output clock which is synchronized to the inputs (REF). The frequency synthesizer uses digital techniques to generate output clock and advanced noise shaping techniques to minimize the output jitter. The clock and frame pulse outputs have limited driving capability and should be buffered when driving high capacitance loads.2.4 State MachineAs shown in Figure 1, the state machine controls the DPLL.2.5 Master ClockThe ZL30111 can use either a clock or crystal as the master timing source. For recommended master timing circuits, see the Applications - Master Clock section.ZL30111Data Sheet3.0 DPLL Modes of OperationThe ZL30111 has two possible modes of operation; Normal, and Freerun. The ZL30111 starts up in Freerun mode,it automatically transitions to Normal mode if a valid reference is available and transitions to Freerun mode if the reference fails.3.1 Freerun ModeFreerun mode is typically used when an independent clock source is required or immediately following system power-up before synchronization is achieved.In Freerun mode, the ZL30111 provides timing and synchronization signals which are based on the master clock frequency (supplied to OSCi pin) only and are not synchronized to the reference input signals.The accuracy of the output clock is equal to the accuracy of the master clock (OSCi). So if a ±32ppm output clock is required, the master clock must also be ±32ppm. See Applications - Section 5.2, “Master Clock“.Freerun Mode is also used for short durations while system synchronization is temporarily disrupted. The accuracy of the output clock during these input reference disruptions is better than the accuracy of the master clock (OSCi),but it is off compared to the reference before disruptions.3.2 Normal ModeNormal mode is typically used when a system clock source, synchronized to the network is required. In Normal mode, the ZL30111 provides timing synchronization signals, which are synchronized to the input (REF). The input reference signal may have a nominal frequency of 8kHz, 2.048MHz, 8.192MHz or 19.44MHz. The frequency of the reference inputs are automatically detected by the reference monitors.When the ZL30111 comes out of RESET it will initially go into Freerun mode and generate a clock with the accuracy of its freerunning local oscillator (see Figure 4). If the ZL30111 determines that its selected reference is disrupted (see Figure 3), it will remain in Freerun until the selected reference is no longer disrupted. If the ZL30111determines that the reference is not disrupted (see Figure 3) then the state machine will cause the DPLL to recover from Freerun and transition to Normal mode.When the ZL30111 is operating in Normal mode, if it determines that the input reference is disrupted (Figure 3) then its state machine will cause it to automatically go to Freerun mode. When the ZL30111 determines that its selected reference is not disrupted then the state machine will cause the DPLL to recover from Freerun and transition to Normal mode.Figure 4 - DPLL Mode SwitchingFreerunREF_FAIL=0REF_FAIL=1RSTNormalZL30111Data Sheet 4.0 Measures of PerformanceThe following are some PLL performance indicators and their corresponding definitions.4.1 JitterTiming jitter is defined as the high frequency variation of the clock edges from their ideal positions in time. Wander is defined as the low-frequency variation of the clock edges from their ideal positions in time. High and low frequency variation imply phase oscillation frequencies relative to some demarcation frequency. (Often 10Hz or 20Hz for DS1 or E1, higher for SONET/SDH clocks.) Jitter parameters given in this data sheet are total timing jitter numbers, not cycle-to-cycle jitter.4.2 Jitter Generation (Intrinsic Jitter)Jitter generation is the measure of the jitter produced by the PLL and is measured at its output. It is measured by applying a reference signal with no jitter to the input of the device, and measuring its output jitter. Jitter is usually measured with various band limiting filters depending on the applicable standards.4.3 Jitter TransferJitter transfer or jitter attenuation refers to the magnitude of jitter at the output of a device for a given amount of jitter at the input of the device. Input jitter is applied at various amplitudes and frequencies, and output jitter is measured with various filters depending on the applicable standards.4.4 Lock TimeThis is the time it takes the PLL to frequency lock to the input signal. Phase lock occurs when the input signal and output signal are aligned in phase with respect to each other within a certain phase distance (not including jitter). Lock time is affected by many factors which include:•initial input to output phase difference•initial input to output frequency difference•PLL loop filter bandwidthThe presence of input jitter makes it difficult to define when the PLL is locked as it may not be able to align its output to the input within the required phase distance, dependent on the PLL bandwidth and the input jitter amplitude and frequency.ZL30111Data Sheet5.0 ApplicationsThis section contains ZL30111 application specific details for power supply decoupling, reset operation, clock and crystal operation.5.1 Power Supply DecouplingJitter levels on the ZL30111 output clocks may increase if the device is exposed to excessive noise on its power pins. For optimal jitter performance, the ZL30111 device should be isolated from noise on power planes connected to its 3.3V and 1.8V supply pins. For recommended common layout practices, refer to Zarlink Application Note ZLAN-178.5.2 Master ClockThe ZL30111 can use either a clock or crystal as the master timing source.5.2.1 Clock OscillatorWhen selecting a clock oscillator, numerous parameters must be considered. This includes absolute frequency,frequency change over temperature, output rise and fall times, output levels, duty cycle and phase noise.The output clock should be connected directly (not AC coupled) to the OSCi input of the ZL30111, and the OSCo output should be left open as shown in Figure 5.Figure 5 - Clock Oscillator Circuit1Frequency 20MHz2Tolerance as required (better than +/-50ppm)3Rise & fall time < 8ns 4Duty cycle40% to 60%Table 1 - Clock Oscillator Specification+3.3 V 20MHz OUTGND0.1 µF+3.3 VOSCoZL30111OSCiNo ConnectionZL30111Data Sheet 5.2.2 Crystal OscillatorAlternatively, a Crystal Oscillator may be used. The accuracy of a crystal oscillator depends on the crystal tolerance as well as the load capacitance tolerance. Typically, for a 20MHz crystal specified with a 32pF load capacitance, each 1pF change in load capacitance contributes approximately 9ppm to the frequency deviation. Consequently, capacitor tolerances and stray capacitances have a major effect on the accuracy of the oscillator frequency.The crystal should be a fundamental mode type - not an overtone. The fundamental mode crystal permits a simpler oscillator circuit with no additional filter components and is less likely to generate spurious responses. A typical crystal oscillator specification is shown in Table 2..1Frequency20MHz2Tolerance as required (better than +/-50ppm)3Oscillation mode fundamental4Resonance mode parallel5Load capacitance as required6Maximum series resistance50ΩTable 2 - Crystal Oscillator SpecificationZL30111Data Sheet5.3 Power Up SequenceThe ZL30111 requires that the 3.3V supply is not powered up after the 1.8V supply. This is to prevent the risk of latch-up due to the presence of protection diodes in the IO pads. Two options are given:1. Power-up the 3.3V supply fully first, then power up the 1.8V supply2. Power up the3.3V supply and the 1.8V supply simultaneously, ensuring that the 3.3V supply is never lower than a few hundred millivolts below the 1.8V supply (e.g., by using a schottky diode or controlled slew rate)5.4 Reset CircuitA simple power up reset circuit with about a 60µs reset low time is shown in Figure 6. Resistor R P is for protection only and limits current into the RST pin during power down conditions. The reset low time is not critical but should be greater than 300ns.Figure 6 - Power-Up Reset Circuit+3.3 V RSTR P 1 k ΩC 10 nFR 10 k ΩZL30111ZL30111Data Sheet6.0 Characteristics6.1 AC and DC Electrical Characteristics* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.* Voltages are with respect to ground (GND) unless otherwise stated.* Voltages are with respect to ground (GND) unless otherwise stated.Absolute Maximum Ratings*ParameterSymbol Min.Max.Units 1Supply voltage V DD_R -0.5 4.6V 2Core supply voltage V CORE_R -0.5 2.5V 3Voltage on any digital pin V PIN -0.56V 4Voltage on OSCi and OSCo pin V OSC -0.3V DD + 0.3V 5Current on any pin I PIN 30mA 6Storage temperatureT ST -55125°C 7TQFP 64 pin package power dissipation P PD 500mW8ESD ratingV ESD2 kVRecommended Operating Conditions*CharacteristicsSym.Min.Typ.Max.Units 1Supply voltage V DD 3.1 3.30 3.5V 2Core supply voltage V CORE 1.7 1.80 1.9V 3Operating temperature T A -402585°C 4Input VoltageV I3.33.5VZL30111Data Sheet* Supply voltage and operating temperature are as per Recommended Operating Conditions.* Voltages are with respect to ground (GND) unless otherwise stated.* Supply voltage and operating temperature are as per Recommended Operating Conditions.* Voltages are with respect to ground (GND) unless otherwise stated.Figure 7 - Timing Parameter Measurement Voltage LevelsDC Electrical Characteristics*CharacteristicsSym.Min.Max.Units Notes1Supply current with: OSCi = 0 VI DDS 3.0 6.5mA outputs loaded with 30 pF2OSCi = Clock, OUT_SEL=0I DD 3247mA 4Core supply current with: OSCi = 0 VI CORES 022µA 5OSCi = Clock I CORE 1420mA 6Schmitt trigger Low to Highthreshold pointV t+ 1.43 1.85V All device inputs are Schmitt trigger type.7Schmitt trigger High to Low threshold point V t-0.80 1.10V 8Input leakage current I IL -105105µA V I = V DD or 0 V9High-level output voltageV OH2.4VI OH = 8mA for clock and frame-pulse outputs, 4mA for status outputs 10Low-level output voltageV OL0.4VI OL = 8mA for clock and frame-pulse outputs, 4mA for status outputsAC Electrical Characteristics* - Timing Parameter Measurement Voltage Levels (see Figure 7)CharacteristicsSym.CMOS Units Notes1Threshold voltageV T 0.5xV DD V 2Rise and fall threshold voltage high V HM 0.7xV DD V 3Rise and fall threshold voltage lowV LM0.3xV DDVt IR, t ORTiming Reference PointsALL SIGNALSV HM V T V LMt IF, t OFZL30111Data Sheet* Supply voltage and operating temperature are as per Recommended Operating Conditions.* Period Min/Max values are the limits to avoid a single-cycle fault detection. Short-term and long-term average periods must be within Out-of-Range limits.* Supply voltage and operating temperature are as per Recommended Operating Conditions.Figure 8 - Input to Output TimingAC Electrical Characteristics* - Input Timing (see Figure 8)CharacteristicsSymbol Min.Typ.Max.Units 18 kHz reference period t REF8KP 121125128µs 2 2.048 MHz reference period t REF2P 263488712ns 38.192 MHz reference period t REF8P 63122175ns 419.44 MHz reference period t REF16P 385175ns 5reference pulse width high or lowt REFW15nsAC Electrical Characteristics* - Input to Output Timing (see Figure 8)CharacteristicsSymbol Min.Max.Units 18kHz reference input to F8o delay t REF8KD 08ns 2 2.048MHz reference input to C2o delay t REF2D 210ns 3 2.048MHz reference input to F8o delay t REF2_F8D 210ns 48.192MHz reference input to C8o delay t REF8D 513ns 58.192MHz reference input to F8o delay t REF8_F8D 513ns 619.44MHz reference input to F8o delayt REF9D_F8D8nsREFt REF<xx>Pt REF8kD , t REF<xx>_F8Dt REFWt REF<xx>Dt REFWF8ooutput clock with the same frequency as REF。
Optimal Design Methodology for LLC Resonant Converter
Optimal Design Methodology forLLC Resonant ConverterBing Lu, Wenduo Liu, Yan Liang, Fred C. Lee, Jacobus D. van WykCenter for Power Electronics SystemsVirginia Polytechnic Institute and State University674 Whittemore Hall Blacksburg, VA 24061 USAAbstract: Although LLC resonant converter can achieve wide operation range with high efficiency, lack of design methodology makes it difficult to be implemented. In this paper, based on the theoretical analysis on the operation principles during normal condition and holdup time, the relationship between converter efficiency and operation range with different circuit parameters has be revealed. An optimal design methodology has been developed based on the revealed relationship. A 1MHz, 1kW LLC converter is designed to verify the proposed method.I. I NTRODUCTIONWith the development of power conversion technology, power density becomes the major challenge for front-end AC/DC converters [1] [2] [3]. Although increasing switching frequency can dramatically reduce the passive component size, its effectiveness is limited by the converter efficiency and thermal management design. Meanwhile, to meet the holdup time requirement, bulky capacitors have to be used to provide the energy during holdup time, which is only affected by DC/DC stage operation input voltage range [1]. The relationship between holdup time capacitor requirement and minimum DC/DC stage input voltage for different front-end converter power levels is shown in Figure 1. Apparently, wide operation range DC/DC stage can reduce the holdup time capacitor requirement and improve the system power density. However, when the minimum voltage is less than 200V, very limited effects can be observed.2004006008001000DC/DC minimum operation voltage (V)Holdup time cap requirement (uF)Figure 1. Holdup time capacitor requirement for DC/DC stage withdifferent minimum input voltage.To reduce the holdup time capacitor requirement,different research efforts have been implemented, by usingextra holdup time extension circuit or by developing bettertopologies [4][5][6]. Among different solutions, LLC resonantconverter becomes the most attractive topology due to its highefficiency and wide operation range.LFigure 2. LLC Resonant Converter.0.20.40.60.811.21.4f/f0nVo/(Vin/2)Figure 3. Gain Characteristic of LLC Converter.The LLC resonant converter topology is shown in Figure 2. By utilizing the transformer magnetizing inductance, LLC converter modifies the gain characteristic of series resonant converter (SRC). Its voltage gain characteristics for different loads are shown in Figure 3, due to the half bridge structure,the output voltage is normalized with half of the input voltage. Comparing with SRC, the converter can achieve both Buck mode and Boost mode. When the switching frequency is higher than resonant frequency, voltage gain of LLC converter is always less than one, and it operates as an SRC converterand zero voltage switching (ZVS) can be achieved. When the switching frequency is lower than resonant frequency, fordifferent load conditions, both ZVS and zero current switching(ZCS) could be achieved. At the boundary of ZVS and ZCSregions, as shown in the dashed line in Figure 3, convertervoltage gain reaches it maximum value.According to the circuit operation analysis [4], at the resonant frequency, because the impedance of resonant tank, constructed by L r and C r , is zero, input and output voltages are virtually connected together. Thus, converter voltage gain is equal to one for all the load conditions. When the input AC line exists, DC/DC stage input voltage is generated by PFC stage and it is regulated at 400V. At this condition, by choosing a suitable transformer turns ratio, converter could always operate at resonant frequency. Therefore, the conduction loss and switching loss can be minimized. During holdup time, energy transferred to the load comes from bulky holdup time capacitor. While DC/DC input voltage keeps decreasing, converter reduces its switching frequency to operate in Boost mode and regulate output voltage. Due to the complexity of resonant tank, design of the LLC resonant converter needs to consider three key elements, resonant frequency, characteristic factor, and inductor ratio,rr C L f π210=(1) R n C L Q rr /= (2) rm n L L L = (3)Here f 0 is the resonant frequency, which defines the switching frequency of LLC resonant converter. The characteristic factor Q is the ratio between the characteristicimpedance and the load. L n is defined as the ratio between the magnetizing inductance and the resonant inductance.Although different literatures [9]-[11] have discussed operation principles and benefits of the topology, there is no design guideline developed. Moreover, instead of simply choosing Q value in the conventional SRC or PRC design, LLC requires defining two coupled elements L n and Q.Apparently, try and error method could result in a good design. However, it is time consuming and not cost effective. As a result, the topology is difficult to be adopted by theindustries. In this paper, based on the analysis of LLCresonant converter at different operation conditions, includingthe normal operation and during holdup time, an optimaldesign methodology has been developed. Based on the developed method, designed LLC converter can achieve maximum efficiency with desired operation range, which is verified by a 1MHz LLC resonant converter.II. C IRCUIT O PERATION A NALYSIS O F LLC R ESONANT C ONVERTER A. Normal Operation AnalysisAt normal operation condition, LLC converter inputvoltage is regulated by PFC stage. From the gain characteristiccurves shown in Figure 3, converter gain can keep constant at resonant frequency. Therefore, by designing a suitable transformer turns-ratio to make the converter voltage gainequal to one, at normal operation condition, LLC resonant converter can always operate at its resonant frequency for different load conditions. For most of the time, front-end converter is operating under this operation mode. Therefore, the efficiency at resonant frequency is the key aspect for the LLC converter performance.According to the operation of LLC resonant converter, at resonant frequency, resonant tank current is a pure sinusoidal waveform as shown in Figure 4. The dashed line is the magnetizing inductor current. The equivalent circuit of the operation is shown in Figure 5. At first half line cycle, resonant tank current i r resonates up. At the same time, output voltage is applied to magnetizing inductor. Therefore, the magnetizing inductor current increases linearly. At the end of this half switching cycle, primary switch turns off with peak magnetizing inductor current, and the other switch turns on under ZVS condition with same current. During the other half line cycle, the resonant tank current keeps resonant and output voltage is applied to the magnetizing inductor with reverse polarity. Therefore, the magnetizing inductor current decreases linearly. Thus, a square wave voltage is applied to the magnetizing inductor, and the magnetizing inductor current is a triangle shape as shown in the dashed line in Figure 4. Moreover, at the end of each half switching cycle, magnetizing inductor current reaches its maximum value andthe resonant tank current gets the same value at the same time. Figure 4. Resonant Tank Current Waveform at Resonant Frequency.Figure 5. Equivalent circuit at resonant frequency. The magnetizing inductor peak current can be determined by 4TL nV I m opk = (4) Here n is the transformer turns ratio between the primaryside and secondary side, V O is the output voltage, T is theswitching cycle and L m is magnetizing inductance. Since the resonant tank current at resonant frequency is a sinusoidal wave, it can be represented by the equation)2sin(20φπ+=f I I rms r (5) Here I rms is the resonant tank RMS current, and f 0 is the resonant frequency and φ is the initial angle of the resonant tank current, which represent the phase difference between theresonant tank current and magnetizing inductor current. According to the current waveforms, at the end of each half switching cycle, magnetizing inductor current is equal to the resonant tank current, which means4/)sin(2T L nV I m orms =φ (6)On the other hand, the difference between resonant tankcurrent and magnetizing inductor current is the currenttransferred to the load, thus2)(2/0TnR V dt i i L O T m r =−∫(7) Here R L is the load resistance, n is the transformer turns ratio.By summarizing these equations, the resonant tank RMScurrent can be solved as222248281π+=m L L O rms L T R n nR V I (8) Here V O is the output voltage, n is transformer turns-ratio, R L is load resistance, T is switching cycle at resonantfrequency, and L m is the magnetizing inductance.Since the resonant tank current continuously flows troughthe primary side switches, its RMS value determines the primary side conduction loss. Comparing with the load currentreflected to primary side, resonant tank RMS current is only related to the magnetizing inductance, the load resistance and the switching cycle. While the switching cycle and load resistance are predetermined values for certain converter specifications, resonant tank RMS current is only determined by the magnetizing inductance. Besides the primary side conduction loss, secondary side rectifier conduction loss is also a major concern. For diode rectifier, its conduction loss major comes from diode forward voltage drop and is proportional to the average output current. However, if considering synchronous rectification, it is also desirable to minimize the secondary side RMS current. Since we already get the formulas for both the resonant tank current and magnetizing inductor current, secondary side current can be easily calculated. Based on previous analysis, secondaryRMS can be expressed as1124854122422_+−=m L LO SRMS L T R n nR V I ππ (9)From this equation, same as the primary side RMS current, secondary side RMS current is also entirely determined by the magnetizing inductance.Based on the analysis o the LLC resonant converter operating at resonant frequency, the converter conduction loss is mainly affected by the magnetizing inductance, instead of resonant inductor or the resonant capacitor. At the same time, the primary side switches can achieve ZVS for all the load conditions, the switching loss is mainly coming from the turnoff loss, which is also depends on the magnetizing inductance. Therefore, to design a high efficiency LLC resonant converter, it is essential to find a suitable magnetizing inductor. B. Holdup Time Operation AnalysisDuring the holdup time, input AC line doesn’t exist and PFC stage no longer provides energy to DC/DC stage. All the energy transferred to the load during holdup time is purelycoming from holdup time capacitor. Therefore, the inputvoltage of DC/DC stage will keep decreasing during holduptime. To maintain regulated output voltage, switchingfrequency of the LLC resonant needs to be reduced so that the converter gain can be boosted up. Different from PWMconverters, LLC converter could achieve highest efficiency at high input voltage. During holdup time, the converter operatesfar away from its resonant point and has less efficiency. However, the holdup time only requires 20mS, and lowefficiency could be tolerated and would not cause excessthermal stress.Because the transformer turns ratio is a fixed value, the required gain is determined by the relationship between the input and output voltage, which can be represented by2/in OV nV g = (10) Here, g is the required voltage gain for LLC converter, V O is the output voltage and V in is the input voltage. From thisequation, lower the input voltage, higher the voltage gain is required. As shown in Figure 1, the holdup time capacitor requirement is largely affected by the operation range of the DC/DC stage. Wider operation range can dramatically reduce the holdup time capacitor requirement and improve the whole converter power density. Therefore, wide operation range ofDC/DC stage is desired. The operation range of LLC converter is decided by the peak voltage gain that can be achieved. At normal operation mode, input voltage is 400V and LLC has a voltage gain equal to one. If the converter can achieve a maximum gain of 2, it will be able to regulate output voltage with 400/2=200V input. Obviously, the higher the peak gain, the wider the operation range of LLC resonant converter.Figure 6. Resonant tank current at peak gain pointFrom gain characteristic curves in Figure 3, the peak gain happens when the circuit is running at the boundary of zero current switching (ZCS) and zero voltage switching (ZVS) modes. The resonant tank current at this condition is shown in Figure 6. In each half switching cycle, the magnetizing inductor is firstly charged by the output voltage. After that, itparticipates in the resonance (the resonant tank is constructed by L r, C r and L m) and transfers it stored energy to the resonant capacitor. At the end of each half switching cycle, its current is reset to zero. Therefore, entire energy stored in the magnetizing inductor can be transferred to the load, and the converter gain reaches its peak value. Although the peak gain can be calculated based on the current waveform, it is difficult to solve the equations and get the analytical solution. Therefore, to simplify the analysis, peak gains at different L n and Q combinations are simulated based on the simulation tool Simplis, which can automatically reach the circuit steady state within short simulation time. The peak gains for different L n and Q values are summarized in the contour curves in Figure 7. In this set of curves, each line shows the combinations of different L n and Q values that can achieve same peak voltage gain. For instance, if we want to design a converter with a peak gain of 1.3, any combination of L n and Q along the line 1.3 can be chosen as a valid design.LnQFigure 7. Relationship between converter peak gain and L n, Q Apparently, peak gain is affected by both L n and Q values. By reducing L or Q value, higher peak gain can be achieved.III. D ESIGN M ETHODOLOGY FOR LLC R ESONANT C ONVERTER The LLC resonant converter design goal is to achieve minimum loss with the capability of achieve required maximum gain to ensure wide operation range. According to previous analysis, the relationships between the design parameters L n and Q with the converter performance, especially the conduction loss and the operation range, is revealed. These relationships can be used to develop an optimal design methodology of LLC resonant converter.LLC resonant converter operates under normal operation condition at most of the time. When the input Ac line exists, the DC/DC stage input voltage is a regulated 400V. Therefore, LLC converter could always operates at resonant frequency and achieve optimal efficiency. Thus, it is essential to minimize the loss when converter operates at resonant frequency. Based on the operation analysis at resonant frequency, both the primary and secondary conduction loss is purely determined by the magnetizing inductance, as shown in the following equation:222248281π+=mLLOrms LTRnnRVI(11)1124854122422_+−=mLLOSRMSLTRnnRVIππ(12)Therefore, to minimize conduction loss, the magnetizing inductance should be maximized to reduce RMS currents on primary side and secondary side. In turn, the copper loss of the magnetic components can also be reduced.To achieve high power density, high switching frequencyis always desired, because the passive component size reduces dramatically with increasing switching frequency. However, the switching loss increases linearly with the switching frequency. Therefore, it is also important to minimize the LLC converter switching loss.Based on the operation analysis, LLC converter primary side switches can achieve ZVS turn on for all the load conditions. However, the ZVS condition is ensured by the peak magnetizing current, which can be calculated as4TLnVImopk=(13)Here, n is transformer turns ratio, V O is output voltage, L mis the magnetizing inductance and T is the switching cycle. During the primary side switches commutating period, due to the large magnetizing inductance, the magnetizing inductor current can be assumed to be constant. To ensure ZVS turn on, the peak magnetizing inductor current should be able to discharge MOSFETs junction capacitors within dead time, which can be represented bydeadjbuspk tCVI2> (14)Here V bus is input bus voltage, C j is MOSFET junction capacitance and t dead is the dead time.Although the large turn off current can ensure soft switching condition, it results in larger turn off loss, because primary side switches turning off is hard switching. Therefore smaller turn off current is desirable to reduce turn off loss.By summarizing previous analysis, to achieve minimum conduction loss, the magnetizing inductance is required to be as large as possible. To ensure minimum switching loss, the magnetizing inductor needs to be smaller enough to achieve ZVS condition and large enough to have smaller turn off current. Therefore, considering both conduction loss and switching loss, the optimally designed L m should make the primary side turn off current exactly the same as ZVS requirement. Thus,jdeadm CtTL16⋅= (15)According to the definition of L n and Q r mn L L L =(16)Lr r R n C L Q = (17)together with the resonant frequency rr C L f π210=(18)we can calculate magnetizing inductance asL n m R n Q L f L 202π= (19) Based on this equation, it can be seen that, as long as the production of L n and Q keeps constant, L m is a fixed value. Or in other words, for a designed magnetizing inductance, the relationship between L n and Q is fixed. Once an L n value is chosen, the corresponding Q value can be designed.Besides the converter efficiency, the other major aspect of LLC converter is its operation range. Although the converter efficiency is mainly defined by the magnetizing inductance, the L n and Q value could affect the gain characteristic of LLC resonant converter. As discussed before, wide operation range LLC resonant converter can reduce the holdup time capacitor requirement and improve system power density. To achieve the desired operation range, peak gain is required to be higher than certain level.A 200 kHz 1kW LLC resonant converter with operation range from 250V to 400V is chosen as an example. In this case, the peak voltage gain is required to be larger than 400/250=1.6. From Figure 7, all the L n and Q combinations below line 1.6 could meet the gain requirement. However, this results in infinite solutions for the converter design. Furthermore, considering normal operation efficiency, magnetizing inductance is expected to be maximized. Based on the analysis on the magnetizing inductance, we can get the magnetizing inductance should bedsdeadm C t T L 16⋅=(20) For 200 kHz switching frequency and 100nS dead time, together with 450pF C j (IXFH21N50), we can easily calculate the magnetizing inductance should be around 70uH.Therefore, for required magnetizing inductance of 70uH, a marked line can be added to Figure 7, the peak gain curves, as shown in Figure 8. All the designs along the marked line will have the same magnetizing inductance, which ensures maximum efficiency at normal operation condition. Comparing with peak gain curves, L n has to be larger than 5.5 to meet the gain requirement. However, along the marked line, there could be infinite solutions for the valid design. To further pickup a suitable value for the L n and Q combination,we need to further consider the L n and Q impacts on the circuit operations.LnQFigure 8. Design example of LLC converterAs shown in Figure 9, the gain characteristics for different L n values are summarized. It shows that the larger L n will increase the frequency range of LLC resonant converter. Although at normal operation condition, PFC stage generates a regulated 400V bus, due to the line frequency ripple, LLC converter still needs to do switching frequency modulation to regulated output voltage. Therefore, the switching frequency range should be as small as possible, which requires a minimum L n value. However, larger L n makes it easier to use the transformer leakage inductance to realize the resonant inductor. Therefore, trade off between the converter size and efficiency can be carried out and determine the L n value. Based on the chosen L n and Q values, L r and C r can be calculated accordingly.Figure 9. L n impacts on LLC converter voltage gainIV. E XPERIMENTAL IMPLEMENTATIONTo verify the theoretical analysis, a 1MHz, 1kW LLC resonant converter with wide input voltage range (200V to 400V) and 48V output is designed based on the proposed methodology. To ensure soft switching and minimize turn off loss, the magnetizing inductance is chosen as 14uH. L n is designed as 17 to utilize the transformer leakage inductance, which results in a 0.8uH resonant inductance. The resonant capacitor can be designed accordingly as 33nF.The experimental waveforms at resonant frequency and during holdup time are shown in Figure 10 and Figure 11, respectively. From the experimental results, at resonant frequency, soft switching can be achieved with minimum turn off current. By changing L r and C r combination, the waveform keeps the same, which verifies the analysis that the loss purely relies on the magnetizing inductance. During holdup time, the converter has to reduce switching frequency to boost up voltage gain. As shown in Figure 12, most of the energy stored in the magnetizing inductor is transferred back to the resonant capacitor and gain can be achieved higher than 2. The efficiency curve of the 1MHz LLC resonant converter for different load conditions is shown in Figure 12. The efficiency is more than 92.5% efficiency at full load condition.Resonant tank current (5A/div)Vds (100V/div)Vdiode (100V/div)200nS/divFigure 10. Experimental waveform at resonant frequencyResonant tank current (10A/div)Vds (100V/div)400nS/divFigure 11. Experimental waveform during holdup time20040060080010001200Po(W)E f f i c i e n c yFigure 12. Efficiency of 1MHz LLC resonant ConverterV. S UMMARYSmaller switching loss and the capability of wide input range operation makes LLC resonant converter attractive for front-end AC/DC converters. However, because of its complexity, lack of design method makes the converter less valuable. In this paper, based on the theoretical analysis on the circuit operation at resonant frequency and maximum gain point, the relationship between the converter loss and operation range has been revealed. Based on the relationship, the converter efficiency can be optimized with a suitable magnetizing inductance design. Moreover, by choose L n and Q from the peak gain curves, the operation range of the LLC resonant converter can be ensured. The developed methodology has been implemented into a 1MHz 1kW LLC resonant converter design. The experimental results also verify the theoretical analysis.A CKNOWLEDGMENTThis work made use of ERC Shared Facilities supported by the National Science Foundation under Award Number EEC-9731677. The author would like to acknowledge Ferroxcube provide 3F4 core sample, Ansoft providing Maxwell simulation software, Transim Technology provides Simplis software and NSF providing the research funding.R EFERENCES[1] B. R. Mower, “SSI: building compliant power elements for servers,” inIEEE-APEC Proc., 1999, pp. 23-27[2] J.D. van Wyk, F.C. Lee, D. Boroyevich, Z. Liang; K. Yao, “A futureapproach to integration in power electronics systems,” IEEE-IECON '03. Volume: 1, pp. 1008-1019[3] F.C. Lee, J.D. van Wyk, D.Boroyevich, G. Lu; Z. Liang; P.Barbosa,“Technology trends toward a system-in-a-module in power electronics,” Circuits and Systems Magazine, IEEE , Volume: 2 Issue: 4 , 2002, Page(s): 4 –22[4] B. Yang, F.C. Lee, A.J. Zhang, G. Huang, “LLC resonant converter forfront end DC/DC conversion,” in IEEE-APEC 2002, pp. 1108-1112[5] Y. Jang; M.M. Jovanovic, D.L. Dillman, “Hold-up time extension circuitwith integrated magnetics,” IEEE APEC’05. pp. 219 - 225[6] Y. Xing; L. Huang; X. Cai; S. Sun; “A combined front end DC/DCconverter,” IEEE APEC’03, pp.1095 – 1099[7] G. Ivensky, S. Bronstein, S. Ben-Yaakov, “Approximate analysis of theresonant LCL DC-DC converter,” in IEEE Electrical and Electronics Engineers in Israel, 2004. Proceedings, pp. 44-47[8] A. K. S. Bhat, “Analysis and design of LCL-type series resonantconverter,” IEEE Transactions on Industrial Electronics, Volume: 41, Issue: 1 , Feb. 1994 , pp.118 – 124[9] J.F. Lazar, R. Martinelli, “Steady-state analysis of the LLC seriesresonant converter,” IEEE APEC’01pp. 728 - 735[10] I. Batarseh, R. Liu, A. Ortiz-Conde, A. Yacoub, K. Siri, “Steady stateanalysis and performance characteristics of the LLC-type parallel resonant converter,” PESC’94, pp. 597 - 606[11] A.K.S. Bhat, “Analysis and design of LCL-type series resonantconverter,” Industrial Electronics, IEEE Transactions on Volume 41, Issue 1, Feb. 1994 Page(s):118 – 124。
SILICON LABORATORIES C8051F340 数据手册
C8051F340USB, 48 MIPS, 64 kB Flash, 10-Bit ADC, 48-Pin Mixed-Signal MCUAnalog Peripherals10-Bit ADC-±1 LSB INL; no missing codes-Programmable throughput up to 200 ksps-Up to 17 external inputs; programmable as single-ended or differential -Built-in temperature sensor (±3 °C)Two ComparatorsInternal Voltage Reference: 2.4 V POR/Brown-out DetectorUSB Function Controller-USB specification 2.0 compliant-Full-speed (12 Mbps) or low-speed (1.5 Mbps) operation-Integrated clock recovery; no external crystal required for either full-speed or low-speed operation -Supports eight flexible endpoints -Dedicated 1 kB USB buffer memory-Integrated transceiver; no external resistors requiredOn-Chip Debug-On-chip debug circuitry facilitates full speed, non-intrusive in-system debug (no emulator required)-Provides breakpoints, single stepping-Inspect/modify memory, registers, and USB memory-Superior performance to emulation systems using ICE-chips, target pods, and socketsTemperature Range: –40 to +85 °CHigh-Speed 8051 µC Core-Pipelined instruction architecture; executes 70% of instructions in 1 or 2 system clocks-Up to 48 MIPS throughput with 48 MHz Clock -Expanded interrupt handlerMemory-4352 bytes data RAM (256 + 4 kB)-64 kB Flash; in-system programmable in 512-byte sectors (512 bytes are reserved)-External parallel data memory interfaceDigital Peripherals-40 port I/O; all are 5 V tolerant-Hardware SMBus™ (I 2C™ compatible), SPI™, and 2 UART serial ports available concurrently- 4 general-purpose 16-bit counter/timers-Programmable 16-bit counter array with 5 capture/compare modules Clock Sources-Internal oscillator: 0.25% accuracy with clock recovery enabled; supports all USB and UART modes-External oscillator: Crystal, RC, C, or Clock -On-chip clock multiplier: up to 48 MHzVoltage Regulator-On-chip voltage regulator supports USB bus-powered operation -Regulator bypass mode supports USB self-powered operationOperating Voltage: 2.7 to 5.25 V Package-48-Pin TQFP (lead-free package)Ordering Part Number-C8051F340-GQUC8051F340DK Development KitPackage Information。
Operational Manual
P. Oostenrijk P. Oostenrijk
3.28 3.29
01-10-2007 05-22-2007
P. Oostenrijk P. Oostenrijk
4.00
02-19-2008
P. Oostenrijk
4.01 4.02 4.03
ECHOTRAC MKIII
USER MANUAL Version: 4.03
Odom Hydrographic Systems, Inc. 1450 Seaboard Avenue Baton Rouge, Louisiana USA 70810-6261 Telephone: (225) 769-3051 Fax: (225) 766-5122
1.4
02-16-2005
S.F. Apsey
3.20 3.22
01-16-2006 02-28-2006
P. Oostenrijk P. Oostenrijk
3.23
05-22-2006
P. Oostenrijk
3.25
08-03-2006
P. Oostenrijk
Echotrac MKIII
User Manual
Email@
Number of pages: 50 Date: May 23, 2008
Echotrac MKIII
User Manual
Revision History
Version 0.1 1.0 1.1 1.2 Date 09-19-2002 01-28-2003 03-27-2003 09-09-2003 Author P. Oostenrijk S.F. Apsey S.F. Apsey S.F. Apsey Remarks Initial version – draft Updated manual for firmware version 2.07;Changed default of Tracking Gate. Added Skip Alarms. Added Grey shades. Updated manual for firmware version 2.14: Added Subottom TVG, SB TVG Range, Pre Amp Gain, Dual Light Shade parameters. Changes from Echotrac MKIII 3.05 to 3.06 1-When the Echotrac MKIII is set to read in heave through com4 it will check to see if the first character in the string is an ‘R’ (remote heave). If the first character is an ‘R’ the Echotrac will use the remote heave value for corrections otherwise the Echotrac will use the local heave. 2-Added a parameter called HEAVECORR. This parameter will heave correct the chart when turned on or not heave correct the chart if turned off. The selection of the ‘Heave Out’ serial string will now no longer affect the heave correction on the chart. 3-The parameter DIGILINE will now have a range of 0,1,2,3,4,5,6,7,8,9,10 instead of on or off. When set to 0 the digitizer line will not be printed. If set to any other number, the digitizer line will be printed that many units above the raw bottom. 4-The parameter LIGHTSHADE will now have the selections Chnl2 Dark, Chnl1 Dark, Chnl2 Only and Chnl1 Only. This will reflect how the data and what data will be printed when both channels are turned on. If Chnl2 Dark is selected, Channel 2 will be printed darker than Channel 1. If Chnl2 only is selected then only Channel 2 will be printed. 3.08 04-14-2005 P. Oostenrijk Updated manual for firmware version 3.08 Added section on how to request parameter settings through the serial port. Added UDP port, Hours of operation, Packet size 8/16 bits, outputstring DESO DDV, print German Help. New optimized Deso command handling routines. Re-enabled TVGgainref and Trackinggate in Echotrac Control program. Improved annotation handling. Improved Echotrac Control program network detection interface. Low Frequency pulse width increased to 256. Corrected auto-scaling when draft and index are used. Added support for Echotrac CVM. Fixed: Stopping the synchronization process disabled communication with Echotrac. Added compatibility check and warning for Echotrac Control Program version and Echotrac firmware version. If during synchronization a parameter is missing, the parameter name is now displayed. Improved version control in firmware and diagnostic window. Page 2 of 2 Odom Hydrographic Systems, Inc. May 23, 2008
Macro Converter H 用户手册说明书
The information in this document is furnished for informational use only, is subject to change without notice, and should not be construed as a commitment by Victor Hasselblad AB. The text and images in this document cannot be reprinted or reused without the express permission of Victor Hasselblad AB. Victor Hasselblad AB assumes noresponsibility or liability for any errors or inaccuracies that may appear in this document. Victor Hasselblad AB assumes no responsibility or liability for loss or damage incurred during or as a result of using Hasselblad products. Copyright © 2013 - Victor Hasselblad AB. All rights reserved.Document ID: Macro Converter H / 3023720 / User Manual D / V2 / 2013Macro Converter HThe Macro Converter H (3023720) is designed to improve the close range performanceof wide angle H system lenses. It is primarily intended for use with the HC 50-II lens for optimum performance. The range produced is similar to the use of a 6.6 mm exten-sion tube but the performance is noticeably improved.It features the same outstanding optical and mechanical quality as all the elementsin the Hasselblad HC/HCD lens system. All the glass-to-air surfaces have a multi-layer coating to reduce internal reflections and increase the efficiency of the optical system. The Macro Converter H can only be used together with Hasselblad HC/HCD lenses. Attempts to attach any other type of lens may cause damage.General The Macro Converter is not compatible with the following:• HCD 4–5.5 / 35–90mm Zoom (3023590) • HC 3.5–4.5 / 50–110mm Zoom (3023511)All other HC and HCD lenses (including the HTS 1.5x) can be used but optical performance is optimized when used together the HC 50-II lens (3023052).To obtain the optimum performance with any lens combination, please ensure you have the latest sensor-unit firmware installed and that you use the latest version of Phocus.Attaching and removing the converter The Macro Converter is mounted between the camera and lens in the same manner as an extension tube.Technical Specifications Focal length conversion factor: 1.0x Aperture reduction: 0 stopsLength/diameter: 19.5 mm / 84 mm Weight:182 gOptical design:3 lenses in 2 groupsVisit to download user manuals, datasheets, product brochures, technical information, technical articles, soft-ware and firmware updates etc., as well as news about the latest developments at Hasselblad .Använd “Google Translate”på Internet.Deze tekst in uw taal?Gebruik ‘Google Translate’ op het internet.NLD JPN CHN IND RUS SAUCe texte dans votre langue? Utilisez “Google Translate” sur Internet.Diesen Text in Ihrer Sprache? Verwenden Sie “Google Translate” im Internet.Este texto en su idioma? El uso de “Google Translate” en Internet.Questo testo nella tua lingua? Utilizzare ‘Google Translate’ su Internet.Este texto na sua língua? Usar “Google Translate” na Internet.Denna text på ditt språk? Använd “Google Translate”på Internet.FRADEUESPITAPRTSWECe texte dans votre langue?Utilisez “Google Translate” sur Internet.Diesen Text in Ihrer Sprache?Verwenden Sie “Google Translate” im Internet.Este texto en su idioma?El uso de “Google Translate” en Internet.Questo testo nella tua lingua?Utilizzare ‘Google Translate’ su Internet.Este texto na sua língua?Usar “Google Translate” na Internet.Denna text på ditt språk?Använd “Google Translate”på Internet.Deze tekst in uw taal?Gebruik ‘Google Translate’ op het internet.FRADEUESPITAPRTSWE NLD JPNCHN IND RUS SAUPerformance The MTF diagrams to the right show the dramatic increase in performance when using the Macro Converter H at close range.Lens: HC 50-II Distance: 0,6m Aperture:f/8sing range with Macro Convertersing range for lens without Macro Converterph shows the effect on close range use for the H systemwhen using the Macro Converter.020406080100102030Image height (mm)M T F (%)f/8g range with Macro Converter g range for lens without Macro Converter shows the effect on close range use for the H system hen using the Macro Converter.020406080100102030Image height (mm)M T F (%)f/8The following graph shows the effect on close range use for the H system wide angle lenses when using the Macro Converter H.Focusing range with Macro Converter HFocusing range for lens without Macro Converter H HCD 24HCD 28HC 35HC 50The following graph shows the effect on close range use for the H systemwide angle lenses when using the Macro Converter.08.12 - M a c r o C o n v e r t e r - V 1 - U KS p e c i fi c a t i o n s u b j e c t t o c h a n g e w i t h o u t n o t i c e .0000PERFORMANCEThe MTF diagrams to the right show the dramatic increase inperformance when using theMacro Converter at close range.Lens: HC 50-IIDistance: 0,6mAperture: f/8HCD 24HCD 28HC 35HC 50The following graph shows the effect on close range use for the H system wide angle lenses when using the Macro Converter.08.12 -M a c r o C o n v e r t e r - V 1 - U K S p e c i fi c a t i o n s u b j e c t t o c h a n g e w i t h o u t n o t i c e .000 PERFORMANCEThe MTF diagrams to the rightshow the dramatic increase inperformance when using theMacro Converter at close range.Lens: HC 50-IIDistance: 0,6mAperture: f/80.6 / 2.00.5 / 1.60.4 / 1.3Subject distance [m / ft ]Focusing range with Macro Converter Focusing range for lens without Macro Converter0.3 / 1.00.2 / 0.660.1 / 0.33HCD 24HCD 28HC 35HC 50-II。
RECOM 电源 RACAC DC 转换器 PA-1 产品说明书
RAC AC/DC Conver er4 Watt Single OutputRAC04-K/277IEC60950-1 certified IEC62368-1certified UL62368-1 certifiedCSA/CAN C22.2 No. 62368-1-14 certified EN62368-1 compliant EN60335-1 compliant EN61010-1 compliant IEC/EN61558-1 compliant IEC/EN61558-2-16 compliant EN55032 compliant EN55024 compliantEN55014-1 /-2 compliant IEC/EN61204-3 compliant FCC 47 Part 15CB ReportSelection GuidePart Input Output Output Efficiency Max. CapacitiveNumber Voltage Range Voltage Current (1) typ. (2)Load [(VAC] [VDC] [mA] [%] [µF)RAC04-05SK/277 80-305 5 800 76 7200RAC04-12SK/277 80-305 12 333 78 1000RAC04-15SK/277 80-305 15 267 80 820RAC04-24SK/277 80-305 24 167 80 220On RequestRAC04-3.3SK/277 80-305 3.3 1200 73 10000Notes:Note1: Refer to “Line Derating“ graphNote2: Measured @ 230VAC/50Hz at +25°C with constant resistant mode at full loadDescriptionThe RAC04-K/277 series delivers an uncompromising 4 watts of continuous output power (6W peak) in harsh industrial and household environments. These modules deliver full load output power from -40°C to 75°C across the entire input range of 80VAC to 305VAC and are certified for operation with power derating up to 90°C air ambient. A peak load capability of up to 150% supports dynamic power demands of applications. This series of fully encapsulated AC/DC modules is a complete solution without the need for external components which supports Ecodesign Lot 6 standby mode operation for worldwide applications in automation, industry 4.0, IoT, household, and home automation. With international safety and EMC certifications for industrial, domestic, ITE, and household applications, these are some of the most versatile power modules on the market. Due to their reinforced class II installation rating for floating outputs and their significantly wide margin to class B emissions compliance without external components and a certified 4kV AC (5.25 kV DC) isolation, these are the easiest to use modular power solutions in the industry.nom. Output Power nom. Output VoltageRAC04-__ SK/277Model NumberingS ingleE224736Ordering Examples RAC04-05SK/277 = 5Vout Single RAC04-12SK/277 =12VoutSingleSpecifications (measured @ Ta= 25°C, nom. Vin, full load and after warm-up unless otherwise stated)Specifications (measured @ Ta= 25°C, nom. Vin, full load and after warm-up unless otherwise stated)REGULATIONSParameterCondition ValueOutput Accuracy ±1.0% typ.Line Regulation ±0.5% typ.Load Regulation 1.0% typ.Transient Response25% load step changerecovery time4.0% max.500µs10.5-0.5-1D e v i a t i o n [%]0102030405060708090100Output Load [%]10.50-0.5-1D e v i a t i o n [%]0102030405060708090100Output Load [%]RAC04-05SK/277RAC04-12SK/277Deviation vs. Load(80-305VAC)Specifications (measured @ Ta= 25°C, nom. Vin, full load and after warm-up unless otherwise stated)10.5-0.5-1D e v i a t i o n [%]0102030405060708090100Output Load [%]10.50-0.5-1D e v i a t i o n [%]0102030405060708090100Output Load [%]RAC04-15SK/277RAC04-24SK/277Specifications (measured @ Ta= 25°C, nom. Vin, full load and after warm-up unless otherwise stated)SAFETY AND CERTIFICATIONSCertificate Type Report / File Number StandardAudio/video, information and communication technology equipment - Safety requirements E224736UL62368-1:2014, 2nd Edition CAN/CSA C22.2 No. 62368-1-14, 2nd EditionInformation Technology Equipment, General Requirements for Safety (CB)E491408-A6-CB-1IEC60950-1:2005 + A2:2013, 2nd EditionInformation Technology Equipment, General Requirements for Safety EN60950-1:2006 + A2:2013 Audio/video, information and communication technology equipment - Safety requirements (CB)E491408-A6011-CB-1IEC62368-1:2014, 2nd Edition Audio/video, information and communication technology equipment - Safety requirements (LVD)EN62368-1:2014 + A11:2017 Household and similar electrical appliances - Safety - Part 1: General requirements (LVD)EN60335-1:2012 + A1:2018Safety of power transformers, power supplies, reactors and similar products for supply voltages up to 1100 V IEC61558-1:2005 2nd Edition + A1:2009EN61558-1:2005 + A1:2009Specifications (measured @ Ta= 25°C, nom. Vin, full load and after warm-up unless otherwise stated)Certificate Type Report / File Number StandardSafety of transformers, reactors, power supply units and similar products for supply voltages up to 1100 V - Part 2-16: Particular requirements and tests for switch mode power supply units and transformers for switch mode power supply units (LVD)IEC61558-2-16:2009 + A1:2013, 1st EditionEN61558-2-16:2009 + A1:2013Safety requirements for electrical equipment for measurement, control and laboratory use -Part 1: General requirements (LVD)EN61010-1:2010 RoHS2RoHs-2011/65/EU + AM-2015/863 EMC Compliance (Household)Report / File Number Standard / Criterion Electromagnetic compatibility - Requirements for household appliances, electric tools and similarapparatus - Part 1: Emission (8)EN55014-1:2006 + A2:2011 Electromagnetic compatibility - Requirements for household appliances, electric tools and similarapparatus - Part 2: ImmunityEN55014-2:2015 ESD Electrostatic discharge immunity test Air ±8kV; Contact ±4kV IEC61000-4-2:2008, Criteria B Fast Transient and Burst Immunity AC Power Port: ±1.0kV IEC61000-4-4:2012, Criteria B Surge Immunity AC Power Port: L-N ±1.0kV IEC61000-4-5:2014, Criteria B Immunity to conducted disturbances, induced by radio-frequency fields AC Power Port: 3V EN61000-4-6:2013, Criteria AVoltage Dips and Interruptions Voltage Dips: 100%60%EN61000-4-11:2004, Criteria CEN61000-4-11:2004, Criteria CEMC Compliance (Multimedia)Condition Standard / Criterion Low voltage power supplies, d.c. output - Part 3: Electromagnetic compatibility IEC/EN61204-3:2000, Class B Electromagnetic compatibility of multimedia equipment - Emission requirements (9)EN55032:2015, Class B Information technology equipment - Immunity characteristics - Limits and methods of measurement EN55024:2010 + A1:2015 ESD Electrostatic discharge immunity test Air ±2,4,8kV; Contact ±4kV IEC61000-4-2:2008, Criteria BRadiated, radio-frequency, electromagnetic field immunity test10V/m (80 - 1000MHz)IEC61000-4-3, Criteria A 3V/m (1800MHz, 2600Mhz,3500MHz, 5000MHz)IEC61000-4-3:2006 + A2:2010, Criteria AFast Transient and Burst Immunity AC Power Port: ±2.0kV IEC61000-4-4, Criteria B AC Power Port: ±1.0kV IEC61000-4-4:2012, Criteria ASurge Immunity AC Power Port: L-N ±1.0kV IEC61000-4-5:2014, Criteria A Immunity to conducted disturbances, induced by radio-frequency fields AC Power Port: 10V IEC61000-4-6, Criteria AVoltage Dips and Interruptions Voltage Dips:100% / 30%70%40%IEC61000-4-11:2004, Criteria AIEC61000-4-11:2004, Criteria BIEC61000-4-11:2004, Criteria C Interruptions: >95%IEC61000-4-11:2004, Criteria ALimits of Voltage Fluctuations & Flicker EN61000-3-3:2013 Limitations on the amount of electromagnetic interference allowed from digital and electronicdevicesFCC 47 Part 15 Subpart B:2017, Class B Notes:Note9: If output is connected to GND, please contact RECOM tech support for further informationDIMENSION and PHYSICAL CHARACTERISTICSParameter Type ValueMaterial case/baseplatepottingPCBplastic, (UL94 V-0)silicone, (UL94 V-0)FR4, (UL94 V-0)Dimension (LxWxH)36.7 x 27.2 x 17.4mm Weight30g typ.Specifications (measured @ Ta= 25°C, nom. Vin, full load and after warm-up unless otherwise stated)PACKAGING INFORMATIONParameter Type Value Packaging Dimension (LxWxH)tube506.4 x 29.8 x 25.5mm Packaging Quantity12pcs Storage Temperature Range-40°C to +85°C Storage Humidity non-condensing20% to 90% RH max.The product information and specifications may be subject to changes even without prior written notice.The product has been designed for various applications; its suitability lies in the responsibility of each customer. The products are not authorized for use in safety-critical applications without RECOM’s explicit written consent. A safety-critical application is an application where a failure may reasonably be expected to endanger or cause。
Closed-loop control of DC-DC dual active bridge converters driving single-phase inverters
Hengsi Qin
SolarBridge Technologies, Inc. 9229 Waterford Centre Blvd., Suite 110 Austin, TX 78758 USA
Jonathan W. Kimball
Missouri University of Science and Technology 301 W. 16th St., Rolla, MO 65409 USA kimballjw@
Abstract—The solid state transformer (SST) is a highfrequency power electronic converter as a distribution power transformer. A common three-stage configuration of an SST consists of ac-dc rectifier, isolated dc-dc dual-active-bridge (DAB) converter, and dc-ac inverter. This work addresses the controller design issue for a dc-dc DAB converter when driving a regulated single-phase dc-ac inverter. Since the switching frequency of the inverter stage is much higher than that of the DAB stage, the single-phase inverter is modelled as a 120-Hz current sink. The effect of 120-Hz current by the single-phase inverter is studied. The limitation of PI-controller, low gain at 120 Hz, is investigated. Two methods are proposed to improve the regulation of the output voltage of DAB converters. The first one uses a bandstop filter and feedforward, while the second method uses an additional proportional-resonant controller in the feedback loop. Theoretical analysis, simulation and experiment results are provided. Index Terms—Dual active bridge converter, single phase inverter, solid state transformer, closed-loop control, feedforward, proportional resonant cocontroller is used, it only achieves infinite gain at dc, making it difficult to track and to obtain zero steadystate error at 120 Hz, resulting in high voltage ripple at the output of DAB converters. This work addresses such limitations of a conventional PI controller for a dc-dc DAB converter driving a single-phase dc-ac inverter. Two methods are proposed to solve this issue. The first one adds an additional feedforward path to a conventional PI controller. The second method uses a ProportionalIntegral-Resonant (PI-R) controller, which achieves high gain at 120 Hz. II. S YSTEM C ONFIGURATION AND A PPROXIMATION The schematic of a single-phase SST is shown in Figure 1. The first stage is a single-phase active front-end rectifier, which converts the grid ac voltage to a fixed dc voltage. The second stage is an isolated dc-dc DAB converter, which transfers power between two dc buses with a high-frequency transformer. The “output” dc bus is defined as the bus whose voltage is regulated by the DAB converter, which is the lowvoltage bus on the right in Figure 1. The last stage is a singlephase dc-ac inverter, which generates an ac sinusoidal voltage as the SST’s output voltage. The conventional power flow diagram of a multi-stage SST is given in Figure 2. Ideally, the voltage and current at both the input of the rectifier and the output of the inverter are 60 Hz. Therefore, the input power of the rectifier and the output power of the inverter consist mainly of average power (which is in dc) and ripple power (which is the second order harmonic content in 120 Hz). √ √ P = 2V sin(ωs t) 2I sin(ωs t) = V I (1 + cos (2ωs t)) , (1) where V represents input/output RMS voltage, I represents input/output RMS current, ωs = 2πfs , and fs = 60 Hz is the grid frequency. On the other hand, the conventional control method for a dc-dc DAB converter can only process dc power. This means that the two dc buses must absorb the 120 Hz ripple power, as visualized in Figure 2 (solid lines represent dc power while dash lines represent 120 Hz ripple power). Because 120 Hz is relatively low (second order harmonic), large bus capacitance is needed to reduce the bus voltage fluctuation.
MORNSUN B05_XT-2WR3 Series DC DC Converter Datashe
2W isolated DC-DC converterFixed input voltage,unregulated single outputPatent Protection RoHSFEATURES●Continuous short-circuit protection ●No-load input current as low as 8mA●Operating ambient temperature range:-40℃to+105℃●High efficiency up to 86%●Compact SMD package●I/O isolation test voltage 1.5k VDC●Industry standard pin-outB05_XT-2WR3series are designed for use in distributed power supply systems and especially suitable in applications such as pure digital circuits,low frequency analog circuits,relay-driven circuits and data switching circuits.Selection GuideCertificationPart No.Input Voltage (VDC)OutputFull Load Efficiency (%)Min./Typ.Capacitive Load(µF)Max.Nominal (Range)Voltage (VDC)Current(mA)Max./Min.--B0503XT-2WR35(4.5-5.5) 3.3400/4074/782400B0505XT-2WR35400/4080/842400B05X7XT-2WR37286/2980/841000B0509XT-2WR39222/2281/851000B0512XT-2WR312167/1781/85560B0515XT-2WR315133/1382/86560B0524XT-2WR32483/882/86220Input SpecificationsItemOperating ConditionsMin.Typ.Max.UnitInput Current(full load /no-load)5VDC input3.3VDC output--339/8357/--mA5VDC/7VDC output --477/8500/--9VDC/12VDC output --471/8494/--15VDC/24VDC output--466/8488/--Reflected Ripple Current*--15--Surge Voltage (1sec.max.)-0.7--9VDCInput Filter Capacitance filter Hot PlugUnavailableNote:*Reflected ripple current testing method please refer to DC-DC Converter Application Note for specific operation.Output SpecificationsItemOperating ConditionsMin.Typ.Max.UnitVoltage AccuracySee output regulation curve (Fig.1)Linear RegulationInput voltage change:±1%3.3VDC output----±1.5--5VDC/7VDC/9VDC/12V DC/15VDC/24VDC output ----±1.2Load Regulation10%-100%load3.3VDC output --1020%5VDC/7VDC output--9159VDC output--81012VDC/15VDC output --71024VDC output--610Ripple &Noise*20MHz bandwidth --75200mVp-p Temperature Coefficient Full load--±0.02--%/℃Short-circuit ProtectionContinuous,self-recoveryNote:*The“parallel cable”method is used for ripple and noise test,please refer to DC-DC Converter Application Notes for specific information. General SpecificationsItem Operating Conditions Min.Typ.Max.UnitIsolation Input-output electric strength test for1minute with aleakage current of1mA max.1500----VDC Insulation Resistance Input-output resistance at500VDC1000----MΩIsolation Capacitance Input-output capacitance at100kHz/0.1V--20--pFOperating Temperature Derating when operating temperature≥85℃,(seeFig.2)-40--105℃Storage Temperature-55--125Case Temperature Rise Ta=25℃--25--Storage Humidity Non-condensing5--95%RHReflow Soldering Temperature*Peak temp.Tc≤245℃,maximum durationtime≤60s over217℃Vibration10-150Hz,5G,0.75mm.along X,Y and Z Switching Frequency Full load,nominal input voltage--220--kHz MTBF MIL-HDBK-217F@25℃3500----k hours Moisture Sensitivity Level(MSL)IPC/JEDEC J-STD-020D.1Level1Note:*See also IPC/JEDEC J-STD-020D.1.Mechanical SpecificationsCase Material Black plastic;flame-retardant and heat-resistant(UL94V-0)Dimensions13.20x11.40x7.25mmWeight 1.4g(Typ.)Cooling Method Free air convectionElectromagnetic Compatibility(EMC)Emissions CE CISPR32/EN55032CLASS B(see Fig.4for recommended circuit) RE CISPR32/EN55032CLASS B(see Fig.4for recommended circuit)Immunity ESD IEC/EN61000-4-2Air±8kV,Contact±6kV perf.Criteria B Typical Characteristic Curves3.3VDC output5VDC/7VDC/9VDC/12VDC/15VDC/24VDC outputFig.1Design Reference1.Typical applicationInput and/or output ripple can be further reduced,by connecting a filter capacitor from the input and/or output terminals to ground as shown in Fig.3.Choosing suitable filter capacitor values is very important for a smooth operation of the modules,particularly to avoid start-up problems caused by capacitor values that are too high.For recommended input and output capacitor values refer to Table 1.Vin0VDCCinDC CoutFig.3Table 1:Recommended input and output capacitor valuesVin Cin Vo Cout5VDC 4.7µF/16V3.3VDC/5VDC 10µF/16V ----7VDC/9VDC4.7µF/16V ----12VDC 2.2µF/25V ----15VDC 1µF/25V ----24VDC0.47µF/50V2.EMC compliance circuitFig.4EmissionsC1,C24.7µF /16VC3Refer to the Cout in Fig.3CY 270pF/2kV LDM6.8µH3.For additional information,please refer to DC-DC converter application notes on80O u t p u t P o w e r P e r c e n t (%)Ambient Temp.()℃Temperature Derating CurveSafe Operating AreaFig.2Dimensions and Recommended Layout Tape and Reel InfoNotes:1.For additional information on Product Packaging please refer to .Tube Packaging bag number:58210024,RollPackaging bag number:58200054;2.If the product is not operated within the required load range,the product performance cannot be guaranteed to comply with allparameters in the datasheet;3.The maximum capacitive load offered were tested at input voltage range and full load;4.Unless otherwise specified,parameters in this datasheet were measured under the conditions of Ta=25℃,humidity<75%RH with nominalinput voltage and rated output load;5.All index testing methods in this datasheet are based on our company corporate standards;6.We can provide product customization service,please contact our technicians directly for specific information;7.Products are related to laws and regulations:see"Features"and"EMC";8.Our products shall be classified according to ISO14001and related environmental laws and regulations,and shall be handled byqualified units.MORNSUN Guangzhou Science&Technology Co.,Ltd.Address:No.5,Kehui St.1,Kehui Development Center,Science Ave.,Guangzhou Science City,Huangpu District,Guangzhou,P.R.China Tel:86-20-38601850Fax:86-20-38601272E-mail:***************。
集成电路_Spice,Spectre仿真总结
集成电路_Spice,Spectre仿真总结集成电路_Spice,Spectre仿真总结Designers-Guide to Spice and Spectre 1995 USA Designers-Guide to Spice a nd Spectre — Ken Kundert 11.1 绪论 1. 为什么要读这本书①该书是介于算法和教你如何操作软件之间的一本书可以帮助你更好的使用Simulator的设置。
② Simulator仿出的结果可靠不精确不是否收敛应该如何处理如何设置③读完这本书你应该会 1 Simulator如何计算结果 2 Simulator 会产生何种错误如何识别 3 如何提高仿真精度 4 如何克服不收敛的情况 5 对于一些特殊电路会产生什么错误如何识别 6 明白仿真器里设置convergenceerror control的一些重要参数 7 能知道仿真器的错误信息出在什么地方如何解决2. 电路仿真软件的发展历史①直接方法求出电路的微分方程组用数值积分方法差分化然后用牛顿迭代法求解非线性代数方程组。
?是最准确可靠最通用的方法② Explicit integration methods ?方法问题很多③ relaxiton methods ?方法问题很多 3. Spice Options ① Global Options: Abstol控制电流默认为1pA Vntol控制电压默认为1uV Reltol相对误差对于牛顿收敛准则和截断误差准则同时起作用默认10-3对于重要电路这个应该设置小一些比如说10-5或者10-6Gmin防止非线性器件关断后的浮空节点默认为10-12 Ω-1LimptsPivrelPivtol无用处② DC Analysis Options: ltl1DC工作点最大牛顿迭代次数默认100 ltl2DC Sweep最大牛顿迭代次数默认50 ltl6Source Stepping的最大步长数增加以上3个值可以增加DC牛顿迭代收敛但是会降低速度。
SILICON LABORATORIES C8051F005 说明书
Precision Mixed Signal Copyright © 2004 by Silicon Laboratories6.15.2004C8051F00525 MIPS, 32 kB Flash, 12-Bit ADC, 64-Pin Mixed-Signal MCUAnalog Peripherals12-Bit ADC-±1 LSB INL; no missing codes-Programmable throughput up to 100 ksps-8 external inputs; programmable as single-ended or differential -Programmable amplifier gain: 16, 8, 4, 2, 1, 0.5-Data-dependent windowed interrupt generator -Built-in temperature sensor (±3 °C)Two 12-Bit DACs-Voltage output-10 µsec settling timeTwo Comparators-16 programmable hysteresis values-Configurable to generate interrupts or resetInternal Voltage ReferenceV DD Monitor/Brown-out DetectorOn-Chip JTAG Debug-On-chip emulation circuitry facilitates full-speed, non-intrusive, in-circuit emulation-Supports breakpoints, single stepping, watchpoints, inspect/modify memory, and registers-Superior performance to emulation systems using ICE-chips, target pods, and sockets-Fully compliant with IEEE 1149.1 specificationHigh-Speed 8051 µC Core-Pipelined instruction architecture; executes 70% of Instructions in 1 or 2 system clocks-Up to 25 MIPS throughput with 25 MHz clock-Expanded interrupt handler; up to 21 interrupt sourcesMemory-2304 bytes data RAM-32 kB Flash; in-system programmable in 512-byte sectors (512 bytes are reserved)Digital Peripherals-32 port I/O; all are 5 V tolerant-Hardware SMBus™ (I2C™ compatible), SPI™, and UART serial ports available concurrently-Programmable 16-bit counter/timer array with five capture/compare modules- 4 general-purpose 16-bit counter/timers-Dedicated watchdog timer; bidirectional reset Clock Sources-Internal programmable oscillator: 2–16 MHz -External oscillator: Crystal, RC, C, or Clock -Can switch between clock sources on-the-fly Supply Voltage: 2.7 to 3.6 V-Typical operating current: 12.5 mA at 25 MHz -Multiple power saving sleep and shutdown modes64-Pin TQFPTemperature Range: –40 to +85 °CPrecision Mixed Signal Copyright © 2004 by Silicon Laboratories 6.15.2004Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders25 MIPS, 32 kB Flash, 12-Bit ADC, 64-Pin Mixed-Signal MCUSelected Electrical Specifications(T A = –40 to +85 C°, V DD = 2.7 V unless otherwise specified)Package InformationC8051F005DK Development Kit。
MMC柔性直流输电系统换流阀开关频率优化方法-电源学报
式中 :ice 和 if 分别 为 IGBT 和二极管 导通时流经 器 件的电流 ;UCE0 为 IGBT 的通态电 压偏置 ;rce 为 IG鄄
第 16 卷 第 6 期
电
源
学
报
Vol.16 No.6
总第 2018 80 期 Nov.
2018 年 11 月
电 源 学Supply 报 Journal of Power
中图分类号 :TM464 文献标志码 :A
DOI :10.13234/j.issn.2095鄄2805.2018.6.84
MMC 柔性直流输电系统换流阀开关频率 优化方法
均压控制引起的投入子模块变化所带来的损耗为附加开关损耗paddswapapsw201年月journalpowersupply201假设mmc换流阀交流侧电流滞后于电压如图3所示dcap上桥臂电流电压关系fig3abovearmvoltageabovearmcurrentconverter图中分析图3可知0所以上桥臂在一个工频周期的必要开关损耗为pmmcswapigbtoffapdioderecapigbtonapigbtoffapdioderecapigbtonmmcsw10将其离散化并转化为1秒内的损耗得
当 MMC 应用于高压系统时 , 子模块数一 般 较 多 , 采 用 最 近 电 平 逼 近 调 制 NLM (nearest level mo鄄
dulation ) 方法是其 首选 。 NLM 的工作原理是 , 控制
单 相上 、 下桥臂 处 于 投入状态 子模块的 总 数 保持 不 变 , 通过 改 变其中上 ( 下 ) 桥臂 投入状态 子模块的个 数 , 达到 输出所 需 电压的目的 。 假 设 MMC 的 调 制波为 msin (ωt ), 其中 m 为 调 制比 , 则 a 相 上 、 下 桥 臂 处 于 投 入 状 态 的子 模 块 个 数的计算方式
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Purpose:
Know the true circuits and connections, observe and analyse the Key waveforms of the circuit
uab uac ubc uba uca ucb
3、已知该vd波形中最高电
压为500V,求此时输出电 压平均值Vd。
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0
t ω
Supplement material
Solution 1 1、 T3管损坏
0
ud
uab uac ubc uba uca ucb
ωt
2、α=30º 3、
4 500 Ud 2.34 cos30o 275.81V 6 3 2
A
C
B
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Supplement material
Solution
② 测相控角α并将它调整到38º 假设已测得的A、B、C三相相序为A超前B,B超前C 由于线电压UAB(或UBC或UCA)的正向过零点(从负半周进 入到正半周的过零点)与T6管(或T2管或T4管)的自然换相 点为同一时刻,并且线电压UAB(或UBC或UCA)与T6管(或 T2管或T4管)的触发信号有公共点,因此可用两个探头同时 测线电压UAB(或UBC或UCA)和T6管(或T2管或T4管)的触 发信号得α角,并将它调整到38º 27
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Fig 1. CA6100 Board
Control part
Driving part
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Output ports
Six pulse transformers
Power supply
LSI
Power transformer
Controler of α
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One important feature of CA6100 is that a phase-lockloop (PLL) is ability to provide the synchronous triggering signal with AC input voltage for SCR, instead of a synchronous transformer. The principle of triggering signal is seen in Figure 2.
4. Adjust the voltage of second side in three-phase transformer below 80 V, then turn the controller of α respectively in 60ºand 90º observe and draw the , waveforms of vd, Id, vT and triggering signal;
Supplement material
Solution
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Supplement material
Solution
③ 测ud 的波形 保持α=38º,用一个探头测直流输出母线电压ud 的波形(注 意极性)。 ④ 测id 的波形 保持α=38º,用一个探头测电阻箱两端电压的id波形(注意极 性)
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Understand the request of triggering signal for three-phase Thyristor Full-bridge controllable converter See the attached《CA6100可控硅触发电路》
2
Content:
1
1 Prepare this experiment
Draw the topology of three-phase Thyristor Fullbridge controllable converter Summarize the basic principle of three-phase Thyristor Full-bridge controllable converter when it operates in two-quadrant
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Supplement material
Example 2 一实验电路如图所示。负载为大电感和电阻 箱,晶闸管触发脉冲为单脉冲。假设A、B、C三相电 压平衡,但相序未知,相控角α可以调节。要求用双踪 示波器测量相控角α= 38º时的直流输出电压ud 、输出 电流id 的波形,试说明实验步骤。
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Laboratory 3. Three-phase Thyristor Converter 负责教师:陈洛忠 This experiment will begin from 2011-5-2 For the three-phase Thyristor Full-bridge circuit can operate two-quadrant, i.e. rectifier mode and inverter mode, converter is called in this experiment, instead of rectifier
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Figure 2. principle of triggering signal
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Two types of triggering signal can be provided in the first side of every pulse transformer in CA6100, which can be seen in Figure 3. The double 30ºof them is used in this experiment.
Figure 3. Wave of Triggering signal in the primary side of A phase pulse transformer
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Role ?
The insulated and strong triggering signal for each SCR can be given through the driving circuit seen in Figure 4.
6. Turn off the utility power and Adjust the voltage of transformers to zero after the teacher admits.
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3 Problems 1. How dose ac side inductance effect on the current communicating in this converter circuit? 2. How can this Thyristor controllable converter operate in inverter mode? Try to analyse the reasons.
3. If one of the thyristors in the converter is fault, how can you choose new one to replace that destroyed one ?
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Supplement material
Example 1 三相全控桥整流电路接阻感负载,Ld=∞,直流 侧电流连续,正常工作时突然有一个晶闸管烧断,出现如 下图vd波形。试回答下列问题: 1、判断T1-T6中的哪一个管子损坏?(注T1、T3、T5分别对 应a、b、c三相的上桥臂;T4、T6、T2分别对应a、b、c三 相的下桥臂) ud 2、大致判断相控角α=?
Figure 4. Driving circuit for A phase
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Figure 5. Wave of Triggering signal in the second side of A phase pulse transformer
19
2 Steps of the experiment 1. Check the all equipments and connections in the circuit; 2. Adjust the single-phase transformer to zero voltage; 3. turn on the utility power, the three LED in CA6100 light;
Request:
Step by step safely Do it by oneself Draw carefully waveforms Analyse rightly conclusion
3
Introduction of the experiment circuit
4
DC output
K
G A
AC input
5
6
7
8
9
10
11
Triggering and driving circuit
A general control circuit board named CA6100, which is composed of Large Scale Integration (LSI) is used in this experiment. The CA6100 is seen in Figure 1.
Supplement material
Solution 2 测ud 、id的波形 ① 确定A、B、C相序: 用双踪示波器测自耦调压器三根输出线之间的电压波形即可: 设某相位C相,以此相位公共点测两个线电压vxc、vyc,则相 位超前的是vAC,相位滞后的是vBC。 (注意:示波器探头的接法,两个探头的地接在一起或只接一 个探头的地而另一个探头的地悬空)。