LTC4052-42中文资料

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LTC4056-4.2中文资料

LTC4056-4.2中文资料
, LTC and LT are registered trademarks of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation.
U APPLICATIO S
s s s s s
500 400 300 200 100
CHRG TIMER/SHDN PROG GND
UNDERVOLTAGE CHARGE CURRENT LIMITING
+
1-CELL 4.2V Li-Ion
4056-4.2 TA01
0 4.40 4.45
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CONSTANT CURRENT UNDERVOLTAGE LOCKOUT AT 4.35V 4.50 4.55 4.60 4.65 4.70 ar Telephones Handheld Computers Digital Cameras Charging Docks and Cradles Low Cost and Small Size Chargers
TYPICAL APPLICATIO
VIN Undervoltage Charge Current Limiting
800 VBAT = 4V 700 RPROG = 1.3k ICHG = 700mA INPUT Z = 100mΩ 600 700mA ZXT1M322
IBAT (mA)
VIN 4.5V TO 6.5V CHARGE STATUS 1µF 1µF 1.3k
VCC
LTC4056 ISENSE DRIVE BAT
Input Supply Voltage (VCC) ........................– 0.3V to 10V BAT, CHRG ................................................– 0.3V to 10V DRIVE, PROG, TIMER/SHDN ....... – 0.3V to (VCC + 0.3V) Output Current (ISENSE) ...................................... 900mA Short-Circuit Duration (BAT, ISENSE) ............Continuous Junction Temperature ........................................... 125°C Operating Ambient Temperature Range (Note 2) .............................................. – 40°C to 85°C Storage Temperature Range ................. – 65°C to 150°C Lead Temperature (Soldering, 10 sec).................. 300°C

LTC4054-4.2中文资料

LTC4054-4.2中文资料
元器件交易网
LTC4054-4.2/LTC4054X-4.2 Standalone Linear Li-Ion Battery Charger with Thermal Regulation in ThinSOT
FEATURES
s s
DESCRIPTIO
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s
s s
s s s s s s s s
Cellular Telephones, PDAs, MP3 Players Charging Docks and Cradles Bluetooth Applications
TYPICAL APPLICATIO
VIN 4.5V TO 6.5V
Complete Charge Cycle (750mAh Battery)
The LTC®4054 is a complete constant-current/constantvoltage linear charger for single cell lithium-ion batteries. Its ThinSOT package and low external component count make the LTC4054 ideally suited for portable applications. Furthermore, the LTC4054 is specifically designed to work within USB power specifications. No external sense resistor is needed, and no blocking diode is required due to the internal MOSFET architecture. Thermal feedback regulates the charge current to limit the die temperature during high power operation or high ambient temperature. The charge voltage is fixed at 4.2V, and the charge current can be programmed externally with a single resistor. The LTC4054 automatically terminates the charge cycle when the charge current drops to 1/10th the programmed value after the final float voltage is reached. When the input supply (wall adapter or USB supply) is removed, the LTC4054 automatically enters a low current state, dropping the battery drain current to less than 2µA. The LTC4054 can be put into shutdown mode, reducing the supply current to 25µA. Other features include charge current monitor, undervoltage lockout, automatic recharge and a status pin to indicate charge termination and the presence of an input voltage.

LTC1232 精密电源监控模块说明书

LTC1232 精密电源监控模块说明书

123sn1232 1232fasSYMBOL PARAMETER CONDITIONSMINTYP MAX UNITSV CC Supply Voltage● 4.555.5V V IH ST and PB RST Input High Level ●2V CC +0.3V V ILST and PB RST Input Low Level●–0.30.8VDC ELECTRICAL CHARACTERISTICSSYMBOL PARAMETER CONDITIONS MINTYP MAX UNITS I IL Input Leakage (Note 3)●–11µA I OH Output Current at 2.4V (Note 5)●–1–13mA I OL Output Current at 0.4V (Note 5)●26mAI CC Supply Current (Note 4)●0.52mA V CCTP V CC Trip Point TOL = GND ● 4.5 4.62 4.74 V V CCTP V CC Trip PointTOL = V CC●4.254.37 4.49 V V HYS V CC Trip Point Hysteresis 40mV V RSTRST Output Voltage at V CC = 1VI SINK = 10µA4200mVThe ● denotes the specifications which applyover the full operating temperature. V CC = full operating range.The ● denotes the specifications which apply over the full operatingtemperature. V CC = full operating range.SYMBOL PARAMETER CONDITIONSMIN TYP MAX UNITS t PB PB RST = V IL ●40ms t RST RESET Active Time ●2506101000ms t ST ST Pulse Width●20ns t RPD V CC Detect to RST and RST ●100ns t f V CC Slew Rate 4.75V–4.25V ●300µs t RPU V CC Detect to RST and RSTt R = 5µs●2506101000ms (Reset Active Time)t R V CC Slew Rate 4.25V–4.75V ●0nst TDST Pin Detect to RST and RST TD = GND ●60150250ms (Watchdog Time-Out Period)TD = Floating ●2506101000ms TD = V CC●50012002000ms C IN Input Capacitance 5pF C OUTOutput Capacitance5pFNote 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.Note 2: All voltage values are with respect to GND.Note 3: The PB RST pin is internally pulled up to V CC with an internal impedance of 10k typical. The TD pin has internal bias current.Note 4: Measured with outputs open.Note 5: The RST pin is an open drain output.The ● denotes the specifications which apply over the full operating temperature.V CC = full operating range.AC CHARACTERISTICSRECO E D ED OPERATI G CO DITIO SU U U U WW456Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.7Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● LW/TP 1002 1K REV A • PRINTED IN USA © LINEAR TECHNOLOGY CORPORA TION 19928。

LTC3542资料

LTC3542资料

13542faSynchronous Step-DownDC/DC ConverterThe LTC ®3542 is a high effi ciency monolithic synchronous buck converter using a constant frequency, current mode architecture. Supply current during operation is only 26μA, dropping to <1μA in shutdown. The 2.5V to 5.5V input voltage range makes the LTC3542 ideally suited for single Li-Ion battery-powered applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. The output voltage is adjustable from 0.6V to V IN . Internal power switches are optimized to provide high effi ciency and eliminate the need for an external Schottky diode.Switching frequency is internally set at 2.25MHz, allowing the use of small surface mount inductors and capacitors, and it can synchronize to an external clock signal with a frequency range of 1MHz to 3MHz through the MODE/SYNC pin. The LTC3542 is specifi cally designed to work well with ceramic output capacitors, achieving very low output voltage ripple and a small PCB footprint.The LTC3542 can be confi gured for the power saving Burst Mode ® Operation. For reduced noise and RF interference, the MODE/SYNC pin can be confi gured for pulse skipping operation.■Cellular Telephones■ Wireless and DSL Modems ■ D igital Cameras ■ MP3 Players■ PDAs and Other Handheld Devices■High Effi ciency: Up to 96%■ High Peak Switch Current: 1000mA ■ Low Output Ripple (<20mV P-P Typical) Burst Mode Operation: Only 26μA■ Very Low Quiescent Current: Only 26μA ■ 2.5V to 5.5V Input Voltage Range■ 2.25MHz Constant Frequency Operation■ 1MHz to 3MHz External Frequency Synchronization ■ Low Dropout Operation: 100% Duty Cycle ■ No Schottky Diode Required■ Internal Soft-Start Limits Inrush Current ■ 0.6V Reference Allows Low Output Voltages ■Shutdown Mode Draws <1μA Supply Current ■ ±2% Output Voltage Accuracy■ Current Mode Operation for Excellent Line and Load Transient Response ■ Overtemperature Protected■ Available in 6-Lead 2mm × 2mm DFN and Small TSOTProtected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131, 5994885.μF V IN2.7V TO 5.5VOUT Effi ciency and Power Loss vs Output CurrentOUTPUT CURRENT (mA)30E F F I C I E N C Y (%)POWER LOSS (mW)90100201080507060400.11010010003542 TA01b10010001010.11FEATURESDESCRIPTIONAPPLICATIONSTYPICAL APPLICATION23542faELECTRICAL CHARACTERISTICSInput Supply Voltage (V IN ) ...........................–0.3V to 6V V FB , RUN Voltages .......................................–0.3V to V IN MODE Voltage ................................–0.3V to (V IN + 0.3V)SW Voltage ....................................–0.3V to (V IN + 0.3V)Operating Temperature Range (Note 2)LTC3542E ............................................–40°C to 85°C LTC3542I ...........................................–40°C to 125°CThe ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. V IN = 3.6V unless otherwise noted.SYMBOL PARAMETERCONDITIONSMINTYP MAX UNITSV IN Operating Voltage Range ●2.5 5.5V I FB Feedback Input Current ±30nA V FB Feedback Voltage (Note 4)●0.5880.60.612V ΔV LINE_REG Reference Voltage Line Regulation (Note 4)V IN = 2.5V to 5.5V 0.040.2%/V ΔV LOAD_REGOutput Voltage Load Regulation (Note 4)I LOAD = 100mA to 500mA 0.020.2%Junction Temperature (Note 7) .............................125°C Storage Temperature Range ...................–65°C to 150°C Lead Temperature (Soldering, 10 sec) TSOT-23 ............................................................300°C Refl ow Peak Body Temperature (DFN) ..................260°CABSOLUTE MAXIMUM RATINGS (Note 1)TOP VIEWRUN SWV FB V IN GND DC PACKAGE6-LEAD (2mm × 2mm) PLASTIC DFN4576321MODE/SYNC T JMAX = 125°C, θJA = 102°C/W, θJC = 20°C/W (SOLDERED TO A 4-LAYER BOARD, NOTE 3)EXPOSED PAD (PIN 7) IS GND, MUST BE SOLDERED TO PCBV IN 1GND 2V FB 36 SW 5 MODE/SYNC 4 RUNTOP VIEWS6 PACKAGE6-LEAD PLASTIC TSOT-23T JMAX = 125°C, θJA = 215°C/WPIN CONFIGURATIONORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3542EDC#PBF LTC3542EDC#TRPBF LCFR 6-Lead (2mm × 2mm) Plastic DFN –40°C to 85°C LTC3542IDC#PBF LTC3542IDC#TRPBF LCFR 6-Lead (2mm × 2mm) Plastic DFN –40°C to 125°C LTC3542ES6#PBF LTC3542ES6#TRPBF LCFS 6-Lead Plastic TSOT-23–40°C to 85°C LTC3542IS6#PBFLTC3542IS6#TRPBFLCFS6-Lead Plastic TSOT-23–40°C to 125°CConsult LTC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container.Consult LTC Marketing for information on non-standard lead based fi nish parts.For more information on lead free part marking, go to: /leadfree/ For more information on tape and reel specifi cations, go to: /tapeandreel/33542faTYPICAL PERFORMANCE CHARACTERISTICSNote 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. No pin should exceed 6V.Note 2: The LTC3542 is guaranteed to meet performance specifi cations from 0°C to 85°C. Specifi cations over the –40°C to 85°C operatingtemperature range are assured by design, characterization and correlation with statistical process controls. The LTC3542I is guaranteed over the full –40°C to 125°C operating temperature range.Note 3: Failure to solder the Exposed Pad of the package to the PC board will result in a thermal resistance much higher than 102°C/W.SYMBOL PARAMETERCONDITIONS MIN TYP MAX UNITS I SInput DC Supply Current (Note 5)Active Mode Sleep Mode Shutdown V FB = 0.5VV FB = 0.7V, MODE = 0V RUN = 0V 260.1500351μA μA μA f OSC Oscillator Frequency V FB = 0.6V ●1.82.252.7MHz f SYNC Synchronous Frequency V FB = 0.6V13MHz I LIM Peak Switch CurrentV IN = 3V, V FB = 0.5V, Duty Cycle < 35%6501000mA R DS(ON)P-Channel On Resistance (Note 6)N-Channel On Resistance (Note 6)I SW = 100mA I SW = –100mA0.50.350.650.55ΩΩI SW(LKG)Switch Leakage Current V IN = 5V, V RUN = 0V, V SW = 0V or 5V ±0.01±1μA V UVLO Undervoltage Lockout Threshold V IN Rising V IN Falling1.82.01.9 2.3V V V RUN RUN Threshold ●0.31.5V I RUN RUN Leakage Current ●±0.01±1μA V MODE/SYNC MODE/SYNC Threshold ●0.31.2V I MODE/SYNCMODE/SYNC Leakage Current●±0.01±1μANote 4: The converter is tested in a proprietary test mode that connects the output of the error amplifi er to the SW pin, which is connected to an external servo loop.Note 5: Dynamic supply current is higher due to the internal gate charge being delivered at the switching frequency.Note 6: The DFN switch on resistance is guaranteed by correlation to wafer level measurements.Note 7: T J is calculated from the ambient temperature T A and power dissipation P D according to the following formula: T J = T A + (P D ) • (θJA).Burst Mode OperationPulse Skip Mode OperationStart-Up from ShutdownSW 2V/DIVV IN = 3.6V V OUT = 1.8V I LOAD = 25mAFIGURE 3a CIRCUIT2μs/DIV 3542 G01V OUT 50mV/DIV AC COUPLED I L100mA/DIVSW 2V/DIV I L100mA/DIVV IN = 3.6V V OUT = 1.8V I LOAD = 25mAFIGURE 3a CIRCUIT400ns/DIV 3542 G02VOUT 50mV/DIV AC COUPLED RUN2V/DIV I L100mA/DIVV IN = 3.6V V OUT = 1.8V I LOAD = 0AFIGURE 3a CIRCUIT400μs/DIV3542 G03V OUT 1V/DIVT A = 25°C unless otherwise specifi ed.ELECTRICAL CHARACTERISTICSThe ● denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. V IN = 3.6V unless otherwise noted.43542faStart-Up from ShutdownLoad StepReference Voltage vs TemperatureOscillator Frequency vs TemperatureOscillator Frequency vs Supply VoltageOutput Voltage vs Supply VoltageOutput Voltage vs Load CurrentR DS(ON) vs Input VoltageRUN 2V/DIV I L500mA/DIVV IN = 3.6VV OUT = 1.8V I LOAD = 500mA FIGURE 3a CIRCUIT400μs/DIV 3542 G04V OUT 1V/DIV V OUT 100mV/DIV AC COUPLEDI L500mA/DIVV IN = 3.6V V OUT = 1.8VI LOAD = 30mA TO 500mA FIGURE 3a CIRCUIT20μs/DIV 3542 G05ILOAD 500mA/DIVLoad StepV OUT100mV/DIV AC COUPLEDI L500mA/DIV V IN = 3.6VV OUT = 1.8VI LOAD = 0mA TO 500mA FIGURE 3a CIRCUIT20μs/DIV 3542 G06I LOAD 500mA/DIVTEMPERATURE (°C)–50V R E F (V )0.61000.60750.60500.60250.60000.59750.59500.59250.59000.58750.58500.58250.61250.6150050753542 G07–2525100125INPUT VOLTAGE (V)2–0.5V O U T E R R O R (%)–0.4–0.2–0.100.50.234 4.53542 G10–0.30.30.40.1 2.53.55 5.56LOAD CURRENT (mA)10V O U T E R R O R (%)1.02.010*******3542 G11–1.0–0.50.51.5–1.5–2.0V IN (V)10R D S (O N ) (9)0.10.30.40.550.93542 G120.2326470.60.70.8TEMPERATURE (°C)–50–30–1010305070901101.8F R E Q U E N C Y (M H z )1.92.12.22.32.73542 G082.02.42.52.6SUPPLY VOLTAGE (V)F R E Q U E N C Y (M H z )2.22.32.4563542 G092.12.01.82341.92.72.52.6TYPICAL PERFORMANCE CHARACTERISTICST A = 25°C unless otherwise specifi ed.53542faR DS(ON) vs TemperatureSwitch Leakage vs Input VoltageEffi ciency vs Input VoltageTEMPERATURE (°C)–500R D S (O N ) (Ω)0.10.30.40.5500.93542 G130.20–2575100251250.60.70.8Switch Leakage vs TemperatureTEMPERATURE (°C)–50S W I T C H L E A K A G E (n A )20025030025753542 G15150100–255010012550V IN (V)0L E A K A G E C U R R E N T (p A )20040060012343542 G14580010001003005007009006INPUT VOLTAGE (V)2.510090807060504030453542 G1633.54.55.5E F F I C I E N C Y (%)Effi ciency vs Load CurrentOUTPUT CURRENT (mA)30E F F I C I E N C Y (%)90100201080507060400.11010010003542 G171Effi ciency vs Load CurrentEffi ciency vs Load CurrentOUTPUT CURRENT (mA)30E F F I C I E N C Y (%)90100201080507060400.11010010003542 G181OUTPUT CURRENT (mA)30E F F I C I E N C Y (%)90100201080507060400.11010010003542 G191TYPICAL PERFORMANCE CHARACTERISTICST A = 25°C unless otherwise specifi ed.63542fa3542 BDV FB (Pin 1/Pin 3): Output Feedback Pin. Receives the feedback voltage from an external resistive divider across the output. Nominal voltage for this pin is 0.6V.V IN (Pin 2/Pin 1): Power Supply Pin. Must be closely decoupled to GND.GND (Pin 3/Pin 2): Ground Pin.SW (Pin 4/Pin 6): Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches.MODE/SYNC (Pin 5/Pin 5): Mode Selection and Oscillator Synchronization Pin. This pin controls the operation of the device. When tied to GND or V IN , Burst Mode operation orpulse skipping mode is selected, respectively. Do not fl oat this pin. The oscillation frequency can be synchronized to an external oscillator applied to this pin and pulse skipping mode is automatically selected.RUN (Pin 6/Pin 4): Converter Enable Pin. Forcing this pin above 1.5V enables this part, while forcing it below 0.3V causes the device to shut down. In shutdown, all functions are disabled drawing <1μA supply current. This pin must be driven; do not fl oat.GND (Pin 7, DFN Package Only): Exposed Pad. The Ex-posed Pad is ground. It must be soldered to PCB ground to provide both electrical contact and optimum thermal performance.PIN FUNCTIONS(DFN/TSOT-23)BLOCK DIAGRAMThe LTC3542 uses a constant frequency, current mode, step-down architecture. The operating frequency is set at 2.25MHz and can be synchronized to an external oscillator. To suit a variety of applications, the selectable MOD E/SYNC pin allows the user to trade-off noise for effi ciency.The output voltage is set by an external divider returned to the V FB pin. An error amplifi er compares the divided output voltage with a reference voltage of 0.6V and adjusts the peak inductor current accordingly.Main Control LoopDuring normal operation, the top power switch (P-channel MOSFET) is turned on at the beginning of a clock cycle when the V FB voltage is below the reference voltage. The current fl ows into the inductor and the load increases until the current limit is reached. The switch turns off and energy stored in the inductor fl ows through the bottom switch (N-channel MOSFET) into the load until the next clock cycle. The peak inductor current is controlled by the internally compensated output of the error amplifi er. When the load current increases, the V FB voltage decreases slightly below the reference. This decrease causes the error amplifi er to increase its output voltage until the average inductor cur-rent matches the new load current. The main control loop is shut down by pulling the RUN pin to ground.Low Load Current OperationBy selecting MODE/SYNC pin, two modes are available to control the operation of the LTC3542 at low load currents. Both modes automatically switch from continuous opera-tion to the selected mode when the load current is low. To optimize effi ciency, the Burst Mode operation can be selected. When the converter is in Burst Mode operation, the peak current of the inductor is set to approximately 60mA regardless of the output load. Each burst event can last from a few cycles at light loads to almost continuously cycling with short sleep intervals at moderate loads. In between these burst events, the power MOSFETs and any unneeded circuitry are turned off, reducing the quiescent current to 26μA. In this sleep state, the load current is being supplied solely from the output capacitor. As the output voltage drops, the EA amplifi er’s output rises above the sleep threshold and turns the top MOSFET on. This process repeats at a rate that is dependent on the load demand. By running cycles periodically, the switching losses which are dominated by the gate charge losses of the power MOSFETs are minimized.For lower ripple noise at low load currents, the pulse skip mode can be used. In this mode, the regulator continues to switch at a constant frequency down to very low load currents, where it will begin skipping pulses.Dropout OperationWhen the input supply voltage decreases toward the output voltage, the duty cycle increases to 100%, which is the dropout condition. In dropout, the PMOS switch is turned on continuously with the output voltage being equal to the input voltage minus the voltage drops across the internal P-channel MOSFET and the inductor. An important design consideration is that the R DS(ON) of the P-channel switch increases with decreasing input supply voltage (See Typical Performance Characteristics). Therefore, the user should calculate the power dissipation when the LTC3542 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Information Section). Low Supply OperationTo prevent unstable operation, the LTC3542 incorporates an undervoltage lockout circuit which shuts down the part when the input voltage drops below about 2V.Internal Soft-StartAt start-up when the RUN pin is brought high, the internal reference is linearly ramped from 0V to 0.6V in about 1ms. The regulated feedback voltage follows this ramp resulting in the output voltage ramping from 0% to 100% in 1ms. The current in the inductor during soft-start is defi ned by the combination of the current needed to charge the output capacitance and the current provided to the load as the output voltage ramps up. The start-up waveform, shown in the Typical Performance Characteristics, shows the output voltage start-up from 0V to 1.8V with a 500mA load and V IN = 3.6V (refer to Figure 3a).OPERATION73542fa83542faA general LTC3542 application circuit is shown in Figure1. External component selection is driven by the load require-ment and begins with the selection of the inductor L. Once the inductor is chosen, C IN and C OUT can be selected.the burst clamp. Lower inductor values result in higher ripple current which causes the transition to occur at lower load currents. This causes a dip in effi ciency in the upper range of low current operation. In Burst Mode operation, lower inductance values cause the burst frequency to increase.Inductor Core SelectionD ifferent core materials and shapes change the size/current and price/current relationships of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements and any radiated fi eld/EMI requirements than on what the LTC3542 requires to operate. Table 1 shows some typi-cal surface mount inductors that work well in LTC3542 applications.Input Capacitor (C IN ) SelectionIn continuous mode, the input current of the converter is a square wave with a duty cycle of approximately V OUT /V IN . To prevent large voltage transients, a low equivalent series resistance (ESR) input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by:I I RMS MAXIN≈where the maximum average output current I MAX equals the peak current minus half the peak-to-peak ripple cur-rent, I MAX = I LIM – ΔI L /2. This formula has a maximum at V IN = 2V OUT , where I RMS = I OUT /2. This simple worst-case is commonly used to design because even signifi cant deviations do not offer much relief. Note that capacitor manufacturer’s ripple current ratings are often based on only 2000 hours life time. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Several capacitors may also be paralleled to meet the size or height requirements of theV IN2.7V TO 5.5VOUT Figure 1. LTC3542 General SchematicInductor SelectionThe inductor value has a direct effect on ripple current ΔI L , which decreases with higher inductance and increases with higher V IN or V OUT , as shown in following equation: ΔI V L V V L OUT OOUT IN =⎛⎝⎜⎞⎠⎟ƒ•–1where f O is the switching frequency. A reasonable starting point for setting ripple current is ΔI L = 0.4 • I OUT(MAX), where I OUT(MAX) is 500mA. The largest ripple current ΔI L occurs at the maximum input voltage. To guarantee that the ripple current stays below a specifi ed maximum, the inductor value should be chosen according to the follow-ing equation:L V I V V OUT O L OUT IN MAX =⎛⎝⎜⎞⎠⎟ƒ•–()Δ1The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 600mA rated inductor should be enough for most applications (500mA + 100mA). For better effi ciency, chose a low DC-resistance inductor.The inductor value will also have an effect on Burst Mode operation. The transition to low current operation begins when the inductor’s peak current falls below a level set byAPPLICATIONS INFORMATION93542fadesign. An additional 0.1μF to 1μF ceramic capacitor is also recommended on V IN for high frequency decoupling, when not using an all ceramic capacitor solution.Output Capacitor (C OUT ) SelectionThe selection of C OUT is driven by the required ESR to minimize voltage ripple and load step transients. Typically, once the ESR requirement is satisfi ed, the RMS current rating generally far exceeds the I RIPPLE(P-P) requirement, except for an all ceramic solution. The output ripple (ΔV OUT ) is determined by:ΔΔV I ESR C OUT L OUT ≈+⎛⎝⎜⎞⎠⎟18••ƒO where f O is the switching frequency, C OUT is the outputcapacitance and ΔI L is the inductor ripple current. For a fixed output voltage, the output ripple is highest at maximum input voltage since ΔI L increases with input voltage. If tantalum capacitors are used, it is critical that the capaci-tors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalums, available in case heights ranging from 2mm to 4mm. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP , Kemet T510 andT495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specifi c recommendations.Ceramic Input and Output CapacitorsHigher value, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current rating, high voltage rating and low ESR are tempting for switching regulator use. However, the ESR is so low that it can cause loop stability problems. Since the LTC3542’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used to achieve very low output ripple and small circuit size. X5R or X7R ceramic capacitors are recommended because these dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.Great care must be taken when using only ceramic input and output capacitors. When a ceramic capacitor is used at the input and the power is being supplied through long wires, such as from a wall adapter, a load step at the output can induce ringing at the V IN pin. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, the ringing at the input can be large enough to damage the part. For more information, see Application Note 88. The recommended capacitance value to use is 10μF for both input and output capacitors.Table 1. Representative Surface Mount InductorsMANUFACTURER PART NUMBERVALUE (μH)MAX DC CURRENT (A)DCR (Ω)SIZE (mm 3)SumidaCDRH2D11-2RM 2.20.7800.098 3.2 × 3.2 × 1.2CDRH3D16 2.2 1.20.075 3.8 × 3.8 × 1.8CMD4D11 2.20.950.116 4.4 × 5.8 × 1.2CDH2D09B 3.30.850.15 2.8 × 3 × 1CLS4D094.70.750.15 4.9 × 4.9 × 1Murata LQH32CN 2.20.790.097 2.5 × 3.2 × 1.55LQH43CN 4.70.750.15 4.5 × 3.2 × 2.6TDKIVLC453232 2.20.850.18 4.8 × 3.4 × 3.4VLF3010AT-2R2M1R02.21.00.122.8 × 2.6 × 1APPLICATIONS INFORMATIONOutput Voltage ProgrammingThe output voltage is set by a resistive divider according to the following formula:V V R ROUT =+⎛⎝⎜⎞⎠⎟06121.To improve the frequency response, a feed-forward capaci-tor, C F, may also be used. Great care should be taken to route the V FB line away from noise sources, such as the inductor or the SW line.Mode Selection and Frequency SynchronizationThe MODE/SYNC pin is a multipurpose pin that provides mode selection and frequency synchronization. Connect-ing this pin to GND enables Burst Mode operation, which provides the best low current effi ciency at the cost of a higher output voltage ripple. Connecting this pin to V IN selects pulse skip mode operation, which provides the lowest output ripple at the cost of low current effi ciency. The LTC3542 can also be synchronized to an external clock signal with range from 1MHz to 3MHz by the MODE/SYNC pin. During synchronization, the mode is set to pulse skip and the top switch turn-on is synchronized to the falling edge of the external clock.Effi ciency ConsiderationsThe effi ciency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the effi ciency and which change would produce the most improvement. Effi ciency can be expressed as: Effi ciency = 100% – (L1 + L2 + L3 + ...)where L1, L2, etc. are the individual losses as a percent-age of input power. Although all dissipative elements in the circuit produce losses, three main sources usually account for most of the losses in LTC3542 circuits: 1) V IN quiescent current, 2) I2R loss and 3) switching loss. V IN quiescent current loss dominates the power loss at very low load currents, whereas the other two dominate at medium to high load currents. In a typical effi ciency plot, the effi ciency curve at very low load currents can be misleading since the actual power loss is of no consequence as illustrated in Figure 2.1) The V IN quiescent current is the DC supply current given in the Electrical Characteristics which excludes MOSFET charging current. V IN current results in a small (<0.1%) loss that increases with V IN, even at no load.2) I2R losses are calculated from the DC resistances of the internal switches, R SW, and external inductor, R L. In continuous mode, the average output current fl ows through inductor L, but is “chopped” between the internal top and bottom switches. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET R DS(ON) and the duty cycle (D) as follows:R SW = (R DS(ON)TOP)(D) + (R DS(ON)BOT)(1 – D)The R DS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses:I2R losses = I OUT2(R SW + R L)Figure 2. Power Loss vs Load CurrentOUTPUT CURRENT (mA)1POWERLOSS(mW)1010010000.11010010003542 F020.11APPLICATIONS INFORMATION103542fa3) The switching current is MOSFET gate charging current, that results from switching the gate capacitance of the power MOSFETs. Each time a MOSFET gate is switched from low to high to low again, a packet of charge dQ moves from V IN to ground. The resulting dQ/dt is a current out of V IN that is typically much larger than the DC bias current. In continuous mode, I GATECHG = f O(Q T + Q B), where Q T and Q B are the gate charges of the internal top and bottom MOSFET switches. The gate charge losses are proportional to V IN and thus their effects will be more pronounced at higher supply voltages.Other “hidden” losses such as copper trace and internal battery resistances can account for additional effi ciency degradations in portable systems. The internal battery and fuse resistance losses can be minimized by making sure that C IN has adequate charge storage and very low ESR at the switching frequency. Other losses include diode conduction losses during dead-time and inductor core losses generally account for less than 2% total ad-ditional loss.Thermal ConsiderationsIn most applications the LTC3542 does not dissipate much heat due to its high effi ciency. But in applications where the LTC3542 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 60°C, both power switches will be turned off and the SW node will become high impedance.To avoid the LTC3542 from exceeding the maximum junction temperature, the user need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by:T R = (P D)(θJA)where P D is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient.The junction temperature, T J, is given by:T J = T A + T Rwhere T A is the ambient temperature.As an example, consider the LTC3542 in dropout at an input voltage of 2.7V, a load current of 500mA and an ambient temperature of 70°C. From the typical performance graph of switch resistance, the R DS(ON) of the P-channel switch at 70°C is approximately 0.7Ω. Therefore, power dissipated by the part is:P D = I LOAD2 • R DS(ON) = 175mWFor the DFN package, the θJA is 102°C/W. Thus, the junc-tion temperature of the regulator is:T J = 70°C + 0.175 • 102 = 87.9°Cwhich is below the maximum junction temperature of 125°C.Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (R DS(ON)). Checking Transient ResponseThe regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, V OUT immediately shifts by an amount equal to ΔI LOAD • ESR, where ESR is the effective series resistance of C OUT. ΔI LOAD also begins to charge or dis-charge C OUT, generating a feedback error signal used by the regulator to return V OUT to its steady-state value. During this recovery time, V OUT can be monitored for overshoot or ringing that would indicate a stability problem.The output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. For a detailed explanation of optimizing the compensation components, including a re-view of control loop theory, refer to Application Note 76. In some applications, a more severe transient can be caused by switching loads with large (>1μF) bypass capacitors. The discharged bypass capacitors are effectively put inAPPLICATIONS INFORMATION113542fa。

LTC4213 1 4213f 电子电路保护器说明书

LTC4213 1 4213f 电子电路保护器说明书

2µs/DIV4213 TA01b124213fBias Supply Voltage (V CC )...........................–0.3V to 9V Input VoltagesON, SENSEP, SENSEN.............................–0.3V to 9V I SEL ..........................................–0.3V to (V CC + 0.3V)Output VoltagesGATE .....................................................–0.3V to 15V READY.....................................................–0.3V to 9V Operating Temperature RangeLTC4213C ...............................................0°C to 70°C LTC4213I.............................................–40°C to 85°C Storage Temperature Range.................–65°C to 150°C Lead Temperature (Soldering, 10sec)...................300°CORDER PART NUMBER DDB PART*MARKING T JMAX = 125°C, θJA = 250°C/WEXPOSED PAD (PIN 9)PCB CONNECTION OPTIONALConsult LTC Marketing for parts specified with wider operating temperature ranges.*The temperature grade is identified by a label on the shipping container.LBHVLTC4213CDDB LTC4213IDDB ABSOLUTE AXI U RATI GSW W WU PACKAGE/ORDER I FOR ATIOUUW (Note 1)ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. V CC = 5V, I SEL = 0 unless otherwise noted. (Note 2)SYMBOL PARAMETER CONDITIONSMIN TYP MAX UNITSV CC Bias Supply Voltage ● 2.36V V SENSEP SENSEP Voltage ●06V I CC V CC Supply Current●1.63mA V CC(UVLR)V CC Undervoltage Lockout Release V CC Rising● 1.8 2.07 2.23V ∆V CC(UVHYST)V CC Undervoltage Lockout Hysteresis ●30100160mV I SENSEP SENSEP Input Current V SENSEP = V SENSEN = 5V, Normal Mode 154080µA V SENSEP = V SENSEN = 0, Normal Mode –1±15µA I SENSENSENSEN Input CurrentV SENSEP = V SENSEN = 5V, Normal Mode 154080µA V SENSEP = V SENSEN = 0, Normal Mode –1±15µA V SENSEP = V SENSEN = 5V,50280µAReset Mode or Fault ModeV CBCircuit Breaker Trip Voltage I SEL = 0, V SENSEP = V CC●22.52527.5mV V CB = V SENSEP – V SENSEN I SEL = Floated, V SENSEP = V CC ●455055mV I SEL = V CC, V SENSEP = V CC ●90100110mV V CB(FAST)Fast Circuit Breaker Trip Voltage I SEL = 0, V SENSEP = V CC●63100115mV V CB(FAST)= V SENSEP – V SENSEN I SEL = Floated, V SENSEP = V CC ●126175200mV I SEL = V CC, V SENSEP = V CC ●252325371mV I GATE(UP)GATE Pin Pull Up Current V GATE = 0V●–50–100–150µA I GATE(DN)GATE Pin Pull Down Current ∆V SENSEP – V SENSEN = 200mV, V GATE = 8V ●1040mA ∆V GSMAX External N-Channel Gate Drive V SENSEN = 0, V CC ≥ 2.97V, I GATE = –1µA ● 4.8 6.58V V SENSEN = 0, V CC = 2.3V, I GATE = –1µA ● 2.65 4.38V ∆V GSARMV GS Voltage to Arm Circuit BreakerV SENSEN = 0, V CC ≥ 2.97V ● 4.4 5.47.6V V SENSEN = 0, V CC = 2.3V●2.53.57VTOP VIEWDDB PACKAGE8-LEAD (3mm × 2mm) PLASTIC DFN567894321READY ON I SEL GND V CC SENSEP SENSEN GATE34213f∆V GSMAX – ∆V GSARM Difference Between ∆V GSMAX and V SENSEN = 0, V CC ≥ 2.97V ●0.3 1.1V ∆V GSARMV SENSEN = 0, V CC = 2.3V●0.150.8VV READY(OL)READY Pin Output Low Voltage I READY = 1.6mA, Pull Down Device On ●0.20.4V I READY(LEAK)READY Pin Leakage Current V READY = 5V, Pull Down Device Off ●0±1µA V ON(TH)ON Pin High Threshold ON Rising, GATE Pulls Up ●0.760.80.84V ∆V ON(HYST)ON Pin Hysteresis ON Falling, GATE Pulls Down104090mV V ON(RST)ON Pin Reset Threshold ON Falling, Fault Reset, GATE Pull Down ●0.360.40.44V I ON(IN)ON Pin Input Current V ON = 1.2V●0±1µA ∆V OV Overvoltage Threshold ●0.410.7 1.1V ∆V OV = V SENSEP – V CCt OVOvervoltage Protection Trip Time V SENSEP = V SENSEN = Step 5V to 6.2V 2565160µs t FAULT(SLOW)V CB Trips to GATE Discharging ∆V SENSE Step 0mV to 50mV,●71627µs V SENSEN Falling, V CC = V SENSEP = 5V t FAULT(FAST)V CB(FAST) Trips to GATE Discharging ∆V SENSE Step 0V to 0.3V, V SENSEN Falling,●12.5µs V SENSEP = 5Vt DEBOUNCE Startup De-Bounce Time V ON = 0V to 2V Step to Gate Rising,2760130µs (Exiting Reset Mode)t READY READY Delay Time V GATE = 0V to 8V Step to READY Rising,2250115µs V SENSEP = V SENSEN = 0t OFF Turn-Off Time V ON = 2V to 0.6V Step to GATE Discharging 1.5510µs t ON Turn-On Time V ON = 0.6V to 2V Step to GATE Rising,4816µs (Normal Mode)t RESETReset TimeV ON Step 2V to 0V2080150µsNote 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.ELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. V CC = 5V, I SEL = 0 unless otherwise noted. (Note 2)SYMBOLPARAMETERCONDITIONSMIN TYP MAX UNITSNote 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to ground unless otherwise specified.4564213ft RESET vs Temperaturet FAULT(SLOW) vs V CCt FAULT(SLOW) vs Temperaturet FAULT(FAST) vs V CCt FAULT(FAST) vs TemperatureTYPICAL PERFOR A CE CHARACTERISTICSU WSpecifications are at T A = 25°C. V CC = 5Vunless otherwise noted.t F A U L T (F A S T ) (µs )4213 G230.90.80.71.01.11.21.3TEMPERATURE (°C)–50050100125–252575BIAS SUPPLY VOLTAGE (V)2.010t F A U L T (S L O W ) (µs )14121618 3.0 4.0 5.0 6.04213 G202022 2.53.54.55.5TEMPERATURE (°C)–500501001254213 G21–25257510t F A U L T (S L O W ) (µs )141216182022TEMPERATURE (°C)–500501001254213 G19–252575t R E S E T (µs )60708090100BIAS SUPPLY VOLTAGE (V)2.0t F A U L T (F A S T ) (µs )3.04.05.06.04213 G222.53.54.55.50.90.80.71.01.11.21.374213fPI FU CTIO SU U UREADY (Pin 1): READY Status Output. Open drain output that goes high impedance when the external MOSFET is on and the circuit breaker is armed. Otherwise this pin pulls low.ON (Pin 2): ON Control Input. The LTC4213 is in reset mode when the ON pin is below 0.4V. When the ON pin increases above 0.8V, the device starts up and the GATE pulls up with a 100µA current source. When the ON pin drops below 0.76V, the GATE pulls down. To reset a circuit breaker fault, the ON pin must go below 0.4V.I SEL (Pin 3): Threshold Select Input. With the I SEL pin grounded, float or tied to V CC the V CB is set to 25mV, 50mV or 100mV, respectively. The corresponding V CB(FAST)values are 100mV, 175mV and 325mV.GND (Pin 4): Device Ground.GATE (P in 5): GATE D rive Output. An internal charge pump supplies 100µA pull-up current to the gate of the external N-channel MOSFET. Internal circuitry limits thevoltage between the GATE and SENSEN pins to a safe gate drive voltage of less than 8V. When the circuit breaker trips, the GATE pin abruptly pulls to GND.SENSEN (Pin 6): Circuit Breaker Negative Sense Input.Connect this pin to the source of the external MOSFET.During reset or fault mode, the SENSEN pin discharges the output to ground with 280µA.SENSEP (P in 7): Circuit Breaker Positive Sense Input.Connect this pin to the drain of external N-channel MOSFET.The circuit breaker trips when the voltage across SENSEP and SENSEN exceeds V CB . The input common mode range of the circuit breaker is from ground to V CC + 0.2V when V CC < 2.5V. For V CC ≥ 2.5V, the input common mode range is from ground to V CC + 0.4V.V CC (Pin 8): Bias Supply Voltage Input. Normal operation is between 2.3V and 6V. An internal under-voltage lockout circuit disables the device when V CC < 2.07V.Exposed Pad (Pin 9): Exposed pad may be left open or connected to device ground.8910114213fsupply transient dips below 1.97V of less than 80µs are ignored.ON FunctionWhen V ON is below comparator COMP1’s threshold of 0.4V for 80µs, the device resets. The system leaves reset mode if the ON pin rises above comparator COMP2’s threshold of 0.8V and the UVLO condition is met. Leaving reset mode, the GATE pin starts up after a t DEBOUNCE delay of 60µs. When ON goes below 0.76V, the GATE shuts off after a 5µs glitch filter delay. The output is discharged by the external load when V ON is in between 0.4V to 0.8V. At this state, the ON pin can re-enable the GATE if V ON exceeds 0.8V for more than 8µs. Alternatively, the device resets if the ON pin is brought below 0.4V for 80µs. Once reset, the GATE pin restarts only after the t DEBOUNCE 60µs delay at V ON rising above 0.8V. To protect the ON pin from overvoltage stress due to supply transients, a series resistor of greater than 10k is recommended when the ON pin is connected directly to the supply. An external resis-tive divider at the ON pin can be used with COMP2 to set a supply undervoltage lockout value higher than the inter-nal UVLO circuit. An RC filter can be implemented at the ON pin to increase the powerup delay time beyond the internal 60µs delay.Gate FunctionThe GATE pin is held low in reset mode. 60µs after leaving reset mode, the GATE pin is charged up by an internal 100µA current source. The circuit breaker arms when V GATE > V SENSEN + ∆V GSARM . In normal mode operation,the GATE peak voltage is internally clamped to ∆V GSMAX above the SENSEN pin. When the circuit breaker trips, an internal MOSFET shorts the GATE pin to GND, turning off the external MOSFET.READY StatusThe READY pin is held low during reset and at startup. It is pulled high by an external pullup resistor 50µs after the circuit breaker arms. The READY pin pulls low if the circuit breaker trips or the ON pin is pulled below 0.76V, or V CC drops below undervoltage lockout.∆V GSARM and V GSMAXEach MOSFET has a recommended V GS drive voltage where the channel is deemed fully enhanced and R DSON is minimized. Driving beyond this recommended V GS volt-age yields a marginal decrease in R DSON . At startup, the gate voltage starts at ground potential. The GATE ramps past the MOSFET threshold and the load current begins to flow. When V GS exceeds ∆V GSARM , the circuit breaker is armed and enabled. The chosen MOSFET should have a recommended minimum V GS drive level that is lower than ∆V GSARM . Finally, V GS reaches a maximum at ∆V GSMAX.Trip and Reset Circuit BreakerFigure 2 shows the timing diagram of V GATE and V READY after a fault condition. A tripped circuit breaker can be reset either by cycling the V CC bias supply below UVLO thresh-old or pulling ON below 0.4V for >t RESET . Figure 3 shows the timing diagram for a tripped circuit breaker being reset by the ON pin.Calculating Current LimitThe fault current limit is determined by the R DSON of the MOSFET and the circuit breaker voltage V CB .I V R LIMIT CB DSON=()2The R DSON value depends on the manufacturer’s distribu-tion, V GS and junction temperature. Short Kelvin-sense connections between the MOSFET drain and source to the LTC4213 SENSEP and SENSEN pins are strongly recommended.For a selected MOSFET, the nominal load limit current is given by:I V R LIMIT NOM CB NOM DSON NOM ()()()()=3The minimum load limit current is given by:I V R LIMIT MIN CB MIN DSON MAX ()()()()=4APPLICATIO S I FOR ATIOW UUU1213144213fOperating temperature of 0° to 70°C.R DSON @ 25°C = 100%R DSON @ 0°C = 90%R DSON @ 70°C = 120%MOSFET resistance variation:R DSON(NOM) = 15m • 0.82 = 12.3m ΩR DSON(MAX) = 15m • 1.333 • 0.93 • 1.2 = 15m • 1.488= 22.3m ΩR DSON(MIN) = 15m • 0.667 • 0.80 • 0.90 = 15m • 0.480= 7.2m ΩV CB variation:NOM V CB = 25mV = 100%MIN V CB = 22.5mV = 90%MAX V CB = 27.5mV = 110%The current limits are:I LIMIT(NOM) = 25mV/12.3m Ω = 2.03A I LIMIT(MIN) = 22.5mV/22.3m Ω = 1.01A I LIMIT(MAX) = 27.5mV/7.2m Ω = 3.82AFor proper operation, the minimum current limit must exceed the circuit maximum operating load current with margin. So this system is suitable for operating load current up to 1A. From this calculation, we can start with the general rule for MOSFET R DSON by assuming maxi-mum operating load current is roughly half of the I LIMIT(NOM). Equation 7 shows the rule of thumb.I V R OPMAX CB NOM DSON NOM =()()•()27Note that the R DSON(NOM) is at the LTC4213 nominal operating ∆V GSMAX rather than at typical vendor spec.Table 1 gives the nominal operating ∆V GSMAX at the various operating V CC . From this table users can refer to the MOSFET’s data sheet to obtain the R DSON(NOM) value.Table 1. Nominal Operating ∆V GSMAX for Typical Bias Supply VoltageV CC (V)∆V GSMAX (V)2.3 4.32.5 5.02.7 5.63.0 6.53.37.05.07.06.07.0Load Supply Power-Up after Circuit Breaker Armed Figure 4 shows a normal power-up sequence for the circuit in Figure 1 where the V IN load supply power-up after circuit breaker is armed. V CC is first powered up by an auxiliary bias supply. V CC rises above 2.07V at time point 1. V ON exceeds 0.8V at time point 2. After a 60µs debounce delay, the GATE pin starts ramping up at time point 3. The external MOSFET starts conducting at time point 4. At time point 5, V GATE exceed ∆V GSARM and the circuit breaker is armed. After 50µs (t READY delay), READY pulls high by an external resistor at time point 6. READY signals the V IN load supply module to start its ramp. The load supply begins soft-start ramp at time point 7. The load supply ramp rate must be slow to prevent circuit breaker tripping as in equation (8).∆∆V t I I C IN OPMAX LOADLOAD<−()8Where I OPMAX is the maximum operating current defined by equation 7.For illustration, V CB = 25mV and R DSON = 3.5m Ω at the nominal operating ∆V GSMAX . The maximum operating current is 3.5A (refer to equation 7). Assuming the load can draw a current of 2A at power-up, there is a margin of 1.5A available for C LOAD of 100µF and V IN ramp rate should be <15V/ms. At time point 8, the current through the MOSFET reduces after C LOAD is fully charged.APPLICATIO S I FOR ATIOW UUU1516174213fThe selected MOSFET V GS absolute maximum rating should meet the LTC4213 maximum ∆V GSMAX of 8V.Other MOSFET criteria such as V BDSS , I DMAX , and R DSON should be reviewed. Spikes and ringing above maximum operating voltage should be considered when choosing V BDSS . I DMAX should be greater than the current limit. The maximum operating load current is determined by the R DSON value. See the section on “Calculating Current Limit” for details.Supply RequirementsThe LTC4213 can be powered from a single supply or dual supply system. The load supply is connected to the SENSEP pin and the drain of the external MOSFET. In the single supply case, the V CC pin is connected to the load supply, preferably with an RC filter. With dual supplies,V CC is connected to an auxiliary bias supply V AUX where V AUX voltage should be greater or equal to the load supply voltage. The load supply voltage must be capable of sourcing more current than the circuit breaker limit. If the load supply current limit is below the circuit breaker trip current, the LTC4213 may not react when the output overloads. Furthermore, output overloads may trigger UVLO if the load supply has foldback current limit in a single supply system.V IN Transient and Overvoltage ProtectionInput transient spikes are commonly observed whenever the LTC4213 responds to overload. These spikes can be large in amplitude, especially given that large decoupling capacitors are absent in hot swap environments. These short spikes can be clipped with a transient suppressor of adequate voltage and power rating. In addition, the LTC4213can detect a prolonged overvoltage condition. WhenAPPLICATIO S I FOR ATIOW UUU point 6 should be within the circuit breaker limits. Other-wise, the system fails to start and the circuit breaker trips immediately after arming. In most applications additional external gate capacitance is not required unless C LOAD is large and startup becomes problematic. If an external gate capacitor is employed, its capacitance value should not be excessive unless it is used with a series resistor. This is because a big gate capacitor without resistor slows down the GATE turn off during a fault. An alternative method would be a stepped I SEL pin to allow a higher current limit during startup.In the event of output short circuit or a severe overload, the load supply can collapse during GATE ramp up due to load supply current limit. The chosen MOSFET must withstand this possible brief short circuit condition before time point 6 where the circuit breaker is allowed to trip. Bench short circuit evaluation is a practical verification of a reliable design. To have current limit while powering a MOSFET into short circuit conditions, it is preferred that the load supply sequences to turn on after the circuit breaker is armed as described in an earlier section.Power-Off CycleThe system can be powered off by toggling the ON pin low.When ON is brought below 0.76V for 5µs, the GATE and READY pins are pulled low. The system resets when ON is brought below 0.4V for 80µs.MOSFET SelectionThe LTC4213 is designed to be used with logic (5V) and sub-logic (3V) MOSFETs for V CC potentials above 2.97V with ∆V GSMAX exceeding 4.5V. For a V CC supply range between 2.3V and 2.97V, sub-logic MOSFETs should be used as the minimum ∆V GSMAX is less than 4.5V.1819Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.201630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● © LINEAR TECHNOLOGY CORPORA TION 2005LT/TP 0405 500 • PRINTED IN USA。

IC集成电路型号大全及40系列芯片功能大全

IC集成电路型号大全及40系列芯片功能大全

IC集成电路型号大全及40系列芯片功能大全CD4001 四2输入端或者非门CD4002 双4输入端或者非门CD4006 18位串入/串出移位寄存器CD4007 双互补对加反相器CD4008 4位超前进位全加器CD4009 六反相缓冲/变换器CD4010 六同相缓冲/变换器CD4011 四2输入端与非门CD4012 双4输入端与非门CD4013 双主-从D型触发器CD4014 8位串入/并入-串出移位寄存器CD4015 双4位串入/并出移位寄存器CD4016 四传输门CD4017 十进制计数/分配器CD4018 可预制1/N计数器CD4019 四与或者选择器CD4020 14级串行二进制计数/分频器CD4021 08位串入/并入-串出移位寄存器CD4022 八进制计数/分配器CD4023 三3输入端与非门CD4024 7级二进制串行计数/分频器CD4025 三3输入端或者非门CD4026 十进制计数/7段译码器CD4027 双J-K触发器CD4028 BCD码十进制译码器CD4029 可预置可逆计数器CD4030 四异或者门CD4031 64位串入/串出移位存储器CD4032 三串行加法器CD4033 十进制计数/7段译码器CD4034 8位通用总线寄存器CD4035 4位并入/串入-并出/串出移位寄存CD4038 三串行加法器CD4040 12级二进制串行计数/分频器CD4041 四同相/反相缓冲器CD4042 四锁存D型触发器CD4043 三态R-S锁存触发器("1"触发)CD4044 四三态R-S锁存触发器("0"触发)CD4046 锁相环CD4047 无稳态/单稳态多谐振荡器CD4048 四输入端可扩展多功能门CD4049 六反相缓冲/变换器CD4050 六同相缓冲/变换器CD4051 八选一模拟开关CD4052 双4选1模拟开关CD4053 三组二路模拟开关CD4054 液晶显示驱动器CD4055 BCD-7段译码/液晶驱动器CD4056 液晶显示驱动器CD4059 “N”分频计数器 NSC/TICD4060 14级二进制串行计数/分频器CD4063 四位数字比较器CD4066 四传输门CD4067 16选1模拟开关CD4068 八输入端与非门/与门CD4069 六反相器CD4070 四异或者门CD4071 四2输入端或者门CD4072 双4输入端或者门CD4073 三3输入端与门CD4075 三3输入端或者门CD4076 四D寄存器CD4077 四2输入端异或者非门CD4078 8输入端或者非门/或者门CD4081 四2输入端与门CD4082 双4输入端与门CD4085 双2路2输入端与或者非门CD4086 四2输入端可扩展与或者非门CD4089 二进制比例乘法器CD4093 四2输入端施密特触发器CD4095 三输入端J-K触发器CD4096 三输入端J-K触发器CD4097 双路八选一模拟开关CD4098 双单稳态触发器CD4099 8位可寻址锁存器CD40100 32位左/右移位寄存器CD40101 9位奇偶较验器CD40102 8位可预置同步BCD减法计数器CD40103 8位可预置同步二进制减法计数器CD40104 4位双向移位寄存器CD40105 先入先出FI-FD寄存器CD40106 六施密特触发器CD40107 双2输入端与非缓冲/驱动器CD40108 4字×4位多通道寄存器CD40109 四低-高电平位移器CD40110 十进制加/减,计数,锁存,译码驱动CD40147 10-4线编码器CD40160 可预置BCD加计数器CD40161 可预置4位二进制加计数器CD40162 BCD加法计数器CD40163 4位二进制同步计数器CD40174 六锁存D型触发器CD40175 四D型触发器CD40181 4位算术逻辑单元/函数发生器CD40182 超前位发生器CD40192 可预置BCD加/减计数器(双时钟) CD40193 可预置4位二进制加/减计数器CD40194 4位并入/串入-并出/串出移位寄存CD40195 4位并入/串入-并出/串出移位寄存CD40208 4×4多端口寄存器CD4501 4输入端双与门及2输入端或者非门CD4502 可选通三态输出六反相/缓冲器CD4503 六同相三态缓冲器CD4504 六电压转换器CD4506 双二组2输入可扩展或者非门CD4508 双4位锁存D型触发器CD4510 可预置BCD码加/减计数器CD4511 BCD锁存,7段译码,驱动器CD4512 八路数据选择器CD4513 BCD锁存,7段译码,驱动器(消隐) CD4514 4位锁存,4线-16线译码器CD4515 4位锁存,4线-16线译码器CD4516 可预置4位二进制加/减计数器CD4517 双64位静态移位寄存器CD4518 双BCD同步加计数器CD4519 四位与或者选择器CD4520 双4位二进制同步加计数器CD4521 24级分频器CD4522 可预置BCD同步1/N计数器CD4526 可预置4位二进制同步1/N计数器CD4527 BCD比例乘法器CD4528 双单稳态触发器CD4529 双四路/单八路模拟开关CD4530 双5输入端优势逻辑门CD4531 12位奇偶校验器CD4532 8位优先编码器CD4536 可编程定时器CD4538 精密双单稳CD4539 双四路数据选择器CD4541 可编程序振荡/计时器CD4543 BCD七段锁存译码,驱动器CD4544 BCD七段锁存译码,驱动器CD4547 BCD七段译码/大电流驱动器CD4549 函数近似寄存器CD4551 四2通道模拟开关CD4553 三位BCD计数器CD4555 双二进制四选一译码器/分离器CD4556 双二进制四选一译码器/分离器CD4558 BCD八段译码器CD4560 "N"BCD加法器CD4561 "9"求补器CD4573 四可编程运算放大器CD4574 四可编程电压比较器CD4575 双可编程运放/比较器CD4583 双施密特触发器CD4584 六施密特触发器CD4585 4位数值比较器CD4599 8位可寻址锁存器CD22100 4×4×1交叉点开关0206A 天线开关集成电路03VFG9 发射压控振荡集成电路1021AC 发射压控振荡集成电路1097C 升压集成电路140N 电源取样比较放大集成电路14DN363 伺服操纵集成电路15105 充电操纵集成电路15551 管理卡升压集成电路1710 视频信号处理集成电路1N706 混响延时集成电路20810-F6096 存储集成电路2252B 微处理集成电路2274 延迟集成电路24C01ACEA 存储集成电路24C026 存储集成电路24C04 存储集成电路24C64 码片集成电路24LC16B 存储集成电路24LC65 电可改写编程只读存储集成电路27C1000PC-12 存储集成电路27C2000QC-90 存储集成电路27C20T 存储集成电路27C512 电可改写编程只读存储集成电路2800 红外遥控信号接收集成电路28BV64 码片集成电路28F004 版本集成电路31085 射频电源集成电路32D54 电源、音频信号处理集成电路1732D75 电源、音频信号处理集成电路32D92 电源中频放大集成电路4066B 电子开关切换集成电路4094 移位寄存串入、并出集成电路424260SDJ 存储集成电路4260 动态随机存储集成电路4270351/91B9905 中频放大集成电路4370341/90M9919 中频处理集成电路4464 存储集成电路4558 双运算放大集成电路4580D 双运算放大集成电路47C1638AN-U337 微处理集成电路47C1638AU-353 微处理集成电路47C432GP 微处理集成电路47C433AN-3888 微处理集成电路49/4CR1A 中频放大集成电路5101 天线开关集成电路5G052 发光二极管四位显示驱动集成电路5G24 运算放大集成电路5W01 双运算放大集成电路649/CRIA70612 中频放大集成电路673/3CR2A 多模转换集成电路74122 可重触发单稳态集成电路74HC04 逻辑与非门集成电路74HC04D 六反相集成电路74HC123 单稳态集成电路74HC125 端口功能扩展集成电路74HC14N 六反相集成电路74HC157A 多路转换集成电路74HC165 移相寄存集成电路1874HC245 总线收发集成电路74HC32 或者门四2输入集成电路74HC374八D 触发集成电路74HC573D 存储集成电路74HCT157 多路转换双输入集成电路74HCT4046A 压控振荡集成电路74HCT4538D 单稳态集成电路74HCT4538N 触发脉冲集成电路74HCT86D 异或者门四2输入集成电路74HCU04 与非门集成电路74LS125 端口功能扩展集成电路74LS373 锁存集成电路74LS393 计数双四位二进制集成电路74LS74双D 触发集成电路78014DFP 系统操纵处理集成电路811N 伴音阻容偏置集成电路83D33 压控振荡集成电路85712 场扫描信号校正处理集成电路85713 行扫描信号校正集成电路87C52 微处理集成电路87CK38N-3584 微处理集成电路87CK38N-3627 微处理集成电路89C52 系统操纵处理集成电路89C55 系统操纵处理集成电路93C66 电可改写编程只读存储集成电路93LC56 电可改写编程存储集成电路9821K03 系统操纵集成电路A1642P 背景歌声消除集成电路A701 红外遥控信号接收集成电路A7950 场频识别集成电路19A8772AN 色差信号延迟处理集成电路A9109 功率放大集成电路AAB 电源集成电路ACA650 色度信号解调集成电路ACFP2 色度、亮度信号分离集成电路ACP2371 多伴音、多语言改善集成电路ACVP2205 色度、亮度信号分离集成电路AD1853 立体声数/模转换集成电路AD1858 音频解调集成电路AD722 视频编码集成电路ADC2300E 音频数/模转换集成电路ADC2300J 音频数/模转换集成电路ADC2310E 音频数/模转换集成电路ADV7172 视频编码集成电路ADV7175A 视频编码集成电路AE31201 频率显示集成电路AJ7080 射频调制集成电路AK4321-VF-E1 音频数/模转换集成电路AN1319 双高速电压比较集成电路AN1358S 双运算放大集成电路AN1393 双运算放大集成电路AN1431T 稳压电源集成电路AN1452 音频前置放大集成电路AN1458S 双运算放大集成电路AN206 伴音中频及前置放大集成电路AN222 自动频率操纵集成电路AN236 副载波信号处理集成电路AN239Q 图像、伴音中频放大集成电路AN247P 图像中频放大、AGC操纵集成电路AN253P 调频/调幅中频放大集成电路20AN262 音频前置放大集成电路AN2661NK 视频信号处理集成电路AN2663K 视频信号处理集成电路AN272 音频功率放大集成电路AN2751FAP 视频信号处理集成电路AN281 色度解码集成电路AN2870FC 多功能操纵集成电路AN295 行、场扫描信号处理集成电路AN301 伺服操纵集成电路AN305 视频自动增益操纵集成电路AN306 色度自动相位操纵集成电路AN318 直流伺服操纵集成电路AN320 频率操纵、调谐显示驱动集成电路AN3215K 视频信号处理集成电路AN3215S 视频信号处理集成电路AN3224K 磁头信号记录放大集成电路AN3248NK 亮度信号记录、重放处理集成电路AN331 视频信号处理集成电路AN3311K 磁头信号放大集成电路AN3313 磁头信号放大集成电路AN3321S 录像重放信号处理集成电路AN3331K 磁头信号处理集成电路AN3337NSB 磁头信号放大集成电路AN3380K 磁头信号处理集成电路AN3386NK 磁头信号处理集成电路AN3495K 色度、亮度信号降噪集成电路AN355 伴音中频放大、检波集成电路AN3581S 视频驱动集成电路AN366 调频/调幅中频放大集成电路AN3791 移位操纵集成电路21AN3792 磁鼓伺服操纵接口集成电路AN3795 主轴伺服操纵接口集成电路AN3814K 电机驱动集成电路AN4265 音频功率放大集成电路AN4558 运算放大集成电路AN5010 电子选台集成电路AN5011 电子选台集成电路AN5015K 电子选台集成电路AN5020 红外遥控信号接收集成电路AN5025S 红外遥控信号接收集成电路AN5026K 红外遥控信号接收集成电路AN5031 电调谐操纵集成电路AN5034 调谐操纵集成电路AN5036 调谐操纵集成电路AN5043 调谐操纵集成电路AN5071 频段转换集成电路AN5095K 电视信号处理集成电路AN5110 图像中频放大集成电路AN5130 图像中频、视频检波放大集成电路AN5138NK 图像、伴音中频放大集成电路AN5156K 电视信号处理集成电路AN5177NK 图像、伴音中频放大集成电路AN5179K 图像、伴音中频放大集成电路AN5183K 中频信号处理集成电路AN5195K 中频、色度、扫描信号处理集成电路AN5215 伴音信号处理集成电路AN5520 伴音中频放大及鉴频集成电路AN5222 伴音中频放大集成电路AN5250 伴音中频放大、鉴频及功率放大集成电路AN5262 音频前置放大集成电路22AN5265 音频功率放大集成电路AN5270 音频功率放大集成电路AN5273 双声道音频功率放大集成电路AN5274 双声道音频功率放大集成电路AN5275 中置、3D放大集成电路AN5285K 双声道前置放大集成电路AN5295NK 音频信号切换集成电路AN5312 视频、色度信号处理集成电路AN5313NK 视频、色度信号处理集成电路AN5342 图像水平轮廓校正集成电路AN5342FB 水平清晰度操纵集成电路AN5344FBP 色度信号处理集成电路AN5348K 人工智能信号处理集成电路AN5385K 色差信号放大集成电路AN5410 行、场扫描信号处理集成电路AN5421 同步检测集成电路AN5422 行、场扫描信号处理集成电路AN5512 场扫描输出集成电路AN5515 场扫描输出集成电路AN5521 场扫描输出集成电路AN5532 场扫描输出集成电路AN5534 场扫描输出集成电路AN5551 枕形校正集成电路AN5560 场频识别集成电路AN5600K 中频、亮度、色度及扫描信号处理集成电路AN5601K 视频、色度、同步信号处理集成电路AN5607K 视频、色度、行场扫描信号处理集成电路AN5615 视频信号处理集成电路AN5620X 色度信号处理集成电路AN5621 场扫描输出集成电路23AN5625 色度信号处理集成电路AN5633K 色度信号处理集成电路AN5635 色度解码集成电路AN5635NS 色度解码集成电路AN5637 色度解码、亮度延迟集成电路AN5650 同步信号分离集成电路AN5682K 基色电子开关切换集成电路AN5693K 视频、色度、行场扫描信号处理集成电路AN5712 图像中频放大、AGC操纵集成电路AN5722 图像中频放大、检波集成电路AN5732 伴音中频放大、鉴频集成电路AN5743 音频功率放大集成电路AN5750 行自动频率操纵及振荡集成电路AN5757S 行扫描电源电压操纵集成电路AN5762 场扫描振荡、输出集成电路AN5764 光栅水平位置操纵集成电路AN5765 电源稳压操纵集成电路AN5767 同步信号处理集成电路AN5768 光栅倾斜校正操纵集成电路AN5769 行、场会聚操纵集成电路AN5790N 行扫描信号处理集成电路AN5791 同步脉冲相位与脉宽调整集成电路AN5803 双声道立体声解调集成电路AN5836 双声道前置放大集成电路AN5858K 视频信号操纵集成电路AN5862 视频信号操纵集成电路AN5862S-E1 视频信号开关操纵集成电路AN5870K 模拟信号切换集成电路AN5891K 音频信号处理集成电路AN614 行枕形校正集成电路24AN6210 双声道前置放大集成电路AN6306S 亮度信号处理集成电路AN6308 模拟电子开关集成电路AN6327 视频重放信号处理集成电路AN6341N 伺服操纵集成电路AN6342N 基准分频集成电路AN6344 伺服操纵集成电路AN6345 分频集成电路AN6346N 磁鼓伺服操纵集成电路AN6350 磁鼓伺服操纵集成电路AN6357N 主轴接口集成电路AN6361N 色度信号处理集成电路AN6367NK 色度信号处理集成电路AN6371S 自动相位操纵集成电路AN6387 电机伺服操纵集成电路AN6550 卡拉OK音频放大集成电路AN6554 四运算放大集成电路AN6561 双运算放大集成电路AN6562SG 双运算放大集成电路AN6609N 电机驱动集成电路AN6612 电机稳速操纵集成电路AN6650 电机速度操纵集成电路AN6651 电机速度操纵集成电路AN6652 电机稳速操纵集成电路AN6875 发光二极管五位显示驱动集成电路AN6877 发光二极管七位显示驱动集成电路AN6884 发光二极管五位显示驱动集成电路AN6886 发光二极管五位显示驱动集成电路AN6888 发光二极管显示驱动集成电路AN6914 双电压比较集成电路25AN7085N5 单片录、放音集成电路AN7105 双声道音频功率放大集成电路AN7106K 双声道音频功率放大集成电路AN7108 单片立体声放音集成电路AN710S 单片放音集成电路AN7110E 音频功率放大集成电路AN7114 音频功率放大集成电路AN7116 音频功率放大集成电路AN7118 双声道音频功率放大集成电路AN7118S 双声道音频功率放大集成电路AN7120 音频功率放大集成电路AN7124 双声道音频功率放大集成电路AN7145 双声道音频功率放大集成电路AN7148 双声道音频功率放大集成电路AN7158N 音频功率放大7.5W×2集成电路AN7161N 音频功率放大集成电路AN7164 双声道音频功率放大集成电路AN7171NK 音频功率放大集成电路AN7205 调频/调谐及高频放大集成电路AN7220 调频/调幅中频放大集成电路AN7222 调频/调幅中频放大集成电路AN7223 调频/调幅中频放大集成电路AN7226 调频/调幅中频放大集成电路AN7256 调频/调谐及中频放大集成电路AN7311 双声道前置放大集成电路AN7312 双声道前置放大集成电路AN7315 双声道前置放大集成电路AN7315S 双声道前置放大集成电路AN7320 音频前置放大集成电路AN7396K 双声道前置放大集成电路26AN7397K 双声道前置放大集成电路AN7410 调频立体声多路解码集成电路AN7414 调频立体声解码集成电路AN7420N 调频立体声解码集成电路AN7470 调频立体声解码集成电路AN7805 三端电源稳压+5V/1A集成电路AN7806 三端电源稳压+6V/1A集成电路AN7807 三端电源稳压+7V/1A集成电路AN7808 三端电源稳压+8V/1A集成电路AN7809 电源稳压+9V/1A集成电路AN7810 三端电源稳压+10V/1A集成电路AN7812 三端电源稳压+12V/1A集成电路AN7815 三端电源稳压+15V/1A集成电路AN7818 三端电源稳压+18V/1A集成电路AN7820 三端电源稳压+20V/1A集成电路AN7824 三端电源稳压+24V/1A集成电路AN78L05 三端电源稳压+5V/0.1A集成电路AN78L06 三端电源稳压+6V/0.1A集成电路AN78L08 三端电源稳压+8V/0.1A集成电路AN78L09 三端电源稳压+9V/0.1A集成电路AN78L10 三端电源稳压+10V/0.1A集成电路AN78L12 三端电源稳压+12V/0.1A集成电路AN78L15 三端电源稳压+15V/0.1A集成电路AN78L18 三端电源稳压+18V/0.1A集成电路AN78L20 三端电源稳压+20V/0.1A集成电路AN78L24 三端电源稳压+24V/0.1A集成电路AN78M05 三端电源稳压+5V/0.5A集成电路AN78M06 三端电源稳压+6V/0.5A集成电路AN78M08 三端电源稳压+8V/0.5A集成电路AN78M09 三端电源稳压+9V/0.5A集成电路27AN78M10 三端电源稳压+10V/0.5A集成电路AN78M12 三端电源稳压+12V/0.5A集成电路AN78M15 三端固定式稳压+15V/0.5A集成电路AN78M18 三端电源稳压+18V/0.5A集成电路AN78M20 三端电源稳压+20V/0.5A集成电路AN78M24 三端电源稳压+24V/0.5A集成电路AN7905 三端电源稳压-5V/1A集成电路AN7906 三端电源稳压-6V/1A集成电路AN7908T 三端电源稳压-8V/1A集成电路AN7909T 三端电源稳压-9V/1A集成电路AN7910T 三端电源稳压-10V/1A集成电路AN7912 三端电源稳压-12V/1A集成电路AN7915 三端电源稳压-15V/1A集成电路AN7918 三端电源稳压-18V/1A集成电路AN7920 三端电源稳压-20V/1A集成电路AN7924 三端电源稳压-24V/1A集成电路AN79L05 三端电源稳压-5V/0.1A集成电路AN79L06 三端电源稳压-6V/0.1A集成电路AN79L08 三端电源稳压-8V/0.1A集成电路AN79L09 三端电源稳压-9V/0.1A集成电路AN79L10 三端电源稳压-10V/0.1A集成电路AN79L12 三端电源稳压-12V/0.1A集成电路AN79L15 三端电源稳压-15V/0.1A集成电路AN79L18 三端电源稳压-18V/0.1A集成电路AN79L20 三端电源稳压-20V/0.1A集成电路AN79L24 三端电源稳压-24V/0.1A集成电路AN79M05 三端电源稳压-5V/0.5A集成电路AN79M06 三端电源稳压-6V/0.5A集成电路AN79M08 三端电源稳压-8V/0.5A集成电路AN79M09 三端电源稳压-9V/0.5A集成电路28AN79M10 三端电源稳压-10V/0.5A集成电路AN79M12 三端电源稳压-12V/0.5A集成电路AN79M15 三端电源稳压-15V/0.5A集成电路AN79M18 三端电源稳压-18V/0.5A集成电路AN79M20 三端电源稳压-20V/0.5A集成电路AN79M24 三端电源稳压-24V/0.5A集成电路AN8028 自激式开关电源操纵集成电路AN8270K 主轴电机操纵集成电路AN8280 电机驱动集成电路AN8281S 电机驱动集成电路AN8290S 主轴电机驱动集成电路AN8355S 条形码扫描接收集成电路AN8370S 光电伺服操纵集成电路AN8373S 射频伺服处理集成电路AN8375S 伺服处理集成电路AN8389S-E1 电机驱动集成电路AN8480NSB 主轴电机驱动集成电路AN8481SB-E1 主轴电机驱动集成电路AN8482SB 主轴电机驱动集成电路AN8623FBQ 主轴伺服处理集成电路AN8788FB 电机驱动集成电路AN8802CE1V 伺服处理集成电路AN8813NSBS 主轴电机驱动集成电路AN8819NFB 伺服驱动、直流交换集成电路AN8824FBQ 前置放大集成电路AN8825NFHQ-V 聚焦、循迹误差处理集成电路AN8831SC 视频预视放集成电路AN8832SB-E1 射频放大、伺服处理集成电路AN8837SB-E1 伺服处理集成电路AN89C2051-24PC 微处理集成电路29APU2400U 音频信号处理集成电路APU2470 音频信号处理集成电路AS4C14405-60JC 动态随机存储1M×4集成电路AS4C256K16ED-60JC 存储集成电路ASD0204-015 图文操纵集成电路ASD0204GF-022-3BA显示操纵集成电路AT24C08 存储集成电路AT24C08A 存储集成电路AT24C256-10CI 码片集成电路AT27C010 电可改写编程只读存储集成电路AT27C020 存储集成电路ATMEL834 存储集成电路AVM-1 视频信号处理厚膜集成电路AVM-2 音频信号处理厚膜集成电路AVSIBCP08 倍压整流切换集成电路B0011A 存储集成电路B1218 电子快门操纵集成电路BA033T 三端电源稳压+3.3V集成电路BA10324 四运算放大集成电路BA10393N 双运算放大集成电路BA1102F 杜比降噪处理集成电路BA1106F 杜比降噪处理集成电路BA12ST 电源稳压集成电路BA1310 调频立体声解码集成电路BA1332L 调频立体声解码集成电路BA1350 调频立体声解码集成电路BA1351 调频立体声解码集成电路BA1356 调频立体声解码集成电路BA1360 调频立体声解码集成电路BA15218N 双运算放大集成电路30BA225 可触发双单稳态振荡集成电路BA302 音频前置放大集成电路BA311 音频前置放大集成电路BA313 音频前置放大集成电路BA3283 单片放音集成电路BA328F 双声道前置放大集成电路BA329 双声道前置放大集成电路BA3304F 录放音前置均衡放大集成电路BA3306 音频、前置放大集成电路BA3312N 话筒信号前置放大集成电路BA3313L 自动音量操纵集成电路BA3314 话筒信号前置放大集成电路BA335 自动选曲集成电路BA336 自动选曲集成电路BA340 音频前置放大集成电路BA3402F 双声道前置放大集成电路BA3404F 自返转放音集成电路BA343 双声道前置放大集成电路BA3503F 双声道前置放大集成电路BA3506 单片放音集成电路BA3513FS 单片放音集成电路BA3516 单片放音集成电路BA3706 自动选曲集成电路BA3707 录音带曲间检测集成电路BA3812L 五频段音调补偿集成电路BA3818F 电压比较运放集成电路BA3822LS 双声道五频段显示均衡集成电路BA3828 电子选台预置集成电路BA3880 音频处理集成电路31BA401 调频中频放大集成电路BA402 调频中频放大集成电路BA4110 调频中频放大集成电路BA4234L 调频中频放大集成电路BA4402 调频调谐收音集成电路BA4403 调频高频放大、混频、本振集成电路BA4560 双运算放大集成电路BA5096 数字混响集成电路BA5102A 音频功率放大集成电路BA514 音频功率放大集成电路BA516 音频功率放大集成电路BA5208AF 音频功率放大集成电路BA532 音频功率放大集成电路BA534 音频功率放大集成电路BA5406 双声道音频功率放大集成电路BA5412 音频功率放大集成电路BA547 音频功率放大1.5W集成电路BA5912AFP-YE2 电机驱动、倾斜、加载集成电路BA5981FP-E2 聚焦、循迹驱动集成电路BA5983FB 四通道伺服驱动集成电路BA5983FM-E2 电机驱动集成电路BA6104 发光二极管五位显示驱动集成电路BA6107A 电机伺服操纵集成电路BA6109 加载电机驱动集成电路BA6125 发光二极管五位显示驱动集成电路BA6137 发光二极管五位显示驱动集成电路BA6191 音频操纵集成电路BA6196FP 伺服驱动集成电路BA6208 电机驱动集成电路BA6208D 电机驱动集成电路32BA6209 电机驱动集成电路BA6209N 双向驱动电机集成电路BA6218 加载电机驱动集成电路BA6219 电机驱动集成电路BA6219B 电机驱动集成电路BA6227 电机稳速操纵集成电路BA6238 电机驱动集成电路BA6239 电机双向驱动集成电路BA6239A 电机双向驱动集成电路BA6246M 加载、转盘电机驱动集成电路BA6248 电机驱动集成电路BA6286 电机驱动集成电路BA6287 电机驱动集成电路BA6290 电机驱动集成电路BA6295AFP-E2 加载、倾斜驱动集成电路BA6296FP 电机速度操纵集成电路BA6297AFP 伺服驱动集成电路BA6302A 电机伺服操纵集成电路BA6305 操纵放大集成电路BA6305F 操纵放大集成电路BA6308 电子开关切换集成电路BA6321 电机伺服操纵集成电路BA6392 伺服驱动集成电路BA6395 主轴电机驱动集成电路BA6396FP 伺服驱动集成电路BA6411 电机驱动集成电路BA6435S 主轴电机驱动集成电路BA6459P1 电机驱动集成电路BA6570FP-E2 聚焦、循迹驱动集成电路33BA6664FM 三相主电机驱动集成电路BA6791FP 四通道伺服驱动集成电路BA6796FP 电机驱动集成电路BA6810S 音频显示驱动集成电路BA6844AFP-E2 三相主电机驱动集成电路BA6849FP 主轴电机驱动集成电路BA689 发光二极管十二位显示驱动集成电路BA6893KE2 直流变换驱动集成电路BA6956AN 加载电机驱动集成电路BA6993 双运算放大集成电路BA7001 音频切换集成电路BA7004 测试信号发生集成电路BA7005AL 射频调制集成电路BA7007 信号检测集成电路BA7021 视频信号选择集成电路BA7024 视频信号测试集成电路BA7025L 信号检测集成电路BA7042 振荡集成电路BA7047 调频检波集成电路BA7048N 包络信号检测集成电路BA7106LS 检测信号操纵集成电路BA7180FS 磁头信号放大集成电路BA7212S 磁头信号放大集成电路BA7253S 磁头信号放大集成电路BA7254S 四磁头信号放大集成电路BA7258AS 亮度信号处理集成电路BA7264S 视频信号处理集成电路BA7274S 磁头信号放大集成电路BA7357S 中频放大集成电路BA7604N 电子开关切换集成电路34BA7606F 色差信号切换集成电路BA7655 色度信号处理集成电路BA7665FS-E2 视频输出放大集成电路BA7725FS 混响立体声放大集成电路BA7725S 信号压缩及扩展处理集成电路BA7743FS 磁头信号放大集成电路BA7751ALS 音频信号录放处理集成电路BA7752LS 音频信号处理集成电路BA7755 磁头开关集成电路BA7755AF-E2 磁头开关集成电路BA7765AS 音频信号处理集成电路BA7766SA 音频信号处理集成电路BA7767AS 音频信号处理集成电路BA7797F 音频信号处理集成电路BA8420 特技操纵处理集成电路BAL6309 场同步信号发生集成电路BH3866AS 音频、色度信号前置放大集成电路BH4001 微处理集成电路BH7331P 音频功率放大集成电路BH7770KS 音频信号处理集成电路BL3207 亮度延时集成电路BL3208B 音频延迟混响集成电路BL5132 中频放大集成电路BL54573 电子调频波段转换集成电路BL5612 视频放大、色差矩阵集成电路BM5060 微处理集成电路BM5061 字符发生集成电路BM5069 微处理集成电路BN5115 图像中频放大集成电路BOC31F 单片微处理集成电路35BP5020 视频电源转换集成电路BT852 视频编码集成电路BT864 视频编码集成电路BT866PQFP 微处理集成电路BU12102 时序信号发生解码集成电路BU2092F 扩展集成电路BU2185F 同步信号处理集成电路BU2285FV 时钟信号发生集成电路BU2820 伺服操纵集成电路BU2841FS 视频、蓝背景信号发生集成电路BU2872AK 操作系统操纵、屏显驱动集成电路BU3762AF 红外遥控信号发射集成电路BU4053B 电子开关切换集成电路BU5814F 红外遥控信号发射集成电路BU5994F 红外遥控信号发射集成电路BU6198F 屏幕显示集成电路BU9252F 音频延时集成电路BU9252S 数/模转换集成电路BU9253FS 话筒音频混响集成电路BX1303 音频功率放大集成电路BX1409 红外遥控信号接收集成电路BX7506 主轴电机电源操纵集成电路C1363CA 红外遥控电子选台集成电路C1490HA 红外遥控信号接收集成电路C187 分配、十进制计数集成电路C301 译码BCD-10段集成电路C68639Y 微处理集成电路C75P036 微处理集成电路CA0002 调幅模拟声解调集成电路CA2004 音频功率放大集成电路36CA2006 音频功率放大集成电路CA270AW 视频检波放大集成电路CA3075 调频中频放大集成电路CA3089 调频中频放大集成电路CA3120E 视频信号处理集成电路CA3140 运算放大集成电路CA810 音频功率放大集成电路CA920 行扫描信号处理集成电路CAS126 天线开关集成电路CAT24C16 电可改写编程只读存储集成电路CAT35C104HP 存储集成电路CC4000 或者非门双3输入集成电路CC4008 计数4位二进制集成电路CC40107 与非双2输入缓冲、驱动集成电路CC40174 六D触发集成电路CC40194 移位寄存集成电路CC4025 或者非门3输入集成电路CC4026 译码、驱动、十进制计数集成电路CC4027 上升沿J-K触发集成电路。

LVXT4052资料

LVXT4052资料

MC74LVXT4052Analog Multiplexer/DemultiplexerHigh−Performance Silicon−Gate CMOSThe MC74LVXT4052 utilizes silicon−gate CMOS technology to achieve fast propagation delays, low ON resistances, and low OFF leakage currents. This analog multiplexer/demultiplexer controls analog voltages that may vary across the complete power supply range (from V CC to V EE ).The LVXT4052 is similar in pinout to the high−speed HC4052A and the metal−gate MC14052B. The Channel−Select inputs determine which one of the Analog Inputs/Outputs is to be connected, by means of an analog switch, to the Common Output/Input. When the Enable pin is HIGH, all analog switches are turned off.The Channel−Select and Enable inputs are compatible with standard TTL levels.This device has been designed so the ON resistance (R ON ) is more linear over input voltage than the R ON of metal−gate CMOS analog switches and High−Speed CMOS analog switches.Features•Select Pins Compatible with TTL Levels •Fast Switching and Propagation Speeds •Low Crosstalk Between Switches•Analog Power Supply Range (V CC − V EE ) = *3.0 V to )3.0 V •Digital (Control) Power Supply Range (V CC − GND) = 2.5 to 6.0 V •Improved Linearity and Lower ON Resistance Than Metal−Gate,HSL, or VHC Counterparts •Low Noise•Designed to Operate on a Single Supply with V EE = GND, or Using Split Supplies up to $3.0 V •Break−Before−Make Circuitry •Pb−Free Packages are Available**For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting TechniquesReference Manual, SOLDERRM/D.MARKING DIAGRAMSA=Assembly Location WL or L =Wafer Lot Y=YearWW or W=Work WeekTSSOP−16DT SUFFIX CASE 948FSOEIAJ−16M SUFFIX CASE 966SOIC−16D SUFFIX CASE 751BSee detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet.ORDERING INFORMATIONLVXT4052AWLYWWLVXT 4052ALYWLVXT4052ALYW116116116151614131211102134567V CC 98X2X1X X0X3A B Y0Y2Y Y3Y1Enable V EEGNDFigure 1. Pin Connection and Marking Diagram(Top View)Figure 2. Logic DiagramDouble−Pole, 4−Position Plus Common OffFUNCTION TABLEL L H H XL H L H XControl InputsON Channels Enable SelectB A X0X1X2X3L L L L H X = Don’t CareY0Y1Y2Y3NONEXANALOGINPUTS/OUTPUTSCHANNEL-SELECTINPUTSCC EE COMMONOUTPUTS/INPUTSYNOTE: This device allows independent control of each switch.Channel−Select Input A controls the X−Switch, Input B controls the Y−Switch.ORDERING INFORMATIONSpecifications Brochure, BRD8011/D.*This package is inherently Pb−Free.values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,damage may occur and reliability may be affected.1.Tested to EIA/JESD22−A114−A.2.Tested to EIA/JESD22−A115−A.3.Tested to JESD22−C101−A.4.Tested to EIA/JESD78.RECOMMENDED OPERATING CONDITIONSDEVICE JUNCTION TEMPERATURE VERSUSTIME TO 0.1% BOND FAILURES11101001000Figure 3. Failure Rate vs. Time Junction TemperatureN O R M A L I Z E D F A I L U R E R A T ETIME, YEARSDC CHARACTERISTICS−Digital Section (Voltages Referenced to GND)DC ELECTRICAL CHARACTERISTICS−Analog SectionAC CHARACTERISTICS(Input t = t = 3 ns)AC CHARACTERISTICS(C L = 50 pF, Input t r = t f = 3 ns)ed to determine the no−load dynamic power consumption: P D = C PD V CC f + I CC V CC. ADDITIONAL APPLICATION CHARACTERISTICS(GND = 0 V)Figure 4. On Resistance, Test Set−UpFigure 5. Maximum Off Channel Leakage Current,Any One Channel, Test Set−Up Figure 6. Maximum On Channel Leakage Current,Channel to Channel, Test Set−UpFigure 7. Maximum On Channel Bandwidth, Test Set−UpV V V N/CFigure 8. Maximum Off Channel Feedthrough Isolation, Test Set−UpFigure 9. Maximum Common−Channel Feedthrough Isolation, Test Set−UpConfig = Network Format = T/R (dB)CAL = Trans CalDisplay = Rectan X *A )B Scale Ref = Auto Scale View = Off, Off, Off Trig = Cont ModeSource Amplitude = )13 dB Reference Attenuation = 20 dB Test Attenuation = 0 dBV ISO (dB) = 20 log (V T1/V R1)Format = T/R (dB)CAL = Trans CalDisplay = Rectan X *A )B Scale Ref = Auto Scale View = Off, Off, Off Trig = Cont ModeSource Amplitude = )13 dB Reference Attenuation = 20 dB Test Attenuation = 0 dBV ISOC (dB) = 20 log (V T1/V R1)Figure 10. Charge Injection, Test Set−UpV OUTV INOUTFigure 11. Maximum On Channel Feedthrough On Loss, Test Set−UpFormat = T/R (dB)CAL = Trans CalDisplay = Rectan X *A )B Scale Ref = Auto Scale View = Off, Off, Off Trig = Cont ModeSource Amplitude = )13 dB Reference Attenuation = 20 dB Test Attenuation = 20 dBV ONL (dB) = 20 log (V T1/V R1)Figure 12. Break−Before−Make, Test Set−Up Figure 13. Break−Before−Make TimeCC*TESTPOINTL *TESTPOINT W PZH PZL Figure 16. Propagation Delays, Enable toAnalog Out Figure 17. Propagation Delay, Test Set−UpEnable to Analog OutFigure 18. Power Dissipation Capacitance, Test Set−UpFigure 19. Total Harmonic Distortion, Test Set−UpAPPLICATIONS INFORMATIONThe Channel Select and Enable control pins should be at V CC or GND logic levels. V CC being recognized as a logic high and GND being recognized as a logic low. In this example:V CC = )5 V = logic high GND = 0 V = logic lowThe maximum analog voltage swing is determined by the supply voltages V CC and V EE . The positive peak analog voltage should not exceed V CC . Similarly, the negative peak analog voltage should not go below V EE . In this example,the difference between V CC and V EE is five volts. Therefore,using the configuration of Figure 21, a maximum analog signal of five volts peak−to−peak can be controlled. Unused analog inputs/outputs may be left floating (i.e., not connected). However, tying unused analog inputs andoutputs to V CC or GND through a low value resistor helps minimize crosstalk and feedthrough noise that may be picked up by an unused switch.Although used here, balanced supplies are not a requirement. The only constraints on the power supplies are that:V EE − GND = 0 to *6 volts V CC − GND = 2.5 to 6 volts V CC − V EE = 2.5 to 6 voltsand V EE v GNDWhen voltage transients above V CC and/or below V EE are anticipated on the analog channels, external Germanium or Schottky diodes (D x ) are recommended as shown in Figure 22. These diodes should be able to absorb the maximum anticipated current surges during clipping.Figure 20. Application Example +3.0 V −3.0 V+3.0 V −3.0 VFigure 21. Application Example+5 V GND+5 V GNDFigure 22. External Germanium or Schottky Clipping DiodesFigure 23. Function Diagram, LVXT4052X0X1X2X3Y0Y1Y2Y3YABENABLEXPACKAGE DIMENSIONSNOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION.4.MAXIMUM MOLD PROTRUSION 0.15 (0.006)PER SIDE.5.DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.SBM0.25 (0.010)AST DIM MIN MAX MIN MAX INCHESMILLIMETERS A 9.8010.000.3860.393B 3.80 4.000.1500.157C 1.35 1.750.0540.068D 0.350.490.0140.019F 0.40 1.250.0160.049G 1.27 BSC 0.050 BSC J 0.190.250.0080.009K 0.100.250.0040.009M 0 7 0 7 P 5.80 6.200.2290.244R0.250.500.0100.019____SOIC−16D SUFFIX CASE 751B−05ISSUE JTSSOP−16DT SUFFIX CASE 948F−01ISSUE ADIM MIN MAX MIN MAX INCHESMILLIMETERS A 4.90 5.100.1930.200B 4.30 4.500.1690.177C −−− 1.20−−−0.047D 0.050.150.0020.006F 0.500.750.0200.030G 0.65 BSC 0.026 BSC H 0.180.280.0070.011J 0.090.200.0040.008J10.090.160.0040.006K 0.190.300.0070.012K10.190.250.0070.010L 6.40 BSC 0.252 BSC M0 8 0 8 NOTES:1.DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.2.CONTROLLING DIMENSION: MILLIMETER.3.DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS.MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE.4.DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.5.DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08(0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION.6.TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY .7.DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE −W−.____16X REF KSOEIAJ−16M SUFFIX CASE 966−01ISSUE OON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further noticeto any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.PUBLICATION ORDERING INFORMATION。

cd4052中文资料_数据手册_参数

cd4052中文资料_数据手册_参数

NOTE: When ordering, use the entire part number. The suffixes 96 and R denote tape and reel. The suffix T denotes a small-quantity reel of 250.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
-55 to 125 16 Ld SOIC
CD4051BNSR, CD4052BNSR, CD4053BNSR
-55 to 125 16 Ld SOP
CD4051BPW, CD4051BPWR, CD4052BPW, CD4052BPWR CD4053BPW, CD4053BPWR
-55 to 125 16 Ld TSSOP
- Digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3V to 20V
- Analog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤20VP-P
[ /Title • Low ON Resistance, 125Ω (Typ) Over 15VP-P Signal Input (CD405 Range for VDD-VEE = 18V
1B,
• High OFF Resistance, Channel Leakage of ±100pA (Typ)
LOGIC LEVEL CONVERSION

利特尔比特ltc4059 ltc4059a-900ma-线性锂离子电池充电器用热控制在2-2 dfn

利特尔比特ltc4059 ltc4059a-900ma-线性锂离子电池充电器用热控制在2-2 dfn

124059fbInput Supply Voltage (V CC )...................... –0.3V to 10V BAT, PROG, EN, Li CC, ACPR ................... –0.3V to 10V BAT Short-Circuit Duration...........................Continuous BAT Pin Current............................................... 1000mA PROG Pin Current............................................. 1000µA Junction Temperature.......................................... 125°C Operating Temperature Range (Note 2)..–40°C to 85°C Storage Temperature Range.................–65°C to 125°CORDER PART NUMBER Consult LTC Marketing for parts specified with wider operating temperature ranges.LTC4059EDC LTC4059AEDC ABSOLUTE AXI U RATI GSW W WU PACKAGE/ORDER I FOR ATIOUUW (Note 1)T JMAX = 125°C, θJA = 60°C/W TO 85°C/W (NOTE 3)*Li CC PIN 2 ON LTC4059EDC,ACPR PIN 2 ON LTC4059AEDC EXPOSED PAD (PIN 7) IS GND MUST BE SOLDERED TO PCBTOP VIEW7DC6 PACKAGE6-LEAD (2mm × 2mm) PLASTIC DFN456321GND BAT EN PROG V CCLi CC/ACPR*DC6 PART MARKING LAFU LBJHELECTRICAL CHARACTERISTICSThe ● denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. V CC = 5V unless otherwise noted.SYMBOL PARAMETERCONDITIONSMIN TYP MAX UNITSV CC V CC Supply Voltage●3.758V I CC Quiescent V CC Supply Current V BAT = 4.5V (Forces I BAT and I PROG = 0)●2560µA I CCMS V CC Supply Current in Shutdown V EN = V CC●1025µA I CCUV V CC Supply Current in Undervoltage V CC < V BAT ; V CC = 3.5V, V BAT = 4V ●410µA LockoutV FLOAT V BAT Regulated Output Voltage I BAT = 2mA4.175 4.2 4.225V 4.5V < V CC < 8V, I BAT = 2mA● 4.158 4.2 4.242V I BAT BAT Pin CurrentR PROG = 2.43k, Current Mode, V BAT = 3.8V ●475500525mA R PROG = 12.1k, Current Mode, V BAT = 3.8V ●94100106mA I BMS Battery Drain Current in Shutdown V EN = V CC , V CC > V BAT ●0±1µA I BUV Battery Drain Current in Undervoltage V CC < V BAT , V BAT = 4V●014µA LockoutV UV V CC – V BAT Undervoltage Lockout V CC from Low to High, V BAT = 3.7V ●100150200mV ThresholdV CC from High to Low, V BAT = 3.7V ●03580mV V PROG PROG Pin VoltageR PROG = 2.43k, I PROG = 500µA ● 1.18 1.21 1.24V R PROG = 12.1k, I PROG = 100µA ● 1.18 1.21 1.24V V MS Manual Shutdown Threshold V EN Increasing ●0.30.92 1.2V V MSHYS Manual Shutdown Hysteresis V EN Decreasing 85mV R EN EN Pin Input ResistanceV EN = 5V●1 1.853M ΩV Li CC Voltage Mode Disable Threshold V Li CC Increasing (LTC4059 Only)●0.30.92 1.2V V Li CCHYS Voltage Mode Disable Hysteresis V Li CC Decreasing (LTC4059 Only)85mV V ACPR ACPR Pin Output Low Voltage I ACPR = 300µA (LTC4059A Only)0.250.5V t LIM Junction Temperature In Constant 115°C Temperature ModeR ONPower FET “ON” Resistance I BAT = 150mA (Note 4)8001200m Ω(Between V CC and BAT)Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.Note 2: The LTC4059E/LTC4059AE are guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls.Note 3: Failure to solder the exposed backside of the package to the PC board ground plane will result in a thermal resistance much higher than 60°C/W.Note 4: The FET on-resistance is guaranteed by correlation to wafer level measurements.3454059fbPI FU CTIO SU U UGND (P ins 1, 7): Ground/Exposed Pad. The exposed package pad is ground and must be soldered to the PC board for maximum heat transfer.Li CC (Pin 2, LTC4059): Li-Ion/Constant Current Input Pin. Pulling this pin above V Li CC disables voltage mode thereby providing a constant current to the BAT pin. This feature is useful for charging Nickel chemistry batteries.Tie to GND if unused.ACP R (P in 2, LTC4059A): Open-Drain Power Supply Status Output. When V CC is greater than the undervoltage lockout threshold, the ACPR pin will pull to ground;otherwise the pin is forced to a high impedance state.BAT (P in 3): Charge Current Output. Provides charge current to the battery and regulates the final float voltage to 4.2V. An internal precision resistor divider from this pin sets this float voltage and is disconnected in shutdown mode.V CC (P in 4): Positive Input Supply Voltage. This pin provides power to the charger. V CC can range from 3.75V to 8V. This pin should be bypassed with at least a 1µF capacitor. When V CC is within 35mV of the BAT pin voltage, the LTC4059 enters shutdown mode, dropping I BAT to less than 4µA.PROG (Pin 5): Charge Current Program and Charge Cur-rent Monitor Pin. Connecting a resistor, R PROG , to ground programs the charge current. When charging in constant-current mode, this pin servos to 1.21V. In all modes, the voltage on this pin can be used to measure the charge current using the following formula:I V R BAT PROGPROG=•1000EN (Pin 6): Enable Input Pin. Pulling this pin above the manual shutdown threshold (V MS is typically 0.92V) puts the LTC4059 in shutdown mode, thus terminating a charge cycle. In shutdown mode, the LTC4059 has less than 25µA supply current and less than 1µA battery drain current.Enable is the default state, but the pin should be tied to GND if unused.674059fbOPERATIOUThe LTC4059/LTC4059A are linear battery chargers de-signed primarily for charging single cell lithium-ion bat-teries. Featuring an internal P-channel power MOSFET,the chargers use a constant-current/constant-voltage charge algorithm with programmable current. Charge current can be programmed up to 900mA with a final float voltage accuracy of ±0.6%. No blocking diode or external sense resistor is required; thus, the basic charger circuit requires only two external components. The ACPR pin (LTC4059A) monitors the status of the input voltage with an open-drain output. The Li C C pin (LTC4059) disables constant-voltage operation and turns the LTC4059 into a precision current source capable of charging Nickel chem-istry batteries. Furthermore, the LTC4059/LTC4059A are designed to operate from a USB power source.An internal thermal limit reduces the programmed charge current if the die temperature attempts to rise above a preset value of approximately 115°C. This feature protects the LTC4059/LTC4059A from excessive temperature, and allows the user to push the limits of the power handling capability of a given circuit board without risk of damaging the LTC4059/LTC4059A or external components. Anotherbenefit of the thermal limit is that charge current can be set according to typical, not worst-case, ambient tempera-tures for a given application with the assurance that the charger will automatically reduce the current in worst-case conditions.The charge cycle begins when the voltage at the V CC pin rises approximately 150mV above the BAT pin voltage, a program resistor is connected from the PROG pin to ground, and the EN pin is pulled below the shutdown threshold (typically 0.92V).If the BAT pin voltage is below 4.2V, or the Li CC pin is pulled above V Li CC (LTC4059 only), the LTC4059 will charge the battery with the programmed current. This is constant-current mode. When the BAT pin approaches the final float voltage (4.2V), the LTC4059 enters constant-voltage mode and the charge current begins to decrease.To terminate the charge cycle the EN should be pulled above the shutdown threshold. Alternatively, reducing the input voltage below the BAT pin voltage will also terminate the charge cycle.APPLICATIO S I FOR ATIOW UUU Programming Charge CurrentThe charge current is programmed using a single resistor from the PROG pin to ground. The battery charge current is 1000 times the current out of the PROG pin. The program resistor and the charge current are calculated using the following equations:R V I I VR PROG CHG CHG PROG==10001211000121•.,•.For best stability over temperature and time, 1% metal-film resistors are recommended.The charge current out of the BAT pin can be determinedat any time by monitoring the PROG pin voltage and using the following equation:I V R BAT PROGPROG=•1000Undervoltage Lockout (UVLO)An internal undervoltage lockout circuit monitors the input voltage and keeps the charger in undervoltage lockout until V CC rises approximately 150mV above the BAT pin voltage.The UVLO circuit has a built-in hysteresis of 115mV. If the BAT pin voltage is below approximately 2.75V, then the charger will remain in undervoltage lockout until V CC rises above approximately 3V. During undervoltage lockout conditions, maximum battery drain current is 4µA.Power Supply Status Indicator (ACPR, LTC4059A Only)The power supply status output has two states: pull-down and high impedance. The pull-down state indicates that V CC is above the undervoltage lockout threshold (see Undervoltage Lockout). When this condition is not met,the ACPR pin is high impedance indicating that the LTC4059A is unable to charge the battery.894059fbPower DissipationThe conditions that cause the LTC4059/LTC4059A to reduce charge current through thermal feedback can be approximated by considering the power dissipated in the IC. For high charge currents, the LTC4059 power dissipa-tion is approximately:P D = (V CC – V BAT ) • I BATwhere P D is the power dissipated, V CC is the input supply voltage, V BAT is the battery voltage and I BAT is the charge current. It is not necessary to perform any worst-case power dissipation scenarios because the LTC4059/LTC4059A will automatically reduce the charge current to maintain the die temperature at approximately 115°C.However, the approximate ambient temperature at which the thermal feedback begins to protect the IC is:T A = 115°C – P D θJAT A = 115°C – (V CC – V BAT ) • I BAT • θJAExample: Consider an LTC4059 operating from a 5V wall adapter providing 900mA to a 3.7V Li-Ion battery. The ambient temperature above which the LTC4059/LTC4059A begin to reduce the 900mA charge current is approximately:T A = 115°C – (5V – 3.7V) • (900mA) • 50°C/W T A = 115°C – 1.17W • 50°C/W = 115°C – 59°C T A = 56°CThe LTC4059 can be used above 56°C, but the charge current will be reduced from 900mA. The approximate current at a given ambient temperature can be calculated:I C T V V BAT A CC BAT JA=°()115––•θUsing the previous example with an ambient temperature of 65°C, the charge current will be reduced to approximately:I C C V V C W CC AI mABAT BAT =°°()°=°°=11565537505065770––.•//F urthermore, the voltage at the PROG pin will change proportionally with the charge current as discussed in the Programming Charge Current section.It is important to remember that LTC4059/LTC4059A applications do not need to be designed for worst-case thermal conditions since the IC will automatically reduce power dissipation when the junction temperature reaches approximately 115°C.Board Layout ConsiderationsIn order to be able to deliver maximum charge current under all conditions, it is critical that the exposed metal pad on the backside of the LTC4059/LTC4059A package is soldered to the PC board ground. Correctly soldered to a 2500mm 2 double sided 1oz copper board the LTC4059/LTC4059A have a thermal resistance of approximately 60°C/W. F ailure to make thermal contact between the exposed pad on the backside of the package and the copper board will result in thermal resistances far greater than 60°C/W. As an example, a correctly soldered LTC4059/LTC4059A can deliver over 900mA to a battery from a 5V supply at room temperature. Without a backside thermal connection, this number could drop to less than 500mA.Stability ConsiderationsThe LTC4059 contains two control loops: constant voltage and constant current. The constant-voltage loop is stable without any compensation when a battery is connected with low impedance leads. Excessive lead length, how-ever, may add enough series inductance to require a bypass capacitor of at least 1µF from BAT to GND. Further-more, a 4.7µF capacitor with a 0.2Ω to 1Ω series resistor from BAT to GND is required to keep ripple voltage low when the battery is disconnected.High value capacitors with very low ESR (especially ce-ramic) reduce the constant-voltage loop phase margin.Ceramic capacitors up to 22µF may be used in parallel with a battery, but larger ceramics should be decoupled with 0.2Ω to 1Ω of series resistance.I n constant-current mode, the PROG pin is in the feedback loop, not the battery. Because of the additional pole created by PROG pin capacitance, capacitance on this pin must be kept to a minimum. With no additional capaci-tance on the PROG pin, the charger is stable with program resistor values as high as 12k. However, additional ca-pacitance on this node reduces the maximum allowedAPPLICATIO S I FOR ATIOW UUUFigure 5. Photo of Typical Circuit (2.5mm × 2.7mm) 1011Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.121630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 ● FAX: (408) 434-0507 ● © LINEAR TECHNOLOGY CORPORA TION 2003LT/LT 0505 REV B • PRINTED IN USA。

LTC3632EDD#TRPBF,LTC3632EMS8E#TRPBF,LTC3632IMS8E#PBF,LTC3632IDD#TRPBF, 规格书,Datasheet 资料

LTC3632EDD#TRPBF,LTC3632EMS8E#TRPBF,LTC3632IMS8E#PBF,LTC3632IDD#TRPBF, 规格书,Datasheet 资料

PIN CONFIGURATION
TOP VIEW
TOP VIEW SW VIN ISET SS 1 2 3 4 9 GND 8 7 6 5 GND HYST VFB RUN
SW 1 VIN 2 ISET 3 SS 4 9 GND
8 7 6 -LEAD PLASTIC MSOP TJMAX = 125°C, θJA = 40°C/W, θJC = 5°-10°C/W EXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCB
TYPICAL APPLICATION
5V, 20mA Step-Down Converter
VIN 5V TO 50V 1µF 1mH SW LTC3632 RUN VFB HYST ISET SS GND VIN VOUT 5V 10µF 20mA
Efficiency and Power Loss vs Load Current
SYMBOL VIN UVLO PARAMETER Input Voltage Operating Range VIN Undervoltage Lockout VIN Overvoltage Lockout DC Supply Current (Note 3) Active Mode Sleep Mode Shutdown Mode Feedback Comparator Trip Voltage Feedback Comparator Hysteresis Voltage Feedback Pin Current Feedback Voltage Line Regulation RUN Pin Threshold Voltage VFB = 1V VIN = 4.5V to 50V RUN Rising RUN Falling Hysteresis RUN = 1.3V RUN < 1V, IHYST = 1mA VHYST = 1.3V VSS < 1.5V SS Pin Floating ISET Floating 500k Resistor from ISET to GND ISET Shorted to GND ISW = –10mA ISW = 10mA

CD4052BMS中文资料

CD4052BMS中文资料
The CD4052BMS is a differential 4 channel multiplexer having two binary control inputs, A and B, and an inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog inputs to the outputs.
BINARY TO
1 OF 4 DECODER
WITH INHIBIT
TG
COMMON X
OUT/IN
TG
13
TG
3
COMMON Y
TG
OUT/IN
*
INH 6
8 VSS
LOGIC LEVEL CONVERSION
*
A 11
*
B 10
*
C9
*
INH 6
TG
7 VEE
TG 1524 0123 Y CHANNELS IN/OUT
H1E
H6W
†CD4052B, CD4053 Only
• Analog and Digital Multiplexing and Demultiplexing
• A/D and D/A Conversion
• Signal Gating
* When these devices are used as demultiplexers the “CHANNEL IN/OUT” terminals are the outputs and the “COMMON OUT/IN” terminals are the inputs.

LTC4054

LTC4054
GND(2):电源地。 BAT(3):充电电流输出脚。向电池提供充电电流,同时控制充电完成电压为 4.2V。内部精确电阻分压
器从改脚引出,控制输出电压。关断模式下,此电阻分压器从改脚断开连接。 VCC(4):电源输入正极。向充电器供电,电压范围 4.5V 至 6.5V。接 1μF 对地电容以减少纹波。 PROG(5):充电电流编程器脚,充电电流监测与充电开关。可通过此脚与地之间链接的 1%电阻来设定
工作范围(2)
2of 6
参数 输入电压
结温
LTC4054
独立线性锂电池充电器
符号
V CC
TJ
数值 -0.3 ~ +10 -40 ~ +80
单位 V °C
直流电学特性
(VCC = 5V, TJ= 25 °C,特别标注除外)
参数
符号 整流输出电压 BAT脚电流 涓流充电电流 涓流隔值电压
4of 6
应用说明
LTC4054
独立线性锂电池充电器
稳定性:
恒流反馈控制环路无需输出电容即可输出稳定的电压给外接在充电器输出端上的电池。如无外接电 池,输出应接一输出电容以 减少纹波。如使用大容量、低ESR的陶瓷电容,则应在电容上串一个1Ω为 佳;如使用钽电容则无需串联电阻。
恒流模式下,PROG脚为反馈环路。恒流模式的稳定性受PROG脚的阻抗影响。如无外加电容于 PROG脚上,则当编程电阻高至20KΩ时,充电器仍能保持稳定;然而,如有外加电容,最大允许编程 电阻将减小。
1of 6
管脚描述
LTC4054
独立线性锂电池充电器
管脚号
1 2 3 4 5
管脚名
CHRG GND BAT VCC PROG
功能

EUP8202-4.2(中文)(相容LTC4002)

EUP8202-4.2(中文)(相容LTC4002)

EUP8202-4.2/8.4A开关模式锂离子/聚合物电池充电器概述EUP8202是一款恒流,恒压锂离子电池充电控制器,它采用了电流模式PWM降压开关结构。

在500KHz的开关频率下,EUP8202给快速充电的单节(4.2V)或双节(8.4V)锂离子电池提供了小巧、简单且高效的解决方案。

EUP8202给电池充电有三个阶段:预充,恒流和恒压。

一个外部的检测电阻设定充电电流的大小(精度为±10%)。

一个内部电阻分压器和精准的参考电压将每节电池的最终浮动电压设定为4.2V±1%。

一个内部比较器检测接近充电结束的情况,而一个内部定时器设定总的充电时间和终止充电循环。

如果电池电压降到一个4.05V每节的内部门限,EUP8202自动重新开始充电。

当直流电源去掉之后,EUP8202同样自动进入休眠模式。

EUP8202可提供8脚的SOP和10脚的TDFN封装。

特点● 宽的输入电源电压范围:4.7V~20V-4.2V版8.9V~20V-8.4V版● 500kHz开关频率● 充电结束时输出指示电流● 3小时的充电终止定时器● 充电电压精度为+1%● 充电电流精度为+10%● 反向电池漏电流低至10uA● 电池自动再充电● 低电源消耗时自动进入休眠模式● 电池温度检测● 陶瓷输出电容稳定● 8引脚SOP封装和10引脚的TDFN封装● 100%无铅符合RoHS要求应用● 小巧笔记本电脑● 便携式DVD● 手持设备典型工作性能典型应用电路图1. 2A单/双节锂离子电池充电器图2. 1.5A单/双节锂离子电池充电器结构方块图图3封装类型引脚配置封装类型引脚配置TDFN-10 SOP-8引脚描述名称TDFN-10SOP-8描述COMP 11补偿,软启动和关闭控制脚。

当COMP 引脚达到850mV 时,充电开始。

推荐的补偿元件为2.2uF(或更大)电容和0.5K 串联电阻。

一个100uA 电流进入补偿电容也可设定软启动时间。

R5F21245SNFP资料

R5F21245SNFP资料

R8C/24 Group, R8C/25 GroupSINGLE-CHIP 16-BIT CMOS MCU1.OverviewThese MCUs are fabricated using a high-performance silicon gate CMOS process, embedding the R8C/Tiny Series CPU core, and are packaged in a 52-pin molded-plastic LQFP or a 64-pin molded-plastic FLGA. It implements sophisticated instructions for a high level of instruction efficiency. With 1 Mbyte of address space, they are capable of executing instructions at high speed.Furthermore, the R8C/25 Group has on-chip data flash (1 KB x 2 blocks).The difference between the R8C/24 Group and R8C/25 Group is only the presence or absence of data flash. Their peripheral functions are the same.1.1ApplicationsElectronic household appliances, office equipment, audio equipment, consumer products, etc.REJ03B0117-0300Rev.3.00Feb 29, 20081.2Performance OverviewTable 1.1 outlines the Functions and Specifications for R8C/24 Group and Table 1.2 outlines the Functions and Specifications for R8C/25 Group.NOTES:1.I 2C bus is a trademark of Koninklijke Philips Electronics N. V.2.Specify the D version if D version functions are to be used.Table 1.1Functions and Specifications for R8C/24 GroupItem SpecificationCPU Number of fundamental instructions89 instructionsMinimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.3 Product Information for R8C/24 GroupPeripheral Functions Ports I/O ports: 41 pins, Input port: 3 pins LED drive ports I/O ports: 8 pinsTimers Timer RA: 8 bits × 1 channelTimer RB: 8 bits × 1 channel(Each timer equipped with 8-bit prescaler)Timer RD: 16 bits × 2 channels(Input capture and output compare circuits)Timer RE: With real-time clock and compare match functionSerial interfaces 2 channels (UART0, UART1)Clock synchronous serial I/O, UARTClock synchronous serial interface 1 channel I 2C bus Interface (1)Clock synchronous serial I/O with chip selectLIN module Hardware LIN: 1 channel (timer RA, UART0)A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits × 1 channel (with prescaler)Reset start selectableInterrupts Internal: 11 sources, External: 5 sources, Software: 4sources, Priority levels: 7 levelsClock Clock generation circuits 3 circuits•XIN clock generation circuit (with on-chip feedback resistor)•On-chip oscillator (high speed, low speed)High-speed on-chip oscillator has a frequency adjustment function•XCIN clock generation circuit (32 kHz)Real-time clock (timer RE)Oscillation stop detection function XIN clock oscillation stop detection function Voltage detection circuit On-chip Power-on reset circuit On-chipElectrical Characteristics Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz)Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)Typ. 0.7 µA (VCC = 3.0 V, stop mode)Flash Memory Programming and erasure voltage VCC = 2.7 to 5.5 VProgramming and erasure endurance 100 timesOperating Ambient Temperature -20 to 85°C (N version)-40 to 85°C (D version)(2)-20 to 105°C (Y version)(3)Package 52-pin molded-plastic LQFP64-pin molded-plastic FLGATable 1.2Functions and Specifications for R8C/25 GroupNOTES:1.I 2C bus is a trademark of Koninklijke Philips Electronics N. V.2.Specify the D version if D version functions are to be used.Item SpecificationCPU Number of fundamental instructions89 instructionsMinimum instruction execution time 50 ns (f(XIN) = 20 MHz, VCC = 3.0 to 5.5 V)100 ns (f(XIN) = 10 MHz, VCC = 2.7 to 5.5 V)200 ns (f(XIN) = 5 MHz, VCC = 2.2 to 5.5 V)Operating mode Single-chip Address space 1 Mbyte Memory capacity Refer to Table 1.4 Product Information for R8C/25 GroupPeripheral Functions Ports I/O ports: 41 pins, Input port: 3 pins LED drive ports I/O ports: 8 pinsTimers Timer RA: 8 bits × 1 channelTimer RB: 8 bits × 1 channel(Each timer equipped with 8-bit prescaler)Timer RD: 16 bits × 2 channels(Input capture and output compare circuits)Timer RE: With real-time clock and compare match functionSerial interface 2 channels (UART0, UART1)Clock synchronous serial I/O, UARTClock synchronous serial interface 1 channel I 2C bus Interface (1)Clock synchronous serial I/O with chip selectLIN module Hardware LIN: 1 channel (timer RA, UART0)A/D converter 10-bit A/D converter: 1 circuit, 12 channels Watchdog timer 15 bits × 1 channel (with prescaler)Reset start selectableInterrupts Internal: 11 sources, External: 5 sources, Software: 4sources, Priority levels: 7 levelsClock Clock generation circuits 3 circuits•XIN clock generation circuit (with on-chip feedbackresistor)•On-chip oscillator (high speed, low speed)High-speed on-chip oscillator has a frequency adjustment function•XCIN clock generation circuit (32 kHz)Real-time clock (timer RE)Oscillation stop detection function XIN clock oscillation stop detection function Voltage detection circuit On-chip Power-on reset circuit On-chipElectrical Characteristics Supply voltage VCC = 3.0 to 5.5 V (f(XIN) = 20 MHz)VCC = 2.7 to 5.5 V (f(XIN) = 10 MHz)VCC = 2.2 to 5.5 V (f(XIN) = 5 MHz)Current consumption Typ. 10 mA (VCC = 5.0 V, f(XIN) = 20 MHz)Typ. 6 mA (VCC = 3.0 V, f(XIN) = 10 MHz)Typ. 2.0 µA (VCC = 3.0 V, wait mode (f(XCIN) = 32 kHz)Typ. 0.7 µA (VCC = 3.0 V, stop mode)Flash memory Programming and erasure voltage VCC = 2.7 to 5.5 VProgramming and erasure endurance 1,0000 times (data flash)1,000 times (program ROM)Operating Ambient Temperature -20 to 85°C (N version)-40 to 85°C (D version)(2)-20 to 105°C (Y version)(3)Package 52-pin molded-plastic LQFP64-pin molded-plastic FLGA1.3Block DiagramFigure 1.1 shows a Block Diagram.1.4Product InformationTable 1.3 lists the Product Information for R8C/24 Group and Table 1.4 lists the Product Information for R8C/25Group.NOTE:1.The user ROM is programmed before shipment.Table 1.3Product Information for R8C/24 GroupCurrent of Feb. 2008 Type No.ROM Capacity RAM Capacity Package Type Remarks R5F21244SNFP 16 Kbytes 1 Kbyte PLQP0052JA-A N version Blank productR5F21245SNFP 24 Kbytes 2 Kbytes PLQP0052JA-A R5F21246SNFP 32 Kbytes 2 Kbytes PLQP0052JA-A R5F21247SNFP 48 Kbytes 2.5 Kbytes PLQP0052JA-A R5F21248SNFP 64 Kbytes 3 Kbytes PLQP0052JA-A R5F21244SNLG 16 Kbytes 1 Kbyte PTLG0064JA-A R5F21246SNLG 32 Kbytes 2 Kbytes PTLG0064JA-A R5F21244SDFP 16 Kbytes 1 Kbyte PLQP0052JA-A D version Blank productR5F21245SDFP 24 Kbytes 2 Kbytes PLQP0052JA-A R5F21246SDFP 32 Kbytes 2 Kbytes PLQP0052JA-A R5F21247SDFP 48 Kbytes 2.5 Kbytes PLQP0052JA-A R5F21248SDFP64 Kbytes 3 Kbytes PLQP0052JA-A R5F21244SNXXXFP 16 Kbytes 1 Kbyte PLQP0052JA-A N version Factoryprogramming product (1)R5F21245SNXXXFP 24 Kbytes 2 Kbytes PLQP0052JA-A R5F21246SNXXXFP 32 Kbytes 2 Kbytes PLQP0052JA-A R5F21247SNXXXFP 48 Kbytes 2.5 Kbytes PLQP0052JA-A R5F21248SNXXXFP 64 Kbytes 3 Kbytes PLQP0052JA-A R5F21244SNXXXLG 16 Kbytes 1 Kbyte PTLG0064JA-A R5F21246SNXXXLG 32 Kbytes 2 Kbytes PTLG0064JA-A R5F21244SDXXXFP 16 Kbytes 1 Kbyte PLQP0052JA-A D version Factoryprogramming product (1)R5F21245SDXXXFP 24 Kbytes 2 Kbytes PLQP0052JA-A R5F21246SDXXXFP 32 Kbytes 2 Kbytes PLQP0052JA-A R5F21247SDXXXFP 48 Kbytes 2.5 Kbytes PLQP0052JA-A R5F21248SDXXXFP64 Kbytes3 KbytesPLQP0052JA-ANOTE:1.The user ROM is programmed before shipment.Table 1.4Product Information for R8C/25 GroupCurrent of Feb. 2008Type No.ROM CapacityRAMCapacity Package Type Remarks Program ROM Data flash R5F21254SNFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0052JA-A N version Blank productR5F21255SNFP 24 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A R5F21256SNFP 32 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A R5F21257SNFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0052JA-A R5F21258SNFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0052JA-A R5F21254SNLG 16 Kbytes 1 Kbyte × 2 1 Kbyte PTLG0064JA-A R5F21256SNLG 32 Kbytes 1 Kbyte × 2 2 Kbytes PTLG0064JA-A R5F21254SDFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0052JA-A D version Blank productR5F21255SDFP 24 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A R5F21256SDFP 32 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A R5F21257SDFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0052JA-A R5F21258SDFP64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0052JA-A R5F21254SNXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0052JA-A N version Factoryprogramming product (1)R5F21255SNXXXFP 24 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A R5F21256SNXXXFP 32 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A R5F21257SNXXXFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0052JA-A R5F21258SNXXXFP 64 Kbytes 1 Kbyte × 2 3 Kbytes PLQP0052JA-A R5F21254SNXXXLG 16 Kbytes 1 Kbyte × 2 1 Kbyte PTLG0064JA-A R5F21256SNXXXLG 32 Kbytes 1 Kbyte × 2 2 Kbytes PTLG0064JA-A R5F21254SDXXXFP 16 Kbytes 1 Kbyte × 2 1 Kbyte PLQP0052JA-A D version Factoryprogramming product (1)R5F21255SDXXXFP 24 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A R5F21256SDXXXFP 32 Kbytes 1 Kbyte × 2 2 Kbytes PLQP0052JA-A R5F21257SDXXXFP 48 Kbytes 1 Kbyte × 2 2.5 Kbytes PLQP0052JA-A R5F21258SDXXXFP64 Kbytes 1 Kbyte × 23 KbytesPLQP0052JA-A1.5Pin AssignmentsFigure 1.4 shows PLQP0052JA-A Package Pin Assignments (Top View). Figure 1.5 shows PTLG0064JA-A Package Pin Assignments.1.6Pin FunctionsTable 1.5 lists Pin Functions.I: InputO: OutputI/O: Input and outputTable 1.5Pin FunctionsTypeSymbolI/O TypeDescriptionPower supply input VCC, VSS I Apply 2.2 V to 5.5 V to the VCC pin. Apply 0 V to the VSS pin.Analog power supply input AVCC, AVSS I Power supply for the A/D converter.Connect a capacitor between AVCC and AVSS.Reset input RESET I Input “L” on this pin resets the MCU.MODE MODE I Connect this pin to VCC via a resistor.XIN clock input XIN I These pins are provided for XIN clock generation circuit I/O.Connect a ceramic resonator or a crystal oscillator between the XIN and XOUT pins. To use an external clock, input it to the XIN pin and leave the XOUT pin open.XIN clock output XOUT O XCIN clock input XCIN I These pins are provided for XCIN clock generation circuit I/O.Connect a crystal oscillator between the XCIN and XCOUT pins. To use an external clock, input it to the XCIN pin and leave the XCOUT pin open.XCIN clock output XCOUT O INT interrupt input INT0 to INT3I INT interrupt input pins.INT0 is timer RD input pin. INT1 is timer RA input pin.Key input interrupt KI0 to KI3I Key input interrupt input pins Timer RA TRAIO I/O Timer RA I/O pin TRAO O Timer RA output pin Timer RB TRBOO Timer RB output pin Timer RDTRDIOA0, TRDIOA1,TRDIOB0, TRDIOB1,TRDIOC0, TRDIOC1,TRDIOD0, TRDIOD1I/OTimer RD I/O portsTRDCLK I External clock input pin Timer RE TREO O Divided clock output pin Serial interfaceCLK0, CLK1I/O Transfer clock I/O pin RXD0, RXD1I Serial data input pins TXD0, TXD1O Serial data output pins I 2C bus interfaceSCL I/O Clock I/O pin SDAI/O Data I/O pin Clock synchronous serial I/O with chip selectSSI I/O Data I/O pinSCS I/O Chip-select signal I/O pin SSCKI/O Clock I/O pin SSOI/O Data I/O pinReference voltage input VREF I Reference voltage input pin to A/D converter A/D converter AN0 to AN11I Analog input pins to A/D converterI/O portP0_0 to P0_7, P1_0 to P1_7, P2_0 to P2_7, P3_0, P3_1,P3_3 to P3_5, P3_7, P4_3 to P4_5, P6_0 to P6_7I/OCMOS I/O ports. Each port has an I/O select direction register, allowing each pin in the port to be directed for input or output individually.Any port set to input can be set to use a pull-up resistor or not by a program.P2_0 to P2_7 also function as LED drive ports.Input port P4_2, P4_6, P4_7IInput-only portsNOTE:1.Can be assigned to the pin in parentheses by a program.Table 1.6Pin Name Information by Pin NumberPinNumber Control PinPortI/O Pin Functions for of Peripheral ModulesInterruptTimerSerial Interface ClockSynchronous Serial I/O with Chip Select I 2C busInterfaceA/D Converter2P3_5SSCK SCL 3P3_3SSI4P3_4SCSSDA5MODE 6XCIN P4_37XCOUT P4_48RESET 9XOUT P4_710VSS/AVSS11XIN P4_612VCC/AVCC13P2_7TRDIOD114P2_6TRDIOC115P2_5TRDIOB116P2_4TRDIOA117P2_3TRDIOD018P2_2TRDIOC019P2_1TRDIOB020P2_0TRDIOA0/TRDCLK21P1_7INT1TRAIO22P1_6CLK023P1_5(INT1)(1)(TRAIO)(1)RXD024P1_4TXD025P1_3KI3AN1127P4_5INT0INT028P6_6INT2TXD129P6_7INT3RXD130P1_2KI2AN1031P1_1KI1AN932P1_0KI0AN833P3_1TRBO 34P3_0TRAO35P6_5CLK136P6_437P6_338P0_7AN041P0_6AN142P0_5AN243P0_4AN344VREFP4_245P6_0TREO46P6_247P6_148P0_3AN449P0_2AN550P0_1AN651P0_0AN752P3_7SSO2.Central Processing Unit (CPU)Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a register bank. There are two sets of register bank.2.1Data Registers (R0, R1, R2, and R3)R0 is a 16-bit register for transfer, arithmetic, and logic operations. The same applies to R1 to R3. R0 can be split into high-order bits (R0H) and low-order bits (R0L) to be used separately as 8-bit data registers. R1H and R1L are analogous to R0H and R0L. R2 can be combined with R0 and used as a 32-bit data register (R2R0). R3R1 is analogous to R2R0.2.2Address Registers (A0 and A1)A0 is a 16-bit register for address register indirect addressing and address register relative addressing. It is also used for transfer, arithmetic, and logic operations. A1 is analogous to A0. A1 can be combined with A0 and as a 32-bit address register (A1A0).2.3Frame Base Register (FB)FB is a 16-bit register for FB relative addressing.2.4Interrupt Table Register (INTB)INTB is a 20-bit register that indicates the start address of an interrupt vector table.2.5Program Counter (PC)PC is 20 bits wide and indicates the address of the next instruction to be executed.2.6User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)The stack pointers (SP), USP, and ISP, are each 16 bits wide. The U flag of FLG is used to switch betweenUSP and ISP.2.7Static Base Register (SB)SB is a 16-bit register for SB relative addressing.2.8Flag Register (FLG)FLG is an 11-bit register indicating the CPU state.2.8.1Carry Flag (C)The C flag retains carry, borrow, or shift-out bits that have been generated by the arithmetic and logic unit.2.8.2Debug Flag (D)The D flag is for debugging only. Set it to 0.2.8.3Zero Flag (Z)The Z flag is set to 1 when an arithmetic operation results in 0; otherwise to 0.2.8.4Sign Flag (S)The S flag is set to 1 when an arithmetic operation results in a negative value; otherwise to 0.2.8.5Register Bank Select Flag (B)Register bank 0 is selected when the B flag is 0. Register bank 1 is selected when this flag is set to 1.2.8.6Overflow Flag (O)The O flag is set to 1 when an operation results in an overflow; otherwise to 0.2.8.7Interrupt Enable Flag (I)The I flag enables maskable interrupts.Interrupt are disabled when the I flag is set to 0, and are enabled when the I flag is set to 1. The I flag is set to 0 when an interrupt request is acknowledged.2.8.8Stack Pointer Select Flag (U)ISP is selected when the U flag is set to 0; USP is selected when the U flag is set to 1.The U flag is set to 0 when a hardware interrupt request is acknowledged or the INT instruction of software interrupt numbers 0 to 31 is executed.2.8.9Processor Interrupt Priority Level (IPL)IPL is 3 bits wide and assigns processor interrupt priority levels from level 0 to level 7.If a requested interrupt has higher priority than IPL, the interrupt is enabled.2.8.10Reserved BitIf necessary, set to 0. When read, the content is undefined.3.Memory3.1R8C/24 GroupFigure 3.1 is a Memory Map of R8C/24 Group. The R8C/24 group has 1 Mbyte of address space from addresses 00000h to FFFFFh.The internal ROM is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine.The internal RAM is allocated higher addresses, beginning with address 00400h. For example, a 2-Kbyte internal RAM area is allocated addresses 00400h to 00BFFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged.Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.3.2R8C/25 GroupFigure 3.2 is a Memory Map of R8C/25 Group. The R8C/25 group has 1 Mbyte of address space from addresses 00000h to FFFFFh.The internal ROM (program ROM) is allocated lower addresses, beginning with address 0FFFFh. For example, a 48-Kbyte internal ROM area is allocated addresses 04000h to 0FFFFh.The fixed interrupt vector table is allocated addresses 0FFDCh to 0FFFFh. They store the starting address of each interrupt routine.The internal ROM (data flash) is allocated addresses 02400h to 02BFFh.The internal RAM area is allocated higher addresses, beginning with address 00400h. For example, a 2-Kbyte internal RAM is allocated addresses 00400h to 00BFFh. The internal RAM is used not only for storing data but also for calling subroutines and as stacks when interrupt requests are acknowledged.Special function registers (SFRs) are allocated addresses 00000h to 002FFh. The peripheral function control registers are allocated here. All addresses within the SFR, which have nothing allocated are reserved for future use and cannot be accessed by users.4.Special Function Registers (SFRs)An SFR (special function register) is a control register for a peripheral function. Tables 4.1 to 4.7 list the special function registers.Table 4.1SFR Information (1)(1)X: Undefined NOTES:1.The blank regions are reserved. Do not access locations in these regions.2.Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect this register.3.The LVD0ON bit in the OFS register is set to 1 and hardware reset.4.Power-on reset, voltage monitor 0 reset or the LVD0ON bit in the OFS register is set to 0, and hardware reset.5.Software reset, watchdog timer reset, and voltage monitor 1 reset or voltage monitor 2 reset do not affect b2 and b3.6.The CSPROINI bit in the OFS register is set to 0.Address RegisterSymbolAfter reset0000h 0001h 0002h 0003h 0004h Processor Mode Register 0PM000h 0005h Processor Mode Register 1PM100h0006h System Clock Control Register 0CM001101000b 0007h System Clock Control Register 1CM100100000b0008h 0009h 000Ah Protect RegisterPRCR 00h 000Bh 000Ch Oscillation Stop Detection Register OCD 00000100b 000Dh Watchdog Timer Reset Register WDTR XXh 000Eh Watchdog Timer Start Register WDTS XXh000Fh Watchdog Timer Control Register WDC 00X11111b 0010h Address Match Interrupt Register 0RMAD000h 0011h 00h 0012h 00h 0013h Address Match Interrupt Enable Register AIER 00h 0014h Address Match Interrupt Register 1RMAD100h 0015h 00h 0016h 00h0017h 0018h 0019h 001Ah 001Bh 001Ch Count Source Protection Mode Register CSPR00h10000000b (6)001Dh 001Eh 001Fh 0020h 0021h 0022h 0023h High-Speed On-Chip Oscillator Control Register 0FRA000h0024h High-Speed On-Chip Oscillator Control Register 1FRA1When shipping 0025h High-Speed On-Chip Oscillator Control Register 2FRA200h0026h 0027h 0028h Clock Prescaler Reset FlagCPSRF 00h0029h High-Speed On-Chip Oscillator Control Register 4FRA4When shipping 002Ah 002Bh High-Speed On-Chip Oscillator Control Register 6FRA6When shipping 002Ch High-Speed On-Chip Oscillator Control Register 7FRA7When shipping0030h 0031h Voltage Detection Register 1(2)VCA100001000b 0032h Voltage Detection Register 2(2)VCA200h (3)00100000b (4)0033h 0034h 0035h 0036h Voltage Monitor 1 Circuit Control Register (5)VW1C 00001000b 0037h Voltage Monitor 2 Circuit Control Register (5)VW2C 00h0038h Voltage Monitor 0 Circuit Control Register (2)VW0C0000X000b (3)0100X001b (4)0039h 003Ah003Eh 003FhTable 4.2SFR Information (2)(1)Address Register Symbol After reset 0040h0041h0042h0043h0044h0045h0046h0047h0048h Timer RD0 Interrupt Control Register TRD0IC XXXXX000b 0049h Timer RD1 Interrupt Control Register TRD1IC XXXXX000b 004Ah Timer RE Interrupt Control Register TREIC XXXXX000b 004Bh004Ch004Dh Key Input Interrupt Control Register KUPIC XXXXX000b 004Eh A/D Conversion Interrupt Control Register ADIC XXXXX000b 004Fh SSU/IIC Interrupt Control Register(2)SSUIC / IICIC XXXXX000b 0050h0051h UART0 Transmit Interrupt Control Register S0TIC XXXXX000b 0052h UART0 Receive Interrupt Control Register S0RIC XXXXX000b 0053h UART1 Transmit Interrupt Control Register S1TIC XXXXX000b 0054h UART1 Receive Interrupt Control Register S1RIC XXXXX000b 0055h INT2 Interrupt Control Register INT2IC XX00X000b 0056h Timer RA Interrupt Control Register TRAIC XXXXX000b 0057h0058h Timer RB Interrupt Control Register TRBIC XXXXX000b 0059h INT1 Interrupt Control Register INT1IC XX00X000b 005Ah INT3 Interrupt Control Register INT3IC XX00X000b 005Bh005Ch005Dh INT0 Interrupt Control Register INT0IC XX00X000b 005Eh005Fh0060h0061h0062h0063h0064h0065h0066h0067h0068h0069h006Ah006Bh006Ch006Dh006Eh006Fh0070h0071h0072h0073h0074h0075h0076h0077h0078h0079h007Ah007Bh007Ch007Dh007Eh007FhX: UndefinedNOTES:1.The blank regions are reserved. Do not access locations in these regions.2.Selected by the IICSEL bit in the PMR register.Table 4.3SFR Information (3)(1)Address Register Symbol After reset 0080h0081h0082h0083h0084h0085h0086h0087h0088h0089h008Ah008Bh008Ch008Dh008Eh008Fh0090h0091h0092h0093h0094h0095h0096h0097h0098h0099h009Ah009Bh009Ch009Dh009Eh009Fh00A0h UART0 Transmit/Receive Mode Register U0MR00h00A1h UART0 Bit Rate Register U0BRG XXh00A2h UART0 Transmit Buffer Register U0TB XXh00A3h XXh00A4h UART0 Transmit/Receive Control Register 0U0C000001000b 00A5h UART0 Transmit/Receive Control Register 1U0C100000010b 00A6h UART0 Receive Buffer Register U0RB XXh00A7h XXh00A8h UART1 Transmit/Receive Mode Register U1MR00h00A9h UART1 Bit Rate Register U1BRG XXh00AAh UART1 Transmit Buffer Register U1TB XXh00ABh XXh00ACh UART1 Transmit/Receive Control Register 0U1C000001000b 00ADh UART1 Transmit/Receive Control Register 1U1C100000010b 00AEh UART1 Receive Buffer Register U1RB XXh00AFh XXh00B0h00B1h00B2h00B3h00B4h00B5h00B6h00B7h00B8h SS Control Register H / IIC bus Control Register 1(2)SSCRH / ICCR100h00B9h SS Control Register L / IIC bus Control Register 2(2)SSCRL / ICCR201111101b 00BAh SS Mode Register / IIC bus Mode Register(2)SSMR / ICMR00011000b 00BBh SS Enable Register / IIC bus Interrupt Enable Register(2)SSER / ICIER00h00BCh SS Status Register / IIC bus Status Register(2)SSSR / ICSR00h / 0000X000b 00BDh SS Mode Register 2 / Slave Address Register(2)SSMR2 / SAR00h00BEh SS Transmit Data Register / IIC bus Transmit Data Register(2)SSTDR / ICDRT FFh00BFh SS Receive Data Register / IIC bus Receive Data Register(2)SSRDR / ICDRR FFhX: UndefinedNOTES:1.The blank regions are reserved. Do not access locations in these regions.2.Selected by the IICSEL bit in the PMR register.Table 4.4SFR Information (4)(1)Address Register Symbol After reset 00C0h A/D Register AD XXh00C1h XXh00C2h00C3h00C4h00C5h00C6h00C7h00C8h00C9h00CAh00CBh00CCh00CDh00CEh00CFh00D0h00D1h00D2h00D3h00D4h A/D Control Register 2ADCON200h00D5h00D6h A/D Control Register 0ADCON000h00D7h A/D Control Register 1ADCON100h00D8h00D9h00DAh00DBh00DCh00DDh00DEh00DFh00E0h Port P0 Register P0XXh00E1h Port P1 Register P1XXh00E2h Port P0 Direction Register PD000h00E3h Port P1 Direction Register PD100h00E4h Port P2 Register P2XXh00E5h Port P3 Register P3XXh00E6h Port P2 Direction Register PD200h00E7h Port P3 Direction Register PD300h00E8h Port P4 Register P4XXh00E9h00EAh Port P4 Direction Register PD400h00EBh00ECh Port P6 Register P6XXh00EDh00EEh Port P6 Direction Register PD600h00EFh00F0h00F1h00F2h00F3h00F4h Port P2 Drive Capacity Control Register P2DRR00h00F5h UART1 Function Select Register U1SR XXh00F6h00F7h00F8h Port Mode Register PMR00h00F9h External Input Enable Register INTEN00h00FAh INT Input Filter Select Register INTF00h00FBh Key Input Enable Register KIEN00h00FCh Pull-Up Control Register 0PUR000h00FDh Pull-Up Control Register 1PUR1XX00XX00b 00FEh00FFhX: UndefinedNOTE:1.The blank regions are reserved. Do not access locations in these regions.Table 4.5SFR Information (5)(1)Address Register Symbol After reset 0100h Timer RA Control Register TRACR00h0101h Timer RA I/O Control Register TRAIOC00h0102h Timer RA Mode Register TRAMR00h0103h Timer RA Prescaler Register TRAPRE FFh0104h Timer RA Register TRA FFh0105h0106h LIN Control Register LINCR00h0107h LIN Status Register LINST00h0108h Timer RB Control Register TRBCR00h0109h Timer RB One-Shot Control Register TRBOCR00h010Ah Timer RB I/O Control Register TRBIOC00h010Bh Timer RB Mode Register TRBMR00h010Ch Timer RB Prescaler Register TRBPRE FFh010Dh Timer RB Secondary Register TRBSC FFh010Eh Timer RB Primary Register TRBPR FFh010Fh0110h0111h0112h0113h0114h0115h0116h0117h0118h Timer RE Second Data Register / Counter Data Register TRESEC00h0119h Timer RE Minute Data Register / Compare Data Register TREMIN00h011Ah Timer RE Hour Data Register TREHR00h011Bh Timer RE Day of Week Data Register TREWK00h011Ch Timer RE Control Register 1TRECR100h011Dh Timer RE Control Register 2TRECR200h011Eh Timer RE Count Source Select Register TRECSR00001000b 011Fh0120h0121h0122h0123h0124h0125h0126h0127h0128h0129h012Ah012Bh012Ch012Dh012Eh012Fh0130h0131h0132h0133h0134h0135h0136h0137h Timer RD Start Register TRDSTR11111100b 0138h Timer RD Mode Register TRDMR00001110b 0139h Timer RD PWM Mode Register TRDPMR10001000b 013Ah Timer RD Function Control Register TRDFCR10000000b 013Bh Timer RD Output Master Enable Register 1TRDOER1FFh013Ch Timer RD Output Master Enable Register 2TRDOER201111111b 013Dh Timer RD Output Control Register TRDOCR00h013Eh Timer RD Digital Filter Function Select Register 0TRDDF000h013Fh Timer RD Digital Filter Function Select Register 1TRDDF100hX: UndefinedNOTE:1.The blank regions are reserved. Do not access locations in these regions.。

LTC2272IUJ#PBF;LTC2272CUJ#PBF;LTC2272CUJ#TRPBF;LTC2273CUJ#TRPBF;中文规格书,Datasheet资料

LTC2272IUJ#PBF;LTC2272CUJ#PBF;LTC2272CUJ#TRPBF;LTC2273CUJ#TRPBF;中文规格书,Datasheet资料

122732faT YPICAL APPLICATIONF EATURESA PPLICATIONS DESCRIPTION Serial Output ADCThe L TC ®2273/L TC2272 are 80Msps/65Msps, 16-bit A/D converters with a high speed serial interface. They are designed for digitizing high frequency, wide dynamic range signals with an input bandwidth of 700MHz. The input range of the ADC can be optimized using the PGA front end. The output data is serialized according to the JEDEC serial interface for data converters specifi cation (JESD204).The L TC2273/L TC2272 are perfect for demanding applica-tions where it is desirable to isolate the sensitive analog circuits from the noisy digital logic. The AC performance includes a 77.7dB Noise Floor and 100dB spurious free dynamic range (SFDR). Ultra low internal jitter of 80fs RMS allows undersampling of high input frequencies with excellent noise performance. Maximum DC specs include ±4.5LSB INL and ±1LSB DNL (no missing codes) over temperature.The encode clock inputs, ENC + and ENC –, may be driven differentially or single-ended with a sine wave, PEC L, LVDS, TTL or CMOS inputs. A clock duty cycle stabilizer allows high performance at full speed with a wide range of clock duty cycles.L , L T , L TC, L TM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.nHigh Speed Serial Interface (JESD204)n Sample Rate: 80Msps/65Msps n 77.7dBFS Noise Floor n 100dB SFDRn SFDR >90dB at 140MHz (1.5V P-P Input Range)n PGA Front End (2.25V P-P or 1.5V P-P Input Range)n 700MHz Full Power Bandwidth S/H n Optional Internal Dither n Single 3.3V Supplyn Power Dissipation: 1100mW/990mW n Clock Duty Cycle Stabilizer nPin Compatible Family 105Msps: L T C 2274 80Msps: L T C 2273 65Msps: L T C 2272n 40-Pin 6mm × 6mm QFN PackagenTelecommunications n Receiversn Cellular Base Stations n Spectrum Analysis n Imaging Systems n ATE128k Point FFT , f IN = 4.93MHz,–1dBFS, PGA = 0FREQUENCY (MHz)0A M P L I T U D E (d B F S )1020304022732G04–130–120–110–100–90–80–70–60–50–40–30–20–100/222732faP IN CONFIGURATIONA BSOLUTE MAXIMUM RATINGS Supply Voltage (V DD ) ...................................–0.3V to 4V Analog Input Voltage (Note 3) .......–0.3V to (V DD + 0.3V) Digital Input Voltage ......................–0.3V to (V DD + 0.3V)Digital Output Voltage ................–0.3V to (OV DD + 0.3V)Power Dissipation .............................................2000mW Operating Temperature RangeL TC2273C/L TC2272C ...............................0°C to 70°C L TC2273I/L TC2272I ..............................–40°C to 85°C Storage Temperature Range ...................–65°C to 150°C Digital Output Supply Voltage (OV DD ) ..........–0.3V to 4VOV DD = V DD (Notes 1, 2)39403837363534333231112012131415TOP VIEW 41UJ PACKAGE40-LEAD (6mm s 6mm) PLASTIC QFN16171819222324252627282998765432V DD V DD GND A IN +A IN–GND GND GND ENC +ENC –GND SYNC –SYNC +GNDGND OV DD CMLOUT +CMLOUT –OV DD GNDG N DV C MS E N S EG N DM S B I N VP G AS C R A MP A T 1P A T 0F A MG N DV D D V D DG N DD I T HI S M O D ES R R 0S R R 1S H D NS H D N2130101T JMAX = 150°C, θJA = 22°C/WEXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCBORDER INFORMATIONLEAD FREE FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGE L TC2273CUJ#PBF L TC2273CUJ#TRPBF L TC2273UJ 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C L TC2273IUJ#PBF L TC2273IUJ#TRPBF L TC2273UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C L TC2272CUJ#PBF L TC2272CUJ#TRPBF L TC2272UJ 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C L TC2272IUJ#PBF L TC2272IUJ#TRPBF L TC2272UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C LEAD BASED FINISH TAPE AND REEL PART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGE L TC2273CUJ L TC2273CUJ#TR L TC2273UJ 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C L TC2273IUJ L TC2273IUJ#TR L TC2273UJ 40-Lead (6mm × 6mm) Plastic QFN –40°C to 85°C L TC2272CUJ L TC2272CUJ#TR L TC2272UJ 40-Lead (6mm × 6mm) Plastic QFN 0°C to 70°C L TC2272IUJL TC2272IUJ#TRL TC2272UJ40-Lead (6mm × 6mm) Plastic QFN–40°C to 85°CConsult L TC Marketing for parts specifi ed with wider operating temperature ranges. *The temperature grade is identifi ed by a label on the shipping container .For more information on lead free part marking, go to: http://www.linear .com/leadfree/ For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/CONVERTER CHARACTERISTICS SYMBOLCONDITIONSMINTYP MAX UNITS Integral Linearity Error Differential Analog Input (Note 5) T A = 25°C ±1.2±4LSB Integral Linearity Error Differential Analog Input (Note 5)l ±1.5±4.5LSB Differential Linearity Error Differential Analog Input l ±0.3±1LSB Offset Error (Note 6)l ±1±8.5mV Offset Drift ±10μV/°C Gain Error External Reference l±0.2±1.5%FS Full-Scale Drift Internal Reference External Reference±30±15ppm/°C ppm/°C T ransition Noise3LSB RMSThe l denotes the specifi cations which apply over the full operatingtemperature range, otherwise specifi cations are at T A = 25°C. (Note 4)/ANALOG INPUTThel denotes denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. (Note 4)SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS V IN Analog Input Range (A IN+ – A IN–) 3.135V ≤ V DD ≤ 3.465V l 1.5 or 2.25V P-P V IN, CM Analog Input Common Mode Differential Input (Note 7)l1 1.25 1.5V I IN Analog Input Leakage Current0V ≤ A IN+, A IN– ≤ V DD (Note 10)l–11μA I SENSE SENSE Input Leakage Current0V ≤ SENSE≤ V DD (Note 11)–33μAC IN Analog Input Capacitance Sample Mode ENC+ < ENC–Hold Mode ENC+ > ENC–6.71.8pFpFt AP Sample-and-HoldAcquisition Delay Time1nst JITTER Sample-and-HoldAcquisition Delay Time Jitter80fs RMSCMRR Analog InputCommon Mode Rejection Ratio1V < (A IN+ = A IN–) <1.5V80dB BW-3dB Full Power Bandwidth R S ≤ 25Ω700MHzDYNAMIC ACCURACYThel denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. A IN = –1dBFS. (Note 4)SYMBOL PARAMETER CONDITIONSL TC2273L TC2272UNITS MIN TYP MAX MIN TYP MAXSNR Signal-to-Noise Ratio5MHz Input (2.25V Range, PGA = 0)5MHz Input (1.5V Range, PGA = 1)77.675.477.675.4dBFSdBFS15MHz Input (2.25V Range, PGA = 0), T A = 25°C 15MHz Input (2.25V Range, PGA = 0)15MHz Input (1.5V Range, PGA = 1)l76.576.277.577.275.376.576.277.577.275.3dBFSdBFSdBFS70MHz Input (2.25V Range, PGA = 0)70MHz Input (1.5V Range, PGA = 1), T A = 25°C70MHz Input (1.5V Range, PGA = 1)l 74.574.277.275.174.874.574.277.275.174.8dBFSdBFSdBFS140MHz Input (2.25V Range, PGA = 0) 140MHz Input (1.5V Range, PGA = 1)76.374.576.374.5dBFSdBFS170MHz Input (2.25V Range, PGA = 0) 170MHz Input (1.5V Range, PGA = 1)75.974.375.974.3dBFSdBFSSFDR Spurious Free DynamicRange 2nd or 3rd Harmonic 5MHz Input (2.25V Range, PGA = 0)5MHz Input (1.5V Range, PGA = 1)100100100100dBcdBc 15MHz Input (2.25V Range, PGA = 0), T A = 25°C15MHz Input (2.25V Range, PGA = 0)15MHz Input (1.5V Range, PGA = 1)l8584959510085849595100dBcdBcdBc 70MHz Input (2.25V Range, PGA = 0)70MHz Input (1.5V Range, PGA = 1), T A = 25°C70MHz Input (1.5V Range, PGA = 1)l84838694928483869492dBcdBcdBc 140MHz Input (2.25V Range, PGA = 0)140MHz Input (1.5V Range, PGA = 1)85908590dBcdBc 170MHz Input (2.25V Range, PGA = 0)170MHz Input (1.5V Range, PGA = 1)80858085dBcdBc/322732faThel denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. A IN = –1dBFS unless otherwise noted. (Note 4)DYNAMIC ACCURACYSYMBOL PARAMETER CONDITIONSL TC2273L TC2272UNITS MIN TYP MAX MIN TYP MAXSFDR Spurious Free DynamicRange 4th Harmonic orHigher 5MHz Input (2.25V Range, PGA = 0)5MHz Input (1.5V Range, PGA = 1)100100100100dBcdBc 15MHz Input (2.25V Range, PGA = 0)15MHz Input (1.5V Range, PGA = 1)l9010010090100100dBcdBc 70MHz Input (2.25V Range, PGA = 0)70MHz Input (1.5V Range, PGA = 1)l9010010090100100dBcdBc 140MHz Input (2.25V Range, PGA = 0)140MHz Input (1.5V Range, PGA = 1)9510095100dBcdBc 170MHz Input (2.25V Range, PGA = 0)170MHz Input (1.5V Range, PGA = 1)90959095dBcdBcS/(N+D)Signal-to-NoisePlus Distortion Ratio 5MHz Input (2.25V Range, PGA = 0)5MHz Input (1.5V Range, PGA = 1)77.575.377.575.3dBFSdBFS 15MHz Input (2.25V Range, PGA = 0), T A = 25°C15MHz Input (2.25V Range, PGA = 015MHz Input (1.5V Range, PGA = 1)l76.375.977.47775.276.375.977.47775.2dBFSdBFSdBFS 70MHz Input (2.25V Range, PGA = 0)70MHz Input (1.5V Range, PGA = 1), T A = 25°C70MHz Input (1.5V Range, PGA = 1)l74.474.176.77574.774.474.176.77574.7dBFSdBFSdBFS 140MHz Input (2.25V Range, PGA = 0)140MHz Input (1.5V Range, PGA = 1)75.374.375.374.3dBFSdBFS 170MHz Input (2.25V Range, PGA = 0)170MHz Input (1.5V Range, PGA = 1)73.473.473.473.4dBFSdBFSSFDR Spurious Free DynamicRange at –25dBFS Dither“OFF”5MHz Input (2.25V Range, PGA = 0)5MHz Input (1.5V Range, PGA = 1)105105105105dBFSdBFS 15MHz Input (2.25V Range, PGA = 0)15MHz Input (1.5V Range, PGA = 1)105105105105dBFSdBFS 70MHz Input (2.25V Range, PGA = 0)70MHz Input (1.5V Range, PGA = 1)105105105105dBFSdBFS 140MHz Input (2.25V Range, PGA = 0)140MHz Input (1.5V Range, PGA = 1)100100100100dBFSdBFS 170MHz Input (2.25V Range, PGA = 0)170MHz Input (1.5V Range, PGA = 1)100100100100dBFSdBFSSFDR Spurious Free DynamicRange at –25dBFS Dither“ON”5MHz Input (2.25V Range, PGA = 0)5MHz Input (1.5V Range, PGA = 1)115115115115dBFSdBFS 15MHz Input (2.25V Range, PGA = 0)15MHz Input (1.5V Range, PGA = 1)l9711511597115115dBFSdBFS 70MHz Input (2.25V Range, PGA = 0)70MHz Input (1.5V Range, PGA = 1)115115115115dBFSdBFS 140MHz Input (2.25V Range, PGA = 0)140MHz Input (1.5V Range, PGA = 1)110110110110dBFSdBFS 170MHz Input (2.25V Range, PGA = 0)170MHz Input (1.5V Range, PGA = 1)105105105105dBFSdBFS/422732faThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. (Note 4)COMMON MODE BIAS CHARACTERISTICSPARAMETER CONDITIONS MIN TYP MAX UNITS V CM Output Voltage I OUT = 0 1.15 1.25 1.35V V CM Output Tempco I OUT = 0l40ppm/°C V CM Line Regulation 3.135V ≤ V DD ≤ 3.465V l1mV/V V CM Output Resistance–1mA ≤ | I OUT | ≤ 1mA l2ΩSYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Encode Inputs (ENC+, ENC–)V ID Differential Input Voltage(Note 7)l0.2VV ICM Common Mode Input Voltage Internally SetExternally Set (Note 7) 1.41.63.0VR IN Input Resistance(See Figure 2)6kΩC IN Input Capacitance3pF SYNC Inputs (SYNC+, SYNC–)V SID SYNC Differential InputVoltage(Note 7)l0.2VV SICM SYNC Common Mode InputVoltage Internally SetExternally Set (Note 7) 1.11.62.2VR SIN SYNC Input Resistance16.5kΩC SIN SYNC Input Capacitance3pF Logic Inputs (DITH, PGA, MSBINV, SCRAM, FAM, SHDN, SRR1, SRR0, ISMODE, PAT1, PAT0)V IH High Level Input Voltage V DD = 3.3V l2V V IL Low Level Input Voltage V DD = 3.3V l0.8V I IN Input Current V IN = 0V to V DD l±20μA C IN Input Capacitance 1.5pF High-Speed Serial Outputs (CMLOUT+, CMLOUT–)V OH Output High Level Directly-Coupled 50Ω to OV DDDirectly-Coupled 100Ω DifferentialAC-CoupledOV DDOV DD – 0.2OV DD – 0.2VVVV OL Output Low Level Directly-Coupled 50Ω to OV DDDirectly-Coupled 100Ω DifferentialAC-Coupled OV DD – 0.4OV DD – 0.6OV DD – 0.6VVVV OCM Output Common ModeVoltage Directly-Coupled 50Ω to OV DDDirectly-Coupled 100Ω DifferentialAC-CoupledOV DD – 0.2OV DD – 0.4OV DD – 0.4VVVR OUT Output Resistance Single-Ended Differential l355010065ΩΩThel denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. (Note 4)DIGITAL INPUTS AND DIGITAL OUTPUTS/522732faTIMING CHARACTERISTICSThel denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. (Note 4)Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: All voltage values are with respect to GND (unless otherwise noted).Note 3: When these pin voltages are taken below GND or above V DD, they will be clamped by internal diodes. This product can handle input currents of greater than 100mA below GND or above V DD without latchup.Note 4: V DD = 3.3V, f SAMPLE = 105MHz differential ENC+/ENC– = 2V P-P sine wave with 1.6V common mode, input range = 2.25V P-P with differential drive (PGA = 0), unless otherwise specifi ed.Note 5: Integral nonlinearity is defi ned as the deviation of a code froma “best fi t straight line” to the transfer curve. The deviation is measured from the center of the quantization band.Note 6: Offset error is the offset voltage measured from –1/2LSB when the output code fl ickers between 0000 0000 0000 0000 and 1111 1111 1111 1111 in 2’s complement output mode.Note 7: Guaranteed by design, not subject to test.Note 8: V DD = 3.3V, f SAMPLE = 80Msps (L TC2273) or 65Msps (L TC2272) input range = 2.25V P-P with differential drive.Note 9: Recommended operating conditions.Note 10: The dynamic current of the switched capacitors analog inputs can be large compared to the leakage current and will vary with the sample rate.Note 11: Leakage current will have higher transient current at power up. Keep drive resistance at or below 1k.Thel denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. A IN = –1dBFS. (Note 4)POWER REQUIREMENTSSYMBOL PARAMETER CONDITIONSL TC2273L TC2272UNITS MIN TYP MAX MIN TYP MAXV DD Analog Supply Voltage l 3.135 3.3 3.465 3.135 3.3 3.465V P SHDN Shutdown Power SHDN = V DD55mWOV DD Output Supply Voltage CMLOUT Directly-Coupled, 50Ω to OV DD (Note 7)CMLOUT Directly-Coupled, 100Ω Diff. (Note 7)CMLOUT AC-Coupled (Note 7)l 1.21.41.4V DDV DDV DD1.21.41.4V DDV DDV DDVVVI VDD Analog Supply Current DC Input l233370300340mAI OVDD Output Supply Current CMLOUT Directly-Coupled, 50Ω to OV DDCMLOUT Directly-Coupled, 100Ω Diff.CMLOUT AC-Coupled l8161681616mAmAmAP DIS Power Dissipation DC Input l110012219901122mWSYMBOL PARAMETER CONDITIONSL TC2273L TC2272UNITS MIN TYP MAX MIN TYP MAXf S Sampling Frequency(Note 9)l20802065MHz t CONV Conversion Period1/f S1/f S s t L ENC Clock Low Time(Note 7)l 4.06 6.2525 5.037.6925ns t H ENC Clock High Time(Note 7)l 4.06 6.2525 5.037.6925ns t AP Sample-and-Hold Aperture Delay0.70.7ns t BIT, UI Period of a Serial Bit t CONV/20t CONV/20s t JIT Total Jitter of CMLOUT± (P-P)BER = 1E–12 (Note 7)l0.350.35UIt R, t F Differential Rise and Fall Time of CMLOUT± (20% to 80%)R TERM = 50Ω, C L = 2pF(Note 7)l5011050110pst SU SYNC to ENC Clock Setup Time(Note 7)l22ns t HD ENC Clock to SYNC Hold Time(Note 7)l 2.5 2.5ns t CS ENC Clock to SYNC Delay(Note 7)l t HD t CONV – t SU t HD t CONV – t SU ns LAT P Pipeline Latency99Cycles LAT SC Latency from SYNC Active to COMMA Out33Cycles LAT SD Latency from SYNC Release to DATA Out22Cycles/622732fa722732fa22732 TD01ANALOG INPUTENC +INTERNAL PARALLEL DATA INTERNAL 8B/10B DATACMLOUT +/CMLOUT –TIMING DIAGRAMSCMLOUT +22732TD02CMLOUT +22732TD03Analog Input to Serial Data Out TimingSYNC + Falling Edge to Comma (K28.5) TimingSYNC + Rising Edge to Data Timing/822732faL TC2273: Differential Non-Linearity (DNL) vs Output CodeL TC2273: AC Grounded Input HistogramL TC2273: 128k Point FFT ,f IN = 5.1MHz, –1dBFS, PGA = 0L TC2273: 64k Point FFT ,f IN = 14.8MHz, –1dBFS, PGA = 0L TC2273: 64k Point FFT ,f IN = 14.8MHz, –10dBFS, PGA = 0L TC2273: SFDR vs Input Level, f IN = 15MHz, PGA = 0, Dither “On”L TC2273: 64k Point 2-Tone FFT , f IN = 14.01MHz and 15.81MHz, –7dBFS, PGA = 0L TC2273: Integral Non-Linearity(INL) vs Output CodeL TC2273: SFDR vs Input Level, f IN = 15MHz, PGA = 0, Dither “Off”OUTPUT CODE0I N L E R R O R (L S B )16384327684915222732G0165536–2.0–1.5–1.0–0.50.00.51.01.52.0OUTPUT CODED N LE R R O R (L S B )16384327684915222732G0265536–1.0–0.8–0.6–0.4–0.20.00.20.40.60.81.0OUTPUT CODE32769C O U N T327793278922732G0332799010002000300040005000600070008000900010000FREQUENCY (MHz)0A M P L I T U D E (d B F S )1020304022732G04–130–120–110–100–90–80–70–60–50–40–30–20–100FREQUENCY (MHz)0A M P L I T U D E (d B F S )1020304022732G05–130–120–110–100–90–80–70–60–50–40–30–20–100FREQUENCY (MHz)0A M P L I T U D E (d B F S )1020304022732G06–130–120–110–100–90–80–70–60–50–40–30–20–100FREQUENCY (MHz)0A M P L I T U D E (d B F S )1020304022732G09–130–120–110–100–90–80–70–60–50–40–30–20–100INPUT LEVEL (dBFS)–80S F D R (d B c A N D d B F S )–70–60–50–40–30–20–1022732G0730405060708090100110120130140V DD = 3.3V , OV DD = 1.5V , T A = 25°C, F S = 80Msps,unless otherwise noted.INPUT LEVEL (dBFS)–80S F D R (d B c A N D d B F S )–70–60–50–40–30–20–10022732G0830405060708090100110120130140TYPICAL PERFORMANCE CHARACTERISTICS /922732faT YPICAL PERFORMANCE CHARACTERISTICS L TC2273: 64k Point 2-Tone FFT ,f IN = 14.01MHz and 15.8MHz, –15dBFS, PGA = 0L TC2273: 64k Point FFT ,f IN = 70MHz, –1dBFS, PGA = 0L TC2273: 64k Point FFT ,f IN = 70MHz, –1dBFS, PGA = 1L TC2273: 128k Point FFT , f IN = 70MHz, –20dBFS, PGA = 0, Dither “Off”L TC2273: 128k Point FFT , f IN = 70MHz, –20dBFS, PGA = 0, Dither “On”L TC2273: 64k Point FFT ,f IN = 140.2MHz, –1dBFS, PGA = 1L TC2273: SFDR vs Input Level, f IN = 140MHz, PGA = 1, Dither “Off”L TC2273: SFDR vs Input Level, f IN = 140MHz, PGA = 1, Dither “On”L TC2273: 64k Point FFT ,f IN = 170.2MHz, –1dBFS, PGA = 1FREQUENCY (MHz)0A M P L I T U D E (d B F S )1020304022732G10–130–120–110–100–90–80–70–60–50–40–30–20–100FREQUENCY (MHz)0A M P L I T U D E (d B F S )1020304022732G11–130–120–110–100–90–80–70–60–50–40–30–20–100FREQUENCY (MHz)0A M P L I T U D E (d B F S )1020304022732G12–130–120–110–100–90–80–70–60–50–40–30–20–100FREQUENCY (MHz)0A M P L I T U D E (d B F S )1020304022732G13–130–120–110–100–90–80–70–60–50–40–30–20–100FREQUENCY (MHz)0A M P L I T U D E (d B F S )1020304022732G14–130–120–110–100–90–80–70–60–50–40–30–20–100FREQUENCY (MHz)0A M P L I T U D E (d B F S )1020304022732G15–130–120–110–100–90–80–70–60–50–40–30–20–100INPUT LEVEL (dBFS)–80S F D R (d B c A N D d B F S )–70–60–50–40–30–20–1022732G1630405060708090100110120130140INPUT LEVEL (dBFS)–80S F D R (d B c A N D d B F S )–70–60–50–40–30–20–10022732G1730405060708090100110120130140FREQUENCY (MHz)0A M P L I T U D E (d B F S )1020304022732G18–130–120–110–100–90–80–70–60–50–40–30–20–100V DD = 3.3V , OV DD = 1.5V , T A = 25°C, F S = 80Msps,unless otherwise noted./1022732faSAMPLE RATE (Msps)20I V D D (m A )70459512022732G25240280320360400TYPICAL PERFORMANCE CHARACTERISTICS L TC2273: 64k Point FFT ,f IN = 250.2MHz, –1dBFS, PGA = 1L TC2273: SFDR vs Input FrequencyL TC2273: SNR vs Input FrequencyL TC2273: SNR and SFDR vs Sample Rate, f IN = 5.1MHzL TC2273: SNR and SFDR vs Supply Voltage (V DD ), f IN = 5.2MHzL TC2273: SFDR vs Analog Input Common Mode Voltage, 5MHz and 70MHz, –1dBFSL TC2273: IV DD vs Sample Rate, 5MHz Sine, –1dBFSFREQUENCY (MHz)0A MP L I T U D E (d B F S )1020304022732G19–130–120–110–100–90–80–70–60–50–40–30–20–100INPUT FREQUENCY (MHz)S F D R (d B c )20022732G2040030010065707580859095100105INPUT FREQUENCY (MHz)S N R (d B F S )20022732G214003001007072747678SAMPLE RATE (Msps)20S N R (d B F S ) A N D S F D R (d B C )1006022732G221208040707580859095100105110SUPPLY VOLTAGE (V)2.8S N R A N D S F D R (d B F S )3.222732G233.43.0707580859095100105110ANALOG INPUT COMMON MODE VOLTAGE (V)0.50S F D R (d B c )0.75 1.00 1.25 1.50 1.7522732G242.006065707580859095100105110V DD = 3.3V , OV DD = 1.5V , T A = 25°C, F S = 80Msps,unless otherwise noted./分销商库存信息:LINEAR-TECHNOLOGYLTC2272IUJ#PBF LTC2272CUJ#PBF LTC2272CUJ#TRPBF LTC2273CUJ#TRPBF LTC2272IUJ#TRPBF LTC2273CUJ#PBF LTC2273IUJ#TRPBF LTC2273IUJ#PBF。

74HC4052电路使用说明手册中文版

74HC4052电路使用说明手册中文版

8. RL=1KΩ;CL=5pF;通道开;Vis=VDD(P-P)/2(正弦波,在 VDD/2 处对称);20lg(Vos/Vis)=-3dB;如图 4 所示
江苏省无锡市蠡园经济开发区滴翠路 100 号 9 栋 2 层
http://www.i-core. cn
邮编:214072
第 8 页 共 15 页 版本:2012-01-B1
表 733-11-I
无锡中微爱芯电子有限公司
Wuxi I-CORE Electronics Co., Ltd.
编号:74HC4052-AX-BJ-47
i-core 74HC4052 2 路四选一模拟开关 产品说明书
说明书发行履历:
版本
发行时间
2010-01-A
2010-01
2012-01-B1 2012-01
i-core 导通电阻
5 9
导通电阻
5 9
任意两个通道导
5
通电阻的差值
9
关断态漏电流
5
(所有通道关断)
9
关断态漏电流
5
(任一通道)
9
RON
115 50
340 160

Vis=0 见图 1
RON
120 65
365 200

Vis=VDD-VEE 见图 1
25

ΔRON 10


Vis=0~VDD-VEE
VEE
8
VSS
功能 B 路独立输入/输出 B 路独立输入/输出 A、B 路各自共用输入/输出 B 路独立输入/输出 B 路独立输入/输出 使能输入(低电平有效) 负电源电压 接地
引脚 9 10 11 12 13 14 15 16

40系列IC资料大全

40系列IC资料大全

40系列IC资料大全型号器件名称厂牌备注CD4000 双3输入端或非门+单非门 TICD4001 四2输入端或非门 HIT/NSC/TI/GOLCD4002 双4输入端或非门 NSCCD4006 18位串入/串出移位寄存器 NSCCD4007 双互补对加反相器 NSCCD4008 4位超前进位全加器 NSCCD4009 六反相缓冲/变换器 NSCCD4010 六同相缓冲/变换器 NSCCD4011 四2输入端与非门 HIT/TICD4012 双4输入端与非门 NSCCD4013 双主-从D型触发器 FSC/NSC/TOSCD4014 8位串入/并入-串出移位寄存器 NSCCD4015 双4位串入/并出移位寄存器 TICD4016 四传输门 FSC/TICD4017 十进制计数/分配器 FSC/TI/MOTCD4018 可预制1/N计数器 NSC/MOTCD4019 四与或选择器 PHICD4020 14级串行二进制计数/分频器 FSCCD4021 08位串入/并入-串出移位寄存器 PHI/NSCCD4022 八进制计数/分配器 NSC/MOTCD4023 三3输入端与非门 NSC/MOT/TICD4024 7级二进制串行计数/分频器 NSC/MOT/TICD4025 三3输入端或非门 NSC/MOT/TICD4026 十进制计数/7段译码器 NSC/MOT/TICD4027 双J-K触发器 NSC/MOT/TICD4028 BCD码十进制译码器 NSC/MOT/TICD4029 可预置可逆计数器 NSC/MOT/TICD4030 四异或门 NSC/MOT/TI/GOLCD4031 64位串入/串出移位存储器 NSC/MOT/TICD4032 三串行加法器 NSC/TICD4033 十进制计数/7段译码器 NSC/TICD4034 8位通用总线寄存器 NSC/MOT/TICD4035 4位并入/串入-并出/串出移位寄存 NSC/MOT/TI CD4038 三串行加法器 NSC/TICD4040 12级二进制串行计数/分频器 NSC/MOT/TICD4041 四同相/反相缓冲器 NSC/MOT/TICD4042 四锁存D型触发器 NSC/MOT/TICD4043 4三态R-S锁存触发器("1"触发) NSC/MOT/TI CD4044 四三态R-S锁存触发器("0"触发) NSC/MOT/TI CD4046 锁相环 NSC/MOT/TI/PHICD4047 无稳态/单稳态多谐振荡器 NSC/MOT/TICD4048 4输入端可扩展多功能门 NSC/HIT/TICD4049 六反相缓冲/变换器 NSC/HIT/TICD4050 六同相缓冲/变换器 NSC/MOT/TICD4051 八选一模拟开关 NSC/MOT/TICD4052 双4选1模拟开关 NSC/MOT/TICD4053 三组二路模拟开关 NSC/MOT/TICD4054 液晶显示驱动器 NSC/HIT/TICD4055 BCD-7段译码/液晶驱动器 NSC/HIT/TICD4056 液晶显示驱动器 NSC/HIT/TICD4059 “N”分频计数器 NSC/TICD4060 14级二进制串行计数/分频器 NSC/TI/MOTCD4063 四位数字比较器 NSC/HIT/TICD4066 四传输门 NSC/TI/MOTCD4067 16选1模拟开关 NSC/TICD4068 八输入端与非门/与门 NSC/HIT/TICD4069 六反相器 NSC/HIT/TICD4070 四异或门 NSC/HIT/TICD4071 四2输入端或门 NSC/TICD4072 双4输入端或门 NSC/TICD4073 三3输入端与门 NSC/TICD4075 三3输入端或门 NSC/TICD4076 四D寄存器CD4077 四2输入端异或非门 HITCD4078 8输入端或非门/或门CD4081 四2输入端与门 NSC/HIT/TICD4082 双4输入端与门 NSC/HIT/TICD4085 双2路2输入端与或非门CD4086 四2输入端可扩展与或非门CD4089 二进制比例乘法器CD4093 四2输入端施密特触发器 NSC/MOT/STCD4094 8位移位存储总线寄存器 NSC/TI/PHICD4095 3输入端J-K触发器CD4096 3输入端J-K触发器CD4097 双路八选一模拟开关CD4098 双单稳态触发器 NSC/MOT/TICD4099 8位可寻址锁存器 NSC/MOT/STCD40100 32位左/右移位寄存器CD40101 9位奇偶较验器CD40102 8位可预置同步BCD减法计数器CD40103 8位可预置同步二进制减法计数器CD40104 4位双向移位寄存器CD40105 先入先出FI-FD寄存器CD40106 六施密特触发器反相器 NSC\TICD40107 双2输入端与非缓冲/驱动器 HAR\TICD40108 4字×4位多通道寄存器CD40109 四低-高电平位移器CD40110 十进制加/减,计数,锁存,译码驱动 STCD40147 10-4线编码器 NSC\MOTCD40160 可预置BCD加计数器 NSC\MOTCD40161 可预置4位二进制加计数器 NSC\MOTCD40162 BCD加法计数器 NSC\MOTCD40163 4位二进制同步计数器 NSC\MOTCD40174 六锁存D型触发器 NSC\TI\MOTCD40175 四D型触发器 NSC\TI\MOTCD40181 4位算术逻辑单元/函数发生器CD40182 超前位发生器CD40192 可预置BCD加/减计数器(双时钟) NSC\TICD40193 可预置4位二进制加/减计数器 NSC\TICD40194 4位并入/串入-并出/串出移位寄存 NSC\MOT CD40195 4位并入/串入-并出/串出移位寄存 NSC\MOT CD40208 4×4多端口寄存器CD4501 4输入端双与门及2输入端或非门CD4502 可选通三态输出六反相/缓冲器CD4503 六同相三态缓冲器CD4504 六电压转换器CD4506 双二组2输入可扩展或非门CD4508 双4位锁存D型触发器CD4510 可预置BCD码加/减计数器CD4511 BCD锁存,7段译码,驱动器CD4512 八路数据选择器CD4513 BCD锁存,7段译码,驱动器(消隐) CD4514 4位锁存,4线-16线译码器CD4515 4位锁存,4线-16线译码器CD4516 可预置4位二进制加/减计数器CD4517 双64位静态移位寄存器CD4518 双BCD同步加计数器CD4519 四位与或选择器CD4520 双4位二进制同步加计数器CD4521 24级分频器CD4522 可预置BCD同步1/N计数器CD4526 可预置4位二进制同步1/N计数器CD4527 BCD比例乘法器CD4528 双单稳态触发器CD4529 双四路/单八路模拟开关CD4530 双5输入端优势逻辑门CD4531 12位奇偶校验器CD4532 8位优先编码器CD4536 可编程定时器CD4538 精密双单稳CD4539 双四路数据选择器CD4541 可编程序振荡/计时器CD4543 BCD七段锁存译码,驱动器CD4544 BCD七段锁存译码,驱动器CD4547 BCD七段译码/大电流驱动器CD4549 函数近似寄存器CD4551 四2通道模拟开关CD4553 三位BCD计数器CD4555 双二进制四选一译码器/分离器CD4556 双二进制四选一译码器/分离器CD4558 BCD八段译码器CD4560 "N"BCD加法器CD4561 "9"求补器CD4573 四可编程运算放大器CD4574 四可编程电压比较器CD4575 双可编程运放/比较器CD4583 双施密特触发器CD4584 六施密特触发器CD4585 4位数值比较器CD4599 8位可寻址锁存器CD22100 4×4×1交*点开关function forumhottag_callback(data){ tags = data; }。

LTC4352中文资料

LTC4352中文资料
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
DESCRIPTION
The LTC®4352 creates a near-ideal diode using an external N-channel MOSFET. It replaces a high power Schottky diode and the associated heat sink, saving power and board area. The ideal diode function permits low loss power ORing and supply holdup applications.
FAULT, STATUS Currents..........................................5mA Operating Ambient Temperature Range
LTC4352C ................................................ 0°C to 70°C LTC4352I.............................................. –40°C to 85°C Storage Temperature Range................... –65°C to 150°C Lead Temperature (Soldering, 10 sec) MS Package...................................................... 300°C

LTC2452资料

LTC2452资料

12452fbT YPICAL APPLICATIONF EATURESA PPLICATIONSD ESCRIPTION ΔΣ ADC with SPI Interface The L TC ®2452 is an ultra-tiny, fully differential, 16-bit, analog-to-digital converter . The L TC2452 uses a single 2.7V to 5.5V supply and communicates through an SPI interface. The ADC is available in an 8-pin, 3mm × 2mm DFN package or TSOT-23 package. It includes an integrated oscillator that does not require any external components. It uses a delta-sigma modulator as a converter core and has no latency for multiplexed applications. The L TC2452 includes a proprietary input sampling scheme that reduces the average input sampling current several orders of magnitude when compared to conventional delta-sigma converters. Additionally, due to its architecture, there is negligible current leakage between the input pins.The L TC2452 can sample at 60 conversions per second, and due to the very large oversampling ratio, has extremely relaxed antialiasing requirements. The L TC2452 includes continuous internal offset and full-scale calibration algo-rithms which are transparent to the user , ensuring accuracy over time and over the operating temperature range. The converter has an external REF pin and the differential input voltage range can extend up to ±V REF .Following a single conversion, the L TC2452 can automati-cally enter a sleep mode and reduce its supply current to less than 0.2μA. If the user reads the ADC once a second, the L TC2452 consumes an average of less than 50μW from a 2.7V supply.Integral Nonlinearity, V CC = 3Vn±V CC Differential Input Rangen 16-Bit Resolution (Including Sign), No Missing Codesn 2LSB Offset Error n 4LSB Full-Scale Errorn 60 Conversions Per Secondn Single Conversion Settling Time for Multiplexed Applicationsn Single-Cycle Operation with Auto Shutdown n 800μA Supply Current n 0.2μA Sleep Currentn Internal Oscillator—No External Components Required n SPI Interfacen Ultra-Tiny 3mm × 2mm DFN and TSOT-23 PackagesnSystem Monitoring n E nvironmental Monitoringn Direct Temperature Measurements n Instrumentationn Industrial Process Control n Data Acquisitionn Embedded ADC UpgradesL , L T , L TC and L TM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.Protected by U.S. Patents, including 6208279, 6411242, 7088280, 7164378.DIFFERENTIAL INPUT VOL TAGE (V)–3I N L (L S B )132452 TA01b–102–2–3–1–2120322452fbP IN CONFIGURATIONA BSOLUTE MAXIMUM RATINGS Supply Voltage (V CC ) ...................................–0.3V to 6V Analog Input Voltage (V IN +, V IN –) ..–0.3V to (V CC + 0.3V)Reference Voltage (V REF ) ..............–0.3V to (V CC + 0.3V)Digital Voltage (V SDO , V SCK , V CS ) ..–0.3V to (V CC + 0.3V)(Notes 1, 2)TOP VIEW9DD8 PACKAGE8-LEAD (3mm s 2mm) PLASTIC DFN 56784321SCK GND REF V CCSDO CS IN +IN –C/I GRADE T JMAX = 125°C, θJA = 76°C/WEXPOSED PAD (PIN 9) IS GND, MUST BE SOLDERED TO PCBSCK 1GND 2REF 3V CC 48 SDO 7CS 6 IN +5 IN –TOP VIEWTS8 PACKAGE8-LEAD PLASTIC TSOT-23C/I GRADE T JMAX = 125°C, θJA = 140°C/WORDER INFORMATIONELECTRICAL CHARACTERISTICSPARAMETERCONDITIONS MIN TYP MAX UNITS Resolution (No Missing Codes)(Note 3)l 16Bits Integral Nonlinearity (Note 4)l 110LSB Offset Error l210LSB Offset Error Drift 0.02LSB/°C Gain Error l0.010.02% of FS Gain Error Drift 0.02LSB/°C T ransition Noise2.2μV RMSPower Supply Rejection DC80dBThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C. (Note 2)Lead Free FinishTAPE AND REEL (MINI)TAPE AND REELPART MARKING*PACKAGE DESCRIPTIONTEMPERATURE RANGE L TC2452CDDB#TRMPBF L TC2452CDDB#TRPBF LDNJ 8-Lead Plastic (3mm × 2mm) DFN 0°C to 70°C L TC2452IDDB#TRMPBF L TC2452IDDB#TRPBF LDNJ 8-Lead Plastic (3mm × 2mm) DFN –40°C to 85°C L TC2452CTS8#TRMPBF L TC2452CTS8#TRPBF L TDPK 8-Lead Plastic TSOT-230°C to 70°C L TC2452ITS8#TRMPBF L TC2452ITS8#TRPBF L TDPK 8-Lead Plastic TSOT-23–40°C to 85°CTRM = 500 pieces. *Temperature grades are identifi ed by a label on the shipping container .Consult L TC Marketing for parts specifi ed with wider operating temperature ranges.Consult L TC Marketing for information on lead based fi nish parts.For more information on lead free part marking, go to: http://www.linear .com/leadfree/For more information on tape and reel specifi cations, go to: http://www.linear .com/tapeandreel/Storage Temperature Range ...................–65°C to 150°C Operating Temperature RangeL TC2452C ................................................0°C to 70°C L TC2452I..............................................–40°C to 85°C32452fbANALOG INPUTS AND REFERENCES The l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C.SYMBOL PARAMETER CONDITIONSMIN TYP MAX UNITSV CC Supply Voltage l 2.75.5V I CCSupply CurrentConversion SleepCS = GND (Note 6)CS = V CC (Note 6)l l8000.212000.6μA μAThe l denotes the specifi cations which apply over the full operating temperature range, otherwise specifi cations are at T A = 25°C.SYMBOL PARAMETERCONDITIONSMIN TYP MAX UNITSV IN +Positive Input Voltage Range l 0V CC V V IN –Negative Input Voltage Range l 0V CC V V REF Reference Voltage Range l2.5V CCV V OR +, V UR +Overrange/Underrange Voltage, IN +V REF = 5V , V IN – = 2.5V (See Figure 3)8LSB V OR –, V UR –Overrange/Underrange Voltage, IN–V REF = 5V , V IN + = 2.5V (See Figure 3)8LSB C ININ +, IN – Sampling Capacitance 0.35pFI DC_LEAK(IN +)IN + DC Leakage Current V IN = GND (Note 10)V IN = V CC (Note 10)l l –10–10111010nA nA I DC_LEAK(IN –)IN – DC Leakage Current V IN = GND (Note 10)V IN = V CC (Note 10)l l –10–10111010nA nA I DC_LEAK(REF)REF DC Leakage Current V REF = 3V (Note 10)l–10110nA I CONVInput Sampling Current (Note 5)50nAThe l denotes the specifi cations which apply over the full operating temperature range,otherwise specifi cations are at T A = 25°C. (Note 2)SYMBOL PARAMETERCONDITIONSMINTYP MAX UNITSV IH High Level Input Voltage l V CC – 0.3V V IL Low Level Input Voltage l 0.3V I IN Digital Input Current l–1010μA C IN Digital Input Capacitance 10pF V OH High Level Output Voltage I O = –800μA l V CC – 0.5VV OL Low Level Output Voltage I O = 1.6mAl 0.4V I OZHi-Z Output Leakage Currentl–1010μADIGITAL INPUTS AND DIGITAL OUTPUTSPOWER REQUIREMENTS42452fbThel denotes the specifi cations which apply over the full operating temperature range,otherwise specifi cations are at T A = 25°C.SYMBOL PARAMETER CONDITIONSMIN TYP MAX UNITS t CONV Conversion Time l 1316.623ms f SCK SCK Frequency Range l 2MHz t lSCK SCK Low Period l 250ns t hSCK SCK High Periodl 250nst 1CS Falling Edge to SDO Low Z (Notes 7, 8)l 0100ns t 2CS Rising Edge to SDO High Z (Notes 7, 8)l 0100ns t 3CS Falling Edge to SCK Falling Edge l 100ns t KQSCK Falling Edge to SDO Valid(Note 7)l100nsTYPICAL PERFORMANCE CHARACTERISTICSNote 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2. All voltage values are with respect to GND. V CC = 2.7V to 5.5V unless otherwise specifi ed. V REFCM = V REF /2, FS = V REFV IN = V IN + – V IN –, –V REF ≤ V IN ≤ V REF ; V INCM = (V IN + + V IN –)/2.Note 3. Guaranteed by design, not subject to test.Note 4. Integral nonlinearity is defi ned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. Guaranteed by design and test correlation.Note 5: CS = V CC . A positive current is fl owing into the DUT pin.Note 6: SCK = V CC or GND. SDO is high impedance.Note 7: See Figure 4.Note 8: See Figure 5.Note 9: Input sampling current is the average input current drawn from the input sampling network while the L TC2452 is actively sampling the input.Note 10: A positive current is fl owing into the DUT pin.T IMING CHARACTERISTICS Integral Nonlinearity, V CC = 5VIntegral Nonlinearity, V CC = 3VMaximum INL vs Temperature(T A = 25°C, unless otherwise noted)DIFFERENTIAL INPUT VOL TAGE (V)–5I N L (L S B )132452 G01–102–2–3–1–2–3–4123405DIFFERENTIAL INPUT VOL TAGE (V)–3I N L (L S B )132452 G02–102–2–3–1–21203TEMPERATURE (°C)–50I N L (L S B )132452 G03–102–2–3–25255075010052452fbTYPICAL PERFORMANCE CHARACTERISTICSOffset Error vs TemperatureGain Error vs TemperatureT ransition Noise vs TemperatureConversion Mode Power Supply Current vs TemperatureSleep Mode Power Supply Current vs TemperatureAverage Power Dissipation vs Temperature, V CC = 3VPower Supply Rejection vs Frequency at V CCConversion Time vs Temperature(T A = 25°C, unless otherwise noted)TEMPERATURE (°C)–50O F F S E T E R R O R (L S B )152452 G04–10234–2–3–4–5–25255075100TEMPERATURE (°C)–50G A I N E R R O R (L S B )152452 G05–10234–2–3–4–5–25255075100TEMPERATURE (°C)–50T R A N S I T I O N N O I S E R M S (μV )6102452 G06457893210–252550750100TEMPERATURE (°C)–50C O N V E R S I O N C U R R E N T (μA )9002452 G074005006007008003002001000–25255075100TEMPERATURE (°C)–50S L E E P C U R R E N T (n A )2502452 G08150200100500–25255075100TEMPERATURE (°C)–50A V E R A G E P O W E R D I S S I P A T I O N (μW )100002452 G091000100100–252550750100FREQUENCY AT V CC (Hz)1R E J E C T I O N (d B )2452 G10–20–40–60–80–100–120101k 10k 100k 1M 10010MTEMPERATURE (°C)–50C O N V E R S I O N T I M E (m s )212452 G1120161718191514–25255075010062452fbBLOCK DIAGRAMPIN FUNCTIONSSCK (Pin 1): Serial Clock Input. SCK synchronizes the serial data output. While digital data is available (the ADC is not in CONVERT state) and CS is LOW (ADC is not in SLEEP state) a new data bit is produced at the SDO output pin following every falling edge applied to the SCK pin.GND (Pin 2): Ground. Connect to a ground plane through a low impedance connection.REF (Pin 3): Reference Input. The voltage on REF can have any value between 2.5V and V CC . The reference voltage sets the full-scale range.V CC (Pin 4): Positive Supply Voltage. Bypass to GND (Pin 2) with a 10μF capacitor in parallel with a low-se-ries-inductance 0.1μF capacitor located as close to the L TC2452 as possible.IN – (Pin 5), IN + (Pin 6): Differential Analog Input.CS (Pin 7): Chip Select (Active LOW) Digital Input. A LOW on this pin enables the SDO digital output. A HIGH on this pin places the SDO output pin in a high imped-ance state.SDO (Pin 8): Three-State Serial Data Output. SDO is used for serial data output during the DATA OUTPUT state and can be used to monitor the conversion status.Exposed Pad (Pin 9): Ground. Must be soldered to PCB ground. For prototyping purposes, this pad may remain fl oating.Figure 1. Functional Block DiagramAPPLICATIONS INFORMATIONCONVERTER OPERATIONConverter Operation CycleThe L TC2452 is a low power, fully differential, delta-sigma analog-to-digital converter with a simple 3-wire SPI in-terface (see Figure 1). Its operation is composed of three successive states: CONVERT, SLEEP and DATA OUTPUT. The operating cycle begins with the CONVERT state, is followed by the SLEEP state, and ends with the DATA OUT-PUT state (see Figure 2). The 3-wire interface consists of serial data output (SDO), serial clock input (SCK), and the active low chip select input (CS).The CONVE RT state duration is determined by the L TC2452 conversion time (nominally 16.6 milliseconds). Once started, this operation can not be aborted except by a low power supply condition (V CC < 2.1V) which generates an internal power-on reset signal.After the completion of a conversion, the L TC2452 enters the SLE E P state and remains there until both the chip select and serial clock inputs are low (CS = SCK = LOW). Following this condition, the ADC transitions into the DATA OUTPUT state.Figure 2. L TC2452 State T ransition Diagram While in the SLEEP state, whenever the chip select input is pulled high (CS = HIGH), the L TC2452’s power supply current is reduced to less than 200nA. When the chip select input is pulled low (CS = LOW), and SCK is maintained at a HIGH logic level, the L TC2452 will return to a normal power consumption level. During the SLEEP state, the result of the last conversion is held indefi nitely in a static register.Upon entering the DATA OUTPUT state, SDO outputs the sign (D15) of the conversion result. During this state, the ADC shifts the conversion result serially through the SDO output pin under the control of the SCK input pin. There is no latency in generating this data and the result corresponds to the last completed conversion. A new bit of data appears at the SDO pin following each falling edge detected at the SCK input pin and appears from MSB to LSB. The user can reliably latch this data on every rising edge of the external serial clock signal driving the SCK pin (see Figure 3).The DATA OUTPUT state concludes in one of two different ways. First, the DATA OUTPUT state operation is completed once all 16 data bits have been shifted out and the clock then goes low. This corresponds to the 16th falling edge of SCK. Second, the DATA OUTPUT state can be aborted at any time by a LOW-to-HIGH transition on the CS input. Following either one of these two actions, the L TC2452 will enter the CONVERT state and initiate a new conver-sion cycle.Power-Up SequenceWhen the power supply voltage (V CC) applied to the con-verter is below approximately 2.1V, the ADC performs a power-on reset. This feature guarantees the integrity of the conversion result.When V CC rises above this critical threshold, the converter generates an internal power-on reset (POR) signal for approximately 0.5ms. The POR signal clears all internal registers. Following the POR signal, the L TC2452 starts a conversion cycle and follows the succession of states shown in Figure 2. The fi rst conversion result following POR is accurate within the specifi cations of the device if the power supply voltage V CC is restored within the operating range (2.7V to 5.5V) before the end of the POR time interval.72452fb82452fbAPPLICATIONS INFORMATIONEase of UseThe L TC2452 data output has no latency, fi lter settling delay or redundant results associated with the conversion cycle. There is a one-to-one correspondence between the conver-sion and the output data. Therefore, multiplexing multiple analog input voltages requires no special actions.The L TC2452 performs offset calibrations every conver-sion. This calibration is transparent to the user and has no effect upon the cyclic operation described previously. The advantage of continuous calibration is stability of the ADC performance with respect to time and temperature.The L TC2452 includes a proprietary input sampling scheme that reduces the average input current by several orders of magnitude when compared to traditional delta-sigma architectures. This allows external fi lter networks to in-terface directly to the L TC2452. Since the average input sampling current is 50nA, an external RC lowpass fi lter using 1kΩ and 0.1μF results in <1LSB additional error . Additionally, there is negligible leakage current between IN + and IN –.Reference Voltage RangeThe L TC2453 reference input range is 2.5V to V CC . For the simplest operation, REF can be shorted to V CC .Input Voltage RangeAs mentioned in the Output Data Format section, the output code is given as 32768•V IN /V REF + 32768. For V IN ≥ V REF , the output code is clamped at 65535 (all ones). For V IN ≤ –V REF , the output code is clamped at 0 (all zeroes).Figure 3. Output Code vs V IN + with V IN – = 0The L TC2452 includes a proprietary system that can, typically, digitize each input 8LSB above V REF and below GND, if the differential input is within ±V REF . As an ex-ample (Figure 3), if the user desires to measure a signal slightly below ground, the user could set V IN – = GND, and V REF = 5V . If V IN + = GND, the output code would be approximately 32768. If V IN + = GND – 8LSB = –1.22 mV , the output code would be approximately 32760.Output Data FormatThe L TC2452 generates a 16-bit direct binary encoded result. It is provided as a 16-bit serial stream through the SDO output pin under the control of the SCK input pin (see Figure 4).Letting V IN = (V IN + – V IN –), the output code is givenas 32768•V IN /V REF + 32768. The first bit output by the L TC2452, D15, is the MSB, which is 1 for V IN + ≥ V IN – and 0 for V IN + < V IN –. This bit is followed by successively less signifi cant bits (D14, D13...) until the LSB is output by the L TC2452. Table 1 shows some example output codes.Table 1. L TC2452 Output Data FormatDIFFERENTIAL INPUT VOL TAGE V IN + – V IN –D15 (MSB)D14D13D12...D2D1D0 (LSB)CORRESPONDING DECIMAL VALUE ≥V REF 11111165535V REF – 1LSB 111110655340.5•V REF 110000491520.5•V REF – 1LSB 10111149151010000032768–1LSB 01111132767–0.5•V REF 010********–0.5•V REF – 1LSB 00111116383≤ –V REFV IN +/V REF +–0.001O U T P U T C O D E412200.0012452 F03–4–120816–8–16–20–0.00500.0050.001592452fbA PPLICATIONS INFORMATION Figure 4. Data Output TimingKQlSCKhSCKDuring the data output operation the CS input pin must be pulled low (CS = LOW). The data output process starts with the most signifi cant bit of the result being present at the SDO output pin (SDO = D15) once CS goes low. A new data bit appears at the SDO output pin after each falling edge detected at the SCK input pin. The output data can be reliably latched by the user using the rising edge of SCK.Conversion Status MonitorFor certain applications, the user may wish to monitor the L TC2452 conversion status. This can be achieved by holding SCK HIGH during the conversion cycle. In this condition, whenever the CS input pin is pulled low (CS = LOW), the SDO output pin will provide an indication of the conversion status. SDO = HIGH is an indication of a conversion cycle in progress while SDO = LOW is anindication of a completed conversion cycle. An example of such a sequence is shown in Figure 5.Conversion status monitoring, while possible, is not re-quired for L TC2452 as its conversion time is fi xed and equal at approximately 16.6ms (23ms maximum). Therefore, external timing can be used to determine the completion of a conversion cycle. SERIAL INTERFACEThe L TC2452 transmits the conversion result and receives the start of conversion command through a synchronous 3-wire interface. This interface can be used during the CONVE RT and SLE E P states to assess the conversion status and during the DATA OUTPUT state to read the conversion result, and to trigger a new conversion.Figure 5. Conversion Status Monitoring ModeSDOSCK = HIGHCS102452fbAPPLICATIONS INFORMATIONSerial Interface Operation ModesThe modes of operation can be summarized as follows:1) The L TC2452 functions with SCK idle high (commonly known as CPOL = 1) or idle low (commonly known as CPOL = 0).2) After the 16th bit is read, the user can choose one of two ways to begin a new conversion. First, one can pull CS high (CS = ↑). Second, one can use a high-low transition on SCK (SCK = ↓).3) At any time during the Data Output state, pulling CS high (CS = ↑) causes the part to leave the I/O state, abort the output and begin a new conversion.4) When SCK = HIGH, it is possible to monitor the conver-sion status by pulling CS low and watching for SDO to go low. This feature is available only in the idle-high (CPOL = 1) mode.Serial Clock Idle-High (CPOL = 1) ExamplesIn Figure 6, following a conversion cycle the L TC2452 automatically enters the low power sleep mode. The user can monitor the conversion status at convenient intervals using CS and SDO.Pulling CS LOW while SCK is HIGH tests whether or not the chip is in the CONVERT state. While in the CONVERT state, SDO is HIGH while CS is LOW . In the SLEEP state, SDO is LOW while CS is LOW . These tests are not required operational steps but may be useful for some applications.When the data is available, the user applies 16 clock cycles to transfer the result. The CS rising edge is then used to initiate a new conversion.The operation example of Figure 7 is identical to that of Figure 6, except the new conversion cycle is triggered by the falling edge of the serial clock (SCK). A 17th clock pulse is used to trigger a new conversion cycle.Figure 6. Idle-High (CPOL = 1) Serial Clock Operation Example.The Rising Edge of CS Starts a New ConversionFigure 7. Idle-High (CPOL = 1) Clock Operation Example.A 17th Clock Pulse is Used to Trigger a New Conversion Cycle112452fbA PPLICATIONS INFORMATION Serial Clock Idle-Low (CPOL = 0) ExamplesIn Figure 8, following a conversion cycle the L TC2452 automatically enters the low-power sleep state. The user determines data availability (and the end of conversion) based upon external timing. The user then pulls CS low (CS = ↓) and uses 16 clock cycles to transfer the result. Following the 16th rising edge of the clock, CS is pulled high (CS = ↑), which triggers a new conversion.The timing diagram in Figure 9 is identical to that of Figure 8, except in this case a new conversion is triggered by SCK. The 16th SCK falling edge triggers a new conversion cycle and the CS signal is subsequently pulled high.Examples of Aborting Cycle using CSFor some applications, the user may wish to abort the I/O cycle and begin a new conversion. If the L TC2452 is in the data output state, a CS rising edge clears the remain-ing data bits from the output registers, aborts the output cycle and triggers a new conversion. Figure 10 shows an example of aborting an I/O with idle-high (CPOL = 1) and Figure 11 shows an example of aborting an I/O with idle-low (CPOL = 0).A new conversion cycle can be triggered using the CS signal without having to generate any serial clock pulses as shown in Figure 12. If SCK is maintained at a low logic level, after the end of a conversion cycle, a new conver-Figure 9. Idle-Low (CPOL = 0) Clock. The 16th SCK Falling Edge T riggers a New ConversionFigure 8. Idle-Low (CPOL = 0) Clock. CS T riggers a New ConversionAPPLICATIONS INFORMATIONFigure 10. Idle-High (CPOL = 1) Clock and Aborted I/O ExampleFigure 11. Idle-Low (CPOL = 0) Clock and Aborted I/O ExampleFigure 12. Idle-Low (CPOL = 0) Clock and Minimum Data Output Length Example 122452fb132452fbsion operation can be triggered by pulling CS low and then high. When CS is pulled low (CS = LOW), SDO will output the sign (D15) of the result of the just completed conversion. While a low logic level is maintained at SCK pin and CS is subsequently pulled high (CS = HIGH) the remaining 15 bits of the result (D14:D0) are discarded and a new conversion cycle starts.Following the aborted I/O, additional clock pulses in the CONVERT state are acceptable, but excessive signal tran-sitions on SCK can potentially create noise on the ADC during the conversion, and thus may negatively infl uence the conversion accuracy.2-Wire OperationThe 2-wire operation modes, while reducing the number of required control signals, should be used only if the L TC2452 low power sleep capability is not required. In addition the option to abort serial data transfers is no longer available. Hardwire CS to GND for 2-wire operation.Figure 13. 2-Wire, Idle-High (CPOL = 1) Serial Clock, Operation ExampleFigure 13 shows a 2-wire operation sequence which uses an idle-high (CPOL = 1) serial clock signal. The conversion status can be monitored at the SDO output. Following a conversion cycle, the ADC enters SLEEP state and the SDO output transitions from HIGH to LOW . Subsequently 16 clock pulses are applied to the SCK input in order to serially shift the 16 bit result. Finally, the 17th clock pulse is applied to the SCK input in order to trigger a new conversion cycle.Figure 14 shows a 2-wire operation sequence which uses an idle-low (CPOL = 0) serial clock signal. The conversion status cannot be monitored at the SDO output. Following a conversion cycle, the L TC2452 bypasses the SLE E P state and immediately enters the DATA OUTPUT state. At this moment the SDO pin outputs the sign (D15) of the conversion result. The user must use external timing in order to determine the end of conversion and result avail-ability. Subsequently 16 clock pulses are applied to SCK in order to serially shift the 16-bit result. The 16th clock falling edge triggers a new conversion cycle.A PPLICATIONS INFORMATION Figure 14. 2-Wire, Idle-Low (CPOL = 0) Serial Clock Operation ExampleAPPLICATIONS INFORMATIONPRESERVING THE CONVERTER ACCURACYThe L TC2452 is designed to minimize the conversion result’s sensitivity to device decoupling, PCB layout, antialiasing circuits, line and frequency perturbations. Nevertheless, in order to preserve the high accuracy capability of this part, some simple precautions are desirable.Digital Signal LevelsDue to the nature of CMOS logic, it is advisable to keep input digital signals near GND or V CC. Voltages in the range of 0.5V to V CC – 0.5V may result in additional current leakage from the part. Undershoot and overshoot should also be minimized, particularly while the chip is converting. It is thus benefi cial to keep edge rates of about 10ns and limit overshoot and undershoot to less than 0.3V.Noisy external circuitry can potentially impact the output under 2-wire operation. In particular, it is possible to get the L TC2452 into an unknown state if an SCK pulse is missed or noise triggers an extra SCK pulse. In this situ-ation, it is impossible to distinguish SDO = 1 (indicating conversion in progress) from valid “1” data bits. As such, CPOL = 1 is recommended for the 2-wire mode. The user should look for SDO = 0 before reading data, and look for SDO = 1 after reading data. If SDO does not return a “0” within the maximum conversion time (or return a “1” after a full data read), generate 16 SCK pulses to force a new conversion.Driving V CC and GNDIn relation to the V CC and GND pins, the L TC2452 combines internal high frequency decoupling with damping elements, which reduce the ADC performance sensitivity to PCB layout and external components. Nevertheless, the very high accuracy of this converter is best preserved by careful low and high frequency power supply decoupling.A 0.1μF, high quality, ceramic capacitor in parallel with a 10μF ceramic capacitor should be connected between the V CC and GND pins, as close as possible to the package. The 0.1μF capacitor should be placed closest to the ADC package. It is also desirable to avoid any via in the circuit path, starting from the converter V CC pin, passing through these two decoupling capacitors, and returning to the converter GND pin. The area encompassed by this circuit path, as well as the path length, should be minimized. Furthermore, as shown in Figure 15, GND is used as the negative reference voltage. It is thus important to keep the GND line quiet and connect GND through a low-imped-ance trace.Very low impedance ground and power planes, and star connections at both V CC and GND pins, are preferable. The V CC pin should have two distinct connections: the fi rst to the decoupling capacitors described above, and the second to the ground return for the power supply voltage source.Driving REFA simplifi ed equivalent circuit for REF is shown in Figure15. Like all other A/D converters, the L TC2452 is only as accurate as the reference it is using. Therefore, it is important to keep the reference line quiet by careful low and high frequency decoupling.Figure 15. L TC2452 Analog Input/Reference Equivalent CircuitVEQ142452fb。

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1Information furnished by Linear Technology Corporation is believed to be accurate and reliable.However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.CONSTANT CURRENTPULSING CURRENTCHARGE CYCLE ENDSC /10LTC4052-4.22405242iInput Supply Voltage (V IN ).......................................12V BAT Voltage...............................................–0.3V to 12V GATE (Note 2).............................................–0.3V to 8V SENSE, TIMER..................................–0.3V to V IN +0.3V CHRG, ACPR .............................................–0.3V to 12V SENSE, BAT Peak Current ......................................1.5A Operating Temperature Range (Note 3)..–40°C to 85°C Junction Temperature (Note 4).............................125°C Storage Temperature Range.................–65°C to 150°C Lead Temperature (Soldering, 10 sec)..................300°CMS8 PART MARKINGT JMAX = 125°C, θJA = 35°C/W EXPOSED PAD IS GROUND.(MUST BE SOLDERED TO PCB).ABSOLUTE AXI U RATI GSW W WU PACKAGE/ORDER I FOR ATIOUUW (Note 1)SYMBOL PARAMETER CONDITIONSMINTYP MAX UNITSV IN Supply Voltage Wall Adapter Open Circuit Voltage q 4.510V I IN Supply Current Fast Charge Mode q 0.71.4mA V BAT Battery Float Voltage0°C ≤ T A ≤ 85°C4.158 4.200 4.242V q4.137 4.200 4.242V V RECHRG Recharge Battery Voltage Threshold Battery Voltage Falling 0°C ≤ T A ≤ 85°C3.9904.050 4.110V q 3.969 4.050 4.110V V MARGIN V BAT – V RECHRG Margin q 75150225mV V IMAX Overcurrent Trip Voltage q 90105120mV I TRICKL Trickle Charge Current V BAT = 2V q 142434mA V TRICKL Trickle Charge Trip Threshold V BAT Rising q2.352.45 2.55V R DS(ON)Internal Switch On-Resistance V BAT = 2.6V 0.450.7ΩV BAT = 4V 0.350.5ΩV GATE GATE Pin Voltage V BAT = 2.6V 6.5V V BAT = 4V 10.5VT TIMER TIMER Period Accuracy C TIMER = 0.1µF, Fast Charge Mode ±10%I LEAK Battery Leakage Through Charger V BAT = 4V, V IN = 0V q1µA V SLEEP Sleep Threshold(V IN – V BAT ) Low to High 204570mV (V IN – V BAT ) High to Low 015mV V ACPR ACPR Pin Output Low Voltage I ACPR = 3mA q 0.50.8V I LEAKACPR ACPR Pin Leakage Current V IN = 0, V ACPR = 6Vq 1µA V CHRG CHRG Pin Output Low Voltage I CHRG = 3mA, Charging, C /10 Not Reached q 0.50.8V I LEAKCHRG CHRG Pin Leakage Current V IN = 0, V CHRG = 6Vq 1µA I CHRG CHRG Pin Pull-Down Current V CHRG = 1V, Charging, C /10 Reached204070µA T SHDN Thermal Shutdown Temperature 140°C ∆T SHDNThermal Shutdown Hysteresis5°CORDER PART NUMBER LTC4052EMS8E-4.212348765TOP VIEWMSE EXPOSED PAD PACKAGE 8-LEAD PLASTIC MSOP BAT GATE CHRG TIMERSENSE ACPR V IN GND Consult LTC Marketing for parts specified with wider operating temperature ranges.LTYYDC ELECTRICAL CHARACTERISTICSThe q denotes the specifications which apply over the full operatingtemperature range, otherwise specifications are at T A = 25°C. V IN = 6V unless otherwise noted.LTC4052-4.23405242iPI FU CTIO SU U USENSE (Pin 1): Overcurrent Sense Input. A sense resistor (R SENSE ) should be connected from V IN to the SENSE pin to program the current limit level. When current limit is tripped, the pass transistor immediately turns off and turns back on after a 640ms time-out period (C TIMER =0.1µF). The on-off cycle will continue as long as the overcurrent condition persists or until the timer runs out.If overcurrent protection is not needed, short SENSE to V IN .ACPR (Pin 2): Wall Adapter AC Present Open-Drain Out-put. When the input voltage (wall adapter) is applied to the LTC4052, this pin is pulled to ground by an internal N-channel MOSFET capable of driving an LED.V IN (Pin 3): Positive Input Supply Voltage (4.5V ≤ V IN ≤10V). Bypass this pin with a 1µF capacitor in series with a 4.7Ω resistor.GND (Pin 4): Electrical Ground Connection and provides a thermal path from the IC to the PC board copper. Use large copper pads and traces for maximum heat transfer.TIMER (Pin 5): Timer Set Pin. The timer period is set by a capacitor (C TIMER ) to ground. The timer period is:t TIMER = (C TIMER • 3Hr)/(0.1µF). The minimum ON time,minimum OFF time and the overcurrent time-out period all scale with t TIMER .CHRG (Pin 6): Charge Status Open-Drain Output. When a depleted battery is being charged, the CHRG pin is pulled to ground by an internal N-channel MOSFET capable of driving an LED. Once the duty cycle at the GATE pin dropsbelow 10%, the N-MOSFET turns off and a weak 40µA current source to ground turns on to indicate a near end-of-charge C /10 condition. When a time-out occurs or the input supply is removed, the CHRG pin becomes high impedance.GATE (Pin 7): Gate Drive Output Pin for Internal and External Pass Transistors. An external N-MOSFET transis-tor can be connected in parallel with the internal transistor to reduce the on-resistance for higher charge current. In this case, an external blocking diode is required to prevent damage to the battery if V IN is shorted to ground. A 10µA current source pulls this pin up to the charge pump potential when turned on and a 40µA current source pulls it down to ground to turn it off. If an overcurrent condition is detected, the GATE pin is immediately pulled to ground.The voltage at this pin is internally clamped to 12V above the GND pin.A series RC network from the GATE to the V IN pin is required to control the slew rate at the V IN pin when the switch is turned on or off. The slew rate control prevents excessive current from the capacitor located in the wall adapter from flowing into the battery when the pass transistor is turned on.BAT (Pin 8): Battery Sense Input Pin. This pin is clamped to 4.7V if the battery is disconnected while charging. An internal resistor divider presets the final float voltage to 4.2V. If the BAT pin drops below 4.05V after the charge cycle has ended, the timer resets and a new charge cycle begins.Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired.Note 2: Absolute Maximum Rating for GATE pin applies only to externally applied voltage. During normal operation the LTC4052-4.2’s internal charge pump can generate GATE pin voltage exceeding absolute maximum but it is internally current limited.Note 3: The LTC4052EMS8E-4.2 is guaranteed to meet performance specifications from 0°C to 70°C. Specifications over the –40°C to 85°C operating temperature range are assured by design, characterization and correlation with statistical process controls.Note 4: Junction temperature T J is calculated from the ambient temperature T A and power dissipation P D according to the following formula: T J = T A + (P D • θJA °C/W)ELECTRICAL CHARACTERISTICS4LTC4052-4.25405242iOPERATIOUInput Voltage (Wall Adapter)The input voltage to the LTC4052 must have some method of current limit capability. The current limit level of the input power source must be lower than the overcurrent limit (I MAX ) set by the sense resistor I MAX = 105mV/(R SENSE + 10m Ω). The 10m Ω represents bond wire resistance internal to the IC. If a wall adapter without current limit is used, or the current limit level is above I MAX , the charger will turn on briefly and then immediately turn off after the overcurrent condition is detected. This cycle will be resumed every 640ms (C TIMER = 0.1µF) until the total charge time has run out. If overcurrent protection is not needed, short the SENSE pin to V IN .Trickle Charge and Defective Battery Detection At the beginning of the charge cycle, if the cell voltage is low (less than 2.45V) the charger goes into a 24mA trickle charge mode. If the low cell voltage persists for one quarter of the total charge time, the battery is considered defective and the charge cycle is terminated. The CHRG pin output is then forced to a high impedance state.Battery Charge CurrentThe battery charge current is determined by the current limit of the input supply (wall adapter). However, this current must not exceed the maximum charge current,I MAX . If an overcurrent condition is detected, the charging is immediately terminated, the GATE pin is pulled to ground and the charge pump turns off. The charging will resume after a 640ms time off (C TIMER = 0.1µF).Programming the TimerThe programmable timer is used to terminate the charge cycle and sets the minimum ON/OFF time and the overcurrent time-off period. The length of the timer is programmed by an external capacitor from the TIMER pin to ground. The total charge time is:Time (Hours) = (3 Hours)(C TIMER /0.1µF) or C TIMER = 0.1µF • Time (Hours)/3 (Hours)The timer starts when the input voltage (at least 40mV greater than V BAT ) is applied. After a time-out has oc-curred, the charging stops and the CHRG pin becomes high impedance.APPLICATIO S I FOR ATIOW UUU When the cell voltage exceeds 2.45V, the charger goes into fast charge mode. In this mode, the charge pump turns on and ramps up the gate voltage of the pass transistor turning it on. The voltage at the V IN pin then ramps down to V BAT plus the voltage drop across the pass transistor and R SENSE , thus reducing the power dissipa-tion in the pass transistor. The charge current is deter-mined by the current limit of the input supply.When the battery voltage reaches the final float voltage,the pass transistor turns off for 100ms (minimum off-time). It remains off as long as the battery voltage stays above the float voltage after the 100ms off-time. After the minimum off-time, if the battery voltage drops below the float voltage, the pass transistor turns back on for at least 400ms (minimum on-time). As the battery approaches full charge, the off-time will get longer and the on-time willstay at 400ms. The voltage at the BAT pin will be slightly higher than the final float voltage due to the ESR associ-ated with the battery pack. This voltage level should not turn on the overvoltage protection circuitry often located in the battery pack. When the duty cycle at the GATE pin drops below 10%, a comparator turns off the N-FET at the CHRG pin and connects a weak current source (40µA) to ground to indicate a near end-of-charge C /10 condition.The pulse charging will continue until the timer stops.An external capacitor at the TIMER pin sets the total charge time, the minimum on- and off-time and the overcurrent retry period. After a time-out has occurred, the charge cycle terminates and the CHRG pin is forced high imped-ance. After the charging stops, if the battery voltage drops below 4V, due to external loading or internal leakage, a new charge cycle will automatically resume.678Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417(408) 432-1900 q FAX: (408) 434-0507 q © LINEAR TECHNOLOGY CORPORA TION 2001LT/TP 0702 1.5K • PRINTED IN USA。

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