TOREX XC61F系列 说明书
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0.7 1.0 3.0 5.0 6.0 7.0
-
-
-
-
50 80 1
TYP. VDF(T)
VDF x 0.05
0.9 1.0 1.3 1.6 2.0
2.2 7.7 10.1 11.5 13.0
-10.0
-0.01
0.01
ʶ100
-
MAX. VDF(T) x 1.02 VDF x 0.08
2.6 3.0 3.4 3.8 4.2 10.0
(*1) The “-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.
XC61F
Series
˙BLOCK DIAGRAMS
(1) CMOS output
Detect Voltage Temperature Characteristics
:ʶ100ppm/ˆ(TYP.)
Built-In Delay Circuit : ᶃ 1ms ~ 50ms
ᶄ 50ms ~ 200ms
ᶅ 80ms ~ 400ms
Output Configuration : N-ch open drain output or CMOS
˙FEATURES
Highly Accurate
: ± 2%
Low Power Consumption : 1.0ЖA(TYP.)[ VIN=2.0V ]
Detect Voltage Range : 1.6V ~ 6.0V in 0.1V increments
Operating Voltage Range : 0.7V ~ 10.0V
Power Dissipation
SOT-89
TO-92
Operating Ambient Temperature
Storage Temperature
SYMBOL VIN IOUT VOUT
Pd
Topr Tstg
RATINGS VSS-0.3~12.0
50 VSS -0.3 ~ VIN + 0.3
-
-2.0
Ta = 25ˆ UNITS CIRCUIT
V
ᶃ
V
ᶃ
ЖA
ᶄ
V
ᶃ
ᶅ mA
ᶆ
-
ЖA
ᶅ
0.1
-
ppm/ˆ ᶃ
200
400
ms
ᶇ
50
VDF (T): Setting detect voltage value Release Voltage: VDR = VDF + VHYS * Release Delay Time: 1ms to 50ms & 80ms to 400ms versions are also available. Note: The power consumption during power-start to output being stable (release operation) is 2ЖA greater than it is after that period
ᶇç Although VIN will rise to a level higher than VDR, VOUT maintains ground voltage level via the delay circuit. ᶈç Following transient delay time, VIN will be output at VOUT. Note that high impedance exists with the N-ch open drain
DESCRIPTION CMOS output N-ch open drain output e.g. 2.5V ˠ ᶄ2 , ᶅ5 e.g. 3.8V ˠ ᶄ3, ᶅ8 50ms ~ 200ms 80ms ~ 400ms 1ms ~ 50ms Within ʶ 2.0% SOT-23 (3,000/Reel) SOT-23 (3,000/Reel) SOT-89 (1,000/Reel) SOT-89 (1,000/Reel) TO-92 Taping Type: Paper type (2,000/Tape) TO-92 Taping Type: Paper type (2,000/Tape) TO-92 Taping Type: Bag (500/Bag) TO-92 Taping Type: Bag (500/Bag)
(completion of release operation) because of delay circuit through current.
4/14
XC61F
Series
˙OPERATIONAL EXPLANATION
˔CMOS output
ᶃç When a voltage higher than the release voltage (VDR) is applied to the voltage input pin (VIN), the voltage will gradually fall. When a voltage higher than the detect voltage (VDF) is applied to VIN, output (VOUT) will be equal to the input at VIN.
TO-92 2 3 1
PIN NAME
VIN VSS VOUT
FUNCTION
Supply Voltage Input Ground Output
2/14
˙PRODUCT CLASSIFICATION
˔Ordering Information
XC61F ᶃᶄᶅᶆᶇᶈᶉôᶊï*1ð
DESIGNATOR ᶃ
˙APPLICATIONS
˔Microprocessor reset circuitry ˔Memory battery back-up circuits ˔Power-on reset circuits ˔Power failure detection ˔System battery life and charge voltage monitors ˔Delay circuitry
ᶅç When VIN falls to a level below that of the minimum operating voltage (VMIN ) output will become unstable. Because the output pin is generally pulled up with configurations, output will be equal to pull up voltage.
VIN = 8.0V
VIN=VDF x 0.9V, VOUT=0V
VIN = 10.0VɼVOUT=10.0V
-30ˆʽToprʽ80ˆ
Release Delay Time (VDR ˠ VOUT inversion)
tDR
VIN changes from 0.6V to 10V
MIN. VDF(T) x 0.98 VDF x 0.02
Operating Ambient Temperature : 30ˆʙ+80ˆ
Packages
: SOT-23
SOT-89
TO-92
Environmentally Friendly : EU RoHS Compliant, Pb Free
* No parts are available with an accuracy of ± 1%
ITEM Output Configuration
SYMBOL C N
ᶄᶅDetect Volt源自ge16 ~ 60ᶆ
Release Output Delay
ᶇ
Detect Accuracy
ᶈᶉ-ᶊ (*1)
Packages (Order Unit)
1 4 5 2 MR MR-G PR PR-G TH TH-G TB TB-G
XC61F Series
Voltage Detectors, Delay Circuit Built-In
ETR0202_006
˙GENERAL DESCRIPTION
The XC61F series are highly accurate, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. A delay circuit is built-in to each detector. Detect voltage is extremely accurate with minimal temperature drift. Both CMOS and N-ch open drain output configurations are available. Since the delay circuit is built-in, peripherals are unnecessary and high density mounting is possible.
Supply Current
ISS
Operating Voltage
VIN
Output Current
IOUT
CMOS Output
Leak
(P-ch)
Current N-ch Open
Drain Output
Detect Voltage
Temperature
Characteristics
ILEAK
˙TYPICAL APPLICATION CIRCUITS
˙TYPICAL PERFORMANCE CHARACTERISTICS
˔Release Delay Time vs. Ambient Temperature
Release Delay Time: tDR (ms)
N-ch open drain output
VSS -0.3 ~ 9
250 500 300 -30ʙ+80 -40ʙ+125
Ta = 25ˆ UNITS
V mA
V
mW
ˆ ˆ
˙ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
Detect Voltage
VDF
Hysteresis Width
VHYS
ΔVDF/ (ΔToprŋVDF)
VIN = 1.5V
VIN = 2.0V
VIN = 3.0V
VIN = 4.0V
VIN = 5.0V
VDF= 1.6V to 6.0V
VIN = 1.0V
VIN = 2.0V
N-ch VDS =0.5V VIN = 3.0V
VIN = 4.0V
VIN = 5.0V
P-ch VDS=2.1V (CMOS Output)
Ambient Temperature:Ta(ˆ)
1/14
XC61F Series
˙PIN CONFIGURATION
1
２
3
VOUT
VIN
VSS
SOT-89 (TOP VIEW)
TO-92 (SIDE VIEW)
˙PIN ASSIGNMENT
SOT-23 3 2 1
PIN NUMBER SOT-89 2 3 1
(2) N-ch open drain output
3/14
XC61F Series
˙ABSOLUTE MAXIMUM RATINGS
PARAMETER Input Voltage
Output Current
CMOS
Output Voltage
N-ch open drain
output
SOT-23
ᶄç When VIN falls below VDF, VOUT will be equal to the ground voltage (VSS) level (detect state). Note that this also applies to N-ch open drain output configurations.
ç Note that high impedance exists at VOUT with the N-ch open drain output configuration. If the pin is pulled up, VOUT will be equal to the pull up voltage.
ᶆç When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), VOUT will be equal to VSS until VIN reaches the VDR level.
-
-
-
-
50 80 1
TYP. VDF(T)
VDF x 0.05
0.9 1.0 1.3 1.6 2.0
2.2 7.7 10.1 11.5 13.0
-10.0
-0.01
0.01
ʶ100
-
MAX. VDF(T) x 1.02 VDF x 0.08
2.6 3.0 3.4 3.8 4.2 10.0
(*1) The “-G” suffix indicates that the products are Halogen and Antimony free as well as being fully RoHS compliant.
XC61F
Series
˙BLOCK DIAGRAMS
(1) CMOS output
Detect Voltage Temperature Characteristics
:ʶ100ppm/ˆ(TYP.)
Built-In Delay Circuit : ᶃ 1ms ~ 50ms
ᶄ 50ms ~ 200ms
ᶅ 80ms ~ 400ms
Output Configuration : N-ch open drain output or CMOS
˙FEATURES
Highly Accurate
: ± 2%
Low Power Consumption : 1.0ЖA(TYP.)[ VIN=2.0V ]
Detect Voltage Range : 1.6V ~ 6.0V in 0.1V increments
Operating Voltage Range : 0.7V ~ 10.0V
Power Dissipation
SOT-89
TO-92
Operating Ambient Temperature
Storage Temperature
SYMBOL VIN IOUT VOUT
Pd
Topr Tstg
RATINGS VSS-0.3~12.0
50 VSS -0.3 ~ VIN + 0.3
-
-2.0
Ta = 25ˆ UNITS CIRCUIT
V
ᶃ
V
ᶃ
ЖA
ᶄ
V
ᶃ
ᶅ mA
ᶆ
-
ЖA
ᶅ
0.1
-
ppm/ˆ ᶃ
200
400
ms
ᶇ
50
VDF (T): Setting detect voltage value Release Voltage: VDR = VDF + VHYS * Release Delay Time: 1ms to 50ms & 80ms to 400ms versions are also available. Note: The power consumption during power-start to output being stable (release operation) is 2ЖA greater than it is after that period
ᶇç Although VIN will rise to a level higher than VDR, VOUT maintains ground voltage level via the delay circuit. ᶈç Following transient delay time, VIN will be output at VOUT. Note that high impedance exists with the N-ch open drain
DESCRIPTION CMOS output N-ch open drain output e.g. 2.5V ˠ ᶄ2 , ᶅ5 e.g. 3.8V ˠ ᶄ3, ᶅ8 50ms ~ 200ms 80ms ~ 400ms 1ms ~ 50ms Within ʶ 2.0% SOT-23 (3,000/Reel) SOT-23 (3,000/Reel) SOT-89 (1,000/Reel) SOT-89 (1,000/Reel) TO-92 Taping Type: Paper type (2,000/Tape) TO-92 Taping Type: Paper type (2,000/Tape) TO-92 Taping Type: Bag (500/Bag) TO-92 Taping Type: Bag (500/Bag)
(completion of release operation) because of delay circuit through current.
4/14
XC61F
Series
˙OPERATIONAL EXPLANATION
˔CMOS output
ᶃç When a voltage higher than the release voltage (VDR) is applied to the voltage input pin (VIN), the voltage will gradually fall. When a voltage higher than the detect voltage (VDF) is applied to VIN, output (VOUT) will be equal to the input at VIN.
TO-92 2 3 1
PIN NAME
VIN VSS VOUT
FUNCTION
Supply Voltage Input Ground Output
2/14
˙PRODUCT CLASSIFICATION
˔Ordering Information
XC61F ᶃᶄᶅᶆᶇᶈᶉôᶊï*1ð
DESIGNATOR ᶃ
˙APPLICATIONS
˔Microprocessor reset circuitry ˔Memory battery back-up circuits ˔Power-on reset circuits ˔Power failure detection ˔System battery life and charge voltage monitors ˔Delay circuitry
ᶅç When VIN falls to a level below that of the minimum operating voltage (VMIN ) output will become unstable. Because the output pin is generally pulled up with configurations, output will be equal to pull up voltage.
VIN = 8.0V
VIN=VDF x 0.9V, VOUT=0V
VIN = 10.0VɼVOUT=10.0V
-30ˆʽToprʽ80ˆ
Release Delay Time (VDR ˠ VOUT inversion)
tDR
VIN changes from 0.6V to 10V
MIN. VDF(T) x 0.98 VDF x 0.02
Operating Ambient Temperature : 30ˆʙ+80ˆ
Packages
: SOT-23
SOT-89
TO-92
Environmentally Friendly : EU RoHS Compliant, Pb Free
* No parts are available with an accuracy of ± 1%
ITEM Output Configuration
SYMBOL C N
ᶄᶅDetect Volt源自ge16 ~ 60ᶆ
Release Output Delay
ᶇ
Detect Accuracy
ᶈᶉ-ᶊ (*1)
Packages (Order Unit)
1 4 5 2 MR MR-G PR PR-G TH TH-G TB TB-G
XC61F Series
Voltage Detectors, Delay Circuit Built-In
ETR0202_006
˙GENERAL DESCRIPTION
The XC61F series are highly accurate, low power consumption voltage detectors, manufactured using CMOS and laser trimming technologies. A delay circuit is built-in to each detector. Detect voltage is extremely accurate with minimal temperature drift. Both CMOS and N-ch open drain output configurations are available. Since the delay circuit is built-in, peripherals are unnecessary and high density mounting is possible.
Supply Current
ISS
Operating Voltage
VIN
Output Current
IOUT
CMOS Output
Leak
(P-ch)
Current N-ch Open
Drain Output
Detect Voltage
Temperature
Characteristics
ILEAK
˙TYPICAL APPLICATION CIRCUITS
˙TYPICAL PERFORMANCE CHARACTERISTICS
˔Release Delay Time vs. Ambient Temperature
Release Delay Time: tDR (ms)
N-ch open drain output
VSS -0.3 ~ 9
250 500 300 -30ʙ+80 -40ʙ+125
Ta = 25ˆ UNITS
V mA
V
mW
ˆ ˆ
˙ELECTRICAL CHARACTERISTICS
PARAMETER
SYMBOL
CONDITIONS
Detect Voltage
VDF
Hysteresis Width
VHYS
ΔVDF/ (ΔToprŋVDF)
VIN = 1.5V
VIN = 2.0V
VIN = 3.0V
VIN = 4.0V
VIN = 5.0V
VDF= 1.6V to 6.0V
VIN = 1.0V
VIN = 2.0V
N-ch VDS =0.5V VIN = 3.0V
VIN = 4.0V
VIN = 5.0V
P-ch VDS=2.1V (CMOS Output)
Ambient Temperature:Ta(ˆ)
1/14
XC61F Series
˙PIN CONFIGURATION
1
２
3
VOUT
VIN
VSS
SOT-89 (TOP VIEW)
TO-92 (SIDE VIEW)
˙PIN ASSIGNMENT
SOT-23 3 2 1
PIN NUMBER SOT-89 2 3 1
(2) N-ch open drain output
3/14
XC61F Series
˙ABSOLUTE MAXIMUM RATINGS
PARAMETER Input Voltage
Output Current
CMOS
Output Voltage
N-ch open drain
output
SOT-23
ᶄç When VIN falls below VDF, VOUT will be equal to the ground voltage (VSS) level (detect state). Note that this also applies to N-ch open drain output configurations.
ç Note that high impedance exists at VOUT with the N-ch open drain output configuration. If the pin is pulled up, VOUT will be equal to the pull up voltage.
ᶆç When VIN rises above the VSS level (excepting levels lower than minimum operating voltage), VOUT will be equal to VSS until VIN reaches the VDR level.