Insyde post code
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#define DXE_SB_INIT 0x48 // South Bridge Middle Initial
#define DXE_IDENTIFY_FLASH_DEVICE 0x49 // Identify Flash device
#define PEI_PCIE_MMIO_INIT 0x74 // PCIE MMIO BAR Initial
#define PEI_NB_REG_INIT 0x75 // North Bridge Early Initial
//
// PEI Functionality
//
#define PEI_SIO_INIT 0x70 // Super I/O initial
#define PEI_CPU_REG_INIT 0x71 // CPU Early Initial
//
// DXE Functionality
//
#define DXE_TCGDXE 0x40 // TPM initial in DXE
#define DXE_SB_SPI_INIT 0x41 // South bridge SPI initial
#define PEI_MEMORY_INIT 0x7E // Memory Initial for Normal boot.
#define PEI_MEMORY_INIT_FOR_CRISIS 0x7F // Memory Initial for Crisis Recovery
#define PEI_FINDING_DXE_CORE 0x8A // Loading DXE core
#define PEI_GO_TO_DXE_CORE 0x8B // Enter DXE core
#define PEI_MEMORY_INSTALL 0x80 // Simple Memory test
#define PEI_TXTPEI 0x81 // TXT function early initial
#define PEI_PROGRAM_CLOCK_GEN 0x7A // Clock Generator Initial
#define PEI_IGD_EARLY_INITIAL 0x7B // Internal Graphic device early initial, PEI_IGDOpRegion
#define PEI_SB_REG_INIT 0x76 // South Bridge Early Initial
#define PEI_PCIE_TRAINING 0x77 // PCIE Training
#define DXE_VARIABLE_INIT_FAIL 0x4C // Fail to initial Variable Service
#define DXE_MTC_INIT 0x4D // MTC Initial
#define DXE_FTW_INIT 0x4A // Fault Tolerant Write verification
#define DXE_VARIABLE_INIT 0x4B // Variable Service Initial
#define SEC_AFTER_MICROCODE_PATCH 0x03 // Setup Cache as RAM
#define SEC_ACCESS_CSR 0x04 // PCIE MMIO Base Address initial
#define PEI_ENTER_RECOVERY_MODE 0x84 // Recovery device initial
#define PEI_RECOVERY_MEDIA_FOUND 0x85 // Found Recovery image
#define SEC_SYSTEM_POWER_ON 0x01 // CPU power on and switch to Protected mode
#define SEC_BEFORE_MICROCODE_PATCH 0x02 // Patching CPU microcode
#define PEI_CPU_AP_INIT 0x72 // Multi-processor Early initial
#define PEI_CPU_HT_RESET 0x73 // HyperTransport initial
#define DXE_SMMACCESS 0x44 // Setup SMM ACCESS service
#define DXE_NB_INIT 0x45 // North bridge Middle initial
#define PEI_RECOVERY_MEDIA_NOT_FOUND 0x86 // Recovery image not found
#define PEI_RECOVERY_LOAD_FILE_DONE 0x87 // Load Recovery Image complete
#define PEI_SWITCH_STACK 0x82 // Start to use Memory
#define PEI_MEMORY_CALLBACK 0x83 // Set cache for physical memory
#define DXE_SMBUS_INIT 0x50 // SMBUS Driver Initial
#define DXE_SMART_TIMER_INIT 0x51 // 8259 Initial
#define SEC_GO_TO_SECSTARTUP 0x09 // Setup BIOS ROM cache
#define SEC_GO_TO_PEICORE 0x0A // Enter Boot Firmware Volume
#define DXE_PCRTC_INIT 0x52 // RTC Initial
#define DXE_SATA_INIT 0x53 // SATA Controller early initial
#define PEI_HECI_INIT 0x7C // HECI Initial
#define PEI_WATCHDOG_INIT 0x7D // Watchdog timer initial
#define SEC_GENERIC_MSRINIT 0x05 // CPU Generic MSR initial
#define SEC_CPU_SPEEDCFG 0x06 // Setup CPU speed
#define DXE_CPU_INIT 0x4E // CPU Middle Initial
#define DXE_MP_CPU_INIT 0x4F // Multi-processor Middle Initial
#define PEI_TPM_INIT 0x78 // TPM Initial
#define PEI_SMBUS_INIT 0x79 // SMBUS Early Initial
#define DXE_SIO_INIT 0x46 // Super I/O DXE initial
#define DXE_LEGACY_REGION 0x47 // Setup Legacy Region service, DXE_LegacyRegion
#define DXE_CF9_RESET 0x42 // Setup Reset service, DXE_CF9Reset
#define DXE_SB_SERIAL_GPIO_INIT 0x43 // South bridge Serial GPIO initial, DXE_SB_SerialGPIO_INIT
#define PEI_RECOVERY_START_FLASH 0x88 // Start Flash BIOS with Recovery image
#define PEI_ENTER_DXEIPL 0x89 // Loading BIOS image to RAM
#define SEC_SETUP_CAR_OK 0x07 // Cache as RAM test
#define SEC_FORCE_MAX_RATIO 0x08 // Tune CPU frequency ratio toቤተ መጻሕፍቲ ባይዱmaximum level
#define DXE_IDENTIFY_FLASH_DEVICE 0x49 // Identify Flash device
#define PEI_PCIE_MMIO_INIT 0x74 // PCIE MMIO BAR Initial
#define PEI_NB_REG_INIT 0x75 // North Bridge Early Initial
//
// PEI Functionality
//
#define PEI_SIO_INIT 0x70 // Super I/O initial
#define PEI_CPU_REG_INIT 0x71 // CPU Early Initial
//
// DXE Functionality
//
#define DXE_TCGDXE 0x40 // TPM initial in DXE
#define DXE_SB_SPI_INIT 0x41 // South bridge SPI initial
#define PEI_MEMORY_INIT 0x7E // Memory Initial for Normal boot.
#define PEI_MEMORY_INIT_FOR_CRISIS 0x7F // Memory Initial for Crisis Recovery
#define PEI_FINDING_DXE_CORE 0x8A // Loading DXE core
#define PEI_GO_TO_DXE_CORE 0x8B // Enter DXE core
#define PEI_MEMORY_INSTALL 0x80 // Simple Memory test
#define PEI_TXTPEI 0x81 // TXT function early initial
#define PEI_PROGRAM_CLOCK_GEN 0x7A // Clock Generator Initial
#define PEI_IGD_EARLY_INITIAL 0x7B // Internal Graphic device early initial, PEI_IGDOpRegion
#define PEI_SB_REG_INIT 0x76 // South Bridge Early Initial
#define PEI_PCIE_TRAINING 0x77 // PCIE Training
#define DXE_VARIABLE_INIT_FAIL 0x4C // Fail to initial Variable Service
#define DXE_MTC_INIT 0x4D // MTC Initial
#define DXE_FTW_INIT 0x4A // Fault Tolerant Write verification
#define DXE_VARIABLE_INIT 0x4B // Variable Service Initial
#define SEC_AFTER_MICROCODE_PATCH 0x03 // Setup Cache as RAM
#define SEC_ACCESS_CSR 0x04 // PCIE MMIO Base Address initial
#define PEI_ENTER_RECOVERY_MODE 0x84 // Recovery device initial
#define PEI_RECOVERY_MEDIA_FOUND 0x85 // Found Recovery image
#define SEC_SYSTEM_POWER_ON 0x01 // CPU power on and switch to Protected mode
#define SEC_BEFORE_MICROCODE_PATCH 0x02 // Patching CPU microcode
#define PEI_CPU_AP_INIT 0x72 // Multi-processor Early initial
#define PEI_CPU_HT_RESET 0x73 // HyperTransport initial
#define DXE_SMMACCESS 0x44 // Setup SMM ACCESS service
#define DXE_NB_INIT 0x45 // North bridge Middle initial
#define PEI_RECOVERY_MEDIA_NOT_FOUND 0x86 // Recovery image not found
#define PEI_RECOVERY_LOAD_FILE_DONE 0x87 // Load Recovery Image complete
#define PEI_SWITCH_STACK 0x82 // Start to use Memory
#define PEI_MEMORY_CALLBACK 0x83 // Set cache for physical memory
#define DXE_SMBUS_INIT 0x50 // SMBUS Driver Initial
#define DXE_SMART_TIMER_INIT 0x51 // 8259 Initial
#define SEC_GO_TO_SECSTARTUP 0x09 // Setup BIOS ROM cache
#define SEC_GO_TO_PEICORE 0x0A // Enter Boot Firmware Volume
#define DXE_PCRTC_INIT 0x52 // RTC Initial
#define DXE_SATA_INIT 0x53 // SATA Controller early initial
#define PEI_HECI_INIT 0x7C // HECI Initial
#define PEI_WATCHDOG_INIT 0x7D // Watchdog timer initial
#define SEC_GENERIC_MSRINIT 0x05 // CPU Generic MSR initial
#define SEC_CPU_SPEEDCFG 0x06 // Setup CPU speed
#define DXE_CPU_INIT 0x4E // CPU Middle Initial
#define DXE_MP_CPU_INIT 0x4F // Multi-processor Middle Initial
#define PEI_TPM_INIT 0x78 // TPM Initial
#define PEI_SMBUS_INIT 0x79 // SMBUS Early Initial
#define DXE_SIO_INIT 0x46 // Super I/O DXE initial
#define DXE_LEGACY_REGION 0x47 // Setup Legacy Region service, DXE_LegacyRegion
#define DXE_CF9_RESET 0x42 // Setup Reset service, DXE_CF9Reset
#define DXE_SB_SERIAL_GPIO_INIT 0x43 // South bridge Serial GPIO initial, DXE_SB_SerialGPIO_INIT
#define PEI_RECOVERY_START_FLASH 0x88 // Start Flash BIOS with Recovery image
#define PEI_ENTER_DXEIPL 0x89 // Loading BIOS image to RAM
#define SEC_SETUP_CAR_OK 0x07 // Cache as RAM test
#define SEC_FORCE_MAX_RATIO 0x08 // Tune CPU frequency ratio toቤተ መጻሕፍቲ ባይዱmaximum level