Allegro_PCB_Designer_datasheet

Cadence Allegro PCB Design SolutionAllegro® PCB Designer is a scalable, proven PCB design environment that addresses technological and method-ological challenges while making the design cycles shorter and predictable. Available in base plus options configuration, the PCB design solution contains everything needed to createa PCB layout with a fully inte-grated design flow. The base—Allegro PCB Designer—includes a common, consistent constraint management solution, PCB Editor, an auto/interactive router, as well as interfaces for manufacturing and mechani-cal CAD. PCB Editor provides a complete placement and rout-ing environment—from basicfloor-planning, placement,and routing to placement replication, advanced interconnect planning—for simple to complex PCB designs. Benefits• Offers a proven, scalable,cost-effective PCB editing and routing solution in on-demand base plus options configuration • Eliminates unnecessary iterationsthrough constraint-driven PCBdesign flow• Supports a comprehensive rule setfor physical, spacing, design forfabrication, assembly and test (DFx),high-density interconnect (HDI), andelectrical (high speed) domains• Features a common, consistentconstraint management systemfor creation, management, andvalidation of constraints from frontto back• Open environment for third partyapplication improves productivitywhile providing access to best ofbreed integrated point toolsFigure 1: Allegro PCB design solution brings together all the tools needed to design simple-to-complex PCBsPCB Editor Technology Constraint-Driven PCB Editing EnvironmentAt the heart of Allegro PCB Designer is a PCB editor—an intuitive, easy-to-use, constraint-driven environment for creat-ing and editing simple to complex PCBs. Its extensive feature set addresses a wide range of design and manufacturability challenges:• A powerful set of floorplanning and placement tools including placement replication for accelerating placement of the design• Powerful shape-based shove, hug interactive etch creation, editing establishes a highly productive interconnect environment while providing real-time, heads-up displays of length and timing margins• Dynamic shape capability offersreal-time copper pour plowing & healing functionality during placement and routing iterationsThe PCB editor can also generate a full suite of phototooling, bare-board fabrica-tion, and test outputs, including Gerber 274x, NC drill, and bare-board test in a variety of formats.Constraint ManagementA constraint management system dis- plays physical/spacing and high-speed rules along with their status (based on the current state of the design) in real time and is available at all stages of the design process. Each worksheet provides a spreadsheet interface that enables users to define, manage, and validate the different rules in a hierarchical fashion. With this powerful application, designers can graphically create, edit, and review constraint sets as graphical topologies that act as electronic blueprints of an ideal implementation strategy. Once they exist in the database, constraints can drive the placement and routing processes for constrained signals.The constraint management system is completely integrated with the PCB editor, and constraints can be validated in real time as the design process proceeds. The result of the validation process is a graphi-cal representation of whether constraintspass (highlighted in green) or fail (high-lighted in red). This approach allowsdesigners to immediately see the progressof the design in the spreadsheets, as wellas the impact of any design changes.Floorplanning and PlacementThe constraint and rules-driven method-ology of PCB design solutions includesa powerful and flexible set of place-ment capabilities, including interactiveand automatic. The engineer or designercan assign components or subcircuitsto specific “rooms” during design entryor floor- planning. Components can befiltered and selected by reference desig-nator, device package/footprint style,associated net name, part number, or theschematic sheet/page number.With thousands of components compris-ing today’s boards, precise managementis critical. Real-time assembly analysisand feedback can facilitate this manage-ment—helping designers increaseproductivity and efficiency by placingcomponents according to corporate orEMS guidelines. Dynamic design-for-assembly (DFA)-driven placement offersreal-time package-to-package clearancechecking during interactive componentplacement (see Figure 2). Driven from atwo-dimensional spreadsheet array ofclasses and package instances, real-timefeedback provides minimum clearancerequirements. Based on the package’sside-to-side, side-to-end, designers cansimultaneously place devices for opti-mum routability, manufacturability, andsignal timing.Placement ReplicationSuperior placement replication technologywithin Allegro PCB Designer allows usersto quickly place and route multiple similarcircuits in a design. It allows users to createa template using one instance of placedand routed circuit that can be applied toother instances within the design. Thesaved placement template can be usedwith other designs where similar circuitsare used. When replicating placement,users can flip or mirror the circuit from toplayer to bottom layer. All associated etchelements, including blind buried vias, aremapped to correct layers when circuit ismoved from top layer to bottom layer.Display and VisualizationThe built-in 3D viewer is available in allPCB Editor products. The 3D environmentsupports several filtering options, cameraviews, graphic display options such assolid, transparency and wireframe, andmouse-driven controls for pan, zoom, andspinning the display. 3D viewing also sup-ports the display of complex via structuresor isolated sections of the board. Multipledisplay windows can be opened using thecontext sensitive command structure, and3D images can be captured and saved inJPEG format. (see Figure 3.)The flipboard capability “flips” the designabout its Y axis inverting the design data-base in the canvas. This “flip” reorganizesthe display of the design such that whatwas displayed as top through to bottombecomes bottom through to top. Havinga true bottom side view from within theCAD system is essential for hardware Figure 2: Design For assembly (DFA) rules driven placement allows for compact placement ofcomponents without introducing errorsengineers when debugging a board in the lab, or for assembly/test engineers on the manufacturing floor. Flipboard is not just limited to viewing; design edits can also be performed while in this mode.Interactive Etch EditingThe routing feature of the PCB editor provides powerful, interactive capabili-ties that deliver controlled automation to maintain user control, while maximizing routing productivity. Real-time, shape- based, any-angle, push/shove routing enables users to choose from “shove- preferred,” “hug-preferred,” or “hug- only” modes.During etch editing, the designer can view a real-time, graphical heads-up display of how much timing slack remains for inter- connect that has high-speed constraints. Interactive routing also enables group routing on multiple nets and interactive tuning of nets with high-speed length or delay constraints.Multi-Line RoutingMulti-line routing allows users to quickly route multiple lines as a group on thePCB. Coupled with “hug-contour” option, this utility can help designers route multiple lines on the flex portion of the rigid-flex design in minutes instead of hours with traditional one trace at a time. Hug-contour option takes care of insert-ing traces with curves that are aligned to contour of the flex portion of the design. (See Figure 4.)PCB ManufacturingA full suite of phototooling, bare-board fabrication, and test outputs, including Gerber 274x, NC drill, and bare-board test in a variety of formats, can be generated. More importantly, Cadence supports the industry initiative toward Gerberless manu-facturing through its Valor ODB++ inter-face that also includes the Valor UniversalViewer. The ODB++ data format creates accurate and reliable manufacturing data for high-quality Gerberless manufacturing.High-Speed DesignIncreasing use of standards-basedadvanced interfaces such as DDR3, DDR4, PCI Express, USB 3.0 are bringing a set of constraints that must be adhered to while implementing a PCB.Allegro PCB Designer through itsHigh-Speed Option makes adhering to constraints on advanced interfaces quick and easy. It offers an extensive range of electrical rules to ensure that the PCB design implementation is complaint with the specification for advanced interfaces. Additionally, it allows users to extend the rules through the use of formulas with existing rules or post-route data such as actual trace lengths.MiniaturizationConstraint-Driven HDI Design FlowWith BGA pin pitches decreasing tobelow 1mm—0.8mm or lower with 0.65 or 0.5mm pin pitches—users are forced to implement a buildup PCB technology using high-density interconnect (HDI).While miniaturization is not necessar-ily the primary objective in many market segments, the move to buildup technol-Figure 3: Built-in 3D viewer allows reviewing of a section of the board or complex via structures with pan, zoom, rotation and spinning to reduce iterations with mechanical design teams or PCBfabricators without introducing errorsFigure 4: Multi-line routing with contour hug option accelerates through no-click routing on flexsection of the PCB designsogy is necessary for fanning out a BGA— particularly if it has three or four rows of pins on each side.The Allegro PCB Designer through its Miniaturization Option offers a proven constraint-driven HDI design flow witha comprehensive set of design rules for all different styles of HDI designs, from a hybrid buildup/core combination to a complete buildup process like ALIVH.In addition, it includes automation for adding HDI to shorten the time to create designs that are correct-by-construction. Embedded ComponentsReducing end product size can be accom-plished in many different ways. One of the approaches PCB designers are taking is to embed packaged components on inner layers. Allegro PCB Designer through its Miniaturization Option offers constraint-driven embedded component placement and routing. It supports traditional direct-attach as well as new indirect-attach tech-niques. Additionally it offers the ability to create and manage cavities on layers speci-fied for embedding components. Design Planning and Routing Highly constrained, high-density designs dominated by bussed interconnect can take significant time to strategically plan and route. Compound this with the density issues of today’s components, new signaling levels, and specific topology requirements—and it’s no wonder that traditional CAD tools and technologies fall short of capturing a designer’s specific routing intent and acting upon it. The Global Route Environment provides the technology and methodology to capture as well as adhere to a designer’s intent. Through the interconnect flow planning architecture and the global route engine, users can for the first time put their expe-rience and design intent into a tool that understands what they want—natively. Users create abstracted interconnect data (through the interconnect flow planning architecture) and can quickly converge on a solution and validate it with the global route engine. The interconnect abstrac-tion reduces the number of elements the system has to deal with—from potentially tens of thousands down to hundreds—resulting in a significant reduction in themanual interaction required.Using the abstracted data, the planningand routing process can be acceleratedby providing a visual/spatial map of theopen area in relation to the data and theuser’s design intent. The route engine canthen deal with the details of the routing,adhering to the specified intent, with-out the user having to both visualize andsolve the interconnect problems at once.This significant simplification over currentdesign tools means users converge on asuccessful interconnect solution far fasterand more easily than ever before, reduc-ing design cycle time through increasedefficiency and productivity. (See Figure 6.)Analog/RF DesignThe Allegro PCB Designer through itsAnalog/RF Design Option offers a mixed-signal design environment, from sche-matic to layout with back annotation,proven to increase RF design productivityup to 50%. It allows engineers to create,integrate, and update analog/ RF/ micro-wave circuits with digital/analog circuitsin the Allegro PCB Design environment.With its rich layout capability and power-ful interfaces with RF simulation tools, itallows engineers to start RF design fromAllegro Design Authoring, Allegro PCBDesigner, or Agilent ADS.Concurrent Team DesignGlobally dispersed design teams are onthe rise, which compounds the challengeof shortening design cycle times. Manualworkarounds that address multi-userissues are time-consuming, slow, andprone to error.Allegro PCB Design Partitioning technol-ogy provides a multi-user, concurrentdesign methodology for faster time tomarket and reduced layout time. Multipledesigners working concurrently on alayout share access to a single database,regardless of team proximity. Designerscan partition designs into multiplesections or areas for layout and editingby several design team members.Designs can be partitioned vertically(sections) with soft boundaries or hori-zontally (layers). As a result, each designercan see all partitioned sections andFigure 6: Allegro Interconnect Flow Planner technology allows users reduce layer counts and shorten design cycle through design planningFigure 5: Dynamic fileting during etch editingshaves significant time from manufacturingprep phaseupdate the design view for monitoring the status and progress of other users’ sections. Such partitioning can dramati-cally reduce over-all design cycles and accelerate the design process.PCB Autorouter TechnologyPCB routing technologies are tightly inte-grated with the PCB editor. Through the PCB Router interface, all design information and constraints are automatically passed from the PCB editor. Once the route is completed, all route information is auto-matically passed back to the PCB editor. Increased design complexity, density,and high-speed routing constraints make manual routing of PCBs difficult andtime-consuming. The challenges inher-ent in complex interconnect routing are best addressed with powerful, automated technology. The robust, production-proven autorouter includes a batch rout-ing mode with extensive user-defined routing strategy control as well as built-in automatic strategy capabilities.DFM Rules-Driven AutoroutingThe design for manufacturing capabil-ity within Allegro PCB Router signifi-cantly improves manufacturing yields. Manufacturing algorithms provide a spreading capability that automatically increases conductor clearances on a space-available basis. Automatic conduc-tor spreading helps improve manufactu-ability by repositioning conductors to create extra space between conductors and pins, conductors and SMD pads, and adjacent conductor segments. Users gain the flexibility to define a range of spacing values or to use the default values. Mitered corners and test points can be added throughout the routing process. The manufacturing algorithms auto-matically use the optimal setback range, starting from the largest to the smallestvalue. Test point insertion automaticallyadds testable vias or pads as test points.Testable vias can be probed on the front,back, or both sides of the PCB, support-ing both single side and clamshell testers.Designers have the flexibility to select thetest point insertion methodology thatconforms to their manufacturing require-ments. Test points can be “fixed” to avoidcostly test fixture modifications. Test pointconstraints include test probe surfaces, viasizes, via grids, and minimum center-to-center distance.High-Speed Constraints-DrivenAutoroutingHigh-speed routing constraints and algo-rithms handle differential pairs, net sched-uling, timing, crosstalk, layer set routing,and the special geometry requirementsdemanded by today’s high-speed circuits.The autorouting algorithms intelligentlyhandle routing around or through vias,and automatically conform to definedlength or timing criteria. Automatic netshielding is used to reduce noise on noise-sensitive nets. Separate design rules maybe applied to different regions of thedesign; for example, you can specify tightclearance rules in the connector area of adesign and less stringent rules elsewhere.Operating System SupportAllegro Platform Technology:• Sun Solaris• Linux• IBM AIX• WindowsOrCAD Technology:• WindowsCadence Services and Support• Cadence application engineers cananswer your technical questions bytelephone, email, or Internet—they canalso provide technical assistance andcustom training• Cadence certified instructors teachmore than 70 courses and bring theirreal-world experience into the classroom• More than 25 Internet LearningSeries (iLS) online courses allow youthe flexibility of training at your owncomputer via the Internet• Cadence Online Support gives you 24x7online access to a knowledge base ofthe latest solutions, technical documen-tation, software downloads, and moreFor More InformationContact Cadence sales at 1.800.746.6223or visit for additionalinformation. To locate a Cadence salesoffice or channel partner in your area, visit/contact_us.Allegro PCB Designer Base Plus Options FeaturesCadence is transforming the global electronics industry through a vision called EDA360.With an application-driven approach to design, our software, hardware, IP, and services help customers realize silicon, SoCs, and complete systems efficiently and profitably. ©2011 Cadence Design Systems, Inc. All rights reserved. Cadence, the Cadence logo, and Allegro are registered trademarks of Cadence Design Systems, Inc., All rights reserved. 22173 05/11 MP/MV/DM/PDF。