TMS320x2833x Multichannel Buffered Serial Port (McBSP) Reference Guide第四章译文

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TMS320x2833x Multichannel Buffered Serial Port (McBSP) Reference Guide第二章翻译

第二章McBSP的操作本节将讨论以下话题：1、数据传输过程2、压扩（压缩和扩张）数据3、时钟和帧数据4、帧相位5、McBSP接收6、McBSP发送7、McBSP 产生的中断和DMA事件2.1 McBSPs 的数据传输过程图2-1显示了McBSP的数据传输路径图。

McBSP的接收操作是三重缓冲，发送操作是双缓冲。

寄存器的使用各不相同，取决于每个串行字的长度是否被定义为16位。

图2-1 McBSP的数据传输路径2.1.1 8位，12位或16位字长的数据传输过程如果字长为16位或更小，数据传输路径的每个阶段，只需要一个16位寄存器。

寄存器DRR2，RBR2，RSR2，DXR2，XSR2是用不到的（写，读，或转移）。

首先，接收数据传递到达DR引脚，并从DR引脚上被转移到接收移位寄存器（RSR1）。

一旦一个完整的字被接收，如果RBR1 没有被以前的数据填满，RSR1的内容被复制到接收缓冲寄存器1（RBR1）。

然后，如果DRR1中之前的内容已经被CPU或DMA控制器读取，RBR1的数据就会被复制到数据接收寄存器1（DRR1）（看图2-1即可）。

如果McBSP压扩功能被执行，则所需的字长为8位，而且，在接收数据被从RBR1到DRR1传递之前，接收数据被扩展到适当的格式。

有关接收过程的更多细节，请参见2.5节。

传输数据是由CPU或DMA控制器写入到数据传输寄存器（DXR1）。

如果在发送移位寄存器（XSR1）中没有数据，在DXR1的数据被复制到XSR1，否则，则当XSR1中之前的数据的最后一位被转移到DX引脚时，DXR1的数据被复制到XSR1中。

如果数据被选中，在传递到XSR1之前，压扩模块会压缩16位的数据成为合适的8位格式的数据。

帧同步传输后，发送器开始从XSR1位到DX引脚进行移位。

有关传输的更多细节，请参见第2.6节。

2.1.2 字长为20,24,32位的数据传输进程如果字长大于16位的，在数据传输路径的每个阶段，则需要两个16位寄存器，寄存器DRR2，RBR2，RSR2，DXR2，XSR2保存最高位的bits。

TMS320F28335核心板：Core28335软件调试指南

如果出现下图所示，则表示仿真器和开发板已连接成功。
第三步：新建一个工程，如下图
第四步：选择路径，输入工程项目名，并确定，则如下图所示
第五步：添加源文件，添加 CMD 文件，如下图所示：注意：源文件有*.c 文件，也有*.asm 文件
添加 CMD 文件跟添加源文件的方法相似，在这里不在赘述。添加完成后整个工程如下所示：
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前言
阅前必读
简介：
本用户指南是 TMS320F28335 DSP 处理模板硬件使用说明书，详细描述了
28335实用版的硬件构成、原理，以及它的使用方法和编程指导。
保修：
所有由株洲市索思达电子有限公司生产制造的硬件和软件产品，保修期为从发货之日起一年。在保修期内由于产品质量原因引起的损坏，株洲市索思达电子有限公司负责免费维修。当在保修期内软件进行了升级，株洲市索思达电子有限公司将免费提供。
参考资料：
TMS320F28x DSP CPU and Instruction Set Reference Guide （文献号 SPRU430）：介绍 TMS320F28x 系列 DSP 的 CPU 结构、指令组、流水线及中断。 TMS320C28x Floating Point Unit and Instruction Set Reference Guide （文献号 SPRUEO2）介绍浮点单元和FPU指令集。 TMS320x28xx, 28xxx Peripheral Reference Guide（文献号绍 TMS320F28x 系列 DSP 的外设。 TMS320x2833x 献号 System Control and Interrupts Reference Guide （文 SPRU566）：介

TMS320F28335教程

2个增强型的eCAN2.0B接口模块
DSP技术应用
2个多通道缓冲串口（MBSP） 1个12C总线接口 12位模数转换模块
80ns转换时间
2X8通道复用输入接口
两个采样保持电路
单/连续通道转换
高达88个可配置通用目的I/O引脚
先进的仿真调试功能
DSP技术应用
硬件支持适时仿真功能
DSP技术应用
(5) 军事——如保密通信、雷达处理、声纳处理、
导航、导弹制导等； (6) 仪器仪表——如频谱分析、函数发生、锁相环、地震处理等； (7) 自动控制——如引擎控制、声控、自动驾驶、机器人控制、磁盘控制等； (8) 医疗——如助听、超声设备、诊断工具、病人监护等；
(9) 家用电器——如高保真音响、音乐合成、音调控制、玩具与游戏、数字电话/视等。
C28x
TM
GPIO 16/32-bit
EMIF SPI
88
32x32-bit
Multiplier
通讯接口 32-bit Timers (3) Each McBSP configurable as SPI Real CAN 2.0b with 32 mailboxes Time 2C at 400 Kbps JTAG I 开发套件 SEED-DEC28335+SEED-XDSusb2.0 Code Composer Studio™ IDE V3.3 DSP技术应用 Software libraries
Sectored
A(18-0) 22 32 32 32
32-bit Auxiliary
Flash
RAM
ROM
D(15-0)
32x32 bit Multiplier

TMS320x2833x Multichannel Buffered Serial Port (McBSP) Reference Guide 第七章翻译译文

第7章接收器配置配置McBSP接收器，请执行以下步骤：1 将McBSP/接收器复位（见7.2节）。

2 对McBSP寄存器进行操作，使其处在接受所需的状态（参见7.1节）。

3 使接收器摆脱复位状态（见7.2节）。

（翻译不明）7.1对McBSP寄存器进行编程，使其处在接受所需的状态下面是当你配置的McBSP接收器时一个重要的任务列表。

每个任务对应一个或多个的McBSP寄存器位字段。

•全局操作：将接收引脚设置为McBSP的引脚。

1.启用/禁用数字回环模式。

2.启用/停用时钟停止模式。

3.启用/禁用接收多频道选择模式。

•数据操作1.选择1或2阶段为接收帧。

2.设置接收字长度（S）。

3.设置接收帧的长度。

4.启用/禁用接收帧同步忽略功能。

5.设置接收压扩模式。

6.设置接收数据的延迟。

7.设置接收符号扩展和理由模式。

8.设置接收中断模式。

•帧同步操作1.设置接收帧同步模式。

2.设置接收帧同步极性。

3.设置采样率发生器（SRG的）帧同步周期和脉冲宽度。

• 时钟操作1.设置接收时钟模式。

2.设置接收时钟极性。

3.设置SRG时钟分频的参数。

4.设置SRG的时钟同步模式。

5.设置SRG的时钟模式（选择输入时钟）。

7.2复位和启用接收器接收器的配置过程的第一步是要使接收器复位，最后一步是使接收器处于使能状态（使它摆脱复位状态）。

表7-1描述了这两个步骤中所使用的位。

7.2.1复位的注意事项串行端口可以通过下面的两步进行初始化：1. DSP复位（XRS信号驱动为低电平）会使接收器，发射器，采样率发生器复位。

当设备复位信号被取消（XRS信号发布），GRST = FRST = RRST = XRST = 0整个串行端口保持在复位状态。

（翻译的我都不明白）2. 直接使用串口控制寄存器RRST和XRST位使串口发射器和接收器复位。

直接使用在SPCR2的GRST位使采样率发生器复位。

由于器件复位或接收器/发射器直接复位而使串口复位时，McBSP引脚的状态如表7-2。

TMS28335资料

TMS320x2833x,2823x Enhanced Capture (eCAP)ModuleReference GuideLiterature Number:SPRUFG4AAugust2008–Revised June20092SPRUFG4A–August2008–Revised June2009Submit Documentation FeedbackPreface (6)1Introduction (9)2Description (9)3Capture and APWM Operating Mode (11)4Capture Mode Description (12)4.1Event Prescaler (12)4.2Edge Polarity Select and Qualifier (13)4.3Continuous/One-Shot Control (13)4.432-Bit Counter and Phase Control (14)4.5CAP1-CAP4Registers (15)4.6Interrupt Control (15)4.7Shadow Load and Lockout Control (16)4.8APWM Mode Operation (17)5Capture Module-Control and Status Registers (18)6Register Mapping (26)7Application of the ECAP Module (26)7.1Example1-Absolute Time-Stamp Operation Rising Edge Trigger (27)7.2Example2-Absolute Time-Stamp Operation Rising and Falling Edge Trigger (30)7.3Example3-Time Difference(Delta)Operation Rising Edge Trigger (32)7.4Example4-Time Difference(Delta)Operation Rising and Falling Edge Trigger (34)8Application of the APWM Mode (36)8.1Example1-Simple PWM Generation(Independent Channel/s) (36)8.2Example2-Multi-channel PWM Generation With Phase Control (37)Appendix A Revision History (40)SPRUFG4A–August2008–Revised June2009Table of Contents3 Submit Documentation FeedbackList of Figures1Multiple eCAP Modules In A2823x/2833x System (10)2Capture and APWM Modes of Operation (11)3Capture Function Diagram (12)4Event Prescale Control (13)5Prescale Function Waveforms (13)6Details of the Continuous/One-shot Block (14)7Details of the Counter and Synchronization Block (15)8Interrupts in eCAP Module (16)9PWM Waveform Details Of APWM Mode Operation (17)10Time-Stamp Counter Register(TSCTR) (18)11Counter Phase Control Register(CTRPHS) (18)12Capture-1Register(CAP1) (18)13Capture-2Register(CAP2) (18)14Capture-3Register(CAP3) (19)15Capture-4Register(CAP4) (19)16ECAP Control Register1(ECCTL1) (19)17ECAP Control Register2(ECCTL2) (21)18ECAP Interrupt Enable Register(ECEINT) (23)19ECAP Interrupt Flag Register(ECFLG) (24)20ECAP Interrupt Clear Register(ECCLR) (24)21ECAP Interrupt Forcing Register(ECFRC) (25)22Capture Sequence for Absolute Time-stamp and Rising Edge Detect (28)23Capture Sequence for Absolute Time-stamp With Rising and Falling Edge Detect (30)24Capture Sequence for Delta Mode Time-stamp and Rising Edge Detect (32)25Capture Sequence for Delta Mode Time-stamp With Rising and Falling Edge Detect (34)26PWM Waveform Details of APWM Mode Operation (36)27Multi-phase(channel)Interleaved PWM Example Using3eCAP Modules (38)4SPRUFG4A–August2008–Revised June2009 List of FiguresSubmit Documentation FeedbackList of Tables1Time-Stamp Counter Register(TSCTR)Field Descriptions (18)2Counter Phase Control Register(CTRPHS)Field Descriptions (18)3Capture-1Register(CAP1)Field Descriptions (18)4Capture-2Register(CAP2)Field Descriptions (19)5Capture-3Register(CAP3)Field Descriptions (19)6Capture-4Register(CAP4)Field Descriptions (19)7ECAP Control Register1(ECCTL1)Field Descriptions (20)8ECAP Control Register2(ECCTL2)Field Descriptions (21)9ECAP Interrupt Enable Register(ECEINT)Field Descriptions (23)10ECAP Interrupt Flag Register(ECFLG)Field Descriptions (24)11ECAP Interrupt Clear Register(ECCLR)Field Descriptions (25)12ECAP Interrupt Forcing Register(ECFRC)Field Descriptions (25)13Control and Status Register Set (26)A-1Changes Made in This Revision (40)SPRUFG4A–August2008–Revised June2009List of Tables5 Submit Documentation FeedbackPrefaceSPRUFG4A–August2008–Revised June2009The enhanced capture(eCAP)module is used in systems where accurate timing of external events is important.This guide describes the TMS320x2833x,2823x Enhanced Capture(eCAP)Module module and how to use it.The eCAP module described in guide is a Type0eCAP.See the TMS320C28xx,28xxx DSP Peripheral Reference Guide for a list of all devices with a eCAP module of the sametype,to determine the differences types,and for a list of device-specific differences within a type.Related Documentation From Texas InstrumentsThe following documents describe the TMS320C2833x/2823x and related support tools and can bedownloaded from the TI website():Data Manual and Errata—ofCPU User's Guides—TMS320C28x CPU and Instruction Set Reference Guide describes the central processing(CPU)and the assembly language instructions of the TMS320C28x fixed-point digital signal processors(DSPs).It also describes emulation features available on these DSPs.TMS320C28x Floating Point Unit and Instruction Set Reference Guide describes theunit and includes the instructions for the FPU.Peripheral Guides—TMS320x28xx,28xxx DSP Peripheral Reference Guide describes the peripheral referenceof the28x digital signal processors(DSPs).TMS320x2833x,2823x System Control and Interrupts Reference Guide describes theinterrupts and system control features of the2833x and2823x digital signal controllers (DSCs).TMS320x2833x,2823x Analog-to-Digital Converter(ADC)Reference Guide describesto configure and use the on-chip ADC module,which is a12-bit pipelined ADC.TMS320x2833x,2823x DSC External Interface(XINTF)Reference Guide describes thewhich is a nonmultiplexed asynchronous bus,as it is used on the2833x and2823x devices.TMS320x2833x,2823x Boot ROM Reference Guide describes the purpose and features ofbootloader(factory-programmed boot-loading software)and provides examples of code.It also describes other contents of the device on-chip boot ROM and identifies where all of the informationis located within that memory.6Preface SPRUFG4A–August2008–Revised June2009Submit Documentation Feedback Related Documentation From Texas Instruments TMS320x2833x,2823x Multichannel Buffered Serial Port(McBSP)Reference Guidethe McBSP available on the2833x and2823x devices.The McBSPs allow direct interface between a DSP and other devices in a system.TMS320x2833x,2823x Direct Memory Access(DMA)Module Reference Guidethe DMA on the2833x and2823x devices.TMS320x2833x,2823x Enhanced Pulse Width Modulator(ePWM)Module Referencedescribes the main areas of the enhanced pulse width modulator that include digital motor control,switch mode power supply control,UPS(uninterruptible power supplies),and other forms ofpower conversion.TMS320x2833x,2823x High-Resolution Pulse Width Modulator(HRPWM)Referencedescribes the operation of the high-resolution extension to the pulse width modulator (HRPWM).TMS320x2833x,2823x Enhanced Capture(eCAP)Module Reference Guide describescapture module.It includes the module description and registers.TMS320x2833x,2823x Enhanced Quadrature Encoder Pulse(eQEP)Module Referencedescribes the eQEP module,which is used for interfacing with a linear or rotary incremental encoder to get position,direction,and speed information from a rotating machine inhigh-performance motion and position control systems.It includes the module description andregisters.TMS320x2833x,2823x Enhanced Controller Area Network(eCAN)Reference Guidethe eCAN that uses established protocol to communicate serially with other controllers in electrically noisy environments.TMS320x2833x,2823x Serial Communications Interface(SCI)Reference Guidethe SCI,which is a two-wire asynchronous serial port,commonly known as a UART.The SCI modules support digital communications between the CPU and other asynchronous peripheralsthat use the standard non-return-to-zero(NRZ)format.TMS320x2833x,2823x DSC Serial Peripheral Interface(SPI)Reference Guide describes-a high-speed synchronous serial input/output(I/O)port-that allows a serial bit stream of programmed length(one to sixteen bits)to be shifted into and out of the device at a programmedbit-transfer rate.TMS320x2833x,2823x Inter-Integrated Circuit(I2C)Module Reference Guide describesand operation of the inter-integrated circuit(I2C)module.Tools Guides—TMS320C28x Assembly Language Tools v5.0.0User's Guide describes the assemblytools(assembler and other tools used to develop assembly language code),assembler directives,macros,common object file format,and symbolic debugging directives for theTMS320C28x device.TMS320C28x Optimizing C/C++Compiler v5.0.0User's Guide describes theC/C++compiler.This compiler accepts ANSI standard C/C++source code and produces TMS320DSP assembly language source code for the TMS320C28x device.TMS320C28x Instruction Set Simulator Technical Overview describes the simulator,within the Code Composer Studio for TMS320C2000IDE,that simulates the instruction set of the C28x™core.TMS320C28x DSP/BIOS5.32Application Programming Interface(API)Reference Guidedevelopment using DSP/BIOS.SPRUFG4A–August2008–Revised June2009Read This First7 Submit Documentation FeedbackRelated Documentation From Texas Instruments TrademarksTMS320C28x,C28x are trademarks of Texas Instruments.Read This First8SPRUFG4A–August2008–Revised June2009Submit Documentation Feedback1Introduction2DescriptionReference GuideSPRUFG4A–August 2008–Revised June 2009The enhanced Capture (eCAP)module is essential in systems where accurate timing of external events is important.This reference guide is applicable for the eCAP found on the TMS320x2823x and the TMS320x2833x family of processors.This includes all Flash-based,ROM-based,and RAM-based devices within the 2823x and 2833x families .Uses for eCAP include:•Speed measurements of rotating machinery (e.g.,toothed sprockets sensed via Hall sensors)•Elapsed time measurements between position sensor pulses •Period and duty cycle measurements of pulse train signals•Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors The eCAP module described in this guide includes the following features:•32-bit time base with 6.67-ns time resolution with a 150-MHz system clock •4-event time-stamp registers (each 32bits)•Edge polarity selection for up to four sequenced time-stamp capture events •Interrupt on either of the four events•Single shot capture of up to four event time-stamps•Continuous mode capture of time-stamps in a four-deep circular buffer •Absolute time-stamp capture•Difference (Delta)mode time-stamp capture•All above resources dedicated to a single input pin•When not used in capture mode,the ECAP module can be configured as a single channel PWM outputThe eCAP module represents one complete capture channel that can be instantiated multiple times depending on the target device.In the context of this guide,one eCAP channel has the following independent key resources:•Dedicated input capture pin •32-bit time base (counter)•4x 32-bit time-stamp capture registers (CAP1-CAP4)•4-stage sequencer (Modulo4counter)that is synchronized to external events,ECAP pin rising/falling edges.•Independent edge polarity (rising/falling edge)selection for all 4events •Input capture signal prescaling (from 2-62)•One-shot compare register (2bits)to freeze captures after 1to 4time-stamp events•Control for continuous time-stamp captures using a 4-deep circular buffer (CAP1-CAP4)scheme •Interrupt capabilities on any of the 4capture eventsMultiple identical eCAP modules can be contained in a system as shown in Figure 1.The number of modules is device-dependent and is based on target application needs.SPRUFG4A–August 2008–Revised June 2009Enhanced Capture (eCAP)Module 9Submit Documentation FeedbackPeripheral Frame 1PeripheralDescription Figure1.Multiple eCAP Modules In A2823x/2833x System10Enhanced Capture(eCAP)Module SPRUFG4A–August2008–Revised June2009Submit Documentation Feedback Capture and APWM Operating Mode 3Capture and APWM Operating ModeYou can use the eCAP module resources to implement a single-channel PWM generator(with32bitcapabilities)when it is not being used for input captures.The counter operates in count-up mode,providing a time-base for asymmetrical pulse width modulation(PWM)waveforms.The CAP1and CAP2 registers become the active period and compare registers,respectively,while CAP3and CAP4registers become the period and capture shadow registers,respectively.Figure2is a high-level view of both the capture and auxiliary pulse-width modulator(APWM)modes ofFigure2.Capture and APWM Modes of OperationA A single pin is shared between CAP and APWM functions.In capture mode,it is an input;in APWM mode,it is anoutput.B In APWM mode,writing any value to CAP1/CAP2active registers also writes the same value to the correspondingshadow registers CAP3/CAP4.This emulates immediate mode.Writing to the shadow registers CAP3/CAP4invokesthe shadow mode.4Capture Mode Description4.1Event PrescalerCapture Mode Description Figure 3shows the various components that implement the capture function.Figure 3.Capture Function Diagram•An input capture signal (pulse train)can be prescaled by N =2-62(in multiples of 2)or can bypass the prescaler.This is useful when very high frequency signals are used as inputs.Figure 4shows a functional diagram and Figure 5shows the operation of the prescale function.12Enhanced Capture (eCAP)ModuleSPRUFG4A–August 2008–Revised June 2009ECAPx pin (from GPIO)PSoutECAPxPSout div 2PSout div 4PSout div 6PSout div 8PSout div 104.2Edge Polarity Select and Qualifier4.3Continuous/One-Shot Control Capture Mode DescriptionFigure 4.Event Prescale ControlAWhen a prescale value of 1is chosen (i.e.ECCTL1[13:9]=0,0,0,0,0)the input capture signal by-passes the prescale logic completely.Figure 5.Prescale Function Waveforms•Four independent edge polarity (rising edge/falling edge)selection MUXes are used,one for each capture event.•Each edge (up to 4)is event qualified by the Modulo4sequencer.•The edge event is gated to its respective CAPx register by the Mod4counter.The CAPx register is loaded on the falling edge.•The Mod4(2bit)counter is incremented via edge qualified events (CEVT1-CEVT4).•The Mod4counter continues counting (0->1->2->3->0)and wraps around unless stopped.•A 2-bit stop register is used to compare the Mod4counter output,and when equal stops the Mod4counter and inhibits further loads of the CAP1-CAP4registers.This occurs during one-shot operation.CEVT1CEVT2CEVT3CEVT4ECCTL2[CONT/ONESHT]4.432-Bit Counter and Phase ControlCapture Mode Description The continuous/one-shot block controls the start/stop and reset (zero)functions of the Mod4counter via a mono-shot type of action that can be triggered by the stop-value comparator and re-armed via software control.Once armed,the eCAP module waits for 1-4(defined by stop-value)capture events before freezing both the Mod4counter and contents of CAP1-4registers (i.e.,time-stamps).Re-arming prepares the eCAP module for another capture sequence.Also re-arming clears (to zero)the Mod4counter and permits loading of CAP1-4registers again,providing the CAPLDEN bit is set.In continuous mode,the Mod4counter continues to run (0->1->2->3->0,the one-shot action is ignored,and capture values continue to be written to CAP1-4in a circular buffer sequence.Figure 6.Details of the Continuous/One-shot BlockThis counter provides the time-base for event captures,and is clocked via the system clock.A phase register is provided to achieve synchronization with other counters,via a hardware and software forced sync.This is useful in APWM mode when a phase offset between modules is needed.On any of the four event loads,an option to reset the 32-bit counter is given.This is useful for time difference capture.The 32-bit counter value is captured first,then it is reset to 0by any of the LD1-LD4signals.Enhanced Capture (eCAP)Module14SPRUFG4A–August 2008–Revised June 2009SYNCOSYNCECCTL2[SYNCI_EN]Delta−modeCTR−OVFCTR[31−0]4.5CAP1-CAP4Registers4.6Interrupt Control Capture Mode DescriptionFigure 7.Details of the Counter and Synchronization BlockThese 32-bit registers are fed by the 32-bit counter timer bus,CTR[0-31]and are loaded (i.e.,capture a time-stamp)when their respective LD inputs are strobed.Loading of the capture registers can be inhibited via control bit CAPLDEN.During one-shot operation,this bit is cleared (loading is inhibited)automatically when a stop condition occurs,i.e.StopValue =Mod4.CAP1and CAP2registers become the active period and compare registers,respectively,in APWM mode.CAP3and CAP4registers become the respective shadow registers (APRD and ACMP)for CAP1and CAP2during APWM operation.An Interrupt can be generated on capture events (CEVT1-CEVT4,CTROVF)or APWM events (CTR =PRD,CTR =CMP).A counter overflow event (FFFFFFFF->00000000)is also provided as an interrupt source (CTROVF).The capture events are edge and sequencer qualified (i.e.,ordered in time)by the polarity select and Mod4gating,respectively.One of these events can be selected as the interrupt source (from the eCAPx module)going to the PIE.Seven interrupt events (CEVT1,CEVT2,CEVT3,CEVT4,CNTOVF,CTR=PRD,CTR=CMP)can be generated.The interrupt enable register (ECEINT)is used to enable/disable individual interrupt eventsources.The interrupt flag register (ECFLG)indicates if any interrupt event has been latched and contains the global interrupt flag bit (INT).An interrupt pulse is generated to the PIE only if any of the interrupt events are enabled,the flag bit is 1,and the INT flag bit is 0.The interrupt service routine must clear the global interrupt flag bit and the serviced event via the interrupt clear register (ECCLR)before any other interrupt pulses are generated.You can force an interrupt event via the interrupt force register (ECFRC).This is useful for test purposes.4.7Shadow Load and Lockout ControlCapture Mode Description Note:The CEVT1,CEVT2,CEVT3,CEVT4flags are only active in capture mode (ECCTL2[CAP/APWM ==0]).The CTR=PRD,CTR=CMP flags are only valid in APWM mode (ECCTL2[CAP/APWM ==1]).CNTOVF flag is valid in both modes.Figure 8.Interrupts in eCAP ModuleIn capture mode,this logic inhibits (locks out)any shadow loading of CAP1or CAP2from APRD and ACMP registers,respectively.In APWM mode,shadow loading is active and two choices are permitted:•Immediate -APRD or ACMP are transferred to CAP1or CAP2immediately upon writing a new value.•On period equal,i.e.,CTR[31:0]=PRD[31:0]Enhanced Capture (eCAP)Module16SPRUFG4A–August 2008–Revised June 20094.8APWM Mode OperationAPRDACMPtime Capture Mode DescriptionMain operating highlights of the APWM section:•The time-stamp counter bus is made available for comparison via 2digital (32-bit)comparators.•When CAP1/2registers are not used in capture mode,their contents can be used as Period and Compare values in APWM mode.•Double buffering is achieved via shadow registers APRD and ACMP (CAP3/4).The shadow register contents are transferred over to CAP1/2registers either immediately upon a write,or on a CTR =PRD trigger.•In APWM mode,writing to CAP1/CAP2active registers will also write the same value to thecorresponding shadow registers CAP3/CAP4.This emulates immediate mode.Writing to the shadow registers CAP3/CAP4will invoke the shadow mode.•During initialization,you must write to the active registers for both period and compare.Thisautomatically copies the initial values into the shadow values.For subsequent compare updates,i.e.,during run-time,you only need to use the shadow registers.Figure 9.PWM Waveform Details Of APWM Mode OperationThe behavior of APWM active high mode (APWMPOL ==0)is as follows:CMP =0x00000000,output low for duration of period (0%duty)CMP =0x00000001,output high 1cycle CMP =0x00000002,output high 2cycles CMP =PERIOD,output high except for 1cycle (<100%duty)CMP =PERIOD+1,output high for complete period (100%duty)CMP >PERIOD+1,output high for complete periodThe behavior of APWM active low mode (APWMPOL ==1)is as follows:CMP =0x00000000,output high for duration of period (0%duty)CMP =0x00000001,output low 1cycle CMP =0x00000002,output low 2cycles CMP =PERIOD,output low except for 1cycle (<100%duty)CMP =PERIOD+1,output low for complete period (100%duty)CMP >PERIOD+1,output low for complete periodCapture Module-Control and Status Registers 5Capture Module-Control and Status RegistersFigure10.Time-Stamp Counter Register(TSCTR)310TSCTRR/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable1.Time-Stamp Counter Register(TSCTR)Field Descriptions Bit(s)Field Description31:0TSCTR Active32-bit counter register that is used as the capture time-baseFigure11.Counter Phase Control Register(CTRPHS)310CTRPHSR/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable2.Counter Phase Control Register(CTRPHS)Field Descriptions Bit(s)Field Description31:0CTRPHS Counter phase value register that can be programmed for phase lag/lead.This register shadowsTSCTR and is loaded into TSCTR upon either a SYNCI event or S/W force via a control edto achieve phase control synchronization with respect to other eCAP and EPWM time-bases.Figure12.Capture-1Register(CAP1)310CAP1R/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable3.Capture-1Register(CAP1)Field DescriptionsBit(s)Field Description31:0CAP1This register can be loaded(written)by:)Time-Stamp(i.e.,counter value TSCTR)during a captureevent)Software-may be useful for test purposes/initialization)APRD shadow register(i.e.,CAP3)when used in APWM modeFigure13.Capture-2Register(CAP2)310CAP2R/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after reset18SPRUFG4A–August2008–Revised June2009 Enhanced Capture(eCAP)Module Capture Module-Control and Status RegistersTable4.Capture-2Register(CAP2)Field DescriptionsBit(s)Field Description31:0CAP2This register can be loaded(written)by:•Time-Stamp(i.e.,counter value)during a capture event•Software-may be useful for test purposes•APRD shadow register(i.e.,CAP4)when used in APWM modeNote:In APWM mode,writing to CAP1/CAP2active registers also writes the same value to thecorresponding shadow registers CAP3/CAP4.This emulates immediate mode.Writing to theshadow registers CAP3/CAP4invokes the shadow mode.Figure14.Capture-3Register(CAP3)310CAP3R/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable5.Capture-3Register(CAP3)Field DescriptionsBit(s)Field Description31:0CAP3In CMP mode,this is a time-stamp capture register.In APWM mode,this is the period shadow(APRD)register.You update the PWM period value through this register.In this mode,CAP3(APRD)shadows CAP1.Figure15.Capture-4Register(CAP4)310CAP4R/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable6.Capture-4Register(CAP4)Field DescriptionsBit(s)Field Description31:0CAP4In CMP mode,this is a time-stamp capture register.In APWM mode,this is the compare shadow(ACMP)register.You update the PWM compare value via this register.In this mode,CAP4(ACMP)shadows CAP2.Figure16.ECAP Control Register1(ECCTL1)15141312111098 FREE/SOFT PRESCALE CAPLDEN R/W-0R/W-0R/W-076543210 CTRRST4CAP4POL CTRRST3CAP3POL CTRRST2CAP2POL CTRRST1CAP1POL R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0R/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after resetCapture Module-Control and Status Registers Table7.ECAP Control Register1(ECCTL1)Field DescriptionsBit(s)Field Value Description15:14FREE/SOFT Emulation Control00TSCTR counter stops immediately on emulation suspend01TSCTR counter runs until=01x TSCTR counter is unaffected by emulation suspend(Run Free)13:9PRESCALE Event Filter prescale select00000Divide by1(i.e,.no prescale,by-pass the prescaler)00001Divide by200010Divide by400011Divide by600100Divide by800101Divide by10...11110Divide by6011111Divide by628CAPLDEN Enable Loading of CAP1-4registers on a capture event0Disable CAP1-4register loads at capture event time.1Enable CAP1-4register loads at capture event time.7CTRRST4Counter Reset on Capture Event40Do not reset counter on Capture Event4(absolute time stamp operation)1Reset counter after Capture Event4time-stamp has been captured(used in difference mode operation)6CAP4POL Capture Event4Polarity select0Capture Event4triggered on a rising edge(RE)1Capture Event4triggered on a falling edge(FE)5CTRRST3Counter Reset on Capture Event30Do not reset counter on Capture Event3(absolute time stamp)1Reset counter after Event3time-stamp has been captured(used in difference mode operation)4CAP3POL Capture Event3Polarity select0Capture Event3triggered on a rising edge(RE)1Capture Event3triggered on a falling edge(FE)3CTRRST2Counter Reset on Capture Event20Do not reset counter on Capture Event2(absolute time stamp)1Reset counter after Event2time-stamp has been captured(used in difference mode operation)2CAP2POL Capture Event2Polarity select0Capture Event2triggered on a rising edge(RE)1Capture Event2triggered on a falling edge(FE)1CTRRST1Counter Reset on Capture Event10Do not reset counter on Capture Event1(absolute time stamp)1Reset counter after Event1time-stamp has been captured(used in difference modeoperation)0CAP1POL Capture Event1Polarity select0Capture Event1triggered on a rising edge(RE)1Capture Event1triggered on a falling edge(FE)20SPRUFG4A–August2008–Revised June2009 Enhanced Capture(eCAP)Module Capture Module-Control and Status RegistersFigure17.ECAP Control Register2(ECCTL2)15111098Reserved APWMPOL CAP/APWM SWSYNCR-0R/W-0R/W-0R/W-076543210 SYNCO_SEL SYNCI_EN TSCTRSTOP REARM STOP_WRAP CONT/ONESHT R/W-0R/W-0R/W-0R/W-0R/W-1R/W-1R/W-0LEGEND:R/W=Read/Write;R=Read only;-n=value after resetTable8.ECAP Control Register2(ECCTL2)Field DescriptionsBit(s)Field Description15:11Reserved Reserved10APWMPOL APWM output polarity select.This is applicable only in APWM operating mode0Output is active high(i.e.,Compare value defines high time)1Output is active low(i.e.,Compare value defines low time)9CAP/APWM CAP/APWM operating mode select0ECAP module operates in capture mode.This mode forces the followingconfiguration:•Inhibits TSCTR resets via CTR=PRD event•Inhibits shadow loads on CAP1and2registers•Permits user to enable CAP1-4register load•CAPx/APWMx pin operates as a capture input1ECAP module operates in APWM mode.This mode forces the followingconfiguration:•Resets TSCTR on CTR=PRD event(period boundary•Permits shadow loading on CAP1and2registers•Disables loading of time-stamps into CAP1-4registers•CAPx/APWMx pin operates as a APWM output8SWSYNC Software-forced Counter(TSCTR)Synchronizing.This provides a convenientsoftware method to synchronize some or all ECAP time bases.In APWM mode,the synchronizing can also be done via the CTR=PRD event.0Writing a zero has no effect.Reading always returns a zero1Writing a one forces a TSCTR shadow load of current ECAP module and anyECAP modules down-stream providing the SYNCO_SEL bits are0,0.After writinga1,this bit returns to a zero.Note:Selection CTR=PRD is meaningful only in APWM mode;however,you canchoose it in CAP mode if you find doing so useful.7:6SYNCO_SEL Sync-Out Select00Select sync-in event to be the sync-out signal(pass through)01Select CTR=PRD event to be the sync-out signal10Disable sync out signal11Disable sync out signal5SYNCI_EN Counter(TSCTR)Sync-In select mode0Disable sync-in option1Enable counter(TSCTR)to be loaded from CTRPHS register upon either a SYNCIsignal or a S/W force event.4TSCTRSTOP Time Stamp(TSCTR)Counter Stop(freeze)Control0TSCTR stopped1TSCTR free-running。

28335多缓冲串口中文资料

1 引言在世界上众多的DSP厂商中，德州仪器公司的DSP始终占据较大的市场份额。

目前得到广泛应用的TI三大DSP处理器系列是TMS320C2000、TMS320C5000和TMS320C6000。

每个系列都有繁多的品种，新的产品层出不穷，更新的速度也非常快，但是基本上每个系列的DSP都有多缓冲串口这一片内外设，利用该外设DSP可以与其他DSP、编码器等其他串口器件进行高速的数据通信。

多缓冲串口的典型应用是它与串口的A/D、D/A芯片连接在一起，实现高速的数字音频采集和传输。

目前，市面上有很多介绍DSP技术的书，但是书中有关多缓冲串口这部分内容的介绍较少，而且多数是直接翻译TI公司多缓冲串口用户使用手册，这样当初学者刚接触多缓冲串口时，入门较难。

针对这个问题，本文综合多个系列的TI公司DSP的多缓冲串口使用手册，再根据自己的理解，从整体到局部，从简单到复杂，先详细地介绍了多缓冲串口进行通信的原理，以及如何配置和控制通信过程等，再比较了各种系列DSP多缓冲串口的区别和联系，最后通过两个小例子，让读者对多缓冲串口具体的使用有了个直观的理解，实验结果的分析对加深多缓冲串口运行机制的理解应该很有帮助。

2 C28x系列DSP的多缓冲串口介绍2.1 通信过程简介多缓冲串口(M ulti c hannel B uffered S erial P ort)，简写为McBSP。

它的通信是靠6个引脚完成的，发送引脚MDX、接收引脚MDR、发送时钟信号引脚MCLKX、接收时钟信号引脚MCLKR、发送帧同步引脚MFSX和接收帧同步引脚MFSR。

后面为了简单起见，发送引脚MDX简写为“DX引脚”省掉了“M”，其他三个引脚同理。

如图1所示，McBSP与其他器件进行通信时，如果字长为16位或者更小(字长为8，12，16)，每个数据传输阶段只需一个16位的寄存器就足够了，DRR2、RBR2、RSR2、DXR2和XSR2不使用。

在这种情况下发送数据时，CPU或者DMA控制器往DXR1寄存器写数据，如果XSR1寄存器没有要发送的数据，那么DXR1中的数据传给XSR1，若XSR1中还有要发送的数据(上次DXR1传给它的值还没有完全从DX引脚移出)，那么DXR1等待上次的值的最后一位从DX引脚移出时才将数据传给XSR1，如果选择了压缩扩展模式(使用虚线框中的Compand Logic，压缩扩展主要是针对μ率或者A率来说的)，那么Compand Logic会将16位的数据压缩成合适的8位的数据格式，然后才将数据传给XSR1。

28335概述

得益于F28335浮点运算单元，从而简化软件开发，缩短开发周期。降低开发成本。
DSP技术应用
采用高性能的静态CMOS技术主频达150MHZ（6.67ns）
低功耗设计，1.9V内核电压，3.3V
Flash编程电压为3.3V
I/O电压
支持JTAG边界扫描接口
高性能32位CPU
16*16位和32*32位的乘法累加操作
C28x
TM
GPIO 16/32-bit
EMIF SPI
88
32x32-bit
Multiplier
通讯接口 32-bit Timers (3) Each McBSP configurable as SPI Real CAN 2.0b with 32 mailboxes Time 2C at 400 Kbps JTAG I 开发套件 SEED-DEC28335+SEED-XDSusb2.0 Code Composer Studio™ IDE V3.3 DSP技术应用 Software libraries
2个增强型的eCAN2.0B接口模块
DSP技术应用
2个多通道缓冲串口（MBSP） 1个12C总线接口 12位模数转换模块
80ns转换时间
2X8通道复用输入接口
两个采样保持电路
单/连续通道转换
高达88个可配置通用目的I/O引脚
先进的仿真调试功能
DSP技术应用
硬件支持适时仿真功能
16*16位的双乘法累加器哈佛总线结构
DSP技术应用
快速中断响应和处理能力统一寻址模式 4M的程序/数据寻址空间
高效的代码转换功能
片上存储器
最多达256K
最多达128K

TMS320F28335中文资料(难得的资料)

标志寄存器由硬件来清零。
EALLOW; // This is needed to write to EALLOW protected registers
PieVectTable.XINT2 = &ISRExint; //告诉中断入口地址
EDIS; // This is needed to disable write to EALLOW protected registers
F28335 是带浮点运算的，动态范围更大。 F2833x 的执行速度，比相同时钟频率的 F28xx 系列定点芯片，快 50%。处理数学运算性能提
升 2.45 倍，控制算法性能提升 1.57 倍，DSP 性能提升 1.38 倍。总体性能提升近 2 倍。
TMS320F28335 的 ADC
TMS320F28335 上有 16 通道、12 位的模数转换器 ADC。他可以被配置为两个独立的 8 通道输入模式，也可以通过配置 AdcRegs.ADCTRL1.bit.SEQ_CASC=1，将其设置为一个 16 通道的级联输入模式。输入的方式可以通过配置 AdcRegs.ADCTRL1.bit.ACQ_PS=1，将其设置为顺序
{
EALLOW; // Before setting PLLCR turn off missing clock detect logic
SysCtrlRegs.PLLSTS.bit.MCLKOFF = 1; SysCtrlRegs.PLLCR.bit.DIV = val; EDIS;
// Optional: Wait for PLL to lock. // During this time the CPU will switch to OSCCLK/2 until // the PLL is staPU will

TMS320x2833x, 2823x DSP Enhanced Controller Area Network (eCAN) User's Guide

TMS320F2833x,2823xEnhanced Controller Area Network(eCAN) Reference GuideLiterature Number:SPRUEU1January20092SPRUEU1–January2009Submit Documentation FeedbackPreface (7)1Architecture (9)1.1CAN Overview (10)1.1.1Features (10)1.1.2Block Diagram (11)1.1.3eCAN Compatibility With Other TI CAN Modules (11)1.2The CAN Network and Module (12)1.2.1CAN Protocol Overview (12)1.3eCAN Controller Overview (13)1.3.1Standard CAN Controller(SCC)Mode (14)1.3.2Memory Map (15)1.3.3eCAN Control and Status Registers (18)1.4Message Objects (19)1.5Message Mailbox (19)1.5.1Transmit Mailbox (23)1.5.2Receive Mailbox (24)1.5.3CAN Module Operation in Normal Configuration (24)2eCAN Registers (25)2.1Mailbox Enable Register(CANME) (26)2.2Mailbox-Direction Register(CANMD) (27)2.3Transmission-Request Set Register(CANTRS) (28)2.4Transmission-Request-Reset Register(CANTRR) (29)2.5Transmission-Acknowledge Register(CANTA) (30)2.6Abort-Acknowledge Register(CANAA) (31)2.7Received-Message-Pending Register(CANRMP) (32)2.8Received-Message-Lost Register(CANRML) (33)2.9Remote-Frame-Pending Register(CANRFP) (34)2.9.1Handling of Remote Frames (34)2.10Global Acceptance Mask Register(CANGAM) (36)2.11Master Control Register(CANMC) (37)2.11.1CAN Module Action in SUSPEND (39)2.12Bit-Timing Configuration Register(CANBTC) (40)2.13Error and Status Register(CANES) (42)2.14CAN Error Counter Registers(CANTEC/CANREC) (44)2.15Interrupt Registers (45)2.15.1Global Interrupt Flag Registers(CANGIF0/CANGIF1) (45)2.15.2Global Interrupt Mask Register(CANGIM) (48)2.15.3Mailbox Interrupt Mask Register(CANMIM) (50)2.15.4Mailbox Interrupt Level Register(CANMIL) (51)2.16Overwrite Protection Control Register(CANOPC) (52)2.17eCAN I/O Control Registers(CANTIOC,CANRIOC) (53)SPRUEU1–January2009Contents3 Submit Documentation Feedback2.18Timer Management Unit (55)2.18.1Time Stamp Functions (55)2.18.2Time-Out Functions (58)2.18.3Behavior/Usage of MTOF0/1Bit in User Applications (60)2.19Mailbox Layout (61)2.19.1Message Identifier Register(MSGID) (61)2.19.2CPU Mailbox Access (62)2.19.3Message-Control Register(MSGCTRL) (63)2.19.4Message Data Registers(CANMDL,CANMDH) (64)2.20Acceptance Filter (65)2.20.1Local-Acceptance Masks(CANLAM) (65)3eCAN Configuration (67)3.1CAN Module Initialization (68)3.1.1CAN Bit-Timing Configuration (69)3.1.2CAN Bit Rate Calculation (69)3.1.3Bit Configuration Parameters for75-MHz CAN Clock (70)3.1.4Bit Configuration Parameters for50-MHz CAN Clock (71)3.1.5EALLOW Protection (72)3.2Steps to Configure eCAN (72)3.2.1Configuring a Mailbox for Transmit (73)3.2.2Transmitting a Message (73)3.2.3Configuring Mailboxes for Receive (73)3.2.4Receiving a Message (74)3.2.5Handling of Overload Situations (74)3.3Handling of Remote Frame Mailboxes (74)3.3.1Requesting Data From Another Node (74)3.3.2Answering a Remote Request (75)3.3.3Updating the Data Field (75)3.4Interrupts (75)3.4.1Interrupts Scheme (77)3.4.2Mailbox Interrupt (77)3.4.3Interrupt Handling (78)3.5CAN Power-Down Mode (80)3.5.1Entering and Exiting Local Power-Down Mode (80)3.5.2Precautions for Entering and Exiting Device Low-Power Modes(LPM) (80)3.5.3Enabling/Disabling Clock to the CAN Module (81)3.5.4Possible Failure Modes External to the CAN Controller Module (81)4SPRUEU1–January2009 ContentsSubmit Documentation FeedbackList of Figures1-1eCAN Block Diagram and Interface Circuit (11)1-2CAN Data Frame (12)1-3Architecture of the eCAN Module (13)1-4eCAN-A Memory Map (16)1-5eCAN-B Memory Map (17)2-1Mailbox-Enable Register(CANME) (26)2-2Mailbox-Direction Register(CANMD) (27)2-3Transmission-Request Set Register(CANTRS) (28)2-4Transmission-Request-Reset Register(CANTRR) (29)2-5Transmission-Acknowledge Register(CANTA) (30)2-6Abort-Acknowledge Register(CANAA) (31)2-7Received-Message-Pending Register(CANRMP) (32)2-8Received-Message-Lost Register(CANRML) (33)2-9Remote-Frame-Pending Register(CANRFP) (34)2-10Global Acceptance Mask Register(CANGAM) (36)2-11Master Control Register(CANMC) (37)2-12Bit-Timing Configuration Register(CANBTC) (40)2-13Error and Status Register(CANES) (42)2-14Transmit-Error-Counter Register(CANTEC) (44)2-15Receive-Error-Counter Register(CANREC) (44)2-16Global Interrupt Flag0Register(CANGIF0) (46)2-17Global Interrupt Flag1Register(CANGIF1) (46)2-18Global Interrupt Mask Register(CANGIM) (48)2-19Mailbox Interrupt Mask Register(CANMIM) (50)2-20Mailbox Interrupt Level Register(CANMIL) (51)2-21Overwrite Protection Control Register(CANOPC) (52)2-22TX I/O Control Register(CANTIOC) (53)2-23RX I/O Control Register(CANRIOC) (54)2-24Time-Stamp Counter Register(CANTSC) (56)2-25Message Object Time Stamp Registers(MOTS) (57)2-26Message-Object Time-Out Registers(MOTO) (58)2-27Time-Out Control Register(CANTOC) (59)2-28Time-Out Status Register(CANTOS) (60)2-29Message Identifier Register(MSGID)Register (61)2-30Message-Control Register(MSGCTRL) (63)2-31Message-Data-Low Register With DBO=0(CANMDL) (64)2-32Message-Data-High Register With DBO=0(CANMDH) (64)2-33Message-Data-Low Register With DBO=1(CANMDL) (64)2-34Message-Data-High Register With DBO=1(CANMDH) (64)2-35Local-Acceptance-Mask Register(LAM n) (66)3-1Initialization Sequence (68)3-2CAN Bit Timing (69)3-3Interrupts Scheme (76)SPRUEU1–January2009List of Figures5 Submit Documentation FeedbackList of Tables1-1Register Map (18)1-2eCAN-A Mailbox RAM Layout (20)1-3Addresses of LAM,MOTS and MOTO registers for mailboxes(eCAN-A) (21)1-4eCAN-B Mailbox Ram Layout (22)1-5Addresses of LAM,MOTS,and MOTO Registers for Mailboxes(eCAN-B) (23)1-6Message Object Behavior Configuration (23)2-1Mailbox-Enable Register(CANME)Field Descriptions (26)2-2Mailbox-Direction Register(CANMD)Field Descriptions (27)2-3Transmission-Request Set Register(CANTRS)Field Descriptions (28)2-4Transmission-Request-Reset Register(CANTRR)Field Descriptions (29)2-5Transmission-Acknowledge Register(CANTA)Field Descriptions (30)2-6Abort-Acknowledge Register(CANAA)Field Descriptions (31)2-7Received-Message-Pending Register(CANRMP)Field Descriptions (32)2-8Received-Message-Lost Register(CANRML)Field Descriptions (33)2-9Remote-Frame-Pending Register(CANRFP)Field Descriptions (34)2-10Global Acceptance Mask Register(CANGAM)Field Descriptions (36)2-11Master Control Register(CANMC)Field Descriptions (37)2-12Bit-Timing Configuration Register(CANBTC)Field Descriptions (40)2-13Error and Status Register(CANES)Field Descriptions (42)2-14Global Interrupt Flag Registers(CANGIF0/CANGIF1)Field Descriptions (47)2-15Global Interrupt Mask Register(CANGIM)Field Descriptions (48)2-16Mailbox Interrupt Mask Register(CANMIM)Field Descriptions (50)2-17Mailbox Interrupt Level Register(CANMIL)Field Descriptions (51)2-18Overwrite Protection Control Register(CANOPC)Field Descriptions (52)2-19TX I/O Control Register(CANTIOC)Field Descriptions (53)2-20RX I/O Control Register(CANRIOC)Field Descriptions (54)2-21Time-Stamp Counter Register(CANTSC)Field Descriptions (56)2-22Message Object Time Stamp Registers(MOTS)Field Descriptions (57)2-23Message-Object Time-Out Registers(MOTO)Field Descriptions (58)2-24Time-Out Control Register(CANTOC)Field Descriptions (59)2-25Time-Out Status Register(CANTOS)Field Descriptions (60)2-26Message Identifier Register(MSGID)Field Descriptions (61)2-27Message-Control Register(MSGCTRL)Field Descriptions (63)2-28Local-Acceptance-Mask Register(LAM n)Field Descriptions (66)3-1BRP Field for Bit Rates(BT=15,TSEG1reg=10,TSEG2reg=2,Sampling Point=80%) (70)3-2Achieving Different Sampling Points With a BT of15 (70)3-3BRP Field for Bit Rates(BT=10,TSEG1reg=6,TSEG2reg=1,Sampling Point=80%) (71)3-4Achieving Different Sampling Points With a BT of20 (71)3-5eCAN Interrupt Assertion/Clearing (78)6SPRUEU1–January2009 List of TablesSubmit Documentation FeedbackPrefaceSPRUEU1–January2009About This ManualThis document describes the enhanced controller area network(eCAN)on the F2833x and F2823xdevices.Notational ConventionsThis document uses the following conventions.•Hexadecimal numbers are shown with the suffix h.For example,the following number is40 hexadecimal(decimal64):40h.Related Documentation From Texas InstrumentsThe following documents describe the F2833x and related peripherals.Copies ofthese documents are available for downloading atData Manual and Errata—ofCPU User's Guides—SPRU430—describes the centralTMS320C28x fixed-point digital signal processors(DSPs).It also describes emulation features available on these DSPs.SPRUEO2—describes thePeripheral Guides—SPRU566—describes the peripheral referenceSPRUFB0—TMS320x2833x,2823x System Control and Interrupts Reference Guide describes the various interrupts and system control features of the2833x digital signal controllers(DSCs).SPRU812—describes how toSPRU949—describes the XINTF,whichis aSPRU963—describes the purpose andand provides examples of code.It also describes other contents of the device on-chip boot ROM and identifies where all ofthe information is located within that memory.SPRUEU1–January2009Read This First7 Submit Documentation FeedbackRelated Documentation From Texas Instruments SPRUFB7—describesthe a DSPand other devices in a system.SPRUFB8—describes the DMAonSPRUG04—switch mode power supply control,UPS(uninterruptible power supplies),and other forms of powerconversion.SPRUG02—describes theSPRUFG4—describes theSPRUG05—encoder to get position,direction,and speed information from a rotating machine in highperformance motion and position control systems.It includes the module description and registers.SPRUEU1—in electrically noisy environments.SPRUFZ5—describesthe SCImodules support digital communications between the CPU and other asynchronous peripherals thatuse the standard non-return-to-zero(NRZ)format.SPRUEU3—describes the SPI-a ofprogrammed length(one to sixteen bits)to be shifted into and out of the device at a programmedbit-transfer rate.SPRUG03—describes theTools Guides—SPRU513—describes the assembly languagetools code),assembler directives,macros,common object file format,and symbolic debugging directives for the TMS320C28x device.SPRU514—describes the TMS320C28x™C/C++code and produces TMS320DSP assembly language source code for the TMS320C28x device.SPRU608—describes the simulator,simulates the instruction set of the C28x™core.SPRU625—Read This First8SPRUEU1–January2009Submit Documentation FeedbackChapter1SPRUEU1–January2009The enhanced Controller Area Network(eCAN)module implemented in the C28x™DSP is a full-CAN controller and is compatible with the CAN 2.0B standard(active).It uses established protocol to communicate serially with other controllers in electrically noisy environments.With32fully configurable mailboxes and time–stamping feature,the eCAN module provides a versatile and robust serial communication interface.The eCAN module described in guide is a Type2eCAN.Refer to theTMS320x28xx,28xxx DSP Peripheral Reference Guide for a list of other devices with a eCAN module of the sametype,to determine the differences and for a list of device-specific differences within a type.Some devices have a second CAN module,eCAN-B.The word eCAN is generically used to refer to the CAN modules.The specific module reference(A or B)is used where appropriate.For a given CAN module,the same address space is used for the module registers in all28xx/28xxx devices.Topic PageSPRUEU1–January2009Architecture9 Submit Documentation Feedback1.1CAN Overview1.1.1FeaturesCAN Overview Figure 1–1shows the major blocks of the eCAN and the interface circuits.The eCAN module has the following features:•Fully compliant with CAN protocol,version 2.0B•Supports data rates up to 1Mbps•Thirty-two mailboxes,each with the following properties:–Configurable as receive or transmit–Configurable with standard or extended identifier–Has a programmable acceptance filter mask–Supports data and remote frame–Supports 0to 8bytes of data–Uses a 32-bit time stamp on received and transmitted message–Protects against reception of new message–Allows dynamically programmable priority of transmit message–Employs a programmable interrupt scheme with two interrupt levels–Employs a programmable interrupt on transmission or reception time-out•Low–power mode•Programmable wake–up on bus activity•Automatic reply to a remote request message•Automatic retransmission of a frame in case of loss of arbitration or error•32-bit time-stamp counter synchronized by a specific message (communication in conjunction with mailbox 16)•Self–test mode–Operates in a loopback mode receiving its own message.A “dummy”acknowledge is provided,thereby eliminating the need for another node to provide the acknowledge bit.10Architecture SPRUEU1–January 2009Submit Documentation Feedback1.1.2Block DiagramControlsAddressDataECAN1INTECAN0INT1.1.3eCAN Compatibility With Other TI CAN Modules CAN OverviewFigure 1-1.eCAN Block Diagram and Interface CircuitA The communication buffers are transparent to the user and are not accessible by user code.The eCAN module is identical to the “High-end CAN Controller (HECC)”used in the TMS470™series microcontrollers from Texas Instruments with some minor changes.The eCAN module features several enhancements (such as increased number of mailboxes with individual acceptance masks,time stamping,etc.)over the CAN module featured in 240x™series of DSPs.For this reason,code written for 240x CAN modules cannot be directly ported to eCAN.However,eCAN follows the same register bit-layout structure and bit functionality as that of 240x CAN (for registers that exist in both devices)i.e.,many registers and bits perform exactly identical functions across these two platforms.This makes code migration a relatively easy task,more so with code written in C language.1.2The CAN Network and Module1.2.1CAN Protocol OverviewBit length– 11-bit identifier + RTR bit for standard frame format– 29-bit identifier + SRR bit + IDE bit + RTR bit for extended frame format Where: RTR = Remote Transmission Request SRR = Substitute Remote Request IDE = Identifier ExtensionNote: Unless otherwise noted, numbers are amount of bits in field.The CAN Network and Module The controller area network (CAN)uses a serial multimaster communication protocol that efficientlysupports distributed real-time control,with a very high level of security,and a communication rate of up to 1Mbps.The CAN bus is ideal for applications operating in noisy and harsh environments,such as in the automotive and other industrial fields that require reliable communication.Prioritized messages of up to eight bytes in data length can be sent on a multimaster serial bus using an arbitration protocol and an error-detection mechanism for a high level of data integrity.The CAN protocol supports four different frame types for communication:•Data frames that carry data from a transmitter node to the receiver nodes•Remote frames that are transmitted by a node to request the transmission of a data frame with the same identifier•Error frames that are transmitted by any node on a bus-error detection•Overload frames that provide an extra delay between the preceding and the succeeding data frames or remote frames.In addition,CAN specification version 2.0B defines two different formats that differ in the length of the identifier field:standard frames with an 11-bit identifier and extended frames with 29-bit identifier.CAN standard data frames contain from 44to 108bits and CAN extended data frames contain 64to 128bits.Furthermore,up to 23stuff bits can be inserted in a standard data frame,and up to 28stuff bits in an extended data frame,depending on the data-stream coding.The overall maximum data frame length is then 131bits for a standard frame and 156bits for an extended frame.The bit fields that make up standard/extended data frames,along with their position as shown in Figure 1-2include the following:•Start of frame•Arbitration field containing the identifier and the type of message being sent •Control field indicating the number of bytes being transmitted.•Up to 8bytes of data•Cyclic redundancy check (CRC)•Acknowledgment •End-of-frame bitsFigure 1-2.CAN Data FrameThe eCAN controller provides the CPU with full functionality of the CAN protocol,version 2.0B.The CAN controller minimizes the CPU’s load in communication overhead and enhances the CAN standard by providing additional features.The architecture of eCAN module,shown in Figure 1-3,is composed of a CAN protocol kernel (CPK)and a message controller.12ArchitectureSPRUEU1–January 2009 eCAN Controller OverviewFigure1-3.Architecture of the eCAN ModuleA The receive and transmit buffers are transparent to the user and are not accessible by user code.Two functions of the CPK are to decode all messages received on the CAN bus according to the CAN protocol and to transfer these messages into a receive buffer.Another CPK function is to transmitmessages on the CAN bus according to the CAN protocol.The message controller of a CAN controller is responsible for determining if any message received by the CPK must be preserved for the CPU use or be discarded.At the initialization phase,the CPU specifies to the message controller all message identifiers used by the application.The message controller is alsoresponsible for sending the next message to transmit to the CPK according to the message’s priority.1.3eCAN Controller OverviewThe eCAN is a CAN controller with an internal32-bit architecture.The eCAN module consists of:•The CAN protocol kernel(CPK)•The message controller comprising:–The memory management unit(MMU),including the CPU interface and the receive control unit (acceptance filtering),and the timer management unit–Mailbox RAM enabling the storage of32messages–Control and status registersAfter the reception of a valid message by the CPK,the receive control unit of the message controllerdetermines if the received message must be stored into one of the32message objects of the mailboxRAM.The receive control unit checks the state,the identifier,and the mask of all message objects todetermine the appropriate mailbox location.The received message is stored into the first mailbox passing the acceptance filtering.If the receive control unit could not find any mailbox to store the receivedmessage,the message is discarded.A message is composed of an11-or29-bit identifier,a control field,and up to8bytes of data.eCAN Controller Overview When a message must be transmitted,the message controller transfers the message into the transmit buffer of the CPK in order to start the message transmission at the next bus-idle state.When more than one message must be transmitted,the message with the highest priority that is ready to be transmitted is transferred into the CPK by the message controller.If two mailboxes have the same priority,then themailbox with the higher number is transmitted first.The timer management unit comprises a time-stamp counter and apposes a time stamp to all messages received or transmitted.It generates an interrupt when a message has not been received or transmitted during an allowed period of time(time-out).The time-stamping feature is available in eCAN mode only.To initiate a data transfer,the transmission request bit(TRS.n)has to be set in the corresponding control register.The entire transmission procedure and possible error handling are then performed without any CPU involvement.If a mailbox has been configured to receive messages,the CPU easily reads its data registers using CPU read instructions.The mailbox may be configured to interrupt the CPU after every successful message transmission or reception.1.3.1Standard CAN Controller(SCC)ModeThe SCC Mode is a reduced functionality mode of the eCAN.Only16mailboxes(0through15)areavailable in this mode.The time stamping feature is not available and the number of acceptance masks available is reduced.This mode is selected by default.The SCC mode or the full featured eCAN mode is selected using the SCB bit(CANMC.13).14Architecture SPRUEU1–January2009 eCAN Controller Overview 1.3.2Memory MapThe eCAN module has two different address segments mapped in the memory.The first segment is used to access the control registers,the status registers,the acceptance masks,the time stamp,and thetime-out of the message objects.The access to the control and status registers is limited to32-bit wide accesses.The local acceptance masks,the time stamp registers,and the time-out registers can beaccessed8-bit,16-bit and32-bit wide.The second address segment is used to access the mailboxes.This memory range can be accessed8-bit,16-bit and32-bit wide.Each of these two memory blocks,shown in Figure1-4,uses512bytes of address space.The message storage is implemented by a RAM that can be addressed by the CAN controller or the CPU.The CPU controls the CAN controller by modifying the various mailboxes in the RAM or the additionalregisters.The contents of the various storage elements are used to perform the functions of theacceptance filtering,message transmission,and interrupt handling.The mailbox module in the eCAN provides32message mailboxes of8-byte data length,a29-bit identifier, and several control bits.Each mailbox can be configured as either transmit or receive.In the eCAN mode, each mailbox has its individual acceptance mask.Note:LAMn,MOTSn and MOTOn registers and mailboxes not used in an application(disabled inthe CANME register)may be used as general-purpose data memory by the CPU.1.3.2.132-bit Access to Control and Status RegistersAs indicated in Section1.3.2,only32-bit accesses are allowed to the Control and Status registers.16-bit access to potentially corrupt the register contents or return false data.The DSPheader files released by TI employs a shadow register structure that aids in32-bit access.Following are a few examples of how the shadow register structure may be employed to perform32-bit reads/writes:Example1-1.Modifying a bit in a registerECanaShadow.CANTIOC.all=ECanaRegs.CANTIOC.all;//Step1ECanaShadow.CANTIOC.bit.TXFUNC=1;//Step2ECanaRegs.CANTIOC.all=ECanaShadow.CANTIOC.all;//Step3Step1:Perform a32-bit read to copy the entire register to its shadowStep2:Modify the needed bit(s)in the shadowStep3:Perform a32-bit write to copy the modified shadow to the original register.Note:Some bits like TAn and RMPn are cleared by writing a1to it.Care should be taken not toclear bits inadvertently.Example1-2.Checking the value of a bit in a registerdo{ECanaShadow.CANTA.all=ECanaRegs.CANTA.all;}while(ECanaShadow.CANTA.bit.TA25==0);//Wait for TA5bit to be set..In the above example,the value of TA25bit needs to be checked.This is done by first copying the entire CANTA register to its shadow(using a32-bit read)and then checking the relevant bit,repeating thisoperation until that condition is satisfied.TA25bit should NOT be checked with the following statement: while(ECanaRegs.CANTA.bit.TA25==0);eCAN−A Control and Status Registers6110h−616118h−61eCAN Controller Overview Figure 1-4.eCAN-A Memory MapArchitecture16SPRUEU1–January 2009 eCAN Controller OverviewFigure1-5.eCAN-B Memory MapeCAN−B Control and Status RegisterseCAN Controller Overview 1.3.3eCAN Control and Status RegistersThe eCAN registers listed in Table1-1are used by the CPU to configure and control the CAN controller and the message objects.Table1-1.Register MapREGISTER NAME(1)ECAN-A ECAN-B SIZE DESCRIPTIONADDRESS ADDRESS(x32)CANME0x60000x62001Mailbox enableCANMD0x60020x62021Mailbox directionCANTRS0x60040x62041Transmit request setCANTRR0x60060x62061Transmit request resetCANTA0x60080x62081Transmission acknowledgeCANAA0x600A0x620A1Abort acknowledgeCANRMP0x600C0x620C1Receive message pendingCANRML0x600E0x620E1Receive message lostCANRFP0x60100x62101Remote frame pendingCANGAM0x60120x62121Global acceptance maskCANMC0x60140x62141Master controlCANBTC0x60160x62161Bit-timing configurationCANES0x60180x62181Error and statusCANTEC0x601A0x621A1Transmit error counterCANREC0x601C0x621C1Receive error counterCANGIF00x601E0x621E1Global interrupt flag0CANGIM0x60200x62201Global interrupt maskCANGIF10x60220x62221Global interrupt flag1CANMIM0x60240x62241Mailbox interrupt maskCANMIL0x60260x62261Mailbox interrupt levelCANOPC0x60280x62281Overwrite protection controlCANTIOC0x602A0x622A1TX I/O controlCANRIOC0x602C0x622C1RX I/O controlCANTSC0x602E0x622E1Time stamp counter(Reserved in SCC mode)CANTOC0x60300x62301Time-out control(Reserved in SCC mode)CANTOS0x60320x62321Time-out status(Reserved in SCC mode)(1)These registers are mapped to Peripheral Frame1.Note:Only32-bit accesses are allowed to the control and status registers.This restriction does notapply to the mailbox RAM area.See Section1.3.2.1for more information.18Architecture SPRUEU1–January2009 Message Objects 1.4Message ObjectsThe eCAN module has32different message objects(mailboxes).Each message object can be configured to either transmit or receive.Each message object has itsindividual acceptance mask.A message object consists of a message mailbox with:•The29-bit message identifier•The message control register•8bytes of message data•A29-bit acceptance mask•A32-bit time stamp•A32-bit time-out valueFurthermore,corresponding control and status bits located in the registers allow control of the message objects.1.5Message MailboxThe message mailboxes are the RAM area where the CAN messages are actually stored after they are received or before they are transmitted.The CPU may use the RAM area of the message mailboxes that are not used for storing messages as normal memory.Each mailbox contains:•The message identifier–29bits for extended identifier–11bits for standard identifier•The identifier extension bit,IDE(MSGID.31)•The acceptance mask enable bit,AME(MSGID.30)•The auto answer mode bit,AAM(MSGID.29)•The transmit priority level,TPL(MSGCTRL.12-8)•The remote transmission request bit,RTR(MSGCTRL.4)•The data length code,DLC(MSGCTRL.3-0)•Up to eight bytes for the data fieldEach of the mailboxes can be configured as one of four message object types(see Table1-5).Transmit and receive message objects are used for data exchange between one sender and(1to n communication link),whereas request and reply message objects are used to set up a one-to-onecommunication link.Table1-2lists the mailbox RAM layout.Message Mailbox Table1-2.eCAN-A Mailbox RAM LayoutMailbox MSGID MSGCTRL CANMDL CANMDHMSGIDL-MSGIDH MSGCTRL-Rsvd CANMDL_L-CANMDL_H CANMDH_L-CANMDH_H 06100-6101h6102-6103h6104-6105h6106-6107h16108-6109h610A-610Bh610C-610Dh610E-610Fh26110-6111h6112-6113h6114-6115h6116-6117h36118-6119h611A-611Bh611C-611Dh611E-611Fh46120-6121h6122-6123h6124-6125h6126-6127h56128-6129h612A-612Bh612C-612Dh612E-612Fh66130-6131h6132-6133h6134-6135h6136-6137h76138-6139h613A-613Bh613C-613Dh613E-613Fh86140-6141h6142-6143h6144-6145h6146-6147h96148-6149h614A-614Bh614C-614Dh614E-614Fh106150-6151h6152-6153h6154-6155h6156-6157h116158-6159h615A-615Bh615C-615Dh615E-615Fh126160-6161h6162-6163h6164-6165h6166-6167h136168-6169h616A-616Bh616C-616Dh616E-616Fh146170-6171h6172-6173h6174-6175h6176-6177h156178-6179h617A-617Bh617C-617Dh617E-617Fh166180-6181h6182-6183h6184-6185h6186-6187h176188-6189h618A-618Bh618C-618Dh618E-618Fh186190-6191h6192-6193h6194-6195h6196-6197h196198-6199h619A-619Bh619C-619Dh619E-619Fh2061A0-61A1h61A2-61A3h61A4-61A5h61A6-61A7h2161A8-61A9h61AA-61ABh61AC-61ADh61AE-61AFh2261B0-61B1h61B2-61B3h61B4-61B5h61B6-61B7h2361B8-61B9h61BA-61BBh61BC-61BDh61BE-61BFh2461C0-61C1h61C2-61C3h61C4-61C5h61C6-61C7h2561C8-61C9h61CA-61CBh61CC-61CDh61CE-61CFh2661D0-61D1h61D2-61D3h61D4-61D5h61D6-61D7h2761D8-61D9h61DA-61DBh61DC-61DDh61DE-61DFh2861E0-61E1h61E2-61E3h61E4-61E5h61E6-61E7h2961E8-61E9h61EA-61EBh61EC-61EDh61EE-61EFh3061F0-61F1h61F2-61F3h61F4-61F5h61F6-61F7h3161F8-61F9h61FA-61FBh61FC-61FDh61FE-61FFh20SPRUEU1–January2009 Architecture。

【世界五百强机密文件】dsp28335相关文档

TMS320x281x和TMS320x2833x/TMS320x2823x之间的区别最近在使用TI的28355芯片，由于以前没有接触过，在网上资料也不多，就去TI官网找英文来看；281x和283/23x都是C2000™系列的芯片，后者较前者有很多增强的地方，下面分开一条一条来写：1：CPU（浮点）2833x增加了FPU32位单精度浮点运算单元，不过新的指令是作为标准C28x指令集的扩展来加进去的，所以能够对定点运算100%兼容，锁存上溢和下溢标志位和PIE相连，方便调试；2：CCS开发环境安装后要装专门的升级包，按顺序装好才能使用28335芯片，然后使用2833x的头文件；然后进入ccs后还有设置一下32浮点运算，加入库文件，这部分在网上有详细介绍，编译器，汇编器，连接器最好5.0以上；3：封装管脚不兼容，需重新画板；4：运行频率和供电电压281x：135MHZ以下1.8v，以上到150MHZ1.9v28335:100MHZ以下1.8v，以上到150MHZ1.9vIO口供电电压都是为3.3v5：上电顺序281x：Vddio先，Vdd后28335：可同时上电，也可使用281x的上电顺序；6：SARAM281x：18*16字；28355:34*16字；最大SARAM块4k*16字，变小了；双内存映射；DMA直接访问SARAM；7：FlashF28335: 256K x 16 FlashF2812：128*16 Flash8：外设28355去除了EV，用3个新的外设代替ePWM,eCAP，eQEP增加了DMA：6通道，每个通道有自己的中断，2种运行方式；I2C Bus；文档升级；ADC：电容10uf-2.2uf，电阻24.9k-22k，AD转换接触后有3个中断可以触发，DMA直接读取结果寄存器；CSM密码位置不同；外部存储器接口DMA可直接读取；去除McBSP上的FIFOs，用DMA替代；eCAN增多1个；SCI增多1个9：中断新增外设中断，5个新的外部中断基于TMS320F28335信号处理板的设计与实现TMS320F28335是，TI公司最新推出的一款32位浮点数字信号控制器，兼顾了DSP强大的处理核心和M CU丰富的片上外设。

DMA模块使用说明—28335

TMS320x2833x,2823x Direct Memory Access (DMA)ModuleReference GuideLiterature Number:SPRUFB8DSeptember2007–Revised April20112SPRUFB8D–September2007–Revised April2011Submit Documentation FeedbackPreface (6)1Introduction (8)2Architecture (10)2.1Block Diagram (10)2.2Peripheral Interrupt Event Trigger Sources (10)2.3DMA Bus (13)3Pipeline Timing and Throughput (13)4CPU Arbitration (15)4.1For the External Memory Interface(XINTF)Zones (15)4.2For All Other Peripherals/Memories (16)5Channel Priority (16)5.1Round-Robin Mode (16)5.2Channel1High Priority Mode (17)6Address Pointer and Transfer Control (17)7ADC Sync Feature (22)8Overrun Detection Feature (24)9Register Descriptions (25)9.1DMA Control Register(DMACTRL)—EALLOW Protected (26)9.2Debug Control Register(DEBUGCTRL)—EALLOW Protected (27)9.3Revision Register(REVISION) (27)9.4Priority Control Register1(PRIORITYCTRL1)—EALLOW Protected (28)9.5Priority Status Register(PRIORITYSTAT) (29)9.6Mode Register(MODE)—EALLOW Protected (30)9.7Control Register(CONTROL)—EALLOW Protected (32)9.8Burst Size Register(BURST_SIZE)—EALLOW Protected (34)9.9BURST_COUNT Register (34)9.10Source Burst Step Register Size(SRC_BURST_STEP)—EALLOW Protected (35)9.11Destination Burst Step Register Size(DST_BURST_STEP)—EALLOW Protected (36)9.12Transfer Size Register(TRANSFER_SIZE)—EALLOW Protected (36)9.13Transfer Count Register(TRANSFER_COUNT) (37)9.14Source Transfer Step Size Register(SRC_TRANSFER_STEP)—EALLOW Protected (37)9.15Destination Transfer Step Size Register(DST_TRANSFER_STEP)—EALLOW Protected (38)9.16Source/Destination Wrap Size Register(SRC/DST_WRAP_SIZE)—EALLOW protected) (38)9.17Source/Destination Wrap Count Register(SCR/DST_WRAP_COUNT) (39)9.18Source/Destination Wrap Step Size Registers(SRC/DST_WRAP_STEP)—EALLOW Protected (39)9.19Shadow Source Begin and Current Address Pointer Registers(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW)—All EALLOW Protected (40)9.20Active Source Begin and Current Address Pointer Registers(SRC_BEG_ADDR/DST_BEG_ADDR) (40)9.21Shadow Destination Begin and Current Address Pointer Registers(SRC_ADDR_SHADOW/DST_ADDR_SHADOW)—All EALLOW Protected (41)9.22Active Destination Begin and Current Address Pointer Registers(SRC_ADDR/DST_ADDR) (41)Appendix A Revision History (42)3 SPRUFB8D–September2007–Revised April2011Table of Contents Submit Documentation FeedbackList of Figures1DMA Block Diagram (10)2Peripheral Interrupt Trigger Input Diagram (12)34-Stage Pipeline DMA Transfer (13)44-Stage Pipeline With One Read Stall(McBSP as source) (14)5DMA State Diagram (21)6ADC Sync Input Diagram (23)7Overrun Detection Logic (24)8DMA Control Register(DMACTRL) (26)9Debug Control Register(DEBUGCTRL) (27)10Revision Register(REVISION) (27)11Priority Control Register1(PRIORITYCTRL1) (28)12Priority Status Register(PRIORITYSTAT) (29)13Mode Register(MODE) (30)14Control Register(CONTROL) (32)15Burst Size Register(BURST_SIZE) (34)16Burst Count Register(BURST_COUNT) (34)17Source Burst Step Size Register(SRC_BURST_STEP) (35)18Destination Burst Step Register Size(DST_BURST_STEP) (36)19Transfer Size Register(TRANSFER_SIZE) (36)20Transfer Count Register(TRANSFER_COUNT) (37)21Source Transfer Step Size Register(SRC_TRANSFER_STEP) (37)22Destination Transfer Step Size Register(DST_TRANSFER_STEP) (38)23Source/Destination Wrap Size Register(SRC/DST_WRAP_SIZE) (38)24Source/Destination Wrap Count Register(SCR/DST_WRAP_COUNT) (39)25Source/Destination Wrap Step Size Registers(SRC/DST_WRAP_STEP) (39)26Shadow Source Begin and Current Address Pointer Registers(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW) (40)27Active Source Begin and Current Address Pointer Registers(SRC_BEG_ADDR/DST_BEG_ADDR) (40)28Shadow Destination Begin and Current Address Pointer Registers(SRC_ADDR_SHADOW/DST_ADDR_SHADOW) (41)29Active Destination Begin and Current Address Pointer Registers(SRC_ADDR/DST_ADDR) (41)4List of Figures SPRUFB8D–September2007–Revised April2011Submit Documentation FeedbackList of Tables1Peripheral Interrupt Trigger Source Options (12)2DMA Register Summary (25)3DMA Control Register(DMACTRL)Field Descriptions (26)4Debug Control Register(DEBUGCTRL)Field Descriptions (27)5Revision Register(REVISION)Field Descriptions (27)6Priority Control Register1(PRIORITYCTRL1)Field Descriptions (28)7Priority Status Register(PRIORITYSTAT)Field Descriptions (29)8Mode Register(MODE)Field Descriptions (30)9Control Register(CONTROL)Field Descriptions (32)10Burst Size Register(BURST_SIZE)Field Descriptions (34)11Burst Count Register(BURST_COUNT)Field Descriptions (34)12Source Burst Step Size Register(SRC_BURST_STEP)Field Descriptions (35)13Destination Burst Step Register Size(DST_BURST_STEP)Field Descriptions (36)14Transfer Size Register(TRANSFER_SIZE)Field Descriptions (36)15Transfer Count Register(TRANSFER_COUNT)Field Descriptions (37)16Source Transfer Step Size Register(SRC_TRANSFER_STEP)Field Descriptions (37)17Destination Transfer Step Size Register(DST_TRANSFER_STEP)Field Descriptions (38)18Source/Destination Wrap Size Register(SRC/DST_WRAP_SIZE)Field Descriptions (38)19Source/Destination Wrap Count Register(SCR/DST_WRAP_COUNT)Field Descriptions (39)20Source/Destination Wrap Step Size Registers(SRC/DST_WRAP_STEP)Field Descriptions (39)21Shadow Source Begin and Current Address Pointer Registers(SRC_BEG_ADDR_SHADOW/DST_BEG_ADDR_SHADOW)Field Descriptions (40)22Active Source Begin and Current Address Pointer Registers(SRC_BEG_ADDR/DST_BEG_ADDR)Field Descriptions (40)23Shadow Destination Begin and Current Address Pointer Registers(SRC_ADDR_SHADOW/DST_ADDR_SHADOW)Field Descriptions (41)24Active Destination Begin and Current Address Pointer Registers(SRC_ADDR/DST_ADDR)Field Descriptions (41)25Document Revision History (42)5 SPRUFB8D–September2007–Revised April2011List of Tables Submit Documentation FeedbackPrefaceSPRUFB8D–September2007–Revised April2011Read This First The DMA module described in this reference guide is a Type0DMA.See the TMS320C28xx,28xxx DSP Peripheral Reference Guide(SPRU566)for a list of all devices with a DMA module of the same type,to determine the differences between the types,and for a list of device-specific differences within a type.Notational ConventionsThis document uses the following conventions.•Hexadecimal numbers are shown with the suffix h or with a leading0x.For example,the following number is40hexadecimal(decimal64):40h or0x40.•Registers in this document are shown in figures and described in tables.–Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name,its beginning and ending bit numbers above,and itsread/write properties below.A legend explains the notation used for the properties.–Reserved bits in a register figure designate a bit that is used for future device expansion.Related DocsThe following documents support the2833x and2823x devices and can be downloaded from the Texas Instruments web site:.Data Manual and Errata—SPRS439—TMS320F28335,TMS320F28334,TMS320F28332,TMS320F28235,TMS320F28234, TMS320F28232Digital Signal Controllers(DSCs)Data Manual contains the pinout,signaldescriptions,as well as electrical and timing specifications for the F2833x/2823x devices.SPRZ272—TMS320F28335,F28334,F28332,TMS320F28235,F28234,F28232Digital Signal Controllers(DSCs)Silicon Errata describes the advisories and usage notes for different versions ofsilicon.CPU User's Guides—SPRU430—TMS320C28x CPU and Instruction Set Reference Guide describes the central processing unit(CPU)and the assembly language instructions of the TMS320C28x fixed-point digital signalprocessors(DSPs).It also describes emulation features available on these DSPs.SPRUEO2—TMS320C28x Floating Point Unit and Instruction Set Reference Guide describes the floating-point unit and includes the instructions for the FPU.Peripheral Guides—SPRU566—TMS320x28xx,28xxx DSP Peripheral Reference Guide describes the peripheral reference guides of the28x digital signal processors(DSPs).SPRUFB0—TMS320x2833x,2823x System Control and Interrupts Reference Guide describes the various interrupts and system control features of the2833x and2823x digital signal controllers(DSCs).SPRU812—TMS320x2833x,2823x Analog-to-Digital Converter(ADC)Reference Guide describes how to configure and use the on-chip ADC module,which is a12-bit pipelined ADC.SPRU949—TMS320x2833x,2823x DSC External Interface(XINTF)Reference Guide describes the XINTF,which is a nonmultiplexed asynchronous bus,as it is used on the2833x and2823x devices.6Preface SPRUFB8D–September2007–Revised April2011Submit Documentation Feedback Related Docs SPRU963—TMS320x2833x,2823x Boot ROM Reference Guide describes the purpose and features of the bootloader(factory-programmed boot-loading software)and provides examples of code.It alsodescribes other contents of the device on-chip boot ROM and identifies where all of the informationis located within that memory.SPRUFB7—TMS320x2833x,2823x Multichannel Buffered Serial Port(McBSP)Reference Guide describes the McBSP available on the2833x and2823x devices.The McBSPs allow directinterface between a DSP and other devices in a system.SPRUFB8—TMS320x2833x,2823x Direct Memory Access(DMA)Module Reference Guide describes the DMA on the2833x and2823x devices.SPRUG04—TMS320x2833x,2823x Enhanced Pulse Width Modulator(ePWM)Module Reference Guide describes the main areas of the enhanced pulse width modulator that include digital motorcontrol,switch mode power supply control,UPS(uninterruptible power supplies),and other forms ofpower conversion.SPRUG02—TMS320x2833x,2823x High-Resolution Pulse Width Modulator(HRPWM)Reference Guide describes the operation of the high-resolution extension to the pulse width modulator(HRPWM).SPRUFG4—TMS320x2833x,2823x Enhanced Capture(eCAP)Module Reference Guide describes the enhanced capture module.It includes the module description and registers.SPRUG05—TMS320x2833x,2823x Enhanced Quadrature Encoder Pulse(eQEP)Module Reference Guide describes the eQEP module,which is used for interfacing with a linear or rotaryincremental encoder to get position,direction,and speed information from a rotating machine inhigh-performance motion and position control systems.It includes the module description andregisters.SPRUEU1—TMS320x2833x,2823x Enhanced Controller Area Network(eCAN)Reference Guide describes the eCAN that uses established protocol to communicate serially with other controllers inelectrically noisy environments.SPRUFZ5—TMS320x2833x,2823x Serial Communications Interface(SCI)Reference Guide describes the SCI,which is a two-wire asynchronous serial port,commonly known as a UART.TheSCI modules support digital communications between the CPU and other asynchronous peripheralsthat use the standard non-return-to-zero(NRZ)format.SPRUEU3—TMS320x2833x,2823x DSC Serial Peripheral Interface(SPI)Reference Guide describes the SPI-a high-speed synchronous serial input/output(I/O)port-that allows a serial bitstream of programmed length(one to sixteen bits)to be shifted into and out of the device at aprogrammed bit-transfer rate.SPRUG03—TMS320x2833x,2823x Inter-Integrated Circuit(I2C)Module Reference Guide describes the features and operation of the inter-integrated circuit(I2C)module.Tools Guides—SPRU513—TMS320C28x Assembly Language Tools v5.0.0User's Guide describes the assembly language tools(assembler and other tools used to develop assembly language code),assemblerdirectives,macros,common object file format,and symbolic debugging directives for theTMS320C28x device.SPRU514—TMS320C28x Optimizing C/C++Compiler v5.0.0User's Guide describes the TMS320C28x™C/C++compiler.This compiler accepts ANSI standard C/C++source code andproduces TMS320DSP assembly language source code for the TMS320C28x device.SPRU608—TMS320C28x Instruction Set Simulator Technical Overview describes the simulator, available within the Code Composer Studio for TMS320C2000IDE,that simulates the instructionset of the C28x™core.SPRU625—TMS320C28x DSP/BIOS5.32Application Programming Interface(API)Reference Guide describes development using DSP/BIOS.7 SPRUFB8D–September2007–Revised April2011Read This First Submit Documentation FeedbackReference GuideSPRUFB8D–September2007–Revised April2011 TMS320x2833x Direct Memory Access(DMA)ModuleThe direct memory access(DMA)module provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU,thereby freeing up bandwidth for other system functions.Additionally,the DMA has the capability to orthogonally rearrange the data as it is transferred as well as“ping-pong”data between buffers.These features are useful for structuring data into blocks for optimal CPU processing.1IntroductionThe strength of a digital signal controller(DSC)is not measured purely in processor speed,but in total system capabilities.As a part of the equation,any time the CPU bandwidth for a given function can be reduced,the greater the system capabilities.Many times applications spend a significant amount of their bandwidth moving data,whether it is from off-chip memory to on-chip memory,or from a peripheral such as an analog-to-digital converter(ADC)to RAM,or even from one peripheral to another.Furthermore,many times this data comes in a format that is not conducive to the optimum processing powers of the CPU.The DMA module described in this reference guide has the ability to free up CPU bandwidth and rearrange the data into a pattern for more streamlined processing.The DMA module is an event-based machine,meaning it requires a peripheral interrupt trigger to start a DMA transfer.Although it can be made into a periodic time-driven machine by configuring a timer as the interrupt trigger source,there is no mechanism within the module itself to start memory transfersperiodically.The interrupt trigger source for each of the six DMA channels can be configured separately and each channel contains its own independent PIE interrupt to let the CPU know when a DMA transfers has either started or completed.Five of the six channels are exactly the same,while Channel1has one additional feature:the ability to be configured at a higher priority than the others.At the heart of the DMA is a state machine and tightly coupled address control logic.It is this address control logic that allows for rearrangement of the block of data during the transfer as well as the process of ping-ponging databetween buffers.Each of these features,along with others will be discussed in detail in this document.DMA Overview:•6channels with independent PIE interrupts•Peripheral interrupt trigger sources–ADC sequencer1and sequencer2–Multichannel Buffered Serial Port A and B(McBSP-A,McBSP-B)transmit and receive–XINT1-7and XINT13–CPU Timers–ePWM1-6ADCSOCA and ADSOCB signals–Software•Data sources/destinations:–L4-L716K x16SARAM–All XINTF zones–ADC memory bus mapped result registers–McBSP-A and McBSP-B transmit and receive buffers–ePWM1-6/HRPWM1-6Peripheral Frame3mapped registers•Word Size:16-bit or32-bit(McBSPs limited to16-bit)•Throughput:4cycles/word(5cycles/word for McBSP reads)8TMS320x2833x Direct Memory Access(DMA)Module SPRUFB8D–September2007–Revised April2011Submit Documentation Feedback Introduction NOTE:The ePWM/HRPWM are not present on all devices and/or revisions.See the TMS320x28xx,28xxx DSP Peripheral Reference Guide(SPRU566)for specifics.9 SPRUFB8D–September2007–Revised April2011TMS320x2833x Direct Memory Access(DMA)Module Submit Documentation FeedbackArchitecture 2Architecture2.1Block DiagramFigure1shows a device level block diagram of the DMA.Figure1.DMA Block DiagramA The ePWM/HRPWM registers must be remapped to PF3(through bit0of the MAPCNF register)before they can beaccessed by the DMA.The ePWM/HRPWM connection to DMA is not present in silicon revision0.2.2Peripheral Interrupt Event Trigger SourcesThe peripheral interrupt event trigger can be independently configured as one of eighteen differentsources for each of the six DMA channels.Included in these sources are8external interrupt signals which can be connected to most of the general-purpose input/output(GPIO)pins on the device.This addssignificant flexibility to the event trigger capabilities.A bit field called PERINTSEL in the MODE register of each channel is used to select that channels interrupt trigger source.An active peripheral interrupt trigger will be latched into the PERINTFLG bit of the CONTROL register,and if the respective interrupt and DMA channel is enabled(see the MODE.CHx[PERINTE]and CONTROL.CHx[RUNSTS]bits),it will be serviced by the DMA channel.Upon receipt of a peripheral interrupt event signal,the DMA will automatically send a clear signal to the interrupt source so that subsequent interrupt events will occur.Regardless of the value of the MODE.CHx[PERINTSEL]bit field,software can always force a trigger by using the CONTROL.CHx[PERINTFRC]bit.Likewise,software can always clear a pending DMA trigger using the CONTROL.CHx[PERINTCLR]bit.10TMS320x2833x Direct Memory Access(DMA)Module SPRUFB8D–September2007–Revised April2011Submit Documentation Feedback Architecture Once a particular interrupt trigger sets a channel’s PERINTFLG bit,the bit stays pending until the priority logic of the state machine starts the burst transfer for that channel.Once the burst transfer starts,the flag is cleared.If a new interrupt trigger is generated while a burst is in progress,the burst will complete before responding to the new interrupt trigger(after proper prioritization).If a third interrupt trigger occurs before the pending interrupt is serviced,an error flag is set in the CONTROL.CHx[OVRFLG]bit.If a peripheral interrupt trigger occurs at the same time as the latched flag is being cleared,the peripheral interrupttrigger has priority and the PERINTFLG will remain set.Figure2shows a diagram of the trigger select circuit.See the MODE.CHx[PERINTSEL]bit fielddescription for the complete list of peripheral interrupt trigger sources.11 SPRUFB8D–September2007–Revised April2011TMS320x2833x Direct Memory Access(DMA)Module Submit Documentation FeedbackNoneSEQ1INT SEQ2INT EPWM5SOCBEPWM6SOCA EPWM6SOCB...Architecture Figure 2.Peripheral Interrupt Trigger Input DiagramTable 1shows the interrupt trigger source options that are available for each channel.Table 1.Peripheral Interrupt Trigger Source OptionsPeripheralInterrupt Trigger Source CPUDMA Software bit (CHx.CONTROL.PERINTFRC)only ADCSequencer 1Interrupt Sequencer 2Interrupt External Interrupts External Interrupt 1External Interrupt 2External Interrupt 3External Interrupt 4External Interrupt 5External Interrupt 6External Interrupt 7External Interrupt 13CPU Timers Timer 0OverflowTimer 1OverflowTimer 2OverflowMcBSP-AMcBSP-A Transmit Buffer Empty McBSP-A Receive Buffer Full McBSP-BMcBSP-B Transmit Buffer Empty McBSP-B Receive Buffer Full ePWM1(1)ADC Start of Conversion A ADC Start of Conversion B ePWM2(1)ADC Start of Conversion AADC Start of Conversion BePWM3(1)ADC Start of Conversion A (1)The ePWM1-6are not present on all devices and/or revisions.Seethe TMS320x28xx,28xxx DSP Peripheral Reference Guide(SPRU566)for specifics.12TMS320x2833x Direct Memory Access (DMA)ModuleSPRUFB8D–September 2007–Revised April 2011Submit Documentation FeedbackSYSCLKAddr bus Data bus Generate address Pipeline Timing and ThroughputTable 1.Peripheral Interrupt Trigger Source Options(continued)PeripheralInterrupt Trigger Source ADC Start of Conversion B ePWM4(1)ADC Start of Conversion A ADC Start of Conversion B ePWM5(1)ADC Start of Conversion A ADC Start of Conversion B ePWM6(1)ADC Start of Conversion AADC Start of Conversion B2.3DMA BusThe DMA bus architecture consists of a 22-bit address bus,a 32-bit data read bus,and a 32-bit data write bus.Memories and register locations connected to the DMA bus are via interfaces that sometimes share resources with the CPU memory or peripheral bus.Arbitration rules are defined in Section 4.The following resources are connected to the DMA bus:•XINTF Zones 0,6&7•L4SARAM•L5SARAM•L6SARAM•L7SARAM•ADC Memory Mapped Result Registers•McBSP-A and McBSP-B Data Receive Registers (DRR2/DRR1)and Data Transmit Registers(DXR2/DXR1)•ePWM1-6/HRPWM1-6Register when mapped to Peripheral Frame 33Pipeline Timing and ThroughputThe DMA consists of a 4-stage pipeline as shown in Figure 3.The one exception to this is when a DMA channel is configured to have one of the McBSPs as its data source.A read of a McBSP DRR register stalls the DMA bus for one cycle during the read portion of the transfer,as shown in Figure 4.Figure 3.4-Stage Pipeline DMA Transfer13SPRUFB8D–September 2007–Revised April 2011TMS320x2833x Direct Memory Access (DMA)Module Submit Documentation FeedbackSYSCLKAddr bus Data bus Generate addressPipeline Timing and Throughput Figure 4.4-Stage Pipeline With One Read Stall (McBSP as source)14TMS320x2833x Direct Memory Access (DMA)Module SPRUFB8D–September 2007–Revised April 2011Submit Documentation Feedback CPU ArbitrationIn addition to the pipeline there are a few other behaviors of the DMA that affect it’s total throughput•A1-cycle delay is added at the beginning of each burst•A1-cycle delay is added when returning from a CH1high priority interrupt•32-bit transfers run at double the speed of a16-bit transfer(i.e.,it takes the same amount of time to transfer a32-bit word as it does a16-bit word)•Collisions with the CPU may add delay slots(see Section4)For example,to transfer12816-bit words from ADC to RAM a channel can be configured to transfer8 bursts of16words/burst.This will give:8bursts*[(4cycles/word*16words/burst)+1]=520cyclesIf instead the channel were configured to transfer the same amount of data32bits at a time(the word size is configured to32bits)the transfer would take:8bursts*[(4cycles/word*8words/burst)+1]=264cycles4CPU ArbitrationTypically,DMA activity is independent of the CPU activity.Under the circumstance where both the DMA and the CPU are attempting to access memory or a peripheral register within the same interfaceconcurrently,an arbitration procedure will occur.The one exception is with the memory mapped(PF0) ADC registers,which do not create a conflict when read by both the CPU and the DMA simultaneously, even if different addresses are accessed.Any combined accesses between the different interfaces,orwhere the CPU access is outside of the interface that the DMA is accessing do not create a conflict.The interfaces which internally contain conflicts are:•XINTF Memory Zones0,6and7•L4RAM•L5RAM•L6RAM•L7RAM•Peripheral Frame3(McBSP-A,McBSP-B,and ePWM1-6/HRPWM1-6)NOTE:The ePWM/HRPWM are not present on all devices and/or revisions.See the TMS320x28xx,28xxx DSP Peripheral Reference Guide(SPRU566)for specifics.4.1For the External Memory Interface(XINTF)Zones•If the CPU and the DMA attempt an access to any of the XINTF zones on the same cycle,the DMA is serviced first,followed by all the pending CPU accesses(in the proper priority order for CPU accesses: write→read→fetch).•If CPU accesses to an XINTF zone are pending or being processed by the XINTF and a DMA access to an XINTF zone is attempted,the DMA access is stalled until all CPU pending accesses arecompleted.For example,if a CPU write and read access is pending and a fetch is in progress,first the fetch is completed,then the CPU write is performed,then the CPU read is performed,and then theDMA access is performed.•There is a1cycle stall if simultaneous write accesses by the CPU and the DMA are attempted.If the DMA or CPU is used to write to the XINTF zones,then the write buffer of the XINTF can help toavoid CPU or DMA stalls.If the CPU or DMA are performing reads from XINTF,then significant stalls can occur.The only concern here is if the DMA is stalled and the DMA misses other higher priority DMAevents such as servicing the ADC which can generate data at a high rate.In such situations,the DMAshould not be used to transfer data on XINTF,if the stalls are too long that there is potential to miss other DMA events.15 SPRUFB8D–September2007–Revised April2011TMS320x2833x Direct Memory Access(DMA)Module Submit Documentation FeedbackChannel Priority The DMA does not support abort mechanisms for DMA reads from XINTF.If the DMA is performing an access to one of the XINTF zones and the DMA access is stalled(XREADY not responding)then the CPU can issue a HARDRESET that would abort the access.HARDRESET behaves like a System Reset on the DMA.Likewise,a HARDRESET needs to be applied to the XINTF hence releasing the peripheral from the struck ready condition.Any data that is write buffered or pending on the XINTF or DMA will be lost.4.2For All Other Peripherals/Memories•If the CPU and the DMA make an access to the same interface in the same cycle,the DMA has priority and the CPU is stalled.•If a CPU access to an interface is in progress and another CPU access to the same interface is pending,for example,the CPU is performing a write operation and a read operation from the CPU ispending,then a DMA access to that same interface has priority over the pending CPU access whenthe current CPU access completes.NOTE:If the CPU is performing a read-modify-write operation and the DMA performs a write to thesame location,the DMA write may be lost if the operation occurs in between the CPU readand the CPU write.For this reason,it is advised not to mix such CPU accesses with DMAaccesses to the same locations.In the case of RAM,a ping-pong scheme can be implemented to avoid the CPU and the DMA accessing the same RAM block concurrently,thus avoiding any stalls or corruption issues.5Channel PriorityTwo priority schemes exist when determining channel priority:Round-robin mode and Channel1high-priority mode.5.1Round-Robin ModeIn this mode,all channels have equal priority and each enabled channel is serviced in round-robin fashion as follows:CH1→CH2→CH3→CH4→CH5→CH6→CH1→CH2→…In the case above,after each channel has transferred a burst of words,the next channel is serviced.You can specify the size of the burst for each channel.Once CH6(or the last enabled channel)has beenserviced,and no other channels are pending,the round-robin state machine enters an idle state.From the idle state,channel1(if enabled)is always serviced first.However,if the DMA is currentlyprocessing another channel x,all other pending channels between x and the end of the round are serviced before CH1.It is in this sense that all the channels are of equal priority.For instance,take an example where CH1,CH4,and CH5are enabled in round-robin mode and CH4is currently being processed.Then CH1and CH5both receive an interrupt trigger from their respective peripherals before CH4completes.CH1and CH5are now both pending.When CH4completes its burst,CH5will be serviced next.Only after CH5completes will CH1be serviced.Upon completion of CH1,if there are no more channels pending,the round-robin state machine will enter an idle state.A more complicated example is shown below:•Assume all channels are enabled,and the DMA is in an idle state,•Initially a trigger occurs on CH1,CH3,and CH5on the same cycle,•When the CH1burst transfer starts,requests from CH3and CH5are pending,•Before completion of the CH1burst,the DMA receives a request from CH2.Now the pending requests are from CH2,CH3,and CH5,•After completing the CH1burst,CH2will be serviced since it is next in the round-robin scheme after CH1.•After the burst from CH2is finished,the CH3burst will be serviced,followed by CH5burst.•Now while the CH5burst is being serviced,the DMA receives a request from CH1,CH3,and CH6.16TMS320x2833x Direct Memory Access(DMA)Module SPRUFB8D–September2007–Revised April2011Submit Documentation Feedback。

TMS320x2833x,2823xDSC接口扩展(XINTF)

中原工学院毕业设计（论文）译文１毕业设计（论文）译文题目名称：TMS320x2833x,2823xDSC 接口扩展(XINTF)学院名称：电子信息学院班级：电气083班学号：200800494311学生姓名：霍兵龙指导教师：王耕2012年 1月中原工学院毕业设计（论文）译文TMS320x2833x,2823xDSC接口扩展(XINTF)参考指南文献编号:SPRU949DSeptember2007–Revised January 2010目录前言 (1)1 功能描述 (3)1.1 与TMS320x281x XINTF的区别 (4)1.2 与TMS320x2834x XINTF差异 (5)1.3访问XINTF空间 (5)1.4写操作紧跟读操作的流水线保护 (7)2 XINTF功能配置 (8)2.1 外部接口(XINTF)配置寄存器及时序寄存器的设置 (8)2.2 XINTF时钟 (9)2.3 写缓冲 (10)2.4 XINTF Zone访问的建立、激活和跟踪时序 (10)2.5 对每个区采样XREADY (11)2.6 储体转接 (12)3 外部DMA支持(XHOLD,XHOLDA) (15)4 建立，激活及跟踪状态的配置 (16)4.1忽略USEREADY信号 (16)4.2同步模式(USEREADY=1,READYMODE=0) (17)4.3异步模式(USEREADY=1,READYMODE=1) (17)5配置XBANK 周期 (20)6 XINTF 寄存器 (21)6.1 XINTF定时寄存器 (22)6.2 XINTF配置寄存器 (24)6.3 XBANK寄存器 (26)6.4 XREVISION寄存器 (27)6.5 XRESET寄存器 (27)7 信号说明 (28)8 波形 (28)附录A 修订历史记录 (32)图目录I中原工学院毕业设计（论文）译文图1、外部接口框图 (6)图2、访问流程图 (9)图3 、XTIMCLK和SYSCLKOUT之间的关系 (10)图4 XINTF 典型16位数据总线连接 (13)图5、XINTF 典型32位数据总线连接 (14)图6、XTIMING0/6/7寄存器分布 (22)图8、XBANK寄存器 (26)图9、XREVISION寄存器 (27)图10、XRESET寄存器 (27)图11、XTIMCLK和XCLKOUT模式的波形 (29)图12、通用读周期（X TIMCLK= SYSCLKOUT模式） (30)图13、通用读周期（XTIMCLK=½ SYSCLKOUT模式） (31)图14、通用的写周期（XTIMCLK= SYSCLKOUT模式） (32)表目录表1 16位模式性能 (14)表2 32位模式性能 (14)表3 依据XTIMCLK周期的持续脉冲 (16)表4、lead/Trail值与XTIMCLK/X2TIMING之间的关系 (18)表5 Active数值与XTIMCLK/X2TIMING方式之间的关系 (19)表6.有效XBANK配置 (21)表7 XINTF配置和控制寄存器映射 (22)表8 XTIMING0/6/7寄存器字段说明 (22)表7 XINTF配置寄存器(XINTCNF2) (24)表9、XINTF配置寄存器字段说明 (25)表10、XBANK寄存器说明 (26)表11、XREVISION寄存器说明 (27)表12、XRESET寄存器说明 (27)表13 、XINTF信号说明 (28)表14、修订 (32)II中原工学院毕业设计（论文）译文前言本文档介绍了在F2833x或F2823x设备中使用的外部接口（XINTF）。

TMS320x2833x Multichannel Buffered Serial Port (McBSP) Reference Guide第六章英文

SPI Operation Using the Clock Stop Mode This chapter explains how to use the McBSP in SPI mode.6.1 SPI Protocol (60)6.2 Clock Stop Mode (60)6.3 Bits Used to Enable and Configure the Clock Stop Mode (60)6.4 Clock Stop Mode Timing Diagrams (61)6.5 Procedure for Configuring a McBSP for SPI Operation (63)6.6 McBSP as the SPI Master (63)6.7 McBSP as an SPI Slave (65)6.1 SPI ProtocolThe SPI protocol is a master-slave configuration with one master device and one or more slave devices. The interface consists of the following four signals:1、Serial data input (also referred to as master in/slave out, or MISO)2、Serial data output (also referred to as master out/slave in, or MOSI)3、Shift-clock (also referred to as SCK)4、Slave-enable signal (also referred to as SS)A typical SPI interface with a single slave device is shown in Figure 6-1.Figure 6-1. Typical SPI InterfaceThe master device controls the flow of communication by providing shift-clock and slave-enable signals. The slave-enable signal is an optional active-low signal that enables the serial data input and output of the slave device (device not sending out the clock).In the absence of a dedicated slave-enable signal, communication between the master and slave is determined by the presence or absence of an active shift-clock. When the McBSP is operating in SPI master mode and the SS signal is not used by the slave SPI port, the slave device must remain enabled at all times, and multiple slaves cannot be used.6.2 Clock Stop ModeThe clock stop mode of the McBSP provides compatibility with the SPI protocol. When the McBSP is configured in clock stop mode, the transmitter and receiver areinternally synchronized so that the McBSP functions as an SPI master or slave device. The transmit clock signal (CLKX) corresponds to the serial clock signal (SCK) of the SPI protocol, while the transmit frame-synchronization signal (FSX) is used as the slave-enable signal (SS).The receive clock signal (MCLKR) and receive frame-synchronization signal (FSR) are not used in the clock stop mode because these signals are internally connected to their transmit counterparts, CLKX and FSX.6.3 Bits Used to Enable and Configure the Clock Stop ModeThe bits required to configure the McBSP as an SPI device are introduced in Table 6-1. Table 6-2 shows how the various combinations of the CLKSTP bit and the polarity bits CLKXP and CLKRP create four possible clock stop mode configurations. The timing diagrams in Section 6.4 show the effects of CLKSTP, CLKXP, and CLKRP.Table 6-1. Bits Used to Enable and Configure the Clock Stop ModeTable 6-2. Effects of CLKSTP, CLKXP, and CLKRP on the Clock Scheme6.4 Clock Stop Mode Timing DiagramsThe timing diagrams for the four possible clock stop mode configurations are shown here. Notice that the frame-synchronization signal used in clock stop mode is active throughout the entire transmission as a slave-enable signal. Although the timing diagrams show 8-bit transfers, the packet length can be set to 8, 12, 16, 20, 24, or 32 bits per packet. The receive packet length is selected with the RWDLEN1 bits of RCR1, and the transmit packet length is selected with the XWDLEN1 bits of XCR1. For clock stop mode, the values of RWDLEN1 and XWDLEN1 must be the same because the McBSP transmit and receive circuits are synchronized to a single clock.Note: Even if multiple words are consecutively transferred, the CLKX signal is always stopped and the FSX signal returns to the inactive state after a packet transfer.When consecutive packet transfers are performed, this leads to a minimum idle timeof two bit-periods between each packet transfer.Figure 6-2. SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP =0, and CLKRP = 0A If the McBSP is the SPI master (CLKXM = 1), MOSI = DX. If the McBSP is the SPI slave (CLKXM = 0), MOSI = DR.B If the McBSP is the SPI master (CLKXM = 1), MISO = DR. If the McBSP is the SPI slave (CLKXM = 0), MISO = DX.Figure 6-3. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 0, CLKRP = 1A If the McBSP is the SPI master (CLKXM = 1), MOSI = DX. If the McBSP is the SPI slave (CLKXM = 0), MOSI = DR.B If the McBSP is the SPI master (CLKXM = 1), MISO = DR. If the McBSP is the SPI slave (CLKXM = 0), MISO = DX.Figure 6-4. SPI Transfer With CLKSTP = 10b (No Clock Delay), CLKXP = 1, and CLKRP = 0A If the McBSP is the SPI master (CLKXM = 1), MOSI = DX. If the McBSP is the SPI slave (CLKXM = 0), MOSI = DR.B If the McBSP is the SPI master (CLKXM = 1), MISO = DR. If the McBSP is the SPI slave (CLKXM = 0), MISO = DX.Figure 6-5. SPI Transfer With CLKSTP = 11b (Clock Delay), CLKXP = 1, CLKRP = 1A If the McBSP is the SPI master (CLKXM = 1), MOSI=DX. If the McBSP is the SPI slave (CLKXM = 0), MOSI = DR.B If the McBSP is the SPI master (CLKXM = 1), MISO=DR. If the McBSP is the SPI slave (CLKXM = 0), MISO = DX.6.5 Procedure for Configuring a McBSP for SPI OperationTo configure the McBSP for SPI master or slave operation:Step 1. Place the transmitter and receiver in reset.Clear the transmitter reset bit (XRST = 0) in SPCR2 to reset the transmitter. Clear the receiver reset bit (RRST = 0) in SPCR1 to reset the receiver.Step 2. Place the sample rate generator in reset.Clear the sample rate generator reset bit (GRST = 0) in SPCR2 to reset the sample rate generator.Step 3. Program registers that affect SPI operation.Program the appropriate McBSP registers to configure the McBSP for proper operation as an SPI master or an SPI slave. For a list of important bits settings, see one of the following topics:1、McBSP as the SPI Master ( Section 6.6)2、McBSP as an SPI Slave ( Section 6.7)Step 4. Enable the sample rate generator.To release the sample rate generator from reset, set the sample rate generatorreset bit (GRST = 1) in SPCR2. Make sure that during the write to SPCR2, you only modify GRST. Otherwise, you modify the McBSP configuration you selected in the previous step.Step 5. Enable the transmitter and receiver.After the sample rate generator is released from reset, wait two sample rate generator clock periods for the McBSP logic to stabilize. If the CPU services the McBSP transmit and receive buffers, then you can immediately enable the transmitter (XRST = 1 in SPCR2) and enable the receiver (RRST = 1 in SPCR1). If the DMA controller services the McBSP transmit and receive buffers, then you must first configure the DMA controller (this includes enabling the channels that service the McBSP buffers). When the DMA controller is ready, make XRST = 1 and RRST = 1. In either case, make sure you only change XRST and RRST when you write to SPCR2 and SPCR1. Otherwise, you modify the bit settings you selected earlier in this procedure. After the transmitter and receiver are released from reset, wait two sample rate generator clock periods for the McBSP logic to stabilize.Step 6. If necessary, enable the frame-synchronization logic of the sample rate generator.After the required data acquisition setup is done (DXR[1,2] is loaded with data), set FRST = 1 if an internally generated frame-synchronization pulse is required (that is, if the McBSP is the SPI master).6.6 McBSP as the SPI MasterAn SPI interface with the McBSP used as the master is shown in Figure 6-6. When the McBSP is configured as a master, the transmit output signal (DX) is used as the MOSI signal of the SPI protocol and the receive input signal (DR) is used as the MISO signal.The register bit values required to configure the McBSP as a master are listed in Table 6-3. After the table are more details about the configuration requirements.Figure 6-6. SPI Interface with McBSP Used as MasterTable 6-3. Bit Values Required to Configure the McBSP as an SPI MasterWhen the McBSP functions as the SPI master, it controls the transmission of data by producing the serial clock signal. The clock signal on the MCLKX pin is enabled only during packet transfers. When packets are not being transferred, the MCLKX pin remains high or low depending on the polarity used.For SPI master operation, the MCLKX pin must be configured as an output. The sample rate generator is then used to derive the CLKX signal from the CPU clock. The clock stop mode internally connects the MCLKX pin to the MCLKR signal so that no external signal connection is required on the MCLKR pin and both the transmit and receive circuits are clocked by the master clock (CLKX).The data delay parameters of the McBSP (XDATDLY and RDATDLY) must be set to 1 for proper SPI master operation. A data delay value of 0 or 2 is undefined in the clock stop mode.The McBSP can also provide a slave-enable signal (SS_) on the FSX pin. If a slave-enable signal is required, the FSX pin must be configured as an output and the transmitter must be configured so that a frame-synchronization pulse is generated automatically each time a packet is transmitted (FSGM = 0). The polarity of the FSX pin is programmable high or low; however, in most cases the pin must be configured active low.When the McBSP is configured as described for SPI-master operation, the bit fields for frame-synchronization pulse width (FWID) and frame-synchronization period (FPER) are overridden, and custom frame-synchronization waveforms are not allowed. To see the resulting waveform produced on the FSX pin, see the timing diagrams in Section 6.4. The signal becomes active before the first bit of a packet transfer, and remains active until the last bit of the packet is transferred. After the packet transfer is complete, the FSX signal returns to the inactive state.6.7 McBSP as an SPI SlaveAn SPI interface with the McBSP used as a slave is shown in Figure 6-7. When the McBSP is configured as a slave, DX is used as the MISO signal and DR is used as the MOSI signal.The register bit values required to configure the McBSP as a slave are listed in Table 6-4. Following the table are more details about configuration requirements.Figure 6-7. SPI Interface With McBSP Used as SlaveTable 6-4. Bit Values Required to Configure the McBSP as an SPI SlaveWhen the McBSP is used as an SPI slave, the master clock and slave-enable signals are generated externally by a master device. Accordingly, the CLKX and FSX pins must be configured as inputs. The MCLKX pin is internally connected to the MCLKR signal, so that both the transmit and receive circuits of the McBSP are clocked by the external master clock. The FSX pin is also internally connected to the FSR signal, and no external signal connections are required on the MCLKR and FSR pins.Although the CLKX signal is generated externally by the master and is asynchronous to the McBSP, the sample rate generator of the McBSP must be enabled for proper SPI slave operation. The sample rate generator must be programmed to its maximum rate of half the CPU clock rate. The internal sample rate clock is then used to synchronize the McBSP logic to the external master clock and slave-enable signals.The McBSP requires an active edge of the slave-enable signal on the FSX input for each transfer. This means that the master device must assert the slave-enable signal at the beginning of each transfer, and deassert the signal after the completion of each packet transfer; the slave-enable signal cannot remain active between transfers. Unlike the standard SPI, this pin cannot be tied low all the time.The data delay parameters of the McBSP must be set to 0 for proper SPI slave operation. A value of 1 or 2 is undefined in the clock stop mode.。

TMS320x28x, 28xxx Serial Peripheral Interface (SPI) Reference Guide (Rev. D)

Mailing Address:
Texas Instruments Post Office Box 655303 Dallas, Texas 75265
Copyright 2006, Texas Instruments Incorporated
Preface
Read This First
About This Manual
This guide describes how the serial peripheral interface works on the TMS320x28xx and TMS320x28xxx DSPs.
Related Documentation From Texas Instruments
The following books describe the TMS320x281x and related support tools that are available on the TI website. TMS320F2809, F2808, F2806, F2802, F2801, F2801x UCD9501, C2802, C2801 DSPs (literature number SPRS230) data sheet contains the pinout, signal descriptions, as well as electrical and timing specifications for the F280x devices. TMS320F2810, TMS320F2811, TMS320F2812, TMS320C2810, TMS320C2811, and TMS320C2812 Digital Signal Processors (literature number SPRS174) data sheet contains the electrical and timing specifications for these devices, as well as signal descriptions and pinouts for all of the available packages. TMS320R2811 and TMS320R2812 Digital Signal Processors (literature number SPRS257) data sheet contains the electrical and timing specifications for these devices, as well as signal descriptions and pinouts for all of the available packages. TMS320C28x DSP CPU and Instruction Set Reference Guide (literature number SPRU430) describes the central processing unit (CPU) and the assembly language instructions of the TMS320C28x fixed-point digital signal processors (DSPs). It also describes emulation features available on these DSPs. TMS320x280x 2801x, 2804x Analog-to-Digital Converter (ADC) Reference Guide (literature number SPRU716) describes the ADC module. The module is a 12−bit pipelined ADC. The analog circuits of this converter, referred to as the core in this document, include the front-end analog multiplexers (MUXs), sample−and−hold (S/H) circuits, the conversion

TMS320x28xx, 28xxx DSP Peripherals Reference Guide

TMS320x28xx,28xxx DSP Peripheral Reference GuideLiterature Number:SPRU566IJune2003–Revised May20092SPRU566I–June2003–Revised May2009Submit Documentation Feedback1Abbreviations (5)2Peripherals Available Per Device (7)3Peripheral Descriptions (10)3.1System Control and Interrupts (10)3.2External Interface(XINTF) (11)3.3Enhanced Controller Area Network(eCAN) (11)3.4Event Manager(EV) (12)3.5Analog Modules (12)3.6Multichannel Buffered Serial Port(McBSP) (13)3.7Serial Communications Interface(SCI) (13)3.8Serial Peripheral Interface(SPI) (14)3.9Boot ROM (14)3.10Inter-Integrated Circuit(I2C)Module (14)3.11Enhanced Quadrature Encoder Pulse(eQEP)Module (15)3.12Enhanced Capture(eCAP)Module (15)3.13Enhanced Pulse Width Modulator(ePWM)Module (16)3.14High-Resolution Pulse Width Modulator(HRPWM)Module (17)3.15Direct Memory Access(DMA) (18)3.16Local Interconnect Network(LIN) (18)3.17Control Law Accelerator(CLA) (18)Appendix A Revision History (19)A.1Changes Made in This Revision (19)SPRU566I–June2003–Revised May2009Table of Contents3 Submit Documentation FeedbackList of Tables1Abbreviation Matrix (5)2TMS320x281x Peripheral Selection Guide (7)3TMS320x280x,TMS320x2801x Peripheral Selection Guide (7)4TMS320x2804x Peripheral Selection Guide (8)5TMS320F2833x,TMS320F2823x Peripheral Selection Guide (8)6TMS320x2834x Peripheral Selection Guide (9)7TMS320F2802x Peripheral Selection Guide (9)8TMS320F2803x Peripheral Selection Guide (9)9External Interface(XINTF)Module Types (11)10Enhanced Controller Area Network(eCAN)Module Types (11)11Event Manager(EV)Module Types (12)12Analog Digital Controller(ADC)Module Types (12)13Comparator Module Types (13)14Multichannel Buffered Serial Port(McBSP)Module Types (13)15Serial Communications Interface(SCI)Module Type (13)16Serial Peripheral Interface(SPI)Module Type Description (14)17Inter-Integrated Circuit(I2C)Module Type Description (15)18Enhanced Quadrature Encoder Pulse(eQEP)Module Type Description (15)19Enhanced Capture(eCAP)Module Types (16)20Enhanced Pulse Width Modulator(ePWM)Module Types (17)21High-Resolution Pulse Width Modulator(HRPWM)Module Types (17)22Direct Memory Access(DMA)Module Types (18)23Local Interconnect Network(LIN)Module Types (18)24Control Law Accelerator(CLA)Module Types (18)List of Tables4SPRU566I–June2003–Revised May2009Submit Documentation Feedback1AbbreviationsReference GuideSPRU566I–June 2003–Revised May 2009This overview guide describes all the peripherals available for TMS320x28xx and TMS320x28xxx devices.Section 2shows the peripherals used by each device.Section 3provides descriptions of the peripherals.the peripheral guide by clicking on number,which is linked to the portable document format (pdf)file.Throughout this document and other peripheral guides,the following abbreviations are used for a series of 28x microcontrollers:•TMS320x28xx refers to TMS320x281x and TMS320x280x devices•TMS320x28xxx refers to TMS320x2801x,TMS320x2804x,TMS320x2833x,TMS320x2834x,TMS320x2802x,and TMS320x2803x devices.Specific device abbreviations are listed in Table 1.Table 1.Abbreviation MatrixDevice AbbreviationGroup Family Device (1)UsedAbbreviationTMS320x281xTMS320F2810,TMS320C2810,SM320F2810-EP (2)2810281xTMS320F2811,TMS320C2811,TMS320R2811,SM320F2811-EP (2)2811TMS320F2812,TMS320C2812,TMS320R2812,SM320F2812-EP (2)2812TMS320x280xTMS320F2801,TMS320C28012801280xTMS320F2802,TMS320C28022802TMS320F28062806TMS320F2808,SM320F2808-EP (2)2808TMS320F28092809TMS320x2801x TMS320F28015280152801x TMS320F2801628016TMS320x2804x TMS320F28044280442804x TMS320F2833xTMS320F28335283352833xTMS320F2833428334TMS320F2833228332TMS320F2823xTMS320F28235282352823xTMS320F2823428234TMS320F2823228232(1)Where F precedes the device abbreviation,it stands for Flash memory;C stands for RAM.(2)Military device that may be abbreviated differently elsewhere;the abbreviations shown are relevant to this document and peripheral selection itary devices in this document all begin with a prefix of SM.SPRU566I–June 2003–Revised May 200928x DSP Peripherals 5Submit Documentation FeedbackAbbreviations Table1.Abbreviation Matrix(continued)Device Abbreviation Group Family Device(1)Used Abbreviation TMS320x2834x TMS320C28346283462834xTMS320C2834528345TMS320C2834428344TMS320C2834328343TMS320C2834228342TMS320C2834128342TMS320x2802x TMS320F28020280202802xTMS320F2802128021TMS320F2802228022TMS320F2802328023TMS320F2802628026TMS320F2802728027TMS320x2803x TMS320F28035280352803xTMS320F2803428034TMS320F2803328033TMS320F2803228032 28x DSP Peripherals6SPRU566I–June2003–Revised May2009Submit Documentation Feedback Peripherals Available Per Device 2Peripherals Available Per DeviceTable2through Table7show the peripherals that are available for each of the28xx,28xxx devices.Theto the document that can be downloaded.Table2.TMS320x281x Peripheral Selection Guide(1)TMS320x281x External Interface(XINTF)0XTMS320x281x Enhanced Controller Area Network(eCAN)0X XTMS320x281x Event Manager(EV)0X XTMS320x281x Analog-to-Digital Converter(ADC)0X XTMS320x281x Multichannel Buffered Serial Port(McBSP)0X XTMS320x281x Serial Communications Interface(SCI)0X XTMS320x281x Serial Peripheral Interface(SPI)0X X(1)A type change represents a major functional feature difference in a peripheral module.Within a peripheral type,there may beminor differences between devices which do not affect the basic functionality of the module.These device-specific differencesare listed in Section3and in the peripheral reference guides.Table3.TMS320x280x,TMS320x2801x Peripheral Selection Guide Peripheral Lit.No.Type(1)280128016280152802,2806,2808,2809 TMS320x280x,2801x,2804x System Control and Interrupts-X X XTMS320x280x,2801x DSP Enhanced Controller Area Network(eCAN)0X XUser's GuideTMS320x280x,2801x,2804x Analog-to-Digital Converter(ADC)1X X XTMS320x280x,2801x,2804x Serial Communications Interface(SCI)0X X XTMS320x280x,2801x,2804x Serial Peripheral Interface(SPI)0X X XTMS320x280x,2801x,2804x Boot ROM-X X XTMS320x280x,2801x,2804x Enhanced Quadrature Encoder Pulse0X(eQEP)TMS320x280x,2801x,2804x Enhanced Pulse Width Modulator0X X XModule(ePWM)TMS320x280x,2801x,2804x Enhanced Capture(eCAP)Module0X X XTMS320x280x,2801x,2804x Inter-Integrated Circuit(I2C)0X X XTMS320x280x,2801x,2804x High-Resolution Pulse-Width Modulator0X X X(HRPWM)(1)A type change represents a major functional feature difference in a peripheral module.Within a peripheral type,there may beminor differences between devices which do not affect the basic functionality of the module.These device-specific differencesare listed in Section3and in the peripheral reference guides.SPRU566I–June2003–Revised May200928x DSP Peripherals7 Submit Documentation FeedbackPeripherals Available Per Device Table4.TMS320x2804x Peripheral Selection Guide(1)TMS320x280x,2801x,2804x Analog-to-Digital Converter(ADC)1XTMS320x280x,2801x,2804x Serial Communications Interface(SCI)0XTMS320x280x,2801x,2804x Serial Peripheral Interface(SPI)0XTMS320x280x,2801x,2804x Boot ROM-XTMS320x280x,2801x,2804x Enhanced Pulse Width Modulator Module(ePWM)0XTMS320x280x,2801x,2804x Inter-Integrated Circuit(I2C)0Xminor differences between devices which do not affect the basic functionality of the module.These device-specific differencesare listed in Section3and in the peripheral reference guides.Table5.TMS320F2833x,TMS320F2823x Peripheral Selection Guide Peripheral Lit.No.Type(1)28335,28334,28332,28235,28234,28232 TMS320F2833x,2823x System Control and Interrupts-XTMS320F2833x,2823x External Interface(XINTF)1XTMS320F2833x,2823x Enhanced Controller Area Network(eCAN)0XTMS320F2833x,2823x Analog-to-Digital Converter(ADC)2XTMS320F2833x,2823x Multichannel Buffered Serial Port(McBSP)1XTMS320F2833x,2823x Serial Communications Interface(SCI)0XTMS320F2833x,2823x Serial Peripheral Interface(SPI)0XTMS320F2833x,2823x Boot ROM-XTMS320F2833x,2823x Enhanced Quadrature Encoder Pulse(eQEP)0XTMS320F2833x,2823x Enhanced Pulse Width Modulator Module(ePWM)0XTMS320F2833x,2823x Enhanced Capture(eCAP)Module0XTMS320F2833x,2823x Inter-Integrated Circuit(I2C)0XTMS320F2833x,2823x High-Resolution Pulse-Width Modulator(HRPWM)0Xminor differences between devices which do not affect the basic functionality of the module.These device-specific differencesare listed in Section3and in the peripheral reference guides.28x DSP Peripherals8SPRU566I–June2003–Revised May2009Submit Documentation Feedback Peripherals Available Per DeviceTable6.TMS320x2834x Peripheral Selection GuidePERIPHERAL GUIDE Lit.No.TYPE(1)28346,28345,28344,28343,TMS320x2834x Delfino External Interface(XINTF)1XTMS320x2834x Delfino Enhanced Controller Area Network(eCAN)0XTMS320x2834x Delfino Multichannel Buffered Serial Port(McBSP)1XTMS320x2834x Delfino Serial Communications Interface(SCI)0XTMS320x2834x Delfino Serial Peripheral Interface(SPI)0XTMS320x2834x Delfino Boot ROM-XTMS320x2834x Delfino Enhanced Quadrature Encoder Pulse(eQEP)0XTMS320x2834x Delfino Enhanced Pulse Width Modulator Module(ePWM)0XTMS320x2834x Delfino Enhanced Capture(eCAP)Module0XTMS320x2834x Delfino Inter-Integrated Circuit(I2C)0XTMS320x2834x Delfino High-Resolution Pulse-Width Modulator(HRPWM)0Xminor differences between devices that do not affect the basic functionality of the module.These device-specific differences are listed in Section3and in the peripheral reference guides.Table7.TMS320F2802x Peripheral Selection GuidePeripheral Lit.No.Type(1)28027,28021,28026,2802028023,28022 TMS320x2802x Piccolo System Control and Interrupts-X XTMS320x2802x,2803x Piccolo Analog-to-Digital Converter(ADC)and Comparator3/0(2)X XTMS320x2802x,2803x Piccolo Serial Communications Interface(SCI)0X XTMS320x2802x,2803x Piccolo Serial Peripheral Interface(SPI)1X XTMS320x2802x Piccolo Boot ROM-X XTMS320x2802x,2803x Piccolo Enhanced Pulse Width Modulator Module(ePWM)1X XTMS320x2802x,2803x Piccolo Enhanced Capture Module(eCAP)0X XTMS320x2802x,2803x Piccolo Inter-Integrated Circuit(I2C)0X Xminor differences between devices that do not affect the basic functionality of the module.These device-specific differences are listed in Section3and in the peripheral reference guides.(2)The is Type3and the comparator module is Type0.See Section3.5for more details.Table8.TMS320F2803x Peripheral Selection GuidePeripheral Lit.No.Type(1)28035,28034,2803328032 TMS320x2803x Piccolo System Control and Interrupts-x xTMS320x2803x Piccolo Enhanced Controller Area Network(eCAN)0x xTMS320x2802x,2803x Piccolo Analog-to-Digital Converter(ADC)and Comparator3/0(2)x xTMS320x2802x,2803x Piccolo Serial Communications Interface(SCI)0x xTMS320x2802x,2803x Serial Peripheral Interface(SPI)1x xTMS320x2803x Piccolo Boot ROM-x x(1)A type change represents a major functional feature difference in a peripheral module.Within a peripheral type,there may beminor differences between devices that do not affect the basic functionality of the module.These device-specific differences are listed in the peripheral reference guides.(2)The ADC module is Type3and the comparator module is Type0.SPRU566I–June2003–Revised May200928x DSP Peripherals9 Submit Documentation Feedback3Peripheral Descriptions3.1System Control and InterruptsPeripheral Descriptions Table 8.TMS320F2803x Peripheral Selection Guide (continued)PeripheralLit.No.Type (1)28035,28034,TMS320x2802x,2803x Piccolo Enhanced Capture Module (eCAP)0x x TMS320x2802x,2803x Piccolo Inter-Integrated Circuit (I2C)0x x TMS320x2802x,2803x High-Resolution Pulse-Width Modulator (HRPWM)1x xTMS320x2803x Piccolo Control Law Accelerator (CLA)0x Brief descriptions of the peripherals are included in the following sections.The device-specific guides are:•TMS320x281x System Control and Interrupts Reference Guide •TMS320x280x,2801x,and 2804x System Control and Interrupts Reference Guide •TMS320x2833x System Control and Interrupts Reference Guide •TMS320x2834x Delfino System Control and Interrupts Reference Guide •TMS320x2802x Piccolo System Control and Interrupts Reference Guide •TMS320x2803x Piccolo System Control and Interrupts Reference Guide These guides include information on the following modules:•Memory,including Flash and OTP configuration •Code security module (CSM)Security is defined with respect to the access of the on-chip program memory and prevents unauthorized copying of proprietary code.The code security module (CSM)blocks access to several on-chip program memory blocks.•Clocking and Low-Power ModesThe clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when a peripheral is not in use.Additionally,the system clock to the serial ports and the event managers,CAP and QEP blocks can be scaled relative to the CPU clock.This enables the timing of peripherals to be decoupled from increasing CPU clock speeds.•32-bit CPU-TimersCPU-Timers 0,1,and 2are identical 32-bit timers with presettable periods and with 16-bit clock prescaling.The timers have a 32-bit count down register,which generates an interrupt when the counter reaches zero.The counter is decremented at the CPU clock speed divided by the prescale value setting.When the counter reaches zero,it is automatically reloaded with a 32-bit period value.CPU-Timers 1and 2are reserved for Real-Time OS (RTOS)applications.CPU-Timer 2is connected to INT14of the CPU.CPU-Timer 1can be connected to INT13of the CPU.CPU-Timer 0is for general use and is connected to the PIE block.•Watchdog TimerThe 28x devices support a watchdog timer.The user software must regularly reset the watchdog counter within a certain time frame;otherwise,the watchdog generates a reset to the processor.The watchdog can be disabled if necessary.•General-purpose inputs/outputs (GPIO)Most of the peripheral signals are multiplexed with general-purpose I/O (GPIO)signals.This enables you to use a pin as GPIO if the peripheral signal or function is not used.On reset,all GPIO pins are configured as inputs.You can then individually program each pin for GPIO mode or peripheral signal mode.For specific inputs,you can also select the number of input qualification cycles to filter unwanted noise glitches.1028x DSP PeripheralsSPRU566I–June 2003–Revised May 2009Submit Documentation Feedback3.2External Interface (XINTF)3.3Enhanced Controller Area Network (eCAN) Peripheral Descriptions•Peripheral framesThe 28x devices contain three peripheral register spaces.Some registers within these frames can be protected from CPU writes by the EALLOW protection mechanism.•Peripheral interrupt expansion (PIE)The PIE block multiplexes numerous interrupt sources into a smaller set of interrupt inputs.The interrupts are grouped into blocks of eight and each group is fed into one of 12CPU interrupt lines (INT1to INT12).Each of the 96interrupts is supported by its own vector stored in a dedicated RAM block that can be overwritten by the user.The vector is automatically fetched by the CPU on servicing the interrupt.It takes nine CPU clock cycles to fetch the vector and save critical CPU registers.Therefore,the CPU can respond quickly to interrupt events.Prioritization of interrupts is controlled in hardware and software.Each individual interrupt can be enabled/disabled within the PIE block.•External InterruptsThe XINTF guides are:•TMS320x281x External Interface (XINTF)Reference Guide•TMS320F2833x,2823xExternal Interface (XINTF)Reference Guide •TMS320x2834x Delfino External Interface (XINTF)Reference Guide The external interface (XINTF)is an asynchronous bus that is used to interface to external devices and memory.Table 9lists the differences between XINTF types,including device-specific differences within each type.Table 9.External Interface (XINTF)Module TypesType DescriptionDevices Covered Device-Specific Options0External Interface with x16Data Bus2810,2811,2812-1External Interface with x16or x32Data Bus 28335,28334,28332,28235,28234,-28232,28346,28345,28344,28343,28342,28341This is the enhanced version of the CAN peripheral.It supports 32mailboxes,time stamping of messages,and is CAN 2.0B-compliant.The eCAN guides are:•TMS320x281x DSP Enhanced Controller Area Network (eCAN)Reference Guide •TMS320x280x,2801x DSP Enhanced Controller Area Network (eCAN)Reference Guide •TMS320x2833x/2823x DSP Enhanced Controller Area Network (eCAN)Reference Guide •TMS320x2834x Delfino Enhanced Controller Area Network (eCAN)Reference Guide •TMS320x2803x Piccolo Enhanced Controller Area Network (eCAN)Reference Guide Table 10lists the differences between eCAN types,including device-specific differences within each type.Table 10.Enhanced Controller Area Network (eCAN)Module TypesModule DescriptionDevices CoveredDevice-Specific OptionsType 0Original eCAN Module Type2810,2811,2812,2801,2802,2806,2808,2809,CAN module clock =SYSCLK 2801628335,28334,28332,28235,28234,28232,CAN module clock =SYSCLK/228035,28034,28033,2803228346,28345,28344,28343,28342,28341CAN module clock =SYSCLK/4SPRU566I–June 2003–Revised May 200928x DSP Peripherals 11Submit Documentation Feedback3.4Event Manager (EV)3.5Analog Modules3.5.1Analog-to-Digital Converter (ADC)3.5.2Comparator Module (COMP)Peripheral Descriptions The event manager module includes general-purpose timers,full-compare/pulse-width modulation (PWM)units,capture inputs (CAP)and quadrature-encoder pulse (QEP)circuits.Two such event managers are provided,which enable two three-phase motors to be driven or four two-phase motors.The event managers on the F281x are compatible to the event managers on the 240x devices (with some minor enhancements).The EV guide is:•TMS320x281x Event Manager Reference GuideTable11lists the differences between EV types,including device-specific differences within each type.Table 11.Event Manager (EV)Module TypesType DescriptionDevices Covered Device-Specific Options 0Original EV Module Type2810,2811,2812-The analog-to-digital converter (ADC)module and comparator module descriptions are in this section.The device-specific ADC guides are:•TMS320x281x Analog-to-Digital Converter (ADC)Reference Guide •TMS320x280x 2801x,2804x Analog-to-Digital Converter (ADC)Module Reference Guide •TMS320x2833x,2823x Analog-to-Digital Controller (ADC)Module Reference Guide •2803x Piccolo Analog-to-Digital Converter (ADC)and Comparator Reference Guide The ADC block is a 12-bit converter,single ended,16-channels.It contains two sample-and-hold units for simultaneous sampling.Table 12lists the differences between ADC types,including device-specific differences within each type.Table 12.Analog Digital Controller (ADC)Module TypesType DescriptionDevices Covered Device-SpecificOptions0Original ADC Module Type2810,2811,2812–1Added Offset Trim and Reference Select registers 2801,2802,2806,2808,2809,28015,–28016,280442Added Internal/External Trim registers(OTP trim)28335,28334,28332,28235,28234,–282323Different control register interface,converts from 028027,28026,28023,28022,28021,–to 3.3V fixed scale range,supports ratiometric 28020,28035,28034,28033,28032VREFHI/VREFLO referencesThe device-specific comparator guides are:•2803x Piccolo Analog-to-Digital Converter (ADC)and Comparator Reference Guide The comparator module includes a 10-bit reference and can be routed to directly control ePWM outputs.Table 13lists the differences between comparator types,including device-specific differences within each 28x DSP Peripherals12SPRU566I–June 2003–Revised May 2009Submit Documentation Feedback3.6Multichannel Buffered Serial Port (McBSP)3.7Serial Communications Interface (SCI) Peripheral DescriptionsTable parator Module TypesType DescriptionDevices CoveredDevice-Specific OptionsOriginal Comparator Module Type28027,28026,28023,28022,28021,28020,–28035,28034,28033,28032The device-specific McBSP guides are:•TMS320x281x Multichannel Buffered Serial Port (McBSP)Reference Guide•TMS320x2833xMultichannel Buffered Serial Port (McBSP)Reference Guide •TMS320x2834x Delfino Multichannel Buffered Serial Port (McBSP)Reference Guide The McBSP is used to connect to E1/T1lines,phone-quality codecs for modem applications orhigh-quality stereo-quality Audio DAC devices.The McBSP receive and transmit registers are supported by a 16-level FIFO.This significantly reduces the overhead for servicing this peripheral.Table 14lists the differences between ADC types,including device-specific differences within each type.Table 14.Multichannel Buffered Serial Port (McBSP)Module TypesType DescriptionDevices Covered Device-SpecificOptions0Original McBSP Module Type2810,2811,2812-1Removed FIFO to allow interconnect with DMA module.28335,28334,28332,28235,-Removed FIFO-related registers (MFFTX,MFFRX,MFFCT,28234,28232,28346,28345,MFFST)28344,28343,28342,28341The SCI is a two-wire asynchronous serial port,commonly known as UART.The SCI supports a receive and transmit FIFO for reducing servicing overhead.The SCI guides are:•TMS320x281x Serial Communications Interface (SCI)Reference Guide •TMS320x280x,2801x,28044Serial Communications Interface (SCI)Reference Guide •TMS320x2833x,2823x Serial Communications Interface (SCI)Reference Guide •TMS320x2834x Delfino Serial Communications Interface (SCI)Reference Guide •TMS320x2802x,2803x Piccolo Serial Communications Interface (SCI)Reference Guide Table 15lists the differences between SCI types,including device-specific differences within each type.Table 15.Serial Communications Interface (SCI)Module TypeType DescriptionDevices CoveredDevice-Specific OptionsOriginal SCI Module Type2810,2811,2812,2801,2802,2806,2808,2809,16-level FIFO28015,28016,28044,28335,28334,28332,28235,28234,28232,28346,28345,28344,28343,28342,28341128027,28026,28023,28022,28021,28020,4-level FIFO28035,28034,28033,28032SPRU566I–June 2003–Revised May 200928x DSP Peripherals 13Submit Documentation Feedback3.8Serial Peripheral Interface (SPI)3.9Boot ROM3.10Inter-Integrated Circuit (I2C)ModulePeripheral Descriptions The SPI is a high-speed,synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits)to be shifted into and out of the device at a programmable bit-transfer rate.Normally,the SPI is used for communications between the DSP controller and external peripherals or anotherprocessor.Typical applications include external I/O or peripheral expansion through devices such as shift registers,display drivers,and ADCs.Multi-device communications are supported by the master/slave operation of the SPI.The port supports a receive and transmit FIFO for reducing servicing overhead.The SPI guide is:•TMS320x281x Serial Peripheral Interface (SPI)Reference Guide•TMS320x280,2801x,2804xSerial PeripheralInterface(SPI)ReferenceGuide •TMS320x2833x,2823x Serial Peripheral Interface (SPI)Reference Guide •TMS320x2834x Delfino Serial Peripheral Interface (SPI)Reference Guide •TMS320x2802x,2803x Piccolo Serial Peripheral Interface (SPI)Reference Guide Table 16lists the differences between SPI types,including device-specific differences within each type.Table 16.Serial Peripheral Interface (SPI)Module Type DescriptionType DescriptionDevices CoveredDevice-Specific OptionsOriginal SPI Module Type2810,2811,2812,2801,2802,2806,2808,–2809,28015,28016,28044,28335,28334,28332,28235,28234,28232,28346,28345,28344,28343,28342,283411Added support for 3-wire28027,28026,28025,28024,28023,28022No STEINV bitbidirectional mode and reduced to 28035,28034,28033,28032Added STEINV bit (inverts 4-level FIFOSPISTE signal to support digital audio receive mode with 2SPIs)The device-specific Boot ROM guides are:•TMS320x281x Boot ROM Reference Guide •TMS320x280x,2801x,2804x DSP Boot ROM Reference Guide •TMS320x2833x,2823x Boot ROM Reference Guide •TMS320x2834x Delfino Boot ROM Reference Guide •TMS320x2802x Piccolo Boot ROM Reference Guide •TMS320x2803x Piccolo Boot ROM Reference Guide The boot ROM is factory-programmable with boot-loading software.Boot-mode signals (general-purpose I/Os)are used to tell the bootloader software which mode to use.The Boot ROM also contains standard math tables such as SIN/COS for use in IQ math related algorithms.The I2C guides include:•TMS320x280x,2801x,2804x Inter-Integrated Circuit (I2C)Module Reference Guide •TMS320x2833x,x2823x Inter-Integrated Circuit (I2C)Module Reference Guide •TMS320x2834x Delfino Inter-Integrated Circuit (I2C)Module Reference Guide •TMS320x2802x,2803x Piccolo Inter-Integrated Circuit (I2C)Module Reference Guide This guide describes the features and operation of the inter-integrated circuit (I2C)module.The I2C module provides an interface between one of these DSPs and devices compliant with PhilipsSemiconductors Inter-IC bus (I2C-bus)specification version 2.1and connected by way of an I2C-bus.External components attached to this 2-wire serial bus can transmit/receive 1-to 8-bit data to/from the DSP through the I2C module.This guide assumes the reader is familiar with the I2C-bus specification.1428x DSP PeripheralsSPRU566I–June 2003–Revised May 2009Submit Documentation Feedback3.11Enhanced Quadrature Encoder Pulse (eQEP)Module3.12Enhanced Capture (eCAP)Module Peripheral DescriptionsTable17liststhe differencesbetween I2Ctypes,includingdevice-specific differences within each type.Table 17.Inter-Integrated Circuit (I2C)Module Type DescriptionType DescriptionDevices CoveredDevice-Specific OptionsOriginal I2C Module Type2801,2802,2806,2808,2809,28015,28016,28044,16-level FIFO28335,28334,28332,28235,28234,28232,28346,28345,28344,28343,28342,2834128027,28026,28023,28022,28021,28020,28035,4-level FIFO28034,28033,28032The eQEP module guides include:•2801x,2804x Enhanced Quadrature Encoder Pule (eQEP)Module Reference Guide •2823x Enhanced Quadrature Encoder Pulse (eQEP)Module Reference Guide •Delfino Enhanced Quadrature Encoder Pulse (eQEP)Module Reference Guide •Piccolo Enhanced Quadrature Encoder Pulse (eQEP)Module Reference GuideThe enhanced quadrature encoder pulse (eQEP)module is used for direct interface with a linear or rotary incremental encoder to get position,direction,and speed information from a rotating machine for use in a high-performance motion and position-control system.Table 18lists the differences between eQEP types,including device-specific differences within each type.Table 18.Enhanced Quadrature Encoder Pulse (eQEP)Module Type DescriptionType DescriptionDevices CoveredDevice-Specific OptionsOriginal eQEP Module Type2801,2802,2806,2808,2809,28044,28335,-28334,28332,28235,28234,28232,28346,28345,28344,28343,28342,28341,28035,28034,28033,28032The eCAP guides are:•TMS320x280x,2801x,2804x Enhanced Capture (eCAP)Module Reference Guide •TMS320x2833x,2823x Enhanced Capture (eCAP)Module Reference Guide •TMS320x2834x Delfino Enhanced Capture (eCAP)Module Reference Guide •TMS320x2802x,2803x Piccolo Enhanced Capture (eCAP)Module Reference Guide The enhanced Capture (eCAP)Module is essential in systems where accurate timing of external events is important.Uses for eCAP include:•Speed measurements of rotating machinery (e.g.,toothed sprockets sensed via Hall sensors)•Elapsed time measurements between position sensor triggers •Period and duty cycle measurements of pulse train signals•Decoding current or voltage amplitude derived from duty cycle encoded current/voltage sensors Table 19lists the differences between eCAP types,including device-specific differences within each type.SPRU566I–June 2003–Revised May 200928x DSP Peripherals 15Submit Documentation Feedback。

TMS320x2833x Multichannel Buffered Serial Port (McBSP) Reference Guide翻译第三章译文

第三章 McBSP(多通道缓冲串口)的采样率发生器。

每个McBSP的包含一个采样率发生器（SRG），可以通过编程来产生一个内部数据时钟（CLKG）和内部帧同步信号（FSG）。

CLKG可用于接收（ DR ）引脚或发送（ DX ）引脚上的数据移位。

FSG的可以用来发起DR或DX引脚上的帧传输。

3.1 框图图3.1采样率发生器的概念框图采样率发生器的时钟源（CLKSRG），可以由LSPCLK 提供，或由一个外部引脚（MCLKX 或MCLKR）提供。

时钟源的选择可由PCR寄存器的SCLKME位和SRGR2寄存器的CLKSM位所决定。

如果一个引脚已经使用，输入信号的极性会随着相应的极性位反转（PCR寄存器的SCLKME或SRGR2寄存器的CLKSM）。

采样率发生器有三级时钟分频器，使CLKG和FSG具有可编程能力。

这三级分频器包括：时钟分频：时钟源根据SRGR1寄存器的CLKGDV位分频产生CLKG。

帧周期分频：CLKG根据SRGR2的FPER位分频，控制从一个帧脉冲的开始到下一个帧脉冲的开始的时间（周期）。

帧同步脉冲宽度递减计数：CLKG周期是根据SRGR1的FWID位计数的，来控制每一帧同步脉冲的宽度。

注意：McBSP无法操作在比源时钟频率的二分之一时钟频率更快的频率。

选择输入时钟频率和CLKGDV的值时应当按照以下原则：CLKG小于或等于时钟源频率的二分之一。

除了三级的时钟分频器，采样率发生器有一个帧同步脉冲检测和时钟同步模块，允许从FSR的引脚上传入的帧同步脉冲和时钟分频同步。

此功能被启用或禁用是由SRGR2的GSYNC位控制的。

详细信息见4.33.1.1 采样率发生器的时钟发生器采样率发生器可以产生时钟信号（ CLKG ），数据发送器和数据接收器单独或者同时使用时钟信号。

使用采样率发生器驱动时钟，由引脚控制寄存器（PCR）上的时钟模式位（ CLKRM和CLKXM ）控制。

当一个时钟模式位设置为1 （ CLKRM = 1：接收，CLKXM = 1：发送），相应的数据时钟（CLKR：接收，CLKX：发送）是由内部采样率发生器的输出时钟（CLKG）驱动。

TMS320x2833x External Interface (XINTF) Reference Guide (Rev. A)

PreliminaryTMS320x2833x DSC External Interface(XINTF)Reference GuideLiterature Number:SPRU949ASeptember2007–Revised October2007Preliminary2SPRU949A–September2007–Revised October2007Submit Documentation FeedbackPreface (5)1TMS320x2833x DSC External Interface(XINTF) (7)1.1Functional Description (7)1.1.1Differences from the TMS320x281x XINTF (7)1.1.2Accessing XINTF Zones (8)1.1.4Write-Followed-by-Read Pipeline Protection (9)1.2XINTF Configuration Overview (10)1.2.1Procedure to Change the XINTF Configuration and Timing Registers (10)1.2.3XINTF Clocking (12)1.2.5Write Buffer (12)1.2.6XINTF Access Lead/Active/Trail Wait-State Timing Per Zone (12)1.2.7XREADY Sampling For Each Zone (13)1.2.8Bank Switching (13)1.2.9Zone Data Bus Width (14)1.3External DMA Support(XHOLD,XHOLDA) (16)1.4Configuring Lead,Active,and Trail Wait States (17)1.5Configuring XBANK Cycles (21)1.6XINTF Registers (22)1.6.1XINTF Timing Registers (22)1.6.2XINTF Configuration Register (26)1.6.3XBANK Register (28)1.6.4XREVISION Register (28)1.6.5XRESET Register (29)1.7Signal Descriptions (30)1.8Waveforms (31)Appendix A Revision History (35)A.1Changes Made in Revision A (35)SPRU949A–September2007–Revised October2007Table of Contents3 Submit Documentation FeedbackPreliminaryList of Figures1-1Typical16-bit Data Bus XINTF Connections (14)1-2Typical32-bit Data Bus XINTF Connections (14)1-3XTIMING0/6/7Register (22)1-4XINTF Configuration Register(XINTCNF2) (26)1-5XBANK Register (28)1-6XREVISION Register (28)1-7XRESET Register (29)1-8XTIMCLK and XCLKOUT Mode Waveforms (31)1-9Generic Read Cycle(XTIMCLK=SYSCLKOUT mode) (32)1-10Generic Read Cycle(XTIMCLK=½SYSCLKOUT mode) (33)1-11Generic Write Cycle(XTIMCLK=SYSCLKOUT mode) (34)List of Tables1-116-bit Mode Behavior (15)1-232-bit Mode Behavior (15)1-3Pulse Duration in Terms of XTIMCLK Cycles (17)1-4Relationship Between Lead/Trail Values and the XTIMCLK/X2TIMING Modes (19)1-5Relationship Between Active Values and the XTIMCLK/X2TIMING Modes (20)1-6Valid XBANK Configurations (21)1-7XINTF Configuration and Control Register Mapping (22)1-8XTIMING0/6/7Register Field Descriptions (22)1-9XINTF Configuration Register Field Descriptions (26)1-10XBANK Register Field Descriptions (28)1-11XREVISION Register Field Descriptions (28)1-12XRESET Register Field Descriptions (29)1-13XINTF Signal Descriptions (30)A-1Change Summary (35)4List of Figures SPRU949A–September2007–Revised October2007Submit Documentation FeedbackPreliminaryPrefaceSPRU949A–September2007–Revised October2007This document describes the external interface(XINTF)used in the F2833x device.The XINTF is a nonmultiplexed asynchronous bus.Notational ConventionsThis document uses the following conventions.•Hexadecimal numbers are shown with the suffix h or with a leading0x.For example,the following number is40hexadecimal(decimal64):40h or0x40.•Registers in this document are shown in figures and described in tables.–Each register figure shows a rectangle divided into fields that represent the fields of the register.Each field is labeled with its bit name,its beginning and ending bit numbers above,and itsread/write properties below.A legend explains the notation used for the properties.–Reserved bits in a register figure designate a bit that is used for future device expansion.Related Documentation From Texas InstrumentsThe following documents describe the related devices and related support tools.Copies of thesedocuments on the Internet at .Tip:Enter the literature number in the search box provided atData Manual—SPRS439—containsthedevices.CPU User's Guides—SPRU430—describes the centralTMS320C28x fixed-point digital signal processors(DSPs).It also describes emulation features available on these DSPs.SPRUEO2—describes thePeripheral Guides—SPRU566—describes the peripheral reference guidesof theSPRUFB0—TMS320x2833x System Control and Interrupts Reference Guide describes the various interrupts and system control features of the2833x digital signal controllers(DSCs).SPRU812—describes how toSPRU949—describes the XINTF,which is aSPRU949A–September2007–Revised October2007Preface5 Submit Documentation FeedbackPreliminaryRelated Documentation From Texas InstrumentsSPRU963—describesthe purposeandfeaturesofthe and provides examples of code.It alsodescribes other contents of the device on-chip boot ROM and identifies where all of the informationis located within that memory.SPRUFB7—describes thea DSP andother devices in a system.SPRUFB8—describes the DMA on the2833x SPRU791—switch mode power supply control,UPS (uninterruptible power supplies),and other forms of powerconversion.SPRU924—describes theSPRU807—describes theSPRU790—encoder to get position,direction,and speed information from a rotating machine in highperformance motion and position control systems.It includes the module description and registers.SPRU074—describesthe noisy environments.SPRU051—describes theSCI,SCI modulessupport digital communications between the CPU and other asynchronous peripherals that use thestandard non-return-to-zero (NRZ)format.SPRU059—describes the SPI -a stream ofprogrammed length (one to sixteen bits)to be shifted into and out of the device at a programmedbit-transfer rate.SPRU721—describes the featuresand Tools Guides—SPRU513—describes the assembly languagetools code),assembler directives,macros,common object file format,and symbolic debugging directives for the TMS320C28x device.SPRU514—describes the TMS320C28x™C/C++code and produces TMS320DSPassembly language source code for the TMS320C28x device.SPRU608—describes the simulator,simulates the instructionset of the C28x™core.SPRU625—6Read This First SPRU949A–September 2007–Revised October 2007Submit Documentation FeedbackPreliminarySPRU949A–September2007–Revised October2007The external interface(XINTF)is a nonmultiplexed asynchronous bus,similar to the TMS320x281x external interface.This guide is applicable for the XINTF found on the TMS320x2833x family of processors.This includes all Flash-based and RAM-based devices within the2833x family.1.1Functional DescriptionThe XINTF is mapped into three fixed memory-mapped zones as defined in Section1.1.3.Each of the28x XINTF zones has a chip-select signal that is toggled when an access is made to thatparticular zone.On some devices the chip-select signals for two zones may be internally ANDed together to form a single shared chip select.In this manner,the same memory is connected to both zones orexternal decode logic can be used to separate the two.Each of the three zones can also be programmed with a specified number of wait states,strobe signal set-up and hold timing.The number of wait states,set-up and hold timing is separately specified for a read access and a write access.In addition,each zone can be programmed for extending wait states externally using the XREADY signal or not.The programmable wait-state,chip-select and programmable strobetiming enables glueless interface to external memories and peripherals.You specify the set-up/hold and access wait states for each XINTF zone by configuring the associated XTIMINGx registers.The access timing is based on an internal clock called XTIMCLK.XTIMCLK can be set to the same rate as the SYSCLKOUT or to one-half of SYSCLKOUT.The rate of XTIMCLK applies to all of the XINTF zones.XINTF bus cycles begin on the rising edge of XCLKOUT and all timings andevents are generated with respect to the rising edge of XTIMCLK.1.1.1Differences from the TMS320x281x XINTFThe XINTF described in this document is very similar to the TMS320x281x XINTF.The main differences are:•Data Bus Width:Each XINTF zone can be configured individually to use a16-bit or32-bit data ing the32-bitmode improves performance since32bits of data can be read or written in a single access.The databus width does not change the size of the XINTF zones or memory reach.In32-bit mode,the lowestaddress line XA0becomes a2nd write enable.The281x XINTF is limited to a16-bit data bus.•Address Bus Reach:The address reach has been extended to20address lines.Zone6and Zone7both use the fulladdress reach of1M x16words each.The281x address reach is512k x16words.•Direct Memory Access(DMA):All three XINTF zones are connected to the on-chip DMA module.The DMA can be used to copy code and data to or from the XINTF while the CPU is processing other data.The281x devices do notinclude a DMA.SPRU949A–September2007–Revised October2007TMS320x2833x DSC External Interface(XINTF)7 Submit Documentation Feedback1.1.2Accessing XINTF ZonesPreliminaryFunctional Description•XINTF Clock Enable:The XINTF clock (XTIMCLK)is disabled by default to save power.XTIMCLK can be enabled by writing a 1to bit 12of the PCLKCR3register.PCLKCR3is documented in the device-specific system control and interrupts user's guide.For the F2833xSystem Control and Interrupts Reference Guide (literature number Turning off XTIMCLK does not turn off XCLKOUT.There is a separate control to On the 281x,XTIMCLK is always enabled.•XINTF Pin MUXing:Many of the XINTF pins are MUXed with general purpose I/O.The GPIO mux registers must be configured for XINTF operation before you can use the XINTF.On the 281x the XINTF has dedicated pins.•Number of Zones and Chip Select Signals:The number of XINTF zones has been reduced to 3:Zone 0,Zone 6and Zone 7.Each of these zones has a dedicated chip select signal.Zone 0is still read-followed-by write protected as described in Section 1.1.4.On the 2812devices,some zone chip-select signals are shared between zones.Zone 0XZCS0AND1and Zone 6and Zone 7share XZCS6AND7.•Zone 7Memory Mapping:Zone 7is always mapped.On the 281x devices the MPNMC input signal determines if Zone 7is mapped.Zone 6and 7do not share any locations.On 281x,Zone 7is mirrored within Zone 6.•Zone Memory Map Locations:Zone 0starts at address 0x4000and is 4K x 16.On 281x Zone 0starts at address 0x2000and is 8K x 16.Zone 6and 7are both 1M x 16and start at 0x100000and 0x200000respectively.On 281x these two zones are 512K x 16and 16K x 16.•EALLOW protection:The XINTF registers are now EALLOW protected.On 281x the XINTF registers were not EALLOWprotected.For timing information refer to the latest data manual for your particular device.An XINTF zone is a region in the 28x memory map that is directly connected to the external interface.Section 1.1.3shows zone locations.The memory or peripheral attached to a zone can be accesseddirectly with the CPU or Code Composer Studio.Each XINTF zone can be individually configured with unique read and write access timing and each has an associated zone chip-select signal.This chip-select signal is pulled low so that an access to that zone is currently taking place.On 2833x devices,all zone chip select signals are independent.The external address bus,XA,is 20bits wide and is shared by all of the zones.What external addresses are generated depends on which zones are being accessed,as follow:•Zone 0uses external addresses 0x00000-0x00FFF.That is,an access to the first location in Zone 0will issue external addresses 0x00000along with chip select 0(XZCS0).An access to the last location in the zone will issue address 0x00FFF with XZCS0.•Zone 6and 7both use external addresses 0x00000-0xFFFFF.Depending on which zone is accessed,the appropriate zone chip select signal (XZCS6or XZCS7)will also go low.8TMS320x2833x DSC External Interface (XINTF)SPRU949A–September 2007–Revised October 2007Submit Documentation Feedback1.1.4Write-Followed-by-Read Pipeline ProtectionMOVTBIT @REG1,AL @REG2,#BIT_X ReadWriteMOVTBIT @REG1,AL @REG2,#BIT_XReadWritePreliminaryFunctional DescriptionA Each zone can be programmed with different wait states,setup and hold timings.A dedicated zone chip select(XZCS)signal toggles when an access to a particular zone is performed.These features enable glueless connectionto many external memories and peripherals.B Zones 1–5are reserved for future expansion.CZones 0,6,and 7are always enabled.In the 28x CPU pipeline,the read phase of an operation occurs before the write phase.Due to thisordering,a write followed by a read access can actually occur in the opposite order:read followed bywrite.For example,the following lines of code perform a write to one location followed by a read from another.Due to the 28x CPU pipeline,the read operation will be issued before the write as shown:On 28x devices,regions of memory where peripheral registers are common are protected from this order reversal by hardware.These regions of memory are said to be read-followed-by-write pipeline protected.XINTF Zone 0is by default read-followed-by-write pipeline protected.Write and read accesses to Zone 0are executed in the same order that they are written.For example,a write followed by a read is executed in the same order it was written as shown below:SPRU949A–September 2007–Revised October 2007TMS320x2833x DSC External Interface (XINTF)9Submit Documentation Feedback1.2XINTF Configuration Overview1.2.1Procedure to Change the XINTF Configuration and Timing RegistersPreliminaryXINTF Configuration OverviewThe 28x CPU automatically protects writes followed by reads to the same memory location.The protection mechanism described above is for cases where the address is not the same,but within a given region of protected memory.In this case,the order of execution is preserved by the CPU automatically insertingenough NOP cycles for the write to complete before the read occurs.This execution ordering becomes a concern only when peripherals are mapped to the XINTF.A write to one register may update status bits in another register.In this case,the write to the first register mustfinish before the read to the second register takes place.If the write and read operations are performed in the natural pipeline order,the wrong status may be read since the write would happen after the read.This reversal is not a concern when memory is mapped to the XINTF.Thus,Zone 0would not typically be used to access memory but instead would be used only to access external peripherals.If other zones are used to access peripherals that require write-followed-by-read instruction order to bepreserved the following solutions can be used:•Add up to 3NOP assembly instructions between a write and read instructions.Fewer than three can be used if the code is analyzed and it is found that the pipeline stalls for other reasons.•Move other instructions before the read to make sure that the write and read are at least three CPU cycles apart.•Use the -mv compiler option to automatically insert NOP assembly instructions between write and read accesses.This option should be used with caution because this out-of-order execution is a concernonly when accessing peripherals mapped to XINTF and not normal memory accesses.This section is an overview of the XINTF parameters that can be configured to fit particular systemrequirements.The exact configuration used depends on the operating frequency of the 28x,switchingcharacteristics of the XINTF,and the timing requirements of the external devices.Detailed information on each of these parameters is given in the following sections.Because a change to the XINTF configuration parameters will cause a change to the access timing,code that configures these parameters should not execute from the XINTF itself.During an XINTF configuration or timing change no accesses to the XINTF can be in progress.Thisincludes instructions still in the CPU pipeline,write accesses in the XINTF write buffer,data reads orwrites,instruction pre-fetch operations and DMA accesses.To be sure that no access takes place during the configuration follow these steps:1.Make sure that the DMA is not accessing the XINTF.2.Follow the procedure shown in Section 1.2.2to safely modify the XTIMING0/6/7,XBANK,orXINTCNF2registers.10TMS320x2833x DSC External Interface (XINTF)SPRU949A–September 2007–Revised October 2007Submit Documentation FeedbackWait eight cycles to let the write instructions propogate through the CPU pipeline. This must be done before the return-from-function call is made.Write instructions to XTIMING0/6/7, XBANK, or XINTCNF2The XINTF write buffer must be empty before the configuration change.The stack must not be in external memory.The function that changes the configuration cannot execute from the XINTF.Branch or call is required to properly flush the CPU pipeline before the configuration change.PreliminaryXINTF Configuration OverviewPreliminary XINTF Configuration Overview1.2.3XINTF ClockingThere are two clocks used by the XINTF module:XTIMCLK and XCLKOUT.Section1.2.4shows therelationship between these two clocks and the CPU clock,SYSCLKOUT.All accesses to all of the XINTF zones are based on the frequency of the internal XINTF clock,XTIMCLK.When configuring the XINTF,you must choose the ratio for the internal XINTF clock,XTIMCLK,withrespect to SYSCLKOUT.XTIMCLK can be configured to be either equal or one half of SYSCLKOUT by writing to the XTIMCLK bit in the XINTFCNF2register.By default XTIMCLK is one-half of SYSCLKOUT.All XINTF accesses begin on the rising edge of the external clock out,XCLKOUT.In addition,external logic may be clocked off of XCLKOUT.The frequency of XCLKOUT can be configured as a ratio of the internal XINTF clock,XTIMCLK.XCLKOUT can be configured to be either equal or one-half of XTIMCLK by writing to the CLKMODE bit in the XINTFCNF2register.By default,XCLKOUT is one-half of XTIMCLK, or one-fourth of the CPU clock,SYSCLKOUT.To reduce system noise,you may choose to not output XCLKOUT on a pin.This is done by writing a1to the XINTCNF2[CLKOFF]bit.1.2.5Write BufferBy default,write access buffering is disabled.In most cases,to improve performance of the XINTF,you should enable write buffering.Up to three writes to the XINTF can be buffered without stalling the CPU.The write buffer depth is configured in the XINTCNF2register.1.2.6XINTF Access Lead/Active/Trail Wait-State Timing Per ZoneAn XINTF zone is a region of memory-mapped addresses that directly access the external interface.The timing of any read or write access to an XINTF zone can be divided into the following three portions:Lead, Active,and Trail.The number of XTIMCLK cycle wait states for each portion of an access can beconfigured for each XINTF zone in the corresponding zone XTIMING register.Timing for read accesses can be configured separately from timing for write accesses.In addition,to facilitate connections to slow external devices the X2TIMING bit can be used to double the specified lead/active and trail wait states fora particular zone.During the lead portion,the chip-select signal for the zone being accessed is taken low and the address is placed on the address bus(XA).The total lead period,in XTIMCLK cycles can be configured in the zone’s XTIMING register.By default,the lead period is set to the maximum six XTIMCLK cycles for both read and write accesses.12TMS320x2833x DSC External Interface(XINTF)SPRU949A–September2007–Revised October20071.2.7XREADY Sampling For Each Zone 1.2.8Bank Switching PreliminaryXINTF Configuration OverviewDuring the active period,the access to the external device is made.For a read access,the read strobe (XRD)is brought low and data is latched into the DSP.For a write access,the write enable(XWE0)strobe is brought low and data is placed on the data bus(XD).If the zone is configured to sample the XREADY signal,the external device can control the XREADY signal to further extend the active period beyond the programmed wait states.The total active period for any access that does not sample XREADY is1XTIMCLK cycle plus the number wait states specified in the corresponding XTIMING register.By default,the active wait states are set to the14XTIMCLK cycles for both read and write accesses.The trail period serves as a hold time in which the chip-select signal remains low but the read and write strobes are brought back high.The total trail period,in XTIMCLK cycles can be configured in the zone’s XTIMING register.By default the trail period is set to the maximum six XTIMCLK cycles for both read and write accesses.Based on system requirements,the lead,active and trail wait state values can be configured to best fit the devices connected to a particular XINTF zone.The following should be considered when selecting the timing parameters:•Minimum wait state requirements as described in Section1.4•The timing characteristics of the XINTF,as described in the device data manual•The timing requirements of the external device•Any additional delays between the28x device and the external deviceBy sampling XREADY,the external device can extend the active portion of the access.All of the XINTF zones on a device share the same XREADY input signal but each XINTF zone can individually be configured to either sample or ignore the XREADY signal.In addition,the sampling can be specified as synchronous or asynchronous for each zone.•Synchronous samplingIf XREADY is sampled synchronously,then the XREADY signal must meet set-up and hold timing relative to one XTIMCLK edge before the end of the active period.That is,XREADY will be sampled one XTIMCLK cycle before the total lead+active cycles specified for the access.•Asynchronous samplingIf XREADY is sampled asynchronously,then the XREADY signal must meet set-up and hold timing relative to three XTIMCLK cycles before the end of the active period.That is,XREADY will be sampled three XTIMCLK cycles before the total lead+active cycles specified for the access.In both the synchronous and asynchronous case if the XREADY sample is found to be low,the active portion of the cycle is extended by one XTIMCLK cycle and XREADY is sampled again during the next XTIMCLK cycle.This pattern continues until XREADY is sampled high at which time the access will complete normally.If a zone is configured to sample XREADY,then it is done so for both read and write accesses to that zone.By default each XINTF zone is configured to sample XREADY in the asynchronous mode.When using the XREADY signal,you should consider minimum XINTF wait state requirements as described in Section1.4.The minimum requirements are different when sampling XREADY in the synchronous mode mode,depending on the following:•The timing characteristics of the XINTF,as described in the device data sheet.•The timing requirements of the external device.•Any additional delays between the28x device and the external device.When jumping from one XINTF zone to another XINTF zone,a slow device may require extra cycles in order to release the bus in time for another device to gain access.Bank switching allows you to specify a particular zone for which extra cycles will be added for any access that crosses into or out of the specified zone.The zone and number of cycles is configured in the XBANK register.The number of cycles must meet the requirements described in Section1.5.Preliminary XINTF Configuration Overview1.2.9Zone Data Bus WidthEach XINTF zone can individually be configured for a16-bit or32-bit wide data bus.The functionality of the XA0/XWE1signal changes depending on the configuration.When an XINTF zone is configured for 16-bit mode(XTIMINGx[XSIZE]=3),then the XA0/XWE1signal takes on the role of least-significantaddress line(XA0).In this case,a typical XINTF bus connection looks as shown in Figure1-1.Thebehavior of the XWE0and XA0/XWE1signals is summarized in Table1-1and Table1-2.Figure1-1.Typical16-bit Data Bus XINTF ConnectionsWhen an XINTF zone is configured for32-bit mode(XTIMINGx[XSIZE]=1),the XA0/XWE1signal is the active low write strobe XWE1.XWE1is used,along with XWE0for32-bit bus operation as shown inFigure1-2.Figure1-2.Typical32-bit Data Bus XINTF Connections14TMS320x2833x DSC External Interface(XINTF)SPRU949A–September2007–Revised October2007PreliminaryXINTF Configuration OverviewTable1-1.16-bit Mode Behavior16-bit Mode Write Access XA0/XWE1XWE0no access P(1)016-bit value at even address0116-bit value at odd address11(1)P=previous valueTable1-2.32-bit Mode Behavior32-bit Mode Write Access XA0/XWE1XWE0no access1116-bit value at even address1016-bit value at odd address0132-bit value00Preliminary External DMA Support(XHOLD,XHOLDA)1.3External DMA Support(XHOLD,XHOLDA)The XINTF supports direct memory access(DMA)to its local(off-chip)program and data spaces.This is accomplished with the XHOLD signal input and XHOLDA output.When XHOLD is asserted(low active)a request to the external interface is generated to hold all outputs from the external interface a highimpedance state.Upon completion of all outstanding accesses to the external interface,XHOLDA isasserted(low active).XHOLDA signals external devices that the external interface has its outputs inhigh-impedance state and that another device can control access to external memory or peripherals.The HOLD Mode bit in XINTCNF2register enables the automatic generation of a XHOLDA signal andgranting access of the external bus,when a valid XHOLD signal is detected.While in HOLD mode,the CPU can continue to execute code from on-chip memory attached to the memory bus.If an attempt ismade to access the external interface while XHOLDA is low,a not ready condition is generated,halting the processor.Status bits in the XINTCNF2register will indicate the state of the XHOLD and XHOLDA signals.If XHOLD is active,and the CPU attempts a write to the XINTF,the write is not buffered and the CPU will stall.The write buffer is disabled.The HOLD mode bit in XINTCNF2register bit will take precedence over the XHOLD input signal.Thus enabling customer code to determine when or not a XHOLD request is to be honored.The XHOLD input signal is synchronized at the input to the XINTF before any actions are taken.Synchronization is with respect to XTIMCLK.The HOLDS bit in XINTCNF2register reflects the current synchronized state of the XHOLD input.On reset,the HOLD mode bit is enabled,allowing for bootload of external memory using an XHOLDrequest.If XHOLD signal is active low during reset,the XHOLDA signal is driven low as per normaloperation.During power up,any undefined values in the XHOLD synchronizing latches are ignored and wouldeventually be flushed out when the clock stabilizes.Hence,synchronizing latches do not need to be reset.If an XHOLD active low signal is detected,the XHOLDA signal is only driven low after all pending XINTF cycles are completed.Any pending CPU cycles are blocked and the CPU is held in a not-ready state if they are targeted for the XINTF.Definitions:Pending XINTF Cycle—Any cycle that is currently in the XINTF FIFO queue.Pending CPU Cycle—Any cycle that is not in the FIFO queue but is active on the core memory bus.The XHOLD signal should not be removed until the XHOLDA signal becomes active.Unpredictable results will occur if this rule should be violated.The state of the XINTF external signals is as follows in HOLD mode:Signal HOLD Granted ModeXA(19:1)High-impedanceXD(31:0)High-impedanceXA0/XWE1High-impedanceXRD,XWE0,XR/W High-impedanceXZCS0High-impedanceXZCS6High-impedanceXZCS7High-impedance16TMS320x2833x DSC External Interface(XINTF)SPRU949A–September2007–Revised October2007。

TMS320x280xDSP模数转换器（ADC）参考指南

TMS320x280xDSP模数转换器（ADC）参考指南PreliminaryTMS320x280x DSP 模数转换器(ADC)参考指南文献编号:ZHCU0042004年11月–修订2005年6月Preliminary内容目 (3)序7 1模数转换器(ADC) (11)1.1 (12)1.2141.2.1顺序采样模式 (15)1.2.2151.3不间断自动定序模式 (20)1.3.1序列发生器启动/停止模式（具有多个时序触发器的序列发生器启动/停止操作）221.3.2同步采样模式 (24)1.3.3输入触发器说明 (24)1.3.4定序转换期间的中断操作251.4ADC时钟预分频器 (26)1.4.1ADC模块时钟和采样频率271.5低功率模式 (27)1.6281.7序列发生器覆盖功能 (28)1.8内部/外部参考电压选择281.9 (30)2ADC寄存器332.1ADC控制寄存器 (34)2.2最大转换信道数寄存器(ADCMAXCONV)372.3自动定序状态寄存器(ADCASEQSR) (39)2.4ADC状态和标志寄存器(ADCST)392.5ADC参考选择寄存器(ADCREFSEL) (40)2.6ADC偏移微调寄存器(ADCOFFTRIM)412.7ADC输入信道选择定序控制寄存器 (41)2.8ADC转换结果缓冲寄存器(ADCRESULTn) (42)A修订历史记录45Preliminary附图目录1-1ADC模块的结构图 (13)1-2顺序采样模式(SMODE=0) (15)1-3同步采样模式(SMODE=1) (15)1-4级联模式下自动定序的ADC结构图 (16)1-5带双序列发生器的自动定序的ADC结构图 (17)1-6不间断自动定序模式的流程图 (22)1-7ePWM触发器启动序列发生器的示例 (23)1-8定序转换期间的中断操作 (26)1-9ADC内核时钟和采样保持(S/H)时钟 (27)1-10到ADC的时钟链 (27)1-11外部参考的外部偏置 (29)1-12 (30)1-13采样0-V参考电压的理想代码分布 (31)2-1ADC控制寄存器1(ADCTRL1)（地址偏移00h） (34)2-2ADC控制寄存器2(ADCTRL2)（地址偏移01h） (35)2-3ADC控制寄存器3(ADCTRL3)（地址偏移18h） (37)2-4最大转换信道数寄存器(ADCMAXCONV)（偏移地址02h）(38)2-5自动定序状态寄存器(ADCASEQSR)（地址偏移07h） (39) 2-6ADC状态和标志寄存器(ADCST)（地址偏移19h） (40)2-7ADC参考选择寄存器(ADCREFSEL)（地址偏移1Ch） (40)2-8ADC偏移微调寄存器(ADCOFFTRIM)（地址偏移1Dh） (41) 2-9ADC输入信道选择定序控制寄存器(ADCCHSELSEQ1)（地址偏移03h） (41)2-10ADC输入信道选择定序控制寄存器(ADCCHSELSEQ2)（地址偏移04h） (41)2-11ADC输入信道选择定序控制寄存器(ADCCHSELSEQ3)（地址偏移05h） (41)2-12ADC输入信道选择定序控制寄存器(ADCCHSELSEQ4)（地址偏移06h） (42)2-13ADC转换结果缓冲寄存器(ADCRESULTn)-（地址0x7108-0x7117） (42)2-14ADC转换结果缓冲寄存器(ADCRESULTn)-（地址0x0B00-0x0B0F） (42)Preliminary附表目录1-1ADC寄存器 (13)1-2单一工作模式和级联工作模式比较 (18)1-3ADCCHSELSEQn寄存器的值（MAX_CONV1设置为6） (21) 1-4ADCCHSELSEQn的值（MAX_CONV1设置为2） (23)1-5 (24)1-6输入触发器 (24)1-7到ADC的时钟链 (27)1-8 (27)2-1ADC控制寄存器1(ADCTRL1)字段说明 (34)2-2ADC控制寄存器2(ADCTRL2)字段说明 (35)2-3ADC控制寄存器3(ADCTRL3)字段说明 (37)2-4最大转换信道数寄存器(ADCMAXCONV)字段说明 (38)2-5各种转换数的MAX_CONV1的位选择 (38)2-6自动定序状态寄存器(ADCASEQSR)字段说明 (39)2-7活动序列发生器的状态 (39)2-8ADC状态和标志寄存器(ADCST)字段说明 (40)2-9ADC参考选择寄存器(ADCREFSEL)字段说明 (41)2-10ADC偏移微调寄存器(ADCOFFTRIM)字段说明 (41)2-11CONVnn位值和所选的ADC输入信道 (42)PreliminaryPreliminary序言ZHCU004–2004年11月–修订2005年6月请先阅读关于本手册本文档描述了TMS320x280x数字信号处理器(DSP)上可用的模数转换器(ADC)的功能和操作。

TMS320F28xx DSP中内部Flash的应用研究

TMS320F28xx DSP中内部Flash的应用研究TMS320F28xx 片内有128 K×16 bit字的Flash、两块4 K x16bit字的单周期拜访RAM(SARAM)LO和L1、一块8 Kxl6 bit字的单周期拜访RAM(SARAM)HO、两块1 Kxl6 bit字的单周期拜访RAM(SARAM)M0和M1。

因为存储器种类多、容量大，所以从系统的高度来配置各个存储器必需有合适的办法，而这些办法普通都与片内Flash有关。

另外，TMS320F28xx DSP片内有定时器模块(WDT)、引导ROM(ROM bootloader)模块、代码平安模块(CSM)，要合理地用法这些模块为囫囵系统服务，必然也要用到Flash。

由此可以看出，Flash的地位和作用比较显著．所以本文就Flash的几种使用作了讨论。

2 从Flash拷贝段到RAM2．1拷贝中断向量在TMS320F28xx器件中，外设扩展中断(PIE)模块管理中断哀求。

上电时，全部中断向量必需位于非易失性存储器(如 Flash)中，但是要把中断向量拷贝到PIEVECT RAM中，这是用户代码中器件初始化程序的一部分。

PIEVECT RAM是一个特定的RAM块，它在当前TMS320F28xx 器件中是一个256×16的块．在数据空间中的起始地址为 Ox000D00。

把中断向量衔接到Flash，然后在运行时把中断向量拷贝到PIEVECT RAM中，有许多办法可以实现。

一个办法是创建包含函数指针的常量C 结构体，该结构体包括128个32-bit向量。

假如用法DSP281x或者DSP280x外设的结构体．这个结构体叫做PieVectTableInit，它已经在DSP281x_PieVect．c或者 DSP280x_PieVect.c创建(参看TI提供的例程)。

由于这个结构体用法const类型关键词，所以它将会被编译器放置在.econst段中。

MultichannelBuff...

MultichannelBuff...概论本⽂档介绍了2833系列设备的多通道缓冲串⼝（McBSP）1.1简介2833x设备提供了多达两个⾼速多通道缓冲串⾏端⼝（McBSP），这些接⼝允许直接接⼝到系统中的编解码器和其他设备。

McBSP包括数据流路径和控制路径，控制路径由六个引脚连接到外部设备，如图1-1所⽰。

数据通过数据发送（DX）引脚和数据接收（DR）引脚与McBSP接⼝的设备进⾏通信。

在时钟和帧同步下的控制信息是通过以下引脚通信的：发送时钟（CLKX），CLKR（接收时钟），FSX（发送帧同步），和FSR（接收帧同步）。

CPU和DMA控制器使⽤内部的外设总线访问McBSP，并通过16位宽的寄存器与McBSP进⾏通信。

CPU或DMA控制器将要发送的数据发送到数据发送寄存器（DXR1，DXR2），要写⼊DXRs的数据通过发送移位寄存器（XSR1，XSR2）移出到DX。

同样，在DR引脚上接收到的数据被转移到接收移位寄存器（RSR1，RSR2），并复制到接收缓冲寄存器（RBR1，RBR2）。

然后，RBRs的内容被复制到DRRS，该数据可以被CPU或DMA控制器读取。

这使得内部和外部的数据通信是同步运动如果串⾏字长为8位，12位或16位的话，DRR2，RBR2，RSR2，DXR2，XSR2不能被使⽤（写，读，或转移）。

对于更⼤的字长，这些寄存器需要保存⾼位的值。

环回帧和时钟环回被装备到芯⽚级别来使能CLKX和FSX，以此来驱动CLKR和FSR 。

如果启⽤环回，CLKR和FSR将从CLKR和FSR（pads）⽚中获得信号，⽽不是从他们⾃⼰的引脚上。

1.2 McBSP的特征McBSP的功能：1、全双⼯通信2、双缓冲的发送和三重缓冲接收，允许连续的数据流3、独⽴时钟和帧接收和发送4、发送中断到CPU和发送DMA事件到DMA控制器的能⼒5、128通道的发送和接收6、每个通道中能⽤或禁⽤块传输的多通道选择模式7、直接接⼝⾏业标准的编解码器，或者模拟接⼝芯⽚（AIC），和其它串⾏连接到A / D和D / A的设备8、⽀持外部⽣成的时钟信号和帧同步信号9、⼀个可编程的采样率发⽣器的内部时钟信号和帧同步信号的产⽣和控制10、帧同步脉冲和时钟信号的极性可编程11、直接接⼝：T1/E1成帧器IOM-2兼容设备AC97兼容设备（提供必要的多相帧的能⼒。

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第四章Chapter 4 本章描述意外和错误条件，以及如何来处理他们.4.1错误类型构成一个系统错误的五个串口事件：1、接收溢出（RFULL= 1）接收溢出发生在，自从上一个RBR-to-DRR的复制以来DRR1还没有被读取的时候。

因此，接收器没有从RBR(s)复制一个新字到DRR(s)，而且RBR(s)现在没有被从DR转移来的另一个新字所填充。

因此，RFULL=1时就表示有错误情况，即此时任何新数据可以到达DR引脚，并且取代RSR(s)中的内容，之前的字也会丢失。

只要DR不断接收新字，RSR（s）就会被覆盖。

而且DRR1不会被读取。

关于接收器接收溢出的更多细节，请详见4.2节。

2.突发接收帧同步脉冲（RSYNCERR =1）这发生在接受过程中，当RFIG=0且意外的帧同步脉冲发生时。

意外的帧同步脉冲是一个当前帧的所有位收到之前，就开始下一帧的传输。

如此一来，它就会导致数据接收中止并且重新启动。

如果新的数据已从RSR（s）自上次RBR-to-DRR的复制，被复制到RBR（s）上，在RBR（s）上的这个新数据就会丢失。

这是因为在RBR-DRR中没有发生复制；接收被重新开始。

关于接受帧同步错误的更多细节，请详见4.3节。

3.发送器数据覆盖发生这种情况时，中央处理器或DMA控制器在数据复制到XSR之前，已将其在DXR中覆盖。

而被覆盖的数据永远不会到达DX的管脚。

关于覆盖发射器的更多细节，请详见4.4节。

4. 发送器下溢位（XEMPTY=0）如果一种新的帧同步信号在新的数据下载到DXR1之前到达，在DXR（s）中先前的数据就会再次发送。

这种过程会继续为到来的每一个新的帧同步提供脉冲。

关于发射器反向溢位的更多的细节，请详见4.5节。

5. 突发传送帧同步脉冲（XSYNCERR = 1）这发生在传输过程中当XFIG=0，就会发生意外的帧同步脉冲。

意外的帧同步脉冲是一个当前帧的所有位收到之前，就开始下一帧的传输。

如此一来，它就会导致数据接收中止并且重新启动。

如果新的数据已从自上次DXR-to-XSR 的副本被复制到DXR（s）上，在XSR（s）上的电流值就会丢失。

关于接受帧同步传输错误的更多细节，请详见4.6节。

4.2接收器溢出SPCR1 中RFULL= 1表示接收器已经溢出和并处在错误情况下。

RFULL 被置位当所有下列条件都满足时：1、自从上一个RBR-DRR的复制之后（RRDY= 1）DRR1尚未被阅读。

2、RBR1是填满的和RBR-DRR的复制并没有发生。

3、RSR1是填满的，RSR1-RBR的复制还没有发生。

正如在2.5节所述，McBSP的接收，到达DR的数据被不断地移入到RSR1（字长度的16位或更小）或RSR2和RSR1（字长度大于16位）。

一旦一个完整的字被移入到RSR（S），如果在RBR1以前的数据已被复制到DRR1 ，RSR-RBR 的复制就会发生。

当新数据到达在DRR1时，RRDY被置位，而且当数据从DRR1被读出时RRDY位被清零。

直到RRDY= 0，下一个RBR-DRR的复制才会发生，数据被保存在RSR（S）中。

到达DR引脚的新数据被移入RSR中（S），RSR （S）中之前的内容丢失。

如果DRR1在第三个字被移入到RSR1之前不迟于2.5个周期的时间内被读，可以防止数据的丢失。

注：如果需要两个DRRS（字长大于16位），CPU或DMA控制器必须首先读取DRR2 ，然后读取DRR1。

只要DRR1被读取，下一个RBR-DRR的复制就会启动。

如果DRR2没有被首先读取，DRR2中的数据就会丢失。

接收器从复位到开始运行之后，在RFULL置位之前，至少有3个字必须被接收。

以下事件的任何一个可以清除RFULL位，并允许随后的转移被正确读取：1，CPU或DMA控制器读取DRR1。

2，接收器被单独复位（RRST= 0）或作为一个TMS320F28335的复位的一部分。

重新启动接收器需要另一帧同步脉冲。

4.2.1溢出条件的范例图4-1显示了接收溢出条件。

因为在串行字B到达RBR1之前，串行字A不能从DRR1中被读取，B也不能转移到DRR1。

另一个新字到达而且RSR1被填满数据。

DRR1被最终读取，但是不会早于字C结束之前的2.5个周期。

因此，新的数据（D）在RSR1中覆盖字C。

如果不及时读取DRR1中的值，下一个字可以覆盖D。

DFigure 4-1. Overrun in the McBSP Receiver4.2.2防止溢出条件的范例图4-2显示了在RFULL置位的情况下，但是覆盖的情况被一个读取所覆盖，该覆盖是在下一个串行字被完全转移到RSR1之前至少2.5个周期的时候被读取的。

这将确保在接收器尝试从RSR1到RBR1发送字C之前，一个RBR1-DRR1的字B的复制会发生。

Figure 4-2. Overrun Prevented in the McBSP Receiver4.3突发的接收帧同步脉冲4.3.1 节显示了McBSP如何响应其他的接收帧同步脉冲，包括突发脉冲响应。

4.3.2节和4.3.3节显示了一个帧同步错误的例子，而且包含了如何阻止相应的错误。

4.3.1 接收帧同步脉冲可能的响应图4-3显示了接收器用来处理所有输入的帧同步脉冲的决策树。

该图假设接收器已经启动（在SPCR1中RRST=1）。

图中的案例3是发生错误的情况以下三种情况任何一个都可能会发生：案例一：在RCR2中的RFIG = 1时，突发的内部FSX脉冲。

忽略掉接收帧同步脉冲，继续接收。

案例二：正常串口的接收。

接收继续正常工作，因为帧同步脉冲是突发的。

一个接收操作不在进程中，可能有三个原因：1、接收器使能后，FSX是首脉冲。

2、在DRR[1,2]被读取之后，清楚接收器已满的条件（在SPCR1中的RFULL=1），FSX脉冲是首脉冲。

3、串口处在数据包之间的间隔。

在下一个数据的第一位被接收期间，可编程的数据接收延迟（编程RCR2中的RDATDLY位）可能会启动，所以，在最大的帧频率中，在同步帧的第一个bit接收的0-2个周期之前，帧同步可以仍然可被接收到。

案例三：突发的接收帧同步（RFIG = 0）（帧同步脉冲不能被忽略）。

突发的帧同步脉冲可来自外部源或者内部采样率发生器。

在当前帧被完全接收完成之前，如果一个帧同步脉冲开始一个新帧的传输，这个脉冲就会被看做突发的帧同步脉冲，而且接收器将置位SPCR1中的发送帧同步错误位（RSYNCERR）。

通过接收器复位或者该位置零，RSYNCERR能被清零。

如果你想让McBSP来通知CPU接收帧同步错误，你可以设置SPCR1 中的RINTM位来设置一个特殊的接收中断模式。

当RINTM = 11B时，McBSP 发送一个接收中断（XINT）请求到CPU，在每次RSYNCERR被置位的时候。

4.3.2意外的接收帧同步脉冲的示例图4-4显示了串口在数据包之间的间隔期间正常操作时，产生的突发的发送帧同步脉冲。

当突发的帧同步脉冲发生时，RSYNCERR位被置位而且中止接收数据B，数据C的发送也会重新启动。

此外，如果RINTM = 11B，McBSP发送一个接收中断（XINT）要求到CPU。

Figure 4-4. An Unexpected Frame-Synchronization Pulse During a McBSP Reception4．3．3防止突发的接收帧同步脉冲每帧在传输时可能延迟0，1或 2 CLKX周期，这取决于在RCR2 中的RDATDLY位的值。

对于每一个可能的数据延迟，图4-5显示了对应于当前帧的最后一位，在FSX上，什么时候一个新的帧同步脉冲可以安全的产生。

Figure 4-5. Proper Positioning of Frame-Synchronization Pulses4.4 发送器覆盖如McBSP的发送部分（第2.6节）所述，发送器必须复制以前通过CPU或DMA控制器写到DXR的数据到XSR中（S）然后转移XSR中的每一bit到DX 引脚上。

如果新的数据在之前的数据被复制到XSR之前写入到DXR中，在DXR 中之前的数据被复写，然后丢弃4.4.1覆盖条件的示例图4-6显示，如果在DXR1的数据在被发送之前被覆盖，将会发生什么。

最初，DXR1加载了与数据C.，A随后写入到DXR1，并且在C被复制到XSR1之前用D覆盖了C ，。

因此，C从来没有在DX上发送。

Figure 4-6. Data in the McBSP Transmitter Overwritten and Thus Not Transmitted4.4.2防止覆盖通过修改CPU可以防止CPU的复写：1、在写入到DXRS之前，查看SPCR2 中XRDY是否为1。

当数据被从DXR1复制到XSR1时，XRDY被置位，当被写入到DXR1时，XRDY被清零。

2、在写入到DXR（S）之前，等待一个发送中断（XINT）。

当在SPCR2中的XINTM= 00B时，每次XRDY被置位时，发送器发送XINT到CPU。

通过将DMA传输和同步事件XEVT进行同步，可以阻止DMA复写。

每次XRDY被置位时，发送器发送一个XEVT信号。

4.5发送器的下溢通过将SPCR2的XEMPTY位清零，McBSP表明一个发送空（或下溢）条件。

以下事件激活XEMPTY（XEMPTY= 0）：1、自上一个DXR-XSR的复制发生以来，DXR1还没有被加载，在XSR（S）中数据字的所有位都已经被转移到了DX引脚上。

2、发送器被复位（强制SPCR2中的XRST=0，或者设备复位），然后重新启动在下溢条件下，对于每一个新的发送帧同步信号（S），发送器继续发送DXRs 中的旧数据，直到通过CPU或DMA控制器一个新的值被加载到DXR1中为止。

注意：如果两个DXRs是需要的（字长度大于16位），CPU或DMA控制器必须首先载入DXR2，然后加载DXR1。

只要DXR1被加载，这两个DXRs的内容将被复制到发送移位寄存器（XSRs）。

如果不首先加载DXR2，之前DXR2中的内容会被传递到XSR2。

在DXR1中的一个新字被转移到XSR1中时，XEMPTY位被停用（XEMPTY= 1）。

如果PCR中的FSXM=1而且SRGR2中的FSGM=0，发送器产生一个单一的内部FSX脉冲来响应DXR-XSR的复制。

否则，在DX上发送下一个帧之前，发送器必须等待下一个帧同步脉冲。

当发送器脱离复位时（XRST= 1），它是在一个发射准备（在SPCR2中XRDY= 1）和发送空数据（XEMPTY= 0）状态。

如果在内部FSX变为高电平之前，DXR1被CPU或DMA控制器加载，一个有效的的DXR-XSR复制过程会发生。

这使得第一帧的第一个字是有效的，即使是在发送帧同步脉冲产生或检测之前。