MBI5050 Preliminary Datasheet V1.01-CN
MC3413 Preliminary Datasheet (APS-048-0029v1.5)
GENERAL DESCRIPTIONThe MC3413 is a low-noise, integrated digital output 3-axis accelerometer with a feature set optimized for cell phones and consumer product motion sensing. Applications include user interface control, gaming motion input, electronic compass tilt compensation for cell phones, game controllers, remote controls and portable media products.Low noise and low power are inherent in the monolithic fabrication approach, where the MEMS accelerometer is integrated in a single-chip with the electronics integrated circuit.In the MC3413 the internal sample rate can be set from 0.25 to 256 samples / second. Specific tap or sample acquisition conditions can trigger an interrupt to a remote MCU. Alternatively, the device supports the reading of sample and event status via polling. FEATURESRange, Sampling & Power∙±2,4,8,12 or 16g ranges∙8, 10 or 14-bit resolution∙0.25 - 256 samples/sec∙50 - 130 μA typical currentEvent Detection∙Low-noise architecture minimizes false triggering∙Independent X,Y,Z TapSimple System Integration∙I2C interface, up to 400 kHz∙ 2 × 2 × 0.92 mm 12-pin package ‒Pin-compatible to Bosch BMA2xx ∙Single-chip 3D silicon MEMS∙<200µg / √Hz noiseTABLE OF CONTENTS1Order Information (4)1Functional Block Diagram (5)2Packaging and Pin Description (6)2.1Package Outline (6)2.2Package Orientation (7)2.3Pin Description (8)2.4Typical Application Circuit (9)2.5Tape and Reel (10)3Specifications (12)3.1Absolute Maximum Ratings (12)3.2Sensor Characteristics (13)3.3Electrical and Timing Characteristics (14)3.3.1Electrical Power and Internal Characteristics (14)3.3.2I2C Electrical Characteristics (15)3.3.3I2C Timing Characteristics (16)4General Operation (17)4.1Sensor Sampling (17)4.2Offset and Gain Calibration (17)4.3Tap Detection (17)5Operational States (18)6Operational State Flow (19)7Interrupts (20)7.1Enabling and Clearing Interrupts (20)7.2ACQ_INT Interrupt (20)8Sampling (21)8.1Continuous Sampling (21)9I2C Interface (22)9.1Physical Interface (22)9.2Timing (24)9.3I2C Message Format (24)9.4Watchdog Timer (25)10Register Interface (26)10.1Register Summary (27)10.2SR Status Register (29)10.3OPSTAT Device Status Register (30)10.4INTEN Interrupt Enable Register (31)10.5MODE Register (32)10.6SRTFR Sample Rate and Tap Feature Register (33)10.7TAPEN Tap Control Register (34)10.8TTTRX,TTTRY, TTTRZ X, Y and Z Tap Duration and Threshold Registers (35)10.9XOUT_EX, YOUT_EX & ZOUT_EX X, Y, Z-Axis Acceleration Registers (36)10.10OUTCFG Output Configuration Register (37)10.11X-Axis Offset Registers (38)10.12Y-Axis Offset Registers (39)10.13Z-Axis Offset Registers (40)10.14X-Axis Gain Registers (41)10.15Y-Axis Gain Registers (42)10.16Z-Axis Gain Registers (43)10.17PCODE Product Code (44)11Index of Tables (45)12Revision History (46)13Legal (47)2.5 TAPE AND REELDevices are shipped in reels, in standard cardboard box packaging. See Figure 6. MC3413 Tape Dimensions and Figure 7. MC3413 Reel Dimensions.∙Dimensions in mm.∙10 sprocket hole pitch cumulative tolerance ±0.2∙Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole.Figure 6. MC3413 Tape DimensionsFigure 7. MC3413 Reel DimensionsFigure 8. I2C Interface Timing10 REGISTER INTERFACEThe device has a simple register interface which allows a MCU or I2C master to configure and monitor all aspects of the device. This section lists an overview of user programmable registers. By convention, Bit 0 is the least significant bit (LSB) of a byte register.11 INDEX OF TABLESTable 1. Order Information (4)Table 2. Pin Description (8)Table 3. Absolute Maximum Ratings (12)Table 4. Sensor Characteristics (13)Table 5. Electrical Characteristics (14)Table 6. I2C Electrical and Timing Characteristics (15)Table 7. I2C Timing Characteristics (16)Table 8. Operational States (18)Table 9. Forcing Operational States (19)Table 10. I2C Address Selection (22)Table 11. Register Summary (28)Table 12. SR Status Register (29)Table 13. OPSTAT Device Status Register (30)Table 14. INTEN Interrupt Enable Register Settings (31)Table 15. MODE Register Functionality (32)Table 16. SRTFR Register Functionality (33)Table 17. TAPEN Register Settings (34)Table 18. TTTRX, TTTRY and TTTRZ Register Settings (35)Table 19. Extended Accelerometer Registers (36)Table 20. OUTCFG Resolution and Range Select Register Settings (37)13 LEGAL1. M-CUBE reserves the right to make corrections, modifications, enhancements, improvements and other changes to its products and to this document at any time and discontinue any product without notice. The information contained in this document has been carefully checked and is believed to be accurate. However, M-CUBE shall assume no responsibilities for inaccuracies and make no commitment to update or to keep current the information contained in this document.2. M-CUBE products are designed only for commercial and normal industrial applications and are not suitable for other purposes, such as: medical life support equipment; nuclear facilities; critical care equipment; military / aerospace; automotive; security or any other applications, the failure of which could lead to death, personal injury or environmental or property damage. Use of the produ cts in unsuitable applications are at the customer’s own risk and expense.3. M-CUBE shall assume no liability for incidental, consequential or special damages or injury that may result from misapplication or improper use of operation of the product.4. No license, express or implied, by estoppel or otherwise, to any intellectual property rights of M-CUBE or any third party is granted under this document.5. M-CUBE makes no warranty or representation of non-infringement of intellectual property rights of any third party with respect to the products. M-CUBE specifically excludes any liability to the customers or any third party regarding infringement of any intellectual property rights, including the patent, copyright, trademark or trade secret rights of any third party, relating to any combination, machine, or process in which the M-CUBE products are used.6. Examples of use described herein are provided solely to guide use of M-CUBE products and merely indicate targeted characteristics, performance and applications of products. M-CUBE shall assume no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein7. Information described in this document including parameters, application circuits and its constants and calculation formulas, programs and control procedures are provided for the purpose of explaining typical operation and usage. “Typical” parameters that may be provided in M-CUBE data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including “Typicals,” must be validated for each customer application by customer’s technical experts. In no event shall the information described be regarded as a guarantee of conditions or characteristics of the products. Therefore, the customer should evaluate the design sufficiently as whole system under the consideration of various external or environmental conditions and determine their applicatio n at the customer’s own risk. M-CUBE shall assume no responsibility or liability for claims, damages, costs and expenses caused by the customer or any third party, owing to the use of the above information.is a trademark of M-CUBE, Inc.M-CUBE and the M-CUBE logo are trademarks of M-CUBE, Inc.,All other product or service names are the property of their respective owners.© M-CUBE, Inc. 2014. All rights reserved.。
IHLP5050CEER100M06;IHLP5050CEER1R0M06;IHLP5050CEER1R5M06;中文规格书,Datasheet资料
FEATURES • Lowest height (3.5 mm) in this package footprint • Shielded construction • Frequency range up to 5.0 MHz • Lowest DCR/µH, in this package size • Handles high transient current spikes without
DESCRIPTION
IHLP-5050CE-06
1.0 µH
MODEL
INDUCTANCE VALUE
± 20 % INDUCTANCE TOLERANCE
ER
e3
PACKAGE CODE JEDEC LEAD (Pb)-FREE STANDARD
GLOBAL PART NUMBER
I
H
L
P
5
0
5
STANDARD ELECTRICAL SPECIFICATIONS
L0 INDUCTANCE ± 20 % AT 100 kHz,
0.25 V, 0 A (µH)
DCR ± 10 % AT 25 °C (mΩ)
HEAT RATING CURRENT DC TYP.
(A) (3)
SATURATION
(FPGA)
DIMENSIONS in inches [millimeters]
0.508 [12.9] Max.
0.138 [3.5] Max.
0.091 ± 0.01 [2.3 ± 0.3]
Typical Pad Layout
0.195 [4.95]
0.542 [13.76]
0.310 [7.87]
MBI5051 preliminary datasheet V1.00-SC
©Macroblock, Inc. 2012Floor 6-4, No.18, Pu-Ting Rd., Hsinchu, Taiwan 30077, ROC.特色z 与MBI5050封装相容 z 操作电压：3~5.5伏特 z 16个恒流输出通道z恒流输出范围值：-在5伏特操作电压：2~45mA -在3.3伏特操作电压：2~30mAz 极为精确的电流输出值： 通道间一般差异值：<±1.5％ 芯片间一般差异值：<±3％z 内建4K 位SRAM 内存支持1~8扫分时多任务扫描 z 16/14位PWM 灰阶控制 z 扫描S-PWM 技术可提升视觉更新率 z LED 开路侦测 z 内建消隐z GCLK 倍频技术z 6位可程控之电流增益功能z 输出通道间的交错时间迟滞，可避免突波电流 z 高达 30MHz 时钟频率 z具 Schmitt trigger 输入装置产品说明MBI5051是专为LED 全彩显示屏应用设计的驱动芯片，可选择内建16位或是14位灰阶控制的脉波宽度调变功能。
MBI5051内建16位位移寄存器可以将串行的输入资料转换成每个输出通道的灰阶像数。
而且，MBI5051的16个恒流输出通道所输出的电流值不受输出端负载电压影响，并提供一致并且恒定的输出电流。
MBI5051的使用者可以经由选用不同阻值的外接电阻来调整MBI5051各输出级的电流大小。
除此之外，MBI5051的使用者还可以藉由可程序化的电流增益调整来调整64阶的整体LED 的驱动电流。
MBI5051内建SRAM 的创新架构，可支持最高8扫LED 扫描屏。
使用者仅需送一次完整的帧数据(frame data)，并储存在LED 驱动芯片内的SRAM 。
此方式不但可节省数据频带，也可在非常低的数据时钟频率下达到高灰阶的效果。
藉由Scrambled-PWM (S-PWM) 的技术，MBI5051可加强脉波宽度调变的功能，并将导通的时间分散成数个较短的导通时间，进而增加了扫描屏的视觉更新率。
MBI6654 Preliminary Datasheet V1.00-SC
©Macroblock, Inc. 2011Floor 6-4, No.18, Pu-Ting Rd., Hsinchu, Taiwan 30077, ROC.特色z 输入电压范围6~36伏特 z 最大1A 输出恒流z 支援4段开关调光及PWM 调光z 串3颗LED ，350mA 电流，输入电压为12V 时的效率可达97% z 使用Hysteretic PFM ，不需外部补偿设计 z 内建0.3Ω低导通电阻的开关z全方位保护包括：欠压锁定(UVLO)、启动过流保护(Start-Up)、过电流(OCP)、过热断电 (TP)、LED 开路与短路保护产品说明MBI6654为恒流、高亮度、降压型直流对直流转换器，可提供LED 室内/户外照明应用具成本效益的解决方案，为大电流LED 照明提供稳定之电流。
MBI6654使用Hysteretic PFM 架构设计，不需要外部补偿电路，因此可简化电路设计。
MBI6654的输出电流可透过不同阻值的外接电阻来调整各输出级的电流大小，且可在DIMD 脚连接脉宽调变(PWM)讯号进行调光控制。
此外，MBI6654利用新的电源线设计，让使用者在不需额外调光讯号的情况下，即可透过触发输入电压进行4段模拟调光。
MBI6654的特色还包括一系列完整的IC 保护装置。
启动过流保护装置(Start-Up)功能可限制IC 因电源启动时所产生的突波电流。
欠压锁定(UVLO)装置、过热断电装置(TP)和过电流(OCP)装置可确保系统稳定度，且LED 开路与短路保护机制也可避免IC 在不正常运作的情况下损毁。
MBI6654目前提供散热性佳的MSOP-8L 和SOP-8L 两种封装。
应用z 简易型可调光轻钢架/平版灯 z 需简单调光控制的台灯 z 恒流照明源z 培育植物用的照明灯具GD: SOP8L-150-1.27MBI6654 MBI6654MBI6654GD MBI6654GMS电气特性测试电路图(a) (b)(c)(d)V INV SWV OUTI OUT图2. 启动时波形图(V IN=12V, V OUT= 3.2V, R SEN=0.28Ω) 1. MBI6654应用电路中的等效阻抗V IN V DIMP I OUT欠压锁定电压临界值记忆状态门坎100%50%25%12.5%图6. 开关调光的波形图LED开路保护机制MBI6654内建LED开路保护。
VC7916_Preliminary_DS_V1.0
PreliminaryDatasheet Vanchiptech ConfidentialRF Power Amplifier For Quad ‐Band GSM/GPRS/EDGE /TD ‐SCDMA/TD ‐LTE WithSP16T Antenna SwitchProduct ID ：VC7916Version ：V1.0VC7916Vanchip TechnologiesVersion 1.0VC7916Vanchip TechnologiesVersion 1.0Revision HistoryVersion Date Author Modify Description 1.0Aug 2015VanchipPreliminary ReleasePreliminary Datasheet Vanchiptech Confidential2VC7916Featuresz Small package: 5.5 x 5.3 x 0.83mmz8KV ESD Protection at Antenna Portz MIPI RFFE Digital Interfacez Integrate Antenna Switchesz High Linear EDGE Operationz High Efficiency–GSM850/GSM900 38%–DCS1800/PCS1900 32%z14 Low Insertion Loss TRx Portz TRX Ports interchangeable and DC‐Block capacitor lessz Integrated Low Pass TX Harmonic Filter z Advanced HBT/CMOS/SOI Process z GPRS multi‐mode capability Class 12z Support TD‐SCDMA B34/B39z Support TDD‐LTE B39 Product DescriptionThe VC7916is a high‐power, high‐efficiency transmit and receive Front‐End Module for Quad‐bandGSM850/GSM900/DCS1800/PCS1900 operation . The FEM also support Class 12 GPRS multi‐slot operation ,linear EDGEoperation ,TD‐SCDMA HSPA and TDD‐LTE.This FEM builds upon Vanchip’s unique power amplifier technology to provide maximum efficiency and Pout, build in current and voltage regulating technology stable TRP performance under load mismatch. Integrated antenna switch module reduce PCB size, interchangeable TRX ports are easy for layout and application. The module provides 50ohm matched input and output ports and integrated TX low pass filter can achieve best‐in class harmonic performance.The VC7916 can sustain 8KV ESD at Antenna port, without external components needed. The module can sustain 20:1 VSWR on Antenna Port under mismatch condition.Vanchip TechnologiesVersion 1.0Preliminary DatasheetVanchiptech Confidential3VC7916 Function Block DiagramPreliminary Datasheet Vanchiptech Confidential4Absolute Maximum RatingsRecommended Operating ConditionsVanchip TechnologiesParameterRatingUnitSupply‐0.3 to +6V Power Control Voltage (Vramp)‐0.3 to +1.8V Input RF Power 10dBm Max Duty Cycle 50%Output Load VSWR20:1Operating Case Temperature ‐25 to +85°C Storage Temperature ‐55 to +150°C ESD Antenna Port8kV ESD All Pins (Charge Device Model)1000V ESD All Pins (Human Body Model)1000VVC7916Version 1.0ParameterMinTyp.MaxUnitTest ConditionSupply Voltage VCC 3.1 3.5 4.35V Supply Voltage VBATT 3.1 3.5 4.35V MIPI Supply 1.7 1.8 1.9V Vramp ≤1.8V MIPI Signal Level 00.2*VIO V Signal Level Low 0.8*VIO1.8VIO V Signal Level High Leakage Current 20uA Applied DC Only ：VCC=VBATT=4.35V ，TRx Mode Current 100300uA Operating temperature‐20+25+85°CPreliminary Datasheet Vanchiptech Confidential5Vanchip TechnologiesVC7916Version 1.0MIPI RFFE REGISTER MAPRegister AddressData Bit Description Default Notes0x0000[7:5]Reserved000Reserved [4:0]Mode Control 00000Standby=0x00LB_GMSK Tx=0x0AHB_GMSK Tx=0x0ELB_EDGE Tx=0x0BHB_EDGE Tx=0x0FTD ‐SCDMA/TDD LTE Tx=0x0F TRx1=0x10TRx2=0x18TRx3=0x03TRx4=0x02TRx5=0x01TRx6=0x05TRx7=0x09TRx8=0x0D TRx9=0x04TRx10 = 0x08TRx11 = 0x14TRx12 = 0x1C TRx13 = 0x11TRx14 = 0x19Isolation=0x06Isolation=0x07Isolation=0x0C 0x0001[7:4]High BandVreg Reference10000000=2.6V0001=2.65V0100=2.80V0111=2.95V1010=3.10V1101=3.25V 0010=2.70V0101=2.85V1000=3.00V1011=3.15V1110=3.30V0011=2.75V 0110=2.90V 1001=3.05V 1100=3.20V 1111=3.35V [3:0]Low BandVreg Reference10000000=2.6V0001=2.65V0100=2.80V0111=2.95V1010=3.10V1101=3.25V0010=2.70V0101=2.85V1000=3.00V1011=3.15V1110=3.30V0011=2.75V 0110=2.90V 1001=3.05V 1100=3.20V 1111=3.35V0x0002[7:0]Reserved 0x00Reserved 0x0003[7:0]Reserved 0x00Reserved 0x0004[7:0]Reserved 0x00Reserved0x001C[7:6]PWR_MODE 0000=Normal Operation (ACTIVE)01=Default Settings (STARTUP)10=Low Power (LOW POWER) 11=Reserved[5]Trigger_Mask_210:Trigger Enable 1:Trigger Disable [4]Trigger_Mask_110:Trigger Enable 1:Trigger Disable [3]Trigger_Mask_010:Trigger Enable 1:Trigger Disable [2]Trigger_20Not Support [1]Trigger_10Reserved[0]Trigger_001 = Latch Register 0, 1 contents 0x001D [7:0]Product_ID0x85Product ID = 0x850x001E [7:0]Manufacturer_ID[7:0]0x38Manufacture ID[7:0] = 0x380x001F[7:6]Reserved00Reserved[5:4]Manufacturer_ID[9:8]11Manufacture ID[9:8] = 0x11[3:0]USID1111USID = 1111Preliminary Datasheet Vanchiptech Confidential6Test Condition:Frequency= 824 to 849 MHz, Temperature= 25°C , Vbat= 3.5V, Pin= 3dBm,Vramp=1.8VElectrical Specifications （GSM850 GMSK Mode ）Vanchip Technologies*External filter can optimize high order harmonic performanceVC7916ParameterMin.Tpy.Max.UnitConditionOperation Frequency 824849MHz Input Power 036dBm Max Pout should guaranteed at Min input power.Max output power 3334dBm Nominal Condition31.0dBmExtreme Condition (Temperature range ‐20 to 85°C )Input VSWR 2.5:1Pout=5 to 33dBm Pin ≤6dBmEfficiency38%Pout=33dBm; duty cycle = 1:8Max Supply Current under mismatch 2.3A VSWR=10:1; Vramp=Vramp_rated Forward Isolation 1‐52 ‐45dBm Pin=6dBm, Vramp=0.16V Forward Isolation 2‐15dBm Pin=6dBm, Vramp=0.16V 2nd Harmonic*‐40‐33dBm Pout ≤33dBm 3rd Harmonic*‐40‐33dBm Pout ≤33dBm All other harmonic*（< 12.75GHz ）‐33dBm Pout ≤33dBmAll other non ‐harmonic *（<12.75GHz ）‐36dBm Pout=5 to 33dBm Pin ≤6dBmNoise Power‐84dBmƒ=869 to 894MHz, Pout=33dBm, RBW=100KHz‐83dBmƒ=1930 to 1990MHz, Pout=33dBm, RBW=100KHzVersion 1.0Preliminary Datasheet Vanchiptech Confidential7Test Condition:Frequency= 880 to 915 MHz, Temperature= 25°C , Vbat= 3.5V, Pin= 3dBm, Vramp= 1.8VElectrical Specifications （GSM900 GMSK Mode ）Vanchip TechnologiesParameterMin.Tpy.Max.UnitConditionOperation Frequency 880 915MHz Input Power 036dBm Max Pout should guaranteed at Min input power.Max output power 3334dBm Nominal Condition31.5dBmExtreme Condition (Temperature range ‐20 to 85°C )Input VSWR 2.0:1Pout=5 to 33dBm Pin ≤6dBmEfficiency38%Pout=33dBm; duty cycle = 1:8Max Supply Current under mismatch 2.3A VSWR=10:1; Vramp=Vramp_rated Forward Isolation 1‐52 ‐48 dBm Pin=6dBm, Vramp=0.16V Forward Isolation 2‐15dBm Pin=6dBm, Vramp=0.16V 2nd Harmonic*‐40‐33dBm Pout ≤33dBm 3rd Harmonic*‐40‐33dBm Pout ≤33dBm All other harmonic*（< 12.75GHz ）‐33dBm Pout ≤33dBmAll other non ‐harmonic *（<12.75GHz ）‐36dBm Pout=5 to 33dBm Pin ≤6dBmNoise Power‐84dBmƒ=925 to 935MHz, Pout=33dBm, RBW=100KHz‐84dBm ƒ=935 to 960MHz, Pout=33dBm, RBW=100KHz Operation Frequency‐83dBmƒ=1805 to 1880MHz, Pout=33dBm, RBW=100KHz* External filter can optimize high order harmonic performanceVC7916Version 1.0Preliminary Datasheet Vanchiptech Confidential 8Test Condition:Frequency= 1710 to 1785 MHz, Temperature= 25°C, Vbat= 3.5V, Pin= 3dBm,Vramp= 1.8V Vanchip TechnologiesParameter Min.Tpy.Max.Unit ConditionOperation Frequency1710 1785MHzInput Power036dBm Max Pout should guaranteed at Min input power.Max output power 3032dBm Nominal Condition28dBmExtreme Condition (Temperature range ‐20 to85°C)Input VSWR 2.0:1Pout=5 to 30dBm Pin≤6dBm Efficiency32%Pout=30dBm; duty cycle = 1:8 Max Supply Current undermismatch1.5A VSWR=10:1; Vramp=Vramp_rated Forward Isolation 1‐50‐46dBm Pin=6dBm, Vramp=0.16V Forward Isolation 2‐15dBm Pin=6dBm, Vramp=0.16V2nd Harmonic*‐40‐33dBm Pout≤30dBm3rd Harmonic*‐40‐33dBm Pout≤30dBmAll other harmonic*（< 12.75GHz）‐33dBm Pout≤30dBmAll other non‐harmonic*（<12.75GHz）‐36dBm Pout=5 to 30dBm Pin≤6dBmNoise Power ‐84dBmƒ=925 to 935MHz, Pout=30dBm, Pin=6dBm,RBW=100KHz‐84dBmƒ=935 to 960MHz, Pout=30dBm, Pin=6dBm,RBW=100KHzOperation Frequency‐83dBm ƒ=1805 to 1880MHz, Pout=30dBm, Pin=6dBm, RBW=100KHzVC7916Electrical Specifications（DCS1800 GMSK Mode）* External filter can optimize high order harmonic performanceVersion 1.0Preliminary Datasheet Vanchiptech Confidential9Test Condition:Frequency= 1850 to 1910 MHz, Temperature= 25°C , Vbat= 3.5V, Pin= 3dBm, Vramp= 1.8V,Vanchip TechnologiesVC7916Electrical Specifications （PCS1900 GMSK Mode ）*External filter can optimize high order harmonic performanceParameterMin.Tpy.Max.UnitConditionOperation Frequency 1850 1910MHz Input Power 036dBm Max Pout should guaranteed at Min input power.Max output power 3032dBm Nominal Condition28.5dBmExtreme Condition (Temperature range ‐20 to 85°C )Input VSWR 2.5:1Pout=5 to 30dBm Pin ≤6dBmEfficiency32%Pout=30dBm; duty cycle = 1:8Max Supply Current under mismatch 1.5A VSWR=10:1; Vramp=Vramp_rated Forward Isolation 1‐50‐46dBm Pin=6dBm, Vramp=0.16V Forward Isolation 2‐15dBm Pin=6dBm, Vramp=0.16V 2nd Harmonic*‐40‐33dBm Pout ≤30dBm 3rd Harmonic*‐40‐33dBm Pout ≤30dBm All other harmonic*（< 12.75GHz ）‐33dBm Pout ≤30dBmAll other non ‐harmonic *（<12.75GHz ）‐36dBm Pout=5 to 30dBm Pin ≤6dBmNoise Power‐84dBmƒ=869 to 894MHz, Pout=30dBm, Pin=6dBm, RBW=100KHz‐83dBmƒ=1930 to 1990MHz, Pout=30dBm, Pin=6dBm, RBW=100KHzVersion 1.0Test Condition:Frequency= 824 to 949 MHz, Temperature= 25°C , Vbat= 3.5V, Pin adjusted for required Pout, Vramp = 1.8VVanchip TechnologiesParameterMin.Tpy.Max.UnitConditionOperation Frequency 824849MHzInput VSWR2.5:1Max output power（Meet EVM and ACPR Spec ）27.5dBm Vramp= 1.8V Gain 34dB Pout=27.5dBmEfficiency18%Pout=27.5dBm; duty cycle = 1:8Max Supply Current 880mA Pout=27.5dBmACPR ‐60‐57dBc At 400kHz in 30kHZ BW, Pout =27.5dBm EVM RMS5%Pout=27.5dBm Max Noise Power under mismatch‐36dBm Load VSWR=10:1Noise Power-84dBmƒ=869 to 894MHz, Pout=27.5dBm, RBW=100KHz -83dBmƒ=1930 to 1990MHz, Pout=27.5dBm, RBW=100KHzVC7916Electrical Specifications （GSM850 EDGE Mode ）Version 1.0Preliminary Datasheet Vanchiptech Confidential10Test Condition:Frequency= 880 to 915 MHz, Temperature= 25°C , Vbat= 3.5V, Pin adjusted for required Pout, Vramp = 1.8VVanchip TechnologiesParameterMin.Tpy.Max.UnitConditionOperation Frequency 880915MHzInput VSWR2.5:1Max output power（Meet EVM and ACPR Spec ）27.5dBm Vramp= 1.8V Gain 34dB Pout=27.5dBmEfficiency18%Pout=27.5dBm; duty cycle = 1:8Max Supply Current 880mA Pout=27.5dBmACPR ‐60‐57dBc At 400kHz in 30kHZ BW, Pout =27.5dBm EVM RMS5%Pout=27.5dBm Max Noise Power under mismatch‐36dBm Load VSWR=10:1Noise Power‐84dBm ƒ=925 to 935MHz, Pout=27.5dBm, RBW=100KHz ‐84dBm ƒ=935 to 960MHz, Pout=27.5dBm, RBW=100KHz ‐83dBmƒ=1805 to 1880MHz, Pout=27.5dBm, RBW=100KHzVC7916Version 1.0Electrical Specifications （GSM900 EDGE Mode ）Preliminary Datasheet Vanchiptech Confidential11Test Condition:Frequency= 1710 to 1785 MHz, Temperature= 25°C, Vbat= 3.5V, Pin adjusted for required Pout, Vramp= 1.8VVanchip TechnologiesParameter Min.Tpy.Max.Unit Condition Operation Frequency1710 1785MHzInput VSWR 2.5:1Max output power（Meet EVM and ACPR Spec）26.5dBm Vramp= 1.8VGain34dB Pout=26.5dBmEfficiency16%Pout=26.5dBm; duty cycle = 1:8Max Supply Current830mA Pout=26.5dBmACPR‐60‐57dBc At 400kHz in 30kHZ BW, Pout =26dBm EVM RMS5%Pout=26.5dBmMax Noise Power under mismatch‐36dBm Load VSWR=10:1Noise Power ‐84dBmƒ=925 to 935MHz, Pout=26dBm, RBW=100KHz‐84dBmƒ=935 to 960MHz, Pout=26dBm, RBW=100KHz‐83dBmƒ=1805 to 1880MHz, Pout=26dBm, RBW=100KHzVC7916Electrical Specifications（DCS1800 EDGE Mode）Version 1.0Preliminary DatasheetVanchiptech Confidential12Test Condition:Frequency= 1850 to 1910 MHz, Temperature= 25°C , Vbat= 3.5V, Pin adjusted for required Pout, Vramp = 1.8VVanchip TechnologiesParameterMin.Tpy.Max.UnitConditionOperation Frequency 18501910MHzInput VSWR2.5:1Max output power（Meet EVM and ACPR Spec ）26dBm Vramp= 1.8V Gain 33dB Pout=26.5dBmEfficiency16%Pout=26.5dBm; duty cycle = 1:8Max Supply Current 830mA Pout=26.5dBmACPR ‐60‐57dBc At 400kHz in 30kHZ BW, Pout =26.5dBm EVM RMS5%Pout=26.5dBm Max Noise Power under mismatch‐36dBm Load VSWR=10:1Noise Power‐84dBmƒ=869 to 894MHz, Pout=26dBm, RBW=100KHz‐83dBmƒ=1930 to 1990MHz, Pout=26dBm, RBW=100KHzVC7916Electrical Specifications （PCS1900 EDGE Mode ）Version 1.0Preliminary Datasheet Vanchiptech Confidential13Vanchip Technologies VC7916Version 1.0Preliminary DatasheetVanchiptech Confidential14Test Condition:Frequency= 1880 to 1920MHz, 2010 to 2025MHz, Temperature= 25°C, Vbat= 3.5V, Vramp=0V Parameter Min.Tpy.Max.Unit ConditionOperation Frequency 1880 1920MHz 2010 2025MHzGain28dB Pout=25dBmGain Flatness ±0.5dB Pout≤25dBm (HPM)±0.5dB Pin=‐35dBm (LPM)ACLR(±1.6MHz Offset)‐40‐36dBc Pout=25dBmACLR(±3.2MHz Offset)‐57‐48dBc Pout=25dBmEVM5%Pout=25dBmInput VSWR 2.5:1Pout=25dBmNormal Working Current550mA Pout=25dBmNoise Power925MHz to 935MHz‐77dBm Pout=24dBm, RBW=100kHz 935MHz to 965MHz‐83dBm Pout=24dBm, RBW=100kHz 1805MHz to 1880MHz‐75dBm Pout=24dBm, RBW=100kHz All other harmonic* (< 12.75GHz)‐33dBm Pout=24dBm Electrical Specifications（TD-SCDMA Mode）*External filter can optimize high order harmonic performanceVanchip Technologies VC7916Version 1.0Preliminary DatasheetVanchiptech Confidential15Electrical Specifications（TD-LTE Mode）TDD‐LTE Band 39VBAT =3.5 V at Room Temperature +25 °C, Vramp=0VTest LTE signal with QPSK/10MHz/12RBCharacteristics Min Typical Max Unit Test Condition Operating Frequency188019001920MHzMaximum Output Power (Pout_Max)25dBm MPR = 0 (3GPP TS36.101) Gain29dB Pout=25dBm Gain Flatness0.5dB Pout=25dBm Power Added Efficiency17%Pout=25dBm Supply Current530mA POUT = 25 dBm, VBAT = 3.5 VAdjacent Channel Leakage power Ratio ‐42‐33dBc ACLR_EUTRA (Pout=25dBm)‐42‐36dBc ACLR1_UTRA‐52‐43dBc ACLR2_UTRAHarmonic Suppression ‐40‐33dBm2nd Harmonic‐40‐33dBm3rd Harmonic‐33dBm All other harmonics up to 12.75GHzEVM 3.5%Pout = Pout_Max, Load = 50 ohms DC ON/OFF Time10usRF ON/OFF Time6usInput VSWR 1.2:1 1.8:1—Stability (Spurious output)‐36dBm At load VSWR = 10:1, all phases, RBW 1MHzPOUT≤25dBm Ruggedness 20:1—No damage or Permanent Degradation at POUT≤25dBmTest Condition:Temperature = 25°C , Vbat = 3.5V, Vramp = 0VVanchip TechnologiesVC7916Electrical Specifications （TRX Mode ）Version 1.0Preliminary Datasheet Vanchiptech Confidential16UMTS RF Ports TRx1 to TRx14Parameter Minimum Typical Maximum Unit Conditions Frequency Range 699—2690MHz Insertion Loss—0.7 1.0dB 699 MHz to 960 MHz —1 1.4dB 1710 MHz to 1990 MHz — 1.4 1.8dB 2010 MHz to 2690 MHzTRx Mode Return Loss——‐12dB NTCIsolation( Active TRx port to any adjacent TRx port )2632—dB 699 MHz to 960 MHz 2228—dB 1710 MHz to 1990 MHz 2022—dB 2010 MHz to 2690 MHz Isolation( Active TRx port to any non ‐adjacent TRx port )3540—dB 699 MHz to 960 MHz 3035—dB 1710 MHz to 1990 MHz 2528—dB 2010 MHz to 2690 MHz TRx Harmonics (2fo, 3fo )——‐55dBm Pwr_in_at TRx Port = +27 dBmSecond Order Intermodulation Distortion (IMD2)——‐105dBmPin = 20dBm; CW Blk Power = ‐15dBmThird Order Intermodulation Distortion (IMD3)——‐105dBm Leakage power from Tx to TRx Ports ——5dBm Any TX Mode Coupling Factor in TRx Mode‐27dB 699 to 960 MHz ‐23dB 1710 to 1990 MHz ‐22dB 2010 to 2690 MHzCoupling Factor Variation over Output VSWR 1.0‐1.0dB699 to 2690 MHz, VSWR 3:1 at ANT portEVBSchematicillustrationVanchip TechnologiesNote:1. ALL RF Input and output Trace with 50 Ohm microstrip ‐line.2. ANT Port reserve PI type component for improve harmonic performance3. RFIN LB and RFIN HB DC ‐Block less.4. All TRX port DC ‐Block less.VC7916Version 1.0Preliminary Datasheet Vanchiptech Confidential17EVB illustrationVanchip TechnologiesVC7916Version 1.0Preliminary Datasheet Vanchiptech Confidential185.50±0.1m mPart NumberDate Code Trace Code0.83±0.075Pin 15.3±0.1mmVanchip TechnologiesVC7916Pad layout as seen from Top View looking through packageVersion 1.0Package InformationPreliminary Datasheet Vanchiptech Confidential19GNDGNDTRx14TRx13TRx12TRx11GNDGNDANTTRx10TRx9TRx8TRx7TRx6TRx5TRx4TRx3TRx2TRx1GNDNC GND CPL GND GND GND GND GNDGNDTX_LB_INTX_HB_INGNDVIOSDATASCLKVRAMPVCCVBATTPadName DescriptionGnd_PadGND 1,4,11–16,18,20,21,23,38 areground pin;Ground PAD Grid under Device 2 Tx_LB_IN Input Txsignal 824MHz–915 MHz3 Tx_HB_INInput Txsignal 1710MHz–2025MHz5SCLK MiPi Clock 6 SDATA MiPi Data 7 VIO MiPi Power Supply8 VRAMPGMSK Controls GMSK power;EDGE, TD ‐SCDMA, TDD ‐LTE bias 9 VCC Battery supply voltage 10 VBAT Battery supply voltage 17CPL Directional coupler RF output 22 ANT PA output to Antenna 19NC Not connect24~37TRx1~14Wideband TRx switch portVanchip TechnologiesVC7916Note:Unless otherwise specified1.All DIMENSIONS ARE IN MILLMETERS.2.DIMENSIONS AND TOLERANCING IN ACCORDANCE WITH ASME Y14.5M ‐1994.Version 1.0Preliminary Datasheet Vanchiptech Confidential20Package Outline （Unit: mm ）Vanchip Technologies VC7916 Note: Unless otherwise specified1.All DIMENSIONS ARE IN MILLMETERS.2.DIMENSIONS AND TOLERANCING IN ACCORDANCE WITH ASME Y14.5M‐1994.Version 1.0Preliminary DatasheetVanchiptech Confidential21PCB Layout Footprint Recommendation（Unit: mm）For PCB Metal/ StencilPin to Pin Pitch: 0.48L: 0.65W: 0.23For PCB Solder maskPin to Pin Pitch: 0.48L: 0.750W: 0.33VC7916Vanchip Technologies Tape and ReelVC7916 carrier tape basic dimensions are based on EIA 481.The pocket is designed to hold the part for shipping and loading onto SMT manufacturing equipment,while protecting the body and the solder terminals from damaging stresses.Prior to shipping,moisture sensitive parts (MSL level 2a ‐5a)are baked and placed into the pockets of the carrier tape.A cover tape is sealed over the top of the entire length of the carrier tape.The reel is sealed in a moisture barrier ESD bag with the appropriate units of desiccant and a humidity indicator card,which is placed in a cardboard shipping box.It is important to note that unused moisture sensitive parts need to be resealed in the moisture barrier bag.If the reels exceed the exposure limit and need to be rebaked,most carrier tape and shipping reels are not rated as bakeable at 125°C.Version 1.0Preliminary Datasheet Vanchiptech Confidential22。
宽带功放
Preliminary Technical DatasheetBroadband High-Power Instrumentation AmplifiersGT-1020A Microwave Power Amplifier100 MHz to 20 GHz34881 -Rev.A / US10121434881-R e v . A / U S 101214The Giga-tronics GT-1020A Microwave Power Amplifier incorporates broadband MMIC-based architecture. These state-of-the-art amplifiers are based on solid-state parallel MMIC design with exceptionally widebandwidth and high power. The unique circuit topology is highly reliable, with performance that excels where extremes of bandwidth and power are demanded.The Giga-tronics GT-1020A Microwave Power Amplifiers provide excellent pulse fidelity, low intermodulation distortion, high linearity and superior gain flatness without the warm-up time, drift or aging issues of traveling wave tube amplifiers (TWTA). They feature low noise figure, low harmonics and spurious content, and are highly tolerant to load mismatch.1•100 MHz to 20 GHz eliminates band switching, reduces cost and complexity Solid-state technology for low noise, high reliability and long life• Ideal for R&D Lab, ATE Systems, Wireless Communications and Defense EW applications•34881-R e v . A / U S 101214The Giga-tronics GT-1020A Microwave Power Amplifiers offer linear high-power amplification across multi-octive bands. They are ideal for testing in R&D Lab, ATE Systems, wireless communications applications and Defense EW systems. The 100 MHz to 20 GHz frequency range allows broadband testing without band switching or swapping narrow band amplifiers resulting in faster and more accurate testing.The amplifiers can be used in wireless communications and component testing wherever a highly linear amplifier is needed. These microwave power amplifiers with excellent pulse fidelity are ideal for many Aerospace and Defense applications, including EW, ECM, ECCM, radar and satellite system signal simulation and testing. The GT-1020A is an ideal ATE system building block for boosting test signals to overcome cable and connector loss whenever long cable runs are needed in assembly bays, environmental test chambers or field locations.The amplifier typically provides 35 dB of gain over the 100 MHz to 20 GHz frequency range. The GT-1020A can be paired with a Giga-tronics 2420C 20 GHz Microwave Signal Generator or Giga-tronics 2520B 20 GHz Microwave Signal Generator, increasing the overall output power while preserving the synthesizer’s fast switching speed, modulation, and high signal fidelity.234881-R e v . A / U S 101214Frequency RangeGT-1020A100 MHz to 20 GHz, operational to 10 MHzOutput PowerOutput power is specified as minimum saturated power into 50 Ohm load with +5 dBm input, at 23°C ± 5°C Input power for normal operation should be limited to 0 dBm maximum.RangeSpecifications*100 MHz to 10 GHz +28 dBm (600 mW) typical, +26 dBm (400 mW) minimum 10 to 20 GHz+27 dBm (500 mW) typical, +25 dBm (300 mW) minimum* Output power at 1 dB compression > +20 dBm (100 mW)Gain FlatnessNominal gain is 35 dB, minimum gain > 25 dB.Gain flatness is specified as maximum variation with -5 dBm input and 50 Ohm load.RangeSpecifications100 MHz to 20 GHz± 2.5 dB typical, ±3.5 dB maximum334881-R e v . A / U S 1012144Input and Output VSWR100 MHz to 20 GHzInput, 50 ohms 2.0:1 typical Output, 50 ohms2.0:1 typicalAdditional SpecificationsParameter Specifications StabilityUnconditionally Stable Maximum Load VSWR 3:1Maximum Input Power +20 dBmThird Order Intercept +35 dBm typical, referenced to output Harmonic Distortion*< -30 dBc typical Spurious*< -60 dBc typical Reverse Isolation > 50 dBNoise Figure< 5 dB typical, < 7 dB maximum* Note: Harmonics measured at +10 dBm output power. Spurious measured at -5 dBm input power levelGeneral SpecificationsLine Voltage 100 to 240 VAC, 47 to 440 Hz, Single Phase Line Power100 VA maximum Operating Temperature 0°C to +50°C Storage Temperature -20°C to +75°CDimensions 2.5” H x 6.8” D x 7.0” W (64 mm H x 173 mm D x 178 mm W) Weight 4.5 lbs (2 kg)RF ConnectorsSMA (f)34881-R e v . A / U S 101214Ordering InformationGiga-tronics has a network of RF and Microwave instrumentation sales engineers and a staff of factory support personnel to help you find the best, most economical instrument for your specific applications. In addition to helping you select the best instrument for your needs, our staff can provide quotations, assist you in placing orders, and do everything necessary to ensure that your business transactions with Giga-tronics are handled efficiently.Model NumberFrequency RangeGT-1020AMicrowave Power Amplifier, 100 MHz to 20 GHzGiga-tronics Support ServicesAt Giga-tronics, we understand the challenges you face. Our support services begin from the moment you call us. We help you achieve both top-line growth and bottom-line efficiencies by working to identify your precise needs and implement smart and result orientated solutions. We believe and commit ourselves in providing you with more than our superior test solutions. For technical support, contact:Tel: 1-800-726-GIGA (4442) or (925) 328-4669Email: support@UpdatesAll data is subject to change without notice. For the latest information on Giga-tronics products and applications, please visit out website:534881-R e v . A / U S 101214©2010 Giga-tronics Incorporated. All Rights Reserved. All trademarks are the property of their respective owners.。
HS8916_V0.6_Datasheet Preliminary
QUAD-BAND GSM/GPRS/EDGE W Multi-Mode Transmit Module with Fourteen Linear TRx Switch Ports andDual-Band TD-SCDMA B34/39 and TDD LTE B39HS8916 Preliminary DatasheetVersion 0.62016-03-21HS8916 Front-end ModuleProduct Features ApplicationsG N DG N DG N DG N DG N DC P LG NDN CTRX10ANT TRX9TRX8GND GNDGND TRX11TRX12TRX13TRX14•LGA: 5.5 mm x 5.3 mm x 0.85 mm Max•Fully programmable MIPI RFFE control •Fourteen low -insertion-loss TRx ports (fiveultra-low loss) with enhanced linearity, for state-of-the-art 4G performance and GPS /•Cellular handsets encompassing Quad -Band GSM/EDGE, Dual-Band TD-SCDMA, and TDD LTE- Class 4 GSM850/900 - Class 1 DCS1800/PCS1900Product DescriptionThe HS8916 is a high-power, high-efficiency Front-End Module for GSM850/900, DCS1800, PCS1900 operation. The FEM supports Class.12 General Packet Radio Service (GPRS), EDGE multi-slot operation, and TD-SCDMA and TDD LTE linear transmission.The module provides 50 ohm impedance at input and output ports, consists of a CMOS Controller, a SP16T RF switch, a power amplifier supporting GSM850/900, DCS1800/PCS1900, TD-SCDMA bands 34/39, and TDD LTE band 39. The module integrated Tx low pass harmonic filtering can achieve best harmonic performance.The HS8916 provides high-power and high-efficiency Pout for GSM850/900, DCS1800, PCS1900 operation mode. In EDGE and TD-SCDMA / TDD LTE linear modes, VRAMP voltage and MIPI-based bias settings optimize PA linearity and efficiency.Absolute Maximum RatingsMIPI RFFE REGISTER MAP (1 OF 2)MIPI RFFE REGISTER MAP (2 OF 2)Electrical Specifications – TX GSM850/900 Band, GSMK ModeElectrical Specifications – TX GSM850/900 Band, EDGE ModeElectrical Specifications – TX DCS1800/1900 Band, GMSK ModeElectrical Specifications – TX DCS1800/1900 Band, EDGE ModeElectrical Specifications – TX TD-SCDMA B39 BandElectrical Specifications – TX TDD LTE B39 BandElectrical Specifications – TX TD-SCDMA B34 BandElectrical Specifications – Ports TRx1 to TRx14 ModePin-Out DiagramT R X 7T R X 6T R X 5G N DT R X 1T R X 2T R X 3T R X 4HS8916 Application CircuitT R X 7T R X 6T R X 5G N DR X 1T R X 2T R X 3T R X 4Package DrawingThe HS8916 is encapsulated in a 5.5×5.3×0.85mm Land Grid Array (LGA) package on a laminate substrate. The HS8916 is RoHS compliant.。
MBI50_datasheet
ÓMacroblock, Inc. 2003· · · · · · · ··Current AccuracyBetween Channels Between ICsConditions < ±3%< ±6%I OUT = 10 mA ~ 60 mAProduct DescriptionMBI5026 is designed for LED displays. As an enhancement of its predecessor, MBI5016, MBI5026 exploits PrecisionDrive ™ technology to enhance its output characteristics. MBI5026 contains a serial buffer and data latches which convert serial input data into parallel output format. At MBI5026 output stage, sixteen regulated current ports are designed to provide uniform and constant current sinks for driving LEDs within a large range of Vf variations.MBI5026 provides users with great flexibility and device performance while using MBI5026 in their system design for LED display applications, e.g. LED panels. Users may adjust the output current from 5 mA to 90 mA through an external resistor, R ext , which gives users flexibility in controlling the light intensity of LEDs. MBI5026 guarantees to endure maximum 17V at the output port. The high clock frequency, 25 MHz, also satisfies the system requirements of high volume data transmission.Block DiagramTerminal DescriptionPin Configuration LESDI CLKSDOOUT0 1OUT OUT14 OUT15Equivalent Circuits of Inputs and OutputsLE terminalterminalCLK, SDI terminalSDO terminalOUTTiming DiagramTruth TableCLK SDIN = 01 23 45 67 89 1011 1213 1415LEOFF ON OFF ON OFF ON OFF ONOFF ONSDO : don ’t care1OUT OUT3 OUT15Maximum RatingsCharacteristicSymbol Rating Unit Supply Voltage V DD 0~7.0 V Input Voltage V IN -0.4~V DD + 0.4V Output Current I OUT +90 mA Output Voltage V DS -0.5~+20.0V Clock Frequency F CLK 25 MHz GND Terminal CurrentI GND1440 mACNS – type1.52 CF – type 1.30 Power Dissipation (On PCB, Ta=25°C)CP – type P D 1.11 W CNS – type82 CF – type 96 Thermal Resistance (On PCB, Ta=25°C) CP – typeR th(j-a) 112 °C/W Operating Temperature T opr -40~+85 °C Storage TemperatureT stg -55~+150°CRecommended Operating ConditionsTest Circuit for Electrical Characteristics※If the devices are connected in cascade and t r or t f is large, it may be critical to achieve the timing required for data transfer between two cascaded devices.Test Circuit for Switching CharacteristicsLVV IH = V IL =Timing Waveformt of t orOUTn OEApplication InformationConstant CurrentTo design LED displays, MBI5026 provides nearly no variations in current from channel to channel and from IC to IC. This can be achieved by:1) The maximum current variation between channels is less than ±3%, and that between ICs isless than ±6%.2) In addition, the current characteristic of output stage is flat and users can refer to the figureas shown below. The output current can be kept constant regardless of the variations of LED forward voltages (Vf). This performs as a perfection of load regulation.Adjusting Output CurrentThe output current of each channel (I OUT) is set by an external resistor, R ext. The relationship between I out and R ext is shown in the following figure.Also, the output current in milliamps can be calculated from the equation:I OUT is (625 / R ext) x 28.8, approximately,where R ext, in Ω, is the resistance of the external resistor connected to R-EXT terminal.The magnitude of current (as a function of R ext) is around 50mA at 360Ω and 25mA at 720Ω.Package Power Dissipation (P D)The maximum allowable package power dissipation is determined as P D(max) = (Tj – Ta) / R th(j-a). When 16 output channels are turned on simultaneously, the actual package power dissipation is P D(act) = (I DD x V DD) + (I OUT x Duty x V DS x 16). Therefore, to keep P D(act) ≤P D(max), the allowable maximum output current as a function of duty cycle is:I OUT = { [ (Tj – Ta) / R th(j-a) ] – (I DD x V DD) } / V DS / Duty / 16,where Tj = 150°C.(A) I out = 90mA, V DS = 1.0V, 16 output channels activeFor CNS type package, the thermal resistance is R th(j-a) = 82 (°C/W)For CF type package, the thermal resistance is R th(j-a) = 96 (°C/W)For CP type package, the thermal resistance is R th(j-a) = 112 (°C/W)(B) I out = 60mA, V DS = 0.8V, 16 output channels activeFor CNS type package, the thermal resistance is R th(j-a) = 82 (°C/W)For CF type package, the thermal resistance is R th(j-a) = 96 (°C/W)For CP type package, the thermal resistance is R th(j-a) = 112 (°C/W)The maximum power dissipation, P D(max) = (Tj –Ta) / R th(j-a), decreases as the ambient temperature increases.Load Supply Voltage (V LED)MBI5026 are designed to operate with V DS ranging from 0.4V to 1.0V considering the package power dissipating limits. V DS may be higher enough to make P D(act) > P D(max) when V LED= 5V and V DS = V LED– Vf, in which V LED is the load supply voltage. In this case, it is recommended to use the lowest possible supply voltage or to set an external voltage reducer, V DROP.A voltage reducer lets V DS = (V LED– Vf) – V DROP.Resistors or Zener diode can be used in the applications as shown in the following figures.。
MBI5030 Preliminary Datasheet V3.01a-CN
16 位位移缓存器
SDO
图 1
-2-
2008 年 05 月，V3.01
MBI5030
内建 PWM 之 16 位恒流 LED 驱动器
脚位图
GND SDI DCLK LE OUT0 OUT1 OUT2 OUT3 OUT 4 OUT 5 OUT6 OUT7 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VDD R-EXT SDO GCLK OUT15 OUT14 OUT13 OUT12 OUT11 OUT10 OUT9 OUT8
聚积科技 2008 台湾新竹市埔顶路 18 号 6F 之四 电话：+886-3-579-0068，传真：+886-3-579-7534 E-mail: info@ - 1 2008 年 5 月，V3.01
MBI5030
内建 PWM 之 16 位恒流 LED 驱动器
功能方块图
OUT0 OUT1 OUT14 OUT15
R-EXT
输出电流量调 节器
十六位 LED 错误数据
VDD 比较器 比较器 比较器 比较器
GCLK
16/12 位计 数器
16 同步 控制器 状态缓存器
16
16 灰阶映像数据
16
灰阶映像数据
灰阶映像数据
灰阶映像数据
LE
GND
16
缓冲存储器
16 16
SDI DCLK
VDD VIN IOUT VDS IGND GF包装 PD GFN包装 GF包装 Rth(j-a) Topr Tstg HBM(MIL-STD-883G Method 3015.7，人体静电模式) GFN包装
IC datasheet pdf-MBI5030,pdf(16-Channel pwm-Embedded LED Driver)
Macroblock, Inc. 2006Floor 6-4, No.18, Pu-Ting Rd., Hsinchu, Taiwan 30077, ROC.Featuresz Backward compatible with MBI5026 in packagez 16 constant-current output channels z 16-bit/12-bit color depth PWM controlz Scrambled-PWM technology to improve refresh rate z Open/Short-Circuit Detection to detect individual LED errors z 8-bit programmable output current gain z Over temperature warning/protection zConstant output current range: 5 ~ 60mA at 3.3V supply voltage5 ~ 80mA at 5.0V supply voltagez Output current accuracy:between channels: <±1.5% (typ.), and between ICs: <±3% (typ.)z Staggered output delayz Maximum data clock frequency: 25MHz z Schmitt trigger input z 3.0V-5.5V supply voltageProduct DescriptionMBI5030 is designed for LED video applications using internal Pulse Width Modulation (PWM) control with selectable 16-bit or 12-bit color depth. MBI5030 features a 16-bit shift register which converts serial input data into each pixel gray scale of output port. At MBI5030 output port, sixteen regulated current ports are designed to provide uniform and constant current sinks for driving LEDs with a wide range of Vf variations. The output current can be preset through an external resistor. Moreover, the preset current of MBI5030 can be further programmed to 256 gain steps for LED global brightness adjustment.With Scrambled-PWM (S-PWM TM ) technology, MBI5030 enhances Pulse Width Modulation by scrambling the “on” time into several “on” periods. The enhancement equivalently increases the visual refresh rate. When building a 16-bit color depth video, S-PWM™ reduces the flickers and improves the fidelity. MBI5030 offloads the signal timing generation of the host controller which just needs to feed data into drivers. MBI5030 drives the corresponding LEDs to the brightness specified by image data. With MBI5030, all output channels can be built with 16-bit color depth (65,536 gray scales). Each LED’s brightness can be calibrated enough from minimum to maximum brightness with compensated gamma correction or LED deviation information inside the 16-bit image data.GF: SOP24-300-1.00Thin Shrink SOP GTS: TSSOP24-173-0.65Quad Flat No-LeadBlock Diagram Figure 1LE SDI DCLK SDOOUT0 1OUTOUT14 OUT15GCLKPin ConfigurationLE OUT 1OUT OUT OUT OUT 6OUT 7VDD SDO R -EXT OUT8OUT12OUT13OUT14OUT11OUT10OUT9OUT15GCLK MBI5030GF/GTS MBI5030GFNC L KD IV D D-E X TD OC L KEquivalent Circuits of Inputs and OutputsMaximum RatingCharacteristicSymbol Rating Unit Supply Voltage V DD 7 V Input Pin Voltage (SDI)V IN -0.4~V DD +0.4V Output CurrentI OUT +80 mA Sustaining Voltage at OUT Port V DS 17V Data Clock Frequency* F DCLK +25 MHz Gray Scale Clock Frequency F GCLK +25MHz GND Terminal Current I GND +1280 mA GF Type 2.39 GTS Type 3.87 Power Dissipation (On PCB, Ta=25°C) GFN Type P D3.49 WGF Type 52.37 GTS Type 32.34 Thermal Resistance (On PCB, Ta=25°C) GFN TypeR th(j-a) 35.85 °C/W Operating Temperature T opr -40~+85 °C Storage Temperature T stg-55~+150°C*Supply voltage is 5V.GCLK, DCLK, SDI terminal LE terminalSDO terminal VDDOUTFigure 2* Refer to the Timing Waveform, where n=0, 1, 2, 3.**In timing of “Read Configuration” and “Read Error Status Code”, the next DCLK rising edge should be t PD2 after the falling edge of LE.***Refer to Figure 6.* Refer to the Timing Waveform, where n=0, 1, 2, 3.**In timing of “Read Configuration ” and “Read Error Status Code ”, the next DCLK rising edge should be t PD2 after the falling edge of LE. ***Refer to Figure 6.2V IH =V V ILFigure 3Timing Waveform(1)DCLKLESDISDO(2)OUT4nOUT4n+1OUT4n+2OUT4n+3GCLK(3)GCLKOutput Portst OF t OR90%90%10%10%t W(GCLK)Principle of OperationControl CommandSignals CombinationDescriptionCommand Name LE Number of DCLKRising Edge whenLE is assertedThe Action after a Falling Edge of LE Data Latch High 0 or 1 Serial data are transferred to the buffersGlobal Latch High 2 or 3 Buffer data are transferred to the comparatorsRead Configuration High 4 or 5 Move out “configuration register ” to the shift registersEnable “Error detection ” High 6 or 7 Detect the status of each output ’s LED Read “Error status code ” High 8 or 9 Move out “error status code ” of 16 outputs to the shift registersWrite ConfigurationHigh10 or 11Serial data are transferred to the “configuration register ”Data LatchGlobal LatchRead ConfigurationWrite ConfigurationLE SDO SDILE SDI SDOSDO SDISetting Gray Scales of PixelsMBI5030 implements the gray level of each output port using the S-PWM TMcontrol algorithm. With the 16-bit data, all output channels can be built with 65,536 gray scales. The 16-bit input shift register latches 15 times of the gray scale data into each data buffer with a “data latch ” command sequentially. With a “global latch ” command for the 16thgray scale data, the 256-bit data buffers will be clocked in with the MSB first, loading the data from port 15 to port 0.Full Timing for Data LoadingDCLK LE SDI SDOPort 15latchlatch latch latchPort 14Port 1Figure 4Open-Circuit Detection PrincipleThe principle of MBI5030 LED Open-Circuit Detection is based on the fact that the LED loading status is judged by comparing the effective current value (I out, effect ) of each output port with the target current (I out, target ) set by R ext . As shown in the above figure, the knee voltage (V knee ) is the one between triode region and saturation region. The cross point between the loading line and MBI5030 output characteristics curve is the effective output point (V DS, effect , I out,effect ).Thus, after the command of “enabling error detection ”, the output ports of MBI5030 will be turned on for a while.It is required to obtain the stable error status result for 1μ second. Then, the error status saved in the built-in register would be shifted out through SDO pin bit by bit by sending the command of “Read Error Status Code ”. Thus, to detect the status of LED correctly, the output ports of MBI5030 must be turned on. The relationship between the Error Status code and the effective output point is shown below:State of OutputPortCondition of Effective Output Point Detected Open-Circuit Error StatusCode Meaning Off I out, effect =0“0” -I out, effect ≦I out, target and V out, effect ＜V DS, TH “1” Open Circuit OnI out, effect ＝I out, target and V out, effect ≧V DS, TH“0”NormalI IDS kneeDSFigure 5Short-Circuit Detection PrincipleWhen LED is damaged, a short-circuit error may occur. To effectively detect the short-circuit error, LEDs need insufficiently biasing. The principle of MBI5030 LED Short Circuit Detection is based on the fact that the LED loading status is judged by comparing the effective current value(I out, effect) of each output port with the target current(I out, target) set by R ext. When LED is short and the LED forward voltage drops at the output point, V DS,effect will be larger thanV DS,TH ; therefore, the detected short-circuit error status code will be “0”. When normal LED is insufficiently biased, its effective output point would be located at the ramp area of MBI5030 Output Characteristics Curve, compared with LED with a short error falling within the flat zone. The relationship between the Error Status code and the effective output point is shown below:State of Output Port Condition of Effective Output PointDetected Short-CircuitError Status CodeMeaning OFF I out, effect =0 “0”-I out, effect≦I out, target and V DS, effect<V DS, TH“1”Normal ONI out, effect=I out, target and V DS, effect≧V DS, TH“0”Short CircuitFigure 7I out, effect1 = I extINote :t EDD = 1μs is required to obtain the stable error status result.Figure 5Definition of Configuration RegisterMSBLSB FEDCBA 987 6543 21e.g.. Default Value F E D C BA9876 5 4321 0 0 0 0008’b10101011 0Bit Attribute DefinitionValueFunction 0 (Default) Correct F Read Parity bit (even) of configuration register1Parity error0 (Default) Safe (OK)E Read Thermal error flag 1Over temperature (>150°C typ.) 0 (Default) 16 bits DRead/WritePWM gray scale counter112 bits00 (Default)When bit D is set to “0”,64 times of MSB* 10-bitPWM counting and once of LSB* 6-bit PWMcountingWhen bit D is set to “1”, 64 times of MSB 6-bit PWM counting and once of LSB6-bit PWM counting C01When bit D is set to “0”,16 times of MSB 10-bitPWM counting by 1/4GCLK and once of LSB6-bit PWM countingWhen bit D is set to “1”, 16 times of MSB 6-bit PWM counting by 1/4 GCLK and once of LSB 6-bit PWM counting 10When bit D is set to “0”, 4 times of MSB 10-bit PWM counting by 1/16 GCLKand once of LSB 6-bitPWM countingWhen bit D is set to “1”, 4 times of MSB 6-bit PWMcounting by 1/16 GCLK and once of LSB 6-bit PWM counting BRead/WritePWM counting mode selection1116-bit PWM counting 12-bit PWM counting 0 (Default) Auto-synchronization A Read/Write PWM datasynchronizationmode 1Manual synchronization 9~2 Read/WriteCurrent gainadjustment00000000 ~11111111 8’b10101011 (Default)0 (Default)Disable1 Read/Write Thermal protection1Enable** , 25% of setting output current if T TF > 150°C 0 (Default)Enable*** 0Read/WriteTime-out alert of GCLK disconnection 1Disable*Please refer to “Setting the PWM Counting Mode ” section. **Please refer to “TP Function (Thermal Protection)” section. ***Please refer to “Time-Out Alert of GCLK Disconnection ” section.Checking Parity BitThe data of configuration register could refer to the use of even parity bit to check that data has been transmitted accurately. As the transmitting device sends 16-bit configuration register, it counts the total number of fifteen bits. If the number is even, it sets the parity bit to 0; if the number is odd, it sets the parity bit to 1. In this way, configuration register has an even number of 16 bits. Inside MBI5030, the device checks the configuration register to make sure that it has an even number of 16 bits. If it finds an odd number of 16 bits, the device knows there was an error during transmission and modified the parity bit to “1”, otherwise, the parity bit is set to “0” for correct transmission.Thermal Error FlagThe thermal error flag indicates an overheating condition. When IC ’s junction temperature is over 150°C (typ.), the bit “E ” is set to “1”. The bit “E ” can be read out through “Read Configuration ” command.Setting the PWM Gray Scale CounterMBI5030 provides a selectable 16-bit or 12-bit color depth. The value of 16-bit image data of each output will be only implemented according 16-bit or 12-bit PWM counter. The default bit “D ” is set to “0” for 16-bit color depth.Setting the PWM Counting ModeMBI5030 defines the different counting algorithms that support S-PWM TM, scrambled PWM, technology. With S-PWM TM, the total PWM cycles can be broken down into MSB ( Most Significant Bits) and LSB (Least Significant Bits) of gray scale cycles, and the MSB information can be dithered across many refresh cycles to achieve overall same high bit resolution. MBI5030 also allows changing different counting algorithms and provides the better output linearity when there are fewer transitions of output.Mode 00 10-bit x 26 + 6-bit counting# of GCLKs=(210-1)x26+26 6-bit x 26+ 6-bit counting# of GCLKs=(26-1)x26+26 Mode 0110-bit x 22x24 + 6-bit counting # of GCLKs=(210-1)x22x24 +266-bit x 22x24 + 6-bit counting # of GCLKs=(26-1)x22x24 +26Mode 10 10-bit x 24x22 + 6-bit counting # of GCLKs=(210-1)x24x22 +26 6-bit x 24x22+ 6-bit counting# of GCLKs=(26-1)x24x22 +26Mode 11 16 direct counting# of GCLKs=21612 direct counting# of GCLKs=212Synchronization for PWM CountingBetween the data frame and the video frame, when the bit “A ” is set to “0” (Default), MBI5030 will automatically handle the synchronization of previous data and next data for PWM counting. The next image data will be updated to output buffers and start PWM counting when the previous data has finished one internal PWM cycle. It will prevent the lost count of image data resolution and guarantee the data accuracy. In this mode, system controller only needs to provide a continuous running GCLK for PWM counter. The output will be renewed after finishing one of MSB PWM cycles.lobal latch?command□DCLK LE SDI GCLK OUT0~15Figure 8When the bit “A ” is set to “1”, MBI5030 will update the next image data into output buffer immediately, no matter the counting status of previous image data is. In this mode, system controller will synchronize the GCLK accordingimage data outside MBI5030 by itself. Otherwise, the conflict of previous image data and next image data will causeDCLK LE SDI GCLK OUT0~15Figure 9Time-Out Alert of GCLK DisconnectionWhen signal of GCLK is disconnected for around 1 second period, the all output ports will be turned off automatically. This function will protect the LED display system from staying on always and prevent a big current from damaging the power system. The default is set to ‘enable ” when bit “0” is 0. When the GCLK is active again and new serial data are moved in, the driver resumes to work after resetting the internal counters and comparators.Constant CurrentIn LED display application, MBI5030 provides nearly no variation in current from channel to channel and from IC to IC. This can be achieved by:1) The typical current variation between channels is less than 1.5%, and that between ICs is less than ±3%.2) In addition, the current characteristic of output stage is flat and users can refer to the figure as shown below. The output current can be kept constant regardless of the variations of LED forward voltages (V F). This guarantees LED to be performed on the same brightness as user’s specification.Figure 10Setting Output CurrentThe output current (I OUT) is set by an external resistor, R ext. The default relationship between I OUT and R ext is shown in the following figure.Figure 11Also, the output current can be calculated from the equation:V R-EXT=0.63Volt x G; I OUT=(V R-EXT/R ext)x15.5Whereas R ext is the resistance of the external resistor connected to R-EXT terminal and V R-EXT is its voltage. G is the digital current gain, which is set by the bit9 – bit2 of the configuration register. The default value of G is 1. For your information, the output current is about 21mA when R ext=460Ω and 10.8mA when R ext=910Ω if G is set to default value 1. The formula and setting for G are described in next section.Current Gain AdjustmentThe bit 9 to bit 2 of the configuration register set the gain of output current, i.e., G. As totally 8-bit in number, i.e., ranged from 8’b00000000 to 8’b11111111, these bits allow the user to set the output current gain up to 256 levels. These bits can be further defined inside Configuration Register as follows:F E D C B A 9 8 7 6 5 4 3 2 10 -- - - - - HC DA6 DA5 DA4 DA3 DA2 DA1 DA0 - -1. Bit 9 is HC bit. The setting is in low current band when HC=0, and in high current band when HC=1.2. Bit 8 to bit 2 are DA6 ~ DA0.The relationship between these bits and current gain G is: HC=1, D=(256G-128)/3 HC=0, D=(1024G-128)/3and D in the above decimal numeration can be converted to its equivalent in binary form by the following equation: D=DA6x26+DA5x25+DA4x24+DA3x23+DA2x22+DA1x21+DA0x20In other words, these bits can be looked as a floating number with 1-bit exponent HC and 7-bit mantissa DA6~DA0. For example,HC=1, G=1.25, D=(256x1.25-128)/3=64 the D in binary form would be:D=64=1x26+0x25+0x24+0x23+0x22+0x21+0x20The bit 9 to bit 2 of the configuration register are set to 8’b1100,0000.Delay Time of Staggered OutputMBI5030 has a built-in staggered circuit to perform delay mechanism. Among output ports exist a graduated 40ns delay time among n 4OUT , 1n 4OUT + , 2n 4OUT + , and 3n 4OUT + , by which the output ports will be divided to four groups at a different time so that the instant current from the power line will be lowered.Package Power Dissipation (PD)The maximum allowable package power dissipation is determined as P D (max)=(Tj –Ta)/R th(j-a). When 16 output channels are turned on simultaneously, the actual package power dissipation isP D (act)=(I DD xV DD )+(I OUT xDutyxV DS x16). Therefore, to keep P D (act)≤P D (max), the allowable maximum output current as a function of duty cycle is:I OUT ={[(Tj –Ta)/R th(j-a)]–(I DD xV DD )}/V DS /Duty/16, where Tj=150°C.The maximum power dissipation, P D (max)=(Tj –Ta)/R th(j-a), decreases as the ambient temperature increases.Figure 13MBI5030GFMBI5030GTSMBI5030GFNCondition: I OUT =80mA, 16 output channels Device Type R th(j-a) (°C/W) GF 52.37 GTS 32.34 GFN 35.85Figure 12 Safe Operation AreaUsage of Thermal PadThe PCB area L2xW2 is 4 times of the IC ’s area L1xW1.The thickness of the PCB is 1.6mm, copper foil 1 Oz. The thermal pad on the IC ’s bottom has to be mounted on the copper foil.TP Function (Thermal Protection)The TP function is disable by default when bit “1” is set to “0”. If this bit is set to “1”and the junction temperature exceeds the threshold, T X (150°C typ.), the thermal error flag will be turned on and the TP function will besimultaneously enabled. When the TP function is enabled, the output current will decrease to 25%. As soon as the temperature is below (110°C typ.), the thermal error flag will return to the default value “0” and the output current will recover from the 25% current. The average output current is limited, and therefore, the driver is protected from being overheated, however, it will degrade the gray scale.LED Supply Voltage (V LED )MBI5030 are designed to operate with V DS ranging from 0.4V to 0.8V (depending on I OUT =5~80mA) considering the package power dissipating limits. V DS may be higher enough to make P D (act) >P D (max) when V LED =5V and V DS =V LED –V F , in which V LED is the load supply voltage. In this case, it is recommended to use the lowest possible supply voltage or to set an external voltage reducer, V DROP . A voltage reducer lets V DS =(V LED –V F )–V DROP .Resistors or Zener diode can be used in the applications as shown in the following figures.Switching Noise ReductionLED drivers are frequently used in switch-mode applications which always behave with switching noise due to the parasitic inductance on PCB. To eliminate switching noise, refer to “Application Note for 8-bit and 16-bit LED Drivers- Overshoot ”.Figure 15Figure 14L2W2Copper foilL2W2MBI5030GTS Outline DrawingMBI5030GFN Outline Drawing Note: The unit for the outline drawing is mm.Product Top Mark InformationProduct Revision HistoryDatasheet version Device Version Code V1.00 A V2.00 BProduct Ordering InformationPart Number “Pb-free & Green ” Package Type Weight (g) MBI5030GF SOP24-300-1.000.30 MBI5030GTS TSSOP24-173 -0.650.0967 MBI5030GFNQFN24-4*4- 0.50.0379Process CodeG: Green and Pb-free○CodeDevice Version Code The second row of printingThe first row of printing Package Code MBIXXXX ○ ○ MBIXXXX ○ or。
MBI6024 Preliminary Datasheet V2.00-EN
6F-4, No.18, Pu-Ting Rd., Hsinchu, Taiwan 30072, R.O.C.Sink Driver for LED StripsFeaturesz 3x4-channel constant-current sink driver for LED strips z Constant current range: 3~45mAz 3 groups of output current, each group is set by an external resistor z Sustaining voltage at output channels: 17V (max.) z Supply voltage 3V~5.5VzEmbedded 16-bit PWM generator- Gray scale clock generated by the embedded oscillator - S-PWM patented technologyz Two selectable modes to trade off between image quality and transmission bandwidth- 16-bit gray scale mode (with optional 8-bit dot correction) - 10-bit gray scale mode (with optional 6-bit dot correction)z Reliable data transmission- Daisy-chain topology- Two-wire transmission interface - Phase-inversed output clock- Built-in buffer for long distance transmission zFlexible PWM reset modes - Auto-synchronization mode - Manual-synchronization mode z RoHS-compliant packagesApplicationz LED strips z Mesh display z Architectural lightingProduct DescriptionMBI6024 is a 3x4-channel, constant-current, PWM-embedded sink driver for LED strips. MBI6024 provides constant current ranging from 3mA to 45mA for each output channel and are adjustable with three corresponding external resistors. Besides, MBI6024 can support both 3.3V and 5V power systems and sustain 17V at output channels.With Scrambled-PWM (S-PWM) technology, MBI6024 enhances pulse width modulation by scrambling the “on” time into several “on” periods to increase visual refresh rate at the same gray scale performance. Besides, the gray scale clock (GCLK) is generated by the embedded oscillator. Moreover, MBI6024 provides two selectable gray scale modes to trade off between image quality and transmission: 16-bit gray scale mode and 10-bit gray scale mode. The 16-bit gray scale mode provides 65,536 gray scales for each LED to enrich the color. Subject to the 16-bit gray scale mode, the 8-bit dot correction may adjust each LED by 256-step gain to compensate the LED brightness. Furthermore, the 10-bit gray scale mode provides 1,024 gray scales. Subject to the 10-bit gray scale mode, 6-bit dot correction may adjust each LED by 64-step gain.In addition, MBI6024 features a two-wire transmission interface to make cluster-to-cluster connection easier. To improve the transmission quality, MBI6024 provides phase-inversed output clock to eliminate the accumulation of signal pulse width distortion. MBI6024 is also flexible for either manual-synchronization or auto-synchronization. The manual-synchronization is to maintain the synchronization of image frames between ICs. The auto-synchronization is to achieve accurate gray scale, especially when using the built-in oscillator.2413V R-EXTA R-EXTCOUTAn OUTBnMBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsSymbo l tSU tHD tPHL1 tPHL2 tPHL3 tPHL4 tPHL5 tPHL6 tPLH3 tPLH4 tPLH5 tPLH6 tw(I) tWDM tOR tOR1 tOF tOF1 FCKI FOSC VLED=4V VDS=1.0V VIH=VDD VIL=GND IOUT=20mA RL=150Ω CL=10pF C1=4.7uF C2=0.1uF C3=4.7uF CCKO=8pF CSDO=8pFSwitching Characteristics (VDD=3.3V, Ta=25°C)Characteristics Setup Time Hold Time SDI–CKI↓ CKI↓–SDI CKI↑–CKO↓ CKI↓–SDO↑↓ GCLK↑– OUTB0 , OUTA1 , Propagatio n Delay Time (“H” to “L”)OUTB2 ↓ConditionMin. 7.5 7.5 32 40 48 56 32 40 48 56 20 38 3.0 12.0 3.0 30.0 0.2 -Typ. 50 38 40 48 56 64 40 48 56 64 6.0 18.0 6.0 35.0 24.0Max. 48 56 64 72 48 56 64 72 9.0 24.0 9.0 40.0 10 -Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHzGCLK↑– OUTC1 , OUTA3 ,OUTC3↓ ↓GCLK↑– OUTA0 , OUTC0 ,OUTA2GCLK↑– OUTB1 , OUTC2 , OUTB3 ↓ GCLK↑– OUTB0 , OUTA1 ,OUTB2 ↑Propagatio n Delay Time (“L” to “H”)GCLK↑– OUTC1 , OUTA3 ,OUTC3↑ ↑GCLK↑– OUTA0 , OUTC0 ,OUTA2GCLK↑– OUTB1 , OUTC2 , OUTB3 ↑ Pulse Width Minimum Pulse Width of PWM Rise Time CKI*OUTAn ~ OUTCnCKO/SDOOUTAn ~ OUTCnFall TimeCKO/SDOOUTAn ~ OUTCnCKI* Frequency Internal Oscillator*The maximum frequency may be limited by different application conditions. Please refer to the application note for details.- 11 -October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsTest Circuit for Electrical / Switching Characteristics- 12 -October 2011, V2.00MBI6024Timing WaveformPWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsSignal Input and Output with Phase-inversed Output ClockOutput Timing- 13 -October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsPrinciple of OperationMBI6024 provides SPI-like interface (CKI, SDI), a two-wire transmission interface, to address the data, so that MBI6024 receives the data directly without a latch command. The sequence of operation should follow the steps below: Step 1. Set the configuration register Step 2. Send the dot correction data Step 3. Send the gray scale data MBI6024 receives the data packet containing targeted gray scale (GS) data from the controller, and turns on the output channels according to the gray scale data. The gray scale clock of PWM generator, GCLK, is generated by the embedded oscillator.Control Interface: SPI-Like Interface (CKI, SDI)MBI6024 adopts the SPI-like interface (CKI/SDI). By SPI-like interface, MBI6024 samples the data (SDI) at the falling edge of the clock (CKI).The following waveforms is the example of the SPI-like interface.Phase-inversed Output Clock MBI6024 enhances the capability of cascading MBI6024 by phase-inversed output clock function. By phase-inversed output clock, the clock phase will be inversed from CKI to CKO to eliminate the accumulation of the pulse width deviation. This improves the signal integrity of data transmission. The following chart illustrates the phase-inversed output clock results.Original: CKI1 Original: CKO1 Phase-Inverse Clock I:CKO2 Phase-Inverse Clock II: CKO3- 14 -October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsThe Structure of Data PacketMBI6024’s data packet contains three parts: 1. Prefix: The prefix is a symbol of “Silent-to-Reset”, i.e. a time period for MBI6024 to distinguish two data packets. During the prefix, both CKI and SDI should be tied-low and stop for more than 172 CKI cycles. 2. Header: The header defines the cascaded IC numbers and also contains a command to decide the data type. 3. Data: This is the data for each IC. It may be gray scale data, dot correction data, or configuration data. Structure of a data packet:PrefixHeaderData- 15 -October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsSetting the Data Types by the CommandMBI6024 provides six kinds of commands and input data types shown as the table below: Command H[5:0] 6’b11 1111 6’b10 1011 6’b11 0011 6’b10 0111 6’b10 0011 6’b11 0111 Data Type 16-bit gray scale data 10-bit gray scale data 8-bit dot correction data 6-bit dot correction data 16-bit configuration data 10-bit configuration dataOnce MBI6024 receives the SDI=1 (1’b1), MBI6024 will start to check if the data is a valid command or not. If the 6-bit data is a valid command, the driver will latch the specific data according to the protocol. If the 6-bit data is not a valid command, MBI6024 will wait for another SDI=1 (1’b1) to check the validity of the next command. Time-Out Reset for Transmission Abort Time-out reset is to prevent ICs from misreading during the data transmission. If the CKI is tied-low for more than 95 CKI cycles, MBI6024 may identify the wires as disconnection. To prevent from misreading, MBI6024 will ignore the present input data and continuously show the previous image data until the next image data is correctly recognized. The Prefix in the Beginning of a Data Packet MBI6024 identifies the data as a new data packet after time-out, so the prefix in the beginning of a data packet should be more than 172 CKI cycles. If both CKI and SDI are tied-low and stop for more than the setting of CKI time-out period, MBI6024 will start to check the valid command of the next data packet. The prefix between two data packets helps MBI6024 identify the data packet correctly. The following timing diagram illustrates the interval between two data packets in 16-bit gray scale mode.The prefix > 172 CKI cycles- 16 -October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsDefinition of Configuration RegisterMBI6024 provides two configuration register sections: configuration register 1 (CF1) and configuration register 2 (CF2) as defined in the tables below.Configuration Register 1 (CF1):MSB Bit Default Value 9 10 8 7 0 6 11 5 4 1 3 1 2 11 1 LSB 0 0Note: Bit [15:10] should be set as “0” to avoid signal misjudgment. Bit Definition Value 11 9:8 GCLK frequency 10 (default) 01 00 7 6:5 4 Dot correction mode Reserved PWM counter reset PWM data synchronization Phase-inversed output clock Parity check 0 (default) 1 11 (default) 1 (default) 0 1 (default) 0 11 (default) 1 0 (default) Function GCLK=frequency of internal oscillator, i.e. 24MHz (typical). GCLK=oscillator frequency divided by two, i.e. 12MHz (typical). GCLK=oscillator frequency divided by four, i.e. 6MHz (typical). GCLK= oscillator frequency divided by eight, i.e. 3MHz (typical). enable dot correction, bypass dot correction Must fill in ‘11’ Reset PWM counter after programming configuration register Do not reset PWM counter after programming configuration register Automatic synchronization Manual synchronization The waveform is inversed from CKI to CKO; please set the two bits as 2b’11. Other combinations are reserved for internal tests. Enable Disable32:10- 17 -October 2011, V2.00MBI6024GCLK FrequencyPWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsMBI6024 provides four kinds of internal GCLK frequency, which is the internal oscillator frequency divided by 1, 2, 4, and 8, for different applications according to the bits of CF1[9:8]. The internal oscillator frequency is 24MHz (typ.); e.g. if the internal oscillator frequency is divided by 8, the GCLK frequency is 3MHz. Higher GCLK frequency provides higher visual refresh rate, but also higher EMI. If the output current is larger than 40mA, the GCLK frequency is suggested to be lower than 8MHz to keep good linearity at low gray scale level. Dot Correction Mode MBI6024 also provides 8-bit or 6-bit dot correction in 16-bit or 10-bit gray scale mode respectively. Dot correction control helps compensate LED brightness and reduces the loading of calculation in controllers. In addition, with the built-in multiplier, MBI6024 operates dot correction without sacrificing the visual refresh rate. PWM Counter Reset MBI6024 can optionally reset the PWM counter by setting the bit of CF1[4] after programming configuration register. The default setting is to reset the PWM counter to start a new PWM cycle to align the PWM output data for new setting. PWM Data Synchronization MBI6024 is also flexible for either manual-synchronization or auto-synchronization by setting the bit of CF1[3]. For auto-synchronization, the bit of CF1[3] is set to “1” (default). MBI6024 will automatically process the synchronization of previous data and next data for PWM counting. The next image data will be updated to output buffers and start PWM counting when the previous data finishes one internal PWM cycle. For manual-synchronization, the bit of CF1[3] is set to “0”. Once the next input data is correctly recognized, MBI6024 will stop the present PWM cycle and restart a new PWM cycle to show the new data immediately. The advantage of manual-synchronization is to maintain the synchronization of image frames between ICs, but the PWM cycle may not be finished, so the gray scale accuracy is slightly affected. Since S-PWM scrambles the 16-bit PWM cycle into 64 small periods, the gray scale accuracy remains good. For better gray scale performance, auto-synchronization keeps accurate gray scale especially when using the built-in oscillator, but the drawback is the synchronization of image frames between ICs. Parity Check Parity check is to check the data in the header for any error, especially to prevent the configuration register and dot correction register from miswriting.- 18 -October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsConfiguration Register 2 (CF2):Default Value MSB Bit Value 2 1 111 LSB 0Note: Bit [15:3] should be set as “0” to avoid signal misjudgment. Bit 2 1:0 Definition Reserved Reserved Value 1 (default) 11 (default) Function Must fill in ‘1’ Must fill in ‘11’16-bit Configuration DataFor 16-bit configuration data, each word is 16 bits. Each MBI6024 needs 3 words (3x16=48 bits) for the configuration data. However, each configuration data has only 10 bits, and the MSB 6 bits of each word are invalid. Prior to the configuration data, there is a 48-bit header. MBI6024 provides parity check function to check the count of bit to prevent the data transmission error. The data format is shown below:Prefix Both CKI and SDI should be tied-low and stop for more than 172 CKI cycles. 48-bits header Bit Definition 47:42 H[5:0] 41:32 A[9:0] 31:26 25:16 H[5:0] L[9:0]Value 100011 0000000000 100011 N-1 N=Number of IC in seriesFunction The command of 16-bit configuration data Address data. Always send 10’b 0000000000 Double check the command. It should be the same as the prior H[5:0], otherwise the data packet will be ignored. Set the number of IC in series P[3:0] are parity check bits, If it is incorrect, the data packet will be ignored. P[0] is the parity check bit of L[9:0] P[0]=1 if the count of “1” within L[9:0] is odd; P[0]=0 if the count of “1” within L[9:0] is even.15:12P[3:0]0000~1111P[1] is the parity check bit of A[9:0] P[1]=1 if the count of “1” within A[9:0] is odd; P[1]=0 if the count of “1” within A[9:0] is even. P[2] is the parity check bit of H[5:0] P[2]=1 if the count of “1” within H[5:0] is odd; P[2]=0 if the count of “1” within H[5:0] is even. - 19 October 2011, V2.00MBI6024PWM-Embedded 3x4-Channel Constant-Current Sink Driver for LED StripsP[3] is the parity check bit of P[2:0] P[3]=1 if the count of “1” within P[2:0] is odd; P[3]=0 if the count of “1” within P[2:0] is even.11:10 9:0X1[1:0] L[9:0]XX N-1 N=Number of IC in seriesDon’t care. The value is suggested to be “0”. Double check the number of IC in series48-bit configuration data Bit Definition Value Function X2[5:0] are “don’t care” bits. The value is suggested to be “0”. CF1N[9:0] are 10 bits data of configuration register 1 (CF1). The 2nd 47:0 X2[5:0]~CF1N[9:0]~ X2[5:0]~CF1N[9:0]~ X3[12:0]~CF2N[2:0] CF1[9:0] double checks the data of configuration register bank 1 48b’0~48b’1 (CF1). It should be the same as the 1st CF1N[9:0]; otherwise the data will not be written into register. X3[12:0] are “don’t care” bits. The value is suggested to be “0”. CF2N[2:0] are 3 bits data of configuration register 2 (CF2) The configuration data of the last IC is sent first, followed by the previous ICs, and the first IC’s configuration data is sent in the end of the packet.- 20 -October 2011, V2.00PrefixBoth CKI and SDI should be tied-low and stop for more than 172 CKI cycles.30-bit headerBit Definition Value FunctionThe command of 10-bit configuration dataBoth CKI and SDI should be tied-low and stop for more than 172 CKI cycles. 48-bit headerBit DefinitionBoth CKI and SDI should be tied-low and stop for more than 172 CKI cycles. Bit DefinitionAccording to the above equation, the following table shows the examples:The ratio of output turn-on time1/256 x gray scale data2/256 x gray scale dataAccording to the above equation, the following table shows the examples:The ratio of output turn-on time1/64 x gray scale data2/64 x gray scale dataBoth CKI and SDI should be tied-low and stop for more than 172 CKI cycles. Bit DefinitionBoth CKI and SDI should be tied-low and stop for more than 172 CKI cycles. 30-bits headerBit DefinitionMBI6024GP Outline DrawingMBI6024GFN Outline Drawing (Max) (Max)Note 1: The unit for the outline drawing is mm.DisclaimerMacroblock reserves the right to make changes, corrections, modifications, and improvements to their products and documents or discontinue any product or service. Customers are advised to consult their sales representative for the latest product information before ordering. All products are sold subject to the terms and conditions supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. Macroblock’s products are not designed to be used as components in device intended to support or sustain life or in military applications. Use of Macroblock’s products in components intended for surgical implant into the body, or other applications in which failure of Macroblock’s products could create a situation where personal death or injury may occur, is not authorized without the express written approval of the Managing Director of Macroblock. Macroblock will not be held liable for any damages or claims resulting from the use of its products in medical and military applications.Related technologies applied to the product are protected by patents. All text, images, logos and information contained on this document is the intellectual property of Macroblock. Unauthorized reproduction, duplication, extraction, use or disclosure of the above mentioned intellectual property will be deemed as infringement.。
JMS566 Preliminary Datasheet Rev 0_9_2
JMicron/JMS5661.3 SUPPORT DEVICES Hard disk drives Removable media devices 1.4 APPLICATION EXAMPLES1.4.3 USB2.0, USB3.0 to SATA bridgeAn example of one SATA application is illustrated.Revision 0.9.2 © JMicron 2012. All rights reserved.Page 11Copying prohibited.JMicron/JMS566 2. Package Pin-Out2.1 QFN48 6x6 for JMS566-QGGB1A and QFN48 7x7 for JMS566-QGFB1AAVDDH3635343332313029282726 10 11 GPIO[6] VCCK25 VBUS 1212345678GPIO[3]VCCOGPIO[0]GPIO[1]GPIO[2]GPIO[4]TMEVCCKRevision 0.9.2 © JMicron 2012. All rights reserved.Page 12GPIO[5]9AVDDHAVDDLAVDDLXOUTREXTRXNRXPTXNTXPXINNCCopying prohibited.Revision 0.9.2 © JMicron 2012. All rights reserved.36 TME GPIO[0] GPIO[1] VCCK GPIO[2] 5 31 GPIO[3] 6 30 VCCO GPIO[4] GPIO[5] VCCK GPIO[6] VBUS 12 11 25 10 26 9 27 8 28 7 29 4 32 3 33 2 34 1 35REXT AVDDH TXP TXN AVDDL RXN RXP AVDDL XOUT XIN GND AVDDH2.2 LQFP48 7x7 for JMS566-LGEB1APage 13JMicron/JMS566Copying prohibited.JMicron/JMS5662.3 PIN TYPE DEFINITIONPin Type A D I O IO L H Definition Analog Digital Input Output Bi-directional Internal weak pull-low (Max. 164KΩ, Typical 96 KΩ, Min. 61KΩ) Internal weak pull-high (Max. 141KΩ, Typical 93 KΩ, Min. 66KΩ)2.4 PIN DescriptionSignal Name QFN 48 LQFP 48 Type DescriptionSerial ATA interface RXP 30 30 AI SATA Port RX+ Signal. A 10nF capacitor should be connected between this pin and SATA connector. SATA Port RX- Signal. A 10nF capacitor should be connected between this pin and SATA connector. SATA Port TX+ Signal. A 10nF capacitor should be connected between this pin and SATA connector. SATA Port TX- Signal. A 10nF capacitor should be connected between this pin and SATA connector. External Reference Resistance. A 12KΩ±1% external resistor should be connected to this pin.RXN3131AITXP3434AOTXN REXT33 3633 36AO AIUSB3.0 interface SSRXP SSRXN SSTXP 23 22 20 23 22 20 AI AI AO Super Speed RX+ Signal. Super Speed RX- Signal. Super Speed TX+ Signal. A 100nF capacitor should be connected between this pin and USB connector. Super Speed TX- Signal. A 100nF capacitor should be connected between this pin and USB connector. External Reference Resistance. A 12KΩ±1% external resistor should be connected to this pin.SSTXN SSREXT19 1619 16AO AIUSB2.0 interfaceRevision 0.9.2 © JMicron 2012. All rights reserved.Page 14Copying prohibited.JMicron/JMS566Signal Name DM DP VBUS QFN 48 13 15 12 LQFP 48 13 15 12 Type AIO AIO AI USB2.0 Bus D- Signal. USB2.0 Bus D+ Signal. USB2.0/3.0 Cable Power Input. This pin should be connected to the USB connector 5V. Capacitance for internal LDO of USB2.0. A capacitance to ground is recommended on this pin. The value should be 1uF. The output voltage range is 3.3V±10%. Note: This PIN provides power less than 10mA@3.3V. Don’t treat it as a power supply source. DescriptionAV33O1414AOCrystal Interface Crystal Input/Oscillator Input. It is connected to a 25MHz crystal or crystal oscillator. The variation range should be ±350ppm. And the input voltage should range in 3.3V±5%. Crystal Output. It is connected to a crystal. While crystal oscillator is applied, this pin should be reserved as No Connection (NC). The output variation range is around ±350ppm (input dependent). And the output voltage range is 3.3V±5% (input dependent).XIN2727AIXOUT2828AOSwitching Regulator REG_EN AVDDH GND LXO -45 43 44 -45 43 44 AI AI AI AO Switching Regulator Enable. 1: Enable switching regulator. 0: Disable switching regulator. Switching Regulator 3.3V Power Supply. Switching Regulator Ground. Switch Output Pin. An external inductor should be connected to this pin.Control and GPIO interface System Global Reset Input. Active-low to reset the entire chip. An external RC should be connected to this pin. Please refer to the following section for detailed description. MP Test Mode Enable. This pin is reserved for IC mass production testing. Please set this pin to low under normal operation. Chip Operation Mode Selection. [1:0] = 01: USB3.0/USB2.0 to SATA. Others: reserved.RST#3838DIHTME MODE[1] MODE[0]1 42 461 42 46DIHDILRevision 0.9.2 © JMicron 2012. All rights reserved.Page 15Copying prohibited.JMicron/JMS566Signal Name GPIO[0] QFN 48 2 LQFP 48 2 Type Description Serial Flash (SO). After power on status detection, this pin becomes Data Output (SO) of serial flash. This pin is default set to input. Serial Flash (SCK). This pin is Data Clock (SCK) of Serial Flash. This pin is default set to output. Serial Flash (SI). Data Input (SI) of Serial Flash. This pin is default set to output. Serial Flash (CE0#). This pin functions as Chip Enable (CE0#) of Serial Flash. GPIO[4]. This pin can be programmed by customized firmware. GPIO[5]. This pin can be programmed by customized firmware. GPIO[6]. This pin can be programmed by customized firmware. GPIO[7]. This pin can be programmed by customized firmware. 8051 UART Interface / GPIO[8]. This pin can be programmed to the UART interface by customized firmware. 8051 UART Interface / GPIO[9]. This pin can be programmed by customized firmware and also be programmed to the UART interface by customized firmware.DIOHGPIO[1]33DIOHGPIO[2] GPIO[3] GPIO[4] GPIO[5] GPIO[6] GPIO[7] UAO / GPIO[8] UAI / GPIO[9]5 6 8 9 11 41 375 6 8 9 11 41 37DIOH DIOH DIO DIOH DIO DIOL DIO4848DOPower and Ground VCCO VCCK 7 39 4 10 40 17 25 35 18 21 24 29 32 -7 39 4 10 40 17 25 35 18 21 24 29 32 26 47 P P Digital 3.3V Power Supply. Digital 1.0V Power Supply.AVDDHPAnalog 3.3V Power Supply.AVDDLPAnalog 1.0V Power Supply.GND Other NCPGround.26 47----Not Connected or Connected to Ground.Revision 0.9.2 © JMicron 2012. All rights reserved.Page 16Copying prohibited.JMicron/JMS5662.5 LED Indicator By default, GPIO[4] is used as HDD access indicator. If user has different application for LED function, please contact JMicron’s AE before PCB layout. 2.6 GPIO initial value All GPIOs set as input mode and disable internal pull-up function while in reset. After reset, the firmware will program all of GPIOs as input mode. Afterward, the initial value of GPIOs is read and stored in the system RAM for future using.Revision 0.9.2 © JMicron 2012. All rights reserved.Page 17Copying prohibited.JMicron/JMS566 3. External SPI Flash3.1 EXTERNAL FLASH PROM/EPROMFlash model 25LV512 25LD512 CE1007 25LD512 CE0953 25LV010 AE1008 PMC 25LD010 CE1001 PM25LV010 1M PM25LV020 2M 25LD512 AE0935 CommentMXIC25L512 AMC 25L512 MC 25L512 CM1 25L400 1E 25L5121E 25L2005 MC 25L4005 AMC 25L1605 DM2I 25L8005 MC 25L512E 25L1006E 25L2006E 25L4006E 25L8006E 25L1606E 25L3206E 25L6406E 25L4025CM1 MX25L1633E MX25L8035ERevision 0.9.2 © JMicron 2012. All rights reserved.Page 18Copying prohibited.JMicron/JMS566MX25L512E MX25L6445EA25L5120-F A25L20P10 AMIC A25L10PT0 A25L040M-F A25L016M-F A25L032M-FW25X10 AING 25X10AVNIG 25X10BVNIGWinbondW25X10BLSNIG W25X40BLSNIGW25X20BVSNGTP05-50GCP EN25F05-100GIP F20-100 GCP F32-100 H1P EON F10-100 GIP F40-100 GCP F16-100 HIP F80-100 HCP Q64-104 HIP Q80A-100HIPST25P05AVRevision 0.9.2 © JMicron 2012. All rights reserved.Page 19Copying prohibited.JMicron/JMS566M25P10 VP 25PE20VP 25P40VP25VF512 SST 25VF010A 25VF016B 25VF032B25F1024 ATMEL 25FS010 AT25F-512BESMTF25L01PA F25L05PAPCT(SST)25VF010A 25VF512A25Q512T Giga Device 25Q10T 25Q20T 25Q40TvpowerwinsFM25F02 FM25F04Revision 0.9.2 © JMicron 2012. All rights reserved.Page 20Copying prohibited.JMicron/JMS566 4. Clock & Reset4.1 Crystal input Single crystal input (25MHz) is needed. 4.2 Reset input All functions will be initialized by reset except the Analog Power-On Reset Circuit depending on the Power on-off. The reset input pin is the Schmitt trigger input pin. VT+ Schmitt Trigger Low to High Threshold Point is 2.2V and VT- Schmitt Trigger High to Low Threshold Point is 0.7V.Parameter Reset voltage Reset voltage Symbol VT+ VTCondition Low to High High to Low Min 2.2 0.7 Typical Max Unit V VRevision 0.9.2 © JMicron 2012. All rights reserved.Page 21Copying prohibited.JMicron/JMS566 5. Electrical Characteristics5.1 Absolute Maximum RatingParameter Digital 3.3V power supply Digital 1.0V power supply Analog 3.3V power supply Analog 1.0V power supply USB VBUS power supply Digital I/O input voltage Storage Temperature Symbol VCCO(ABS) VCCK(ABS) AVDDH(ABS) AVDDL(ABS) VBUS VI(D) TSTORAGE Condition Min -0.3 -0.3 -0.3 -0.3 4.0 -0.3 -40 Max 3.63 1.2 3.63 1.2 5.5 3.63 150 Unit V V V V V VoC5.2 Recommended Power Supply Operation ConditionsParameter Digital 3.3V power supply Digital 1.0V power supply Analog 3.3V power supply Analog 1.0V power supply Digital I/O input voltage Ambient operation temperature Junction Temperature Symbol VCCO VCCK AVDDH AVDDL VI(D) TA TJ Condition Min 2.97 1.0 2.97 1.0 0 0 -40 Typical 3.3 1.1 3.3 1.1 3.3 Max 3.63 1.2 3.63 1.2 3.63 70 125 Unit V V V V Vo oC C5.3 Recommended External Clock Source ConditionsParameter External reference clock Clock Duty Cycle 45 Symbol Condition Min Typical 25 50 55 Max Unit MHz %Revision 0.9.2 © JMicron 2012. All rights reserved.Page 22Copying prohibited.JMicron/JMS5665.4 Power Supply DC Characteristics 5.4.1 USB2.0 to SATA mode 5.4.1.1 IdleParameter Digital 3.3V power supply Digital 1.0V power supply Analog 3.3V power supply Analog 1.0V power supply Symbol VCCO VCCK AVDDH AVDDL Condition Operate @3.3V Operate @1.1V Operate @3.3V Operate @1.1V Min Typical 0.3 23 15.6 22.8 Max Unit mA mA mA mA5.4.1.2OperatingParameter Symbol VCCO VCCK AVDDH AVDDL Condition Operate @3.3V Operate @1.1V Operate @3.3V Operate @1.1V Min Typical 0.2 48.6 30.5 83.3 Max Unit mA mA mA mADigital 3.3V power supply Digital 1.0V power supply Analog 3.3V power supply Analog 1.0V power supply5.4.1.3 SuspendParameter Digital 3.3V power supply Digital 1.0V power supply Analog 3.3V power supply Analog 1.0V power supply Symbol VCCO VCCK AVDDH AVDDL Condition Operate @3.3V Operate @1.1V Operate @3.3V Operate @1.1V Min Typical 0.3 0.4 0.4 0.1 Max Unit mA mA mA mARevision 0.9.2 © JMicron 2012. All rights reserved.Page 23Copying prohibited.JMicron/JMS5665.4.2 USB3.0 to SATA mode 5.4.2.1 IdleParameter Digital 3.3V power supply Digital 1.0V power supply Analog 3.3V power supply Analog 1.0V power supply Symbol VCCO VCCK AVDDH AVDDL Condition Operate @3.3V Operate @1.1V Operate @3.3V Operate @1.1V Min Typical 0.3 46.1 23.3 98.9 Max Unit mA mA mA mA5.4.2.2OperatingParameter Symbol VCCO VCCK AVDDH AVDDL Condition Operate @3.3V Operate @1.1V Operate @3.3V Operate @1.1V Min Typical 0.3 76.2 37.8 160.1 Max Unit mA mA mA mADigital 3.3V power supply Digital 1.0V power supply Analog 3.3V power supply Analog 1.0V power supply5.4.2.3 SuspendParameter Digital 3.3V power supply Digital 1.0V power supply Analog 3.3V power supply Analog 1.0V power supply Symbol VCCO VCCK AVDDH AVDDL Condition Operate @3.3V Operate @1.1V Operate @3.3V Operate @1.1V Min Typical 0.3 0.4 0.4 2.8 Max Unit mA mA mA mA5.5 I/O DC CharacteristicsParameter Input low voltage Input high voltage Output low voltage Output high voltage Symbol VIL VIH VOL VOH 1.9 1.5 0.3 Condition Min Typical Max 0.7 Unit V V V VRevision 0.9.2 © JMicron 2012. All rights reserved.Page 24Copying prohibited.JMicron/JMS5665.6 Power-On Sequence The Power-On sequence rules are defined in this section. Designers should follow all the rules for external power designs. Detailed explanations are listed as below.T1: Rise time for 3V3 power rail from 0.0V to 3.3V T2: Rise time for 1V0 power rail from 0.0V to 1.1V T3: Time interval between 3.3V power and 1.1V Power. T4: Rise time for RST# signal from 0.0V to 2.2V The recommended power sequence and timing requirements are listed as below.Time T1 T2 T3 T4 Minimum 0.0 ms 0.0 ms 0.0 ms 20 ms Maximum 1.0 ms 1.0 ms 1.0 ms 100 msThe RESET timing constrain is based on the external RC reset circuits. In order to control the charge and discharge time for RC circuits, minimum and maximum requirements are listed. If designers apply timing control chip to control the reset signal, the only requirement will be minimum value. In other words, the maximum value can be skipped without problems.Revision 0.9.2 © JMicron 2012. All rights reserved.Page 25Copying prohibited.JMicron/JMS566 6 Internal Switching Regulator6.1 Application circuit Inductor value = 3.3 +/- 30% uH Input capacitor = 10uF Output capacitor = 20uF (If only 10uF is applied, please reserve space for another 10uF) 6.2 PCB layout guidelines : 1. Route high speed switching node LXO away from sensitive analog area (as crystal, REXT … etc) 2. Connect input/output capacitors to power and ground plane and put input/output capacitors close to IC and keep the high-current paths as short and wide as possible.Revision 0.9.2 © JMicron 2012. All rights reserved.Page 26Copying prohibited.JMicron/JMS566 7 Performance Benchmark7.1 Platform ConfigurationNO. Maker Product North Bridge Z77 South Bridge CPU Type INTEL Core i5 Memory DDR3-133 Test OSMB95ASUSP8Z77-V LX Mac Book PRO 9.1 (2012)N/AMacIvy BridgeWin 7 SP1 Win 8 3450 (3.10 GHz) 3 1 GB Build 9200 Intel Core i7 DDR3 Mac OS X 2.6GHz 1600 8 GB Lion 10.7.47.2 HDD ListNo HD-01 HD HITACHI 1TB Model HDS721010DLE630Revision 0.9.2 © JMicron 2012. All rights reserved.Page 27Copying prohibited.JMicron/JMS5667.3 JMS566 Performance 7.3.1 Win7USB2.0 Performance for Windows 7USB3.0 Performance for Windows 7Revision 0.9.2 © JMicron 2012. All rights reserved.Page 28Copying prohibited.JMicron/JMS5667.3.2 Win8USB2.0 Performance for Windows 8USB3.0 Performance for Windows 8Revision 0.9.2 © JMicron 2012. All rights reserved.Page 29Copying prohibited.JMicron/JMS5667.3.3 MacUSB2.0 Performance for Mac Book PROUSB3.0 Performance for Mac Book UASP ModeRevision 0.9.2 © JMicron 2012. All rights reserved.Page 30Copying prohibited.。
MBI6021 Preliminary Datasheet V1.00-CN
此外，灰阶频率 GCLK 可藉由内部震荡器产生。MBI6021 提供 10 位(1,024)灰阶的丰富颜色变化。
MBI6021 仅需要二线传输，可简化系统设计。为了增强讯号传输质量，MBI6021 提供输出時脈讯号反相设计可增进 长距离传输的质量。此外，MBI6021 提供输出的极性选择，可作为脉宽调变控制器来驱动大电流 LED 驱动器或 MOS。
TEL: +886-3-579-0068, FAX: +886-3-579-7534 E-mail: info@
-1-
2010 年 6 月，V1.00
MBI6021 应用于 RGB LED 像素之内建 PWM 3 通道恒流 LED 驱动器
脚位图
GND
1
POL
2
R-EXTA
应用
z LED建筑物装饰照明 z LED窗帘灯、LED灯条、LED招牌广告字 z LED霓虹灯替代光源 z PWM控制器应用，控制后级LED驱动电路
©Macroblock, Inc. 2010
Floor 6-4, No.18, Pu-Ting Rd., Hsinchu, Taiwan 30077, ROC.
装与 PCB 布局，以达到理想的散热表现。
-6-
2010 年 6 月，V1.00
MBI6021 应用于 RGB LED 像素之内建 PWM 3 通道恒流 LED 驱动器
直流特性 (VDD=5.0V, Ta=25°C)
特性
代表符号
量测条件
电源电压 输出端耐受电压 输出端电流
输出讯号驱动电流
输出端漏电流 电流偏移量(通道间)
-
V
-
0.2
V
0.41
0.44
5050-01_81(中文)
Epec 5050 控制单元技术文档文档版本历史日期注07.01.2013 文档更新 (增加 8 MByte 硬件版本)04.12.2012 文档更新19.10.2012 第一版发布Technical Manual 5050 / MAN000539在解释争议的情况下，以英文为准。
英文版文档可从EPEC 网站或中国办事处获取。
Epec Oy reserves all rights for improvements without prior notice目录1前言 ....................................................................................................................................... 5 1.1 使用的符号 ................................................................................................................ 5 1.2 所需的基本技能 ......................................................................................................... 5 1.3 安全准则 .................................................................................................................... 6 1.4 Warranty .. (6)1.4.1 Limited Liability ............................................................................................... 7 1.5 Environmental Statement (7)1.5.1 WEEE ............................................................................................................. 7 1.5.2 RoHS .............................................................................................................. 7 2 产品概述................................................................................................................................ 8 3 技术参数.............................................................................................................................. 10 4输入输入说明书 ................................................................................................................... 12 4.1 I/O 列表 ................................................................................................................... 12 4.2 配置 I/O ................................................................................................................... 15 4.3 PWM 输出/开关量输出/开关量输入 . (16)4.3.1 PWM/DO/DI_Type005 .................................................................................. 16 4.3.2 PWM/DO/DI_Type006 .................................................................................. 18 4.3.3 PWM/DO/DI/CM_Type007 ........................................................................... 21 4.3.4 PWM/DO/DI/CM_Type008 ........................................................................... 24 4.4 开关量输入/脉冲输入 .. (27)4.4.1 DI/PI_Type001 .............................................................................................. 27 4.4.2 DI/PI_Type002 .............................................................................................. 29 4.4.3 DI/PI_Type003 .............................................................................................. 30 4.4.4 脉冲输入的软件通道 ...................................................................................... 32 4.5 模拟量输入/开关量输入 . (33)4.5.1 AI/DI_Type011 .............................................................................................. 33 4.6 开关量输出 / 地.. (35)4.6.1 DO_GND/DI_Type010 .................................................................................. 35 4.7 参考电源针脚.. (37)4.7.1 +5V REF_Type015 ....................................................................................... 37 4.7.2 +10 V REF_Type004 .................................................................................... 38 4.7.3 电源针脚及其限制 ......................................................................................... 39 4.8 连接范例 (42)4.8.1 DI/PI_Type001的连接范例 ........................................................................... 43 4.8.2 DI/PI_Type002的连接范例 ........................................................................... 45 4.8.3 DI/PI_Type003的连接范例 ........................................................................... 46 4.8.4 PWM/DO/DI_Type005的连接范例 ............................................................... 48 4.8.5 PWM/DO/DI_Type006的连接范例 ............................................................... 50 4.8.6 PWM/DO/DI/CM_Type007的连接范例 ......................................................... 52 4.8.7 PWM/DO/DI/CM/Type008的连接范例 .......................................................... 54 4.8.8 AI/DI_Type011的连接范例 ........................................................................... 56 5总线连接.............................................................................................................................. 58 5.1 CAN 总线 ................................................................................................................. 58 5.2 以太网接口 .............................................................................................................. 59 6内部诊断.............................................................................................................................. 60 6.1 LED 指示灯.............................................................................................................. 60 6.2 温度 . (61)Technical Manual 5050 / MAN000539Epec Oy reserves all rights for improvements without prior notice6.3 错误日志 (61)7APPROVALS AND SAFETY .............................................................................................. 62 7.1 EMC Tests............................................................................................................... 62 7.2 Environmental Tests ............................................................................................... 68 8结构和布线 .......................................................................................................................... 70 8.1 单元尺寸 .................................................................................................................. 70 8.2 安装和清洁 .............................................................................................................. 71 8.3 插入和拔出电缆/连接器 ........................................................................................... 73 8.4 布线 . (75)8.4.1 系统拓扑结构 ................................................................................................ 75 8.4.2 终端电阻........................................................................................................ 75 8.4.3 CAN 总线 ...................................................................................................... 77 8.4.4 以太网 ........................................................................................................... 79 8.4.5 I/O 布线 ......................................................................................................... 80 8.4.6 供电电源........................................................................................................ 85 8.5 焊接 ......................................................................................................................... 88 8.6 系统范例 .................................................................................................................. 89 8.7 附件和订货代码 . (91)Technical Manual 5050 / MAN000539在解释争议的情况下，以英文为准。
电机驱动器PM100 Preliminary Datasheet
Tr Product SummaryFeatures∙300Arms current rating at 300VDC ∙Input Range 160-360VDC∙AC Induction and PM Synchronous options ∙Dual CAN2.0B for heavily automate ∙RS-232interface for simple setup w laptop or serial device ∙Extensive analog and digital l/O∙Sealed enclosure with shielded pow ∙Industry standard sensor interface monitor the vehicle ∙Boot Loader for field upgradeableThe PM100DX is an AC Tractio designed for on-and off-road Ele Hybrid Electric (HEV)applications.drive is fabricated using a patente flux thermal design approach reduces the size and weightof fi andimprovesitslifeinenvironment.With extensive ex automotive and military vehicle powerelectronicsapplications,achieved a major breakthrough Traction Control into a new vehicle.AC Traction Controller for Electric 0VDC input onous motor omated vehicles etup with a d power leads rfaces to able firmwareMajorInverter Ratings:Input Voltage,Operating Output Current,Continuous Output Current,Peak Output FrequencyOutput Power,Continuous Water Flow Rate,Minimum Inlet Coolant Temperature Controller Mass Controller Sizeraction Controller d Electric (EV)or ons.The Traction atented high heat that dramatically the finished drive,theautomotivee experience in icle traction and ons,RMShasgh in integrating hicle.ectric and HybridVehiclesV OP 100..360VDC l O 300Arms l O_pk 500A pk F M 0..±1500Hz P O 100kW elec F R 8LPM (2GPM)T W -40..+80°CM8kg 200x314x85mmRatings :DescriptionSystem Voltage –operatingMaximum System Voltage –non Power Rating (1)-electrical Efficiency (2)Output Current –continuous Output Current –peak Battery Current –continuous Short Circuit ProtectionHardware Overcurrent Protectio Vehicle System PowerOperating Temperature Range –no deratingOperating Temperature Range –derated output powerNon-Operating and Storage Tem Operating Shock Operating VibrationNon-Operating and Shipping Vib (1):Peak Rating is at 300V DC in,PF=(2):Efficiency Rating is at 300V ANALOG I/O :There are 5uncommitted analog and 5dedicated RTD inputs (3100Description Ain1–Ain5Input Range Offset VoltageAC Traction Controller for Electr ParameterV DC non-operating V DCmax P rated ɳl O_cont l O_peak l BATT_cont Type 1Type 2tection V BATT+nge –coolant water T water_op nge –coolant water T water_ope Temperature T no-op T stg S pk S op 10ng Vibration S no-opn,PF=0.8,T water ≤80ºCDC in,PF=.98,T water =80ºC,Rated Power og I/O inputs,intended for general analog signal se 1000Ohm and 2100Ohm calibrated RTD chann ParameterV range V ofslectric and HybridVehiclesValue 100..360V DC500V 100kW elec97%300A rms 550A pk 250A DCY Y Y 8..18V DC -40..+80ºC-40..+105ºC-40..+105ºC -55..+105ºC 40g pk any axis 10g rms 20-1500Hz anyaxis <TBD>nal sensing (0–5V)hannels)Value0..5.00V +50mVGain Accuracy G+5% ADC Resolution12b RTD1–RTD31000Ohm/0ºC Offset–25ºC ambient+3ºC+3ºC Temperature error–additional error overtemperatureRTD4–RTD5100Ohm/0ºC Offset–25ºC ambient+3ºC+3ºC Temperature error–additional error overtemperatureDIGITAL I/O:There are6uncommitted digital inputs,intended for general interface to the vehicle and for feedback from external contactors and switchgear as required in the application.Four inputs are“Switch to Ground”inputs:NOTE:DO NOTpull these pins up to5V or to the system13V bus.They areintended forOpen-Collector orSwitch Closure toGround to actuate. Two remaining inputs are“Switch to Battery”inputs:These are Active HI inputs that need to be pulled up to an external voltage,usually5V or12V. These inputs are safe to24V,and are protected from reverse polarity.High-Current Digital Outputs:There are4high current12V load driver outputs,2Hi-Side and2Lo-Side switches.The Hi-Side switches may be PWM’d at up to1.0kHz,depending on the choice of background interrupt rate. Description Parameter Value Hi-Side DriversOutput Current-Continuous I o_cont 1.5A Output Current-Surge I o_pk7A PWM duty cycle D0–100% PWM Resolution8bLo-Side DriverOutput Current-Continuous I o_cont 1.5A Output Current-Surge I o_pk3AThe Hi-Side drivers have inductive transient freewheeling diodes,and are designed to handle continuous current PWM modulation of loads like relay coils,lamps,pumps and fans,etc.The Lo-Side drivers are protected from inductive flyback by an internal high voltage clamp,so do not require freewheeling diodes in all cases,but are not intended for PWM operation.They may be used as a frequency output(0–1kHz typ)for instrumentation(Tach,etc.)if desired.CAN Interface:There are two CAN2.0B compliant serial ports,capable of operation at100k,250k,500k,and 1MB by software selection.The terminator can be applied or opened under software control during setup.EMI filtering for common-mode and differential-mode noise,and transientsuppressors are used to improve the robustness of the serial I/O system.RS-232Serial Interface:There is one RS-232serial interface with EMI filtering.This port can be used to set up and tune the controller,and to download controller software updates from a PC or terminal.RMS offers a simple serial user monitor that runs on the PC to allow changing parameters,changing the I/O functionality to suit the application needs,and other user-selectable optimizations.Encoder Interface:For applications that use an incremental optical or magnetic encoder,there is a5V interface to power the external encoder and to receive,level translate,and filter the signals from A,B and INDEX channels.The encoder is connected internally to the TI DSP QEP Module(Quadrature Encoder Peripheral),which has specific hardware for wide dynamic range speed and angle calculation from the encoder data.Resolver Interface:Upon request,a resolver can be used in place of the incremental encoder to determine machine rotor position and velocity.This is usually a good idea with Permanent Magnet(PMSM) machines,or any machine with significant rotor saliencies.The resolver is excited by a precision sinusoid,and the sine and cosine winding outputs are filtered for noise and presented to the DSP to be digitized at12b resolution.For more information,consult the factory.Installation:Plumbing connections for the cooling water or antifreeze mixture are required.There are2fluid ports on each side of the unit.The through holes(from side to side)constitute two separate plenums,one for fluid intake and one for outlet fluid pickup.While it generally isn’t critical,it is preferred that the rearmost plenum(the ports furthest from the3AC output terminals)be the fluid inlet,as this keeps the coolest fluid near the DC Link capacitor assembly.It is important to provide fluid from one side,and plug the other port of the intake plenum with a3/8NPT pipe plug or similar.The fluid outlet may be taken from either side,but once again it is preferred to draw the fluid away from the opposite side of the unit(outlet hose on the opposite side of the inverter),while again plugging the alternate port on the outlet plenum.The criss-cross water flow pattern provides the most uniform device operating temperatures and could improve unit operating life.External Signal Connectors:Two sealed automotive connectors are provided to connect to the internal I/O resources.J1and J2are standard AMPSEAL connectors by AMP/Tyco:J1–35p AMPSEAL Plug776164-1with crimp contact770854-1Pin#Pin Name Description Notes1XDCR_PWR2+5V@80mA max Accel Pedal Power13AIN1Analog Input10-5V FS<default=Accel Pedal wiper> 24AIN2Analog Input20-5V FS<default=spare>2GND GND Accel Pedal GND14XDCR_PWR2+5V@80mA max Brake Pedal Power25AIN3Analog Input30-5V FS<default=Brake Pedal wiper> 3AIN4Analog Input40-5V FS<default=spare>15GND GND Brake Pedal GND26XDCR_PWR2+5V@80mA max Spare5V transducer power4RTD11000Ohm RTD Input16RTD21000Ohm RTD Input27RTD31000Ohm RTD Input5RTD4100Ohm RTD Input17GND GND28XDCR_PWR1+5V@80mA max Spare5V transducer power6RTD5100Ohm RTD Input18AIN5Analog Input50-5V FS<default=spare>29n/c7/PROG_ENA Serial Boot Loader enable19GND30DIN1Digital Input1–STG(1)<default=/FWD_ENA>8DIN2Digital Input1-STG<default=/REV_ENA>20DIN3Digital Input1-STG<default=/BRAKE_SW>31DIN4Digital Input1-STG<default=/ENABLE>9DIN5Digital Input1–STB(2)<default=BRAKE_SW>21DIN6Digital Input1-STB<default=AUX_SW>32<reserved>DO NOT CONNECT Hydraulic coil driver+10<reserved>DO NOT CONNECT Hydraulic coil driver-22n/c33CANA_H CAN Channel A Hi11CANA_L CAN Channel A Low23CANB_H CAN Channel B Hi34CANB_L CAN Channel B Low12TXD RS-232Transmit35RXD RS-232Receive(1)–Switch to GND;(2)–Switch to BatteryJ2–23p AMPSEAL Plug7706802-1with crimp contact770854-1Pin#Pin Name Description Notes1XDCR_PWR1+5V@80mA max Encoder Power9ENCA Encoder Channel A input A16ENCB Encoder Channel B input B2ENCZ Encoder Channel Z input Index10GND GND Encoder GND17EXC Resolver excitation output EXC3GND Resolver excitation return/EXC11SIN Resolver Sine winding+SIN18/SIN Resolver Sine winding-/SIN4COS Resolver Cosine winding+COS12/COS Resolver Cosine winding-/COS19GND Resolver Shield GND5<reserved>DO NOT CONNECT Hydraulic coil driver+13<reserved>DO NOT CONNECT Hydraulic coil driver-20SPICLK External SPI connection<default=n/c>6/SPISTE(future upgrades)<default=n/c>14SPISOMI<default=n/c>21SPISIMO<default=n/c>7RLY1Hi-Side Relay Driver1<default=Main Contactor Drive> 15RLY2Hi-Side Relay Driver2<default=n/c>22RLY3Lo-Side Relay Driver3<default=n/c>8RLY4Lo-Side Relay Driver4<default=n/c>23BATT+Main12V power source12V Ignition Power InputExternal Power Connections :DC+/DC-Two rear-mounted terminal blocks are provided to attach the DC Link power from the vehicle to the Traction Controller .To wire these terminals,the cover does not need to be e an M14Allen wrench and remove the round plug above the terminal(s)to be wired.These plugs have an O-ring that seals against the top cover when they are tightened.Insert the wire or cable with the end stripped to 15mm (.625in)through the wall of the box (after removing the EMI gland as shown on theleft).The wire should be visible as it enters the terminal block,and you should be able to see the insulation enter far enough that you can JUST see it.Then tighten the two M6screws (4mm socket wrench)to make the connection:fastener Torque spec Wiring Plug 3Nm M6clamp screws 5Nm M18EMI Gland6NmMotor Connections are handled in the same manner:The three wiring plugs can be removed,and the terminal block accessed from above the inverter to insert the three motor power leads and connect them to the Traction controller .Be careful to observe the torque specifications as detailed above.TheEMI Glands provided inthe wiring kit are meant to land the powercable shield to the inverter case to encloseinternally generated EMI.They are slipped up the cable and screwed home in the end of the box before the wire is connected to the terminal block (to allow free rotation of the cable if necessary).DC MINUSTypical Application Wiring Diagram:PM100AC MOTOR CONTROLLERBASIC VEHICLE APPLICATION SCHEMATICJ1IS35PIN AMPSEAL CONNECTOR,TYCO P/N776164-1J2IS23PIN AMPSEAL CONNECTOR,TYCO P/N770680-1CONTACTS ARE TYCO P/N770854-110Mar2009PM100DX PRELIMINARY DATASHEET Rinehart Motion Systems LLCPhone:503344-508525749SW Canyon Creek Road North Fax:503682-9014Suite 400Email:sales@ Wilsonville,OR Preliminary information –subject to change without notice page 11Functional Description :The PM100is intended as a traction controller for EV and HEV drive systems,and includes both the motor control function and a rudimentary vehicle controller strategy in the same box.The motor control is a torque commanded,Direct Field Oriented Vector motor control technology that has been used on AC Induction and PM Synchronous motors in many applications.The use of Direct Field Orientation,measuring and regulating the machine flux with the use of an observer ,allows the control to track actual torque production in real time,including the effects of transients and disturbances that an Indirect Field Oriented controller cannot handle.The motor control subsystem is mated to a vehicle controller implemented in firmware in the drive DSP controller .This subsystem handles the driver interface (accel and decel /brake pedal inputs,Fwd/Rev controls,etc)and the vehicle interface (power sequencing,built in test,fault handling and safety issues).It is essentially a state machine in front of the motor controller firmware with a defined interface between the two software processes.<control block diagram>By default,out of the box the standard PM100is set up in Speed Control Mode,with default motor parameters loaded.The parameters must be changed to match the load motor ,and the vehicle mass and operating characteristics before running for the first time.These parameters personalize the drive to the motor ,and specify the function of CAN messages and the Analog and digital I/O connections to the vehicle.A wide range of configurations is possible by changing the default setup parameters.Inputs can be moved from one analog port to another or to a CAN message to facilitate interfacing to simple,hardwired system or to a sophisticated CAN network based vehicle with the equivalent of“throttle by wire”.Outputs can be broadcast over CAN for system control or data logging needs.Service and Maintenance :In general,there are no user serviceable items in the PM100Traction Controller family.All service should be done by the factory,or by an authorized repair facility.See the web site for details.There is no general maintenance required for the Traction Controllers.General cleanliness should be observed,and the unit should be thoroughly cleaned before installing,wiring,or re-wiring the controller .。
JXI5020 Preliminary Datasheet V1.01-CN
©聚积科技2009台湾新竹市埔顶路18号6F 之4电话：+886-3-579-0068，传真：+886-3-579-7534 E-mail: info@初始规格书JXI502016位恒流LED 驱动器特色z 16个恒流输出通道 z恒流输出值不受输出端负载电压影响恒流范围值， 3~45mA@V DD =5V ； 3~30mA@V DD =3.3V z极为精确的电流输出值，通道间差异值：<±1.5％(一般值); <±2.5％(最大值)； 芯片间差异值：<±1.5％(一般值); <±3.0％(最大值)。
z 利用一个外接电阻，可设定电流输出值z 快速的输出电流响应，OE ：70ns(保持输出一致性的条件下) z 高达25MHz 时钟频率 z 具Schmitt trigger 输入装置 z 操作电压：3.3/5.0伏特 z无铅环保包装产品说明JXI5020是利用最新PrecisionDrive™技术，专为 LED 显示面板设计的驱动IC ，它内建的CMOS 位移缓存器与栓锁功能，可以将串行的输入数据转换成平行输出数据格式。
JXI5020的输入电压范围值为3.3伏特至5伏特，提供16个电流源，可以在每个输出级提供3~45mA 定电流量以驱动 LED ；且单一颗IC 内输出通道的电流差异小于±2％@I OUT=25m ，±2.5％@I OUT =3mA ；多颗IC 间的输出电流差异小于±3%；电流随着输出端耐受电压(V DS )变化，被控制在每伏特0.1%；且电流受供给电压(V DD )、环境温度的变化也被控制在1%。
使用者可以经由选用不同阻值的外接电阻器来调整 JXI5020各输出级的电流大小，藉此机制，使用者可精确地控制LED 的发光亮度。
JXI5020的设计保证其输出级可耐压17伏特，因此可以在每个输出端串接多个LED 。
ICE1PCS01
Preliminary Datasheet, Version 1.1, 28 May 2003CCM-PFCICE1PCS01ICE1PCS01GStandalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)Power Management & SupplyEdition 2003-05-28Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 München© Infineon Technologies AG 1999. All Rights Reserved.Attention please!The information herein is given to describe certain components and shall not be considered as warranted charac-teristics.Terms of delivery and rights to technical change reserved.We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein.Infineon Technologies is an approved CECC rmationFor further information on technology, delivery terms and conditions and prices please contact your nearest Infi-neon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list).WarningsDue to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office.Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide: see our webpage at CoolMOST™, CoolSET™ are trademarks of Infineon Technologies AG.CCM-PFCRevision History:2003-05-28DatasheetPrevious Version:v1.0CCM-PFCICE1PCS01Preliminary DataStandalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)Product Highlights•Wide Input Range•Output Power Controllable by External Sense Resistor•Programmable Operating Frequency •Output Under-Voltage Detection•Fast Output Dynamic Response during LoadFeatures•Ease of Use with Few External Components •Supports Wide Range •Average Current Control•External Current and Voltage Loop Compensation for Greater User Flexibility•Programmable Operating/Switching Frequency (50kHz - 250kHz)•Max Duty Cycle of 95% (typ) at 125kHz•Trimmed Internal Reference Voltage (5V+2%)•VCC Under-Voltage Lockout•Cycle by Cycle Peak Current Limiting •Over-Voltage Protection •Open Loop Detection•Output Under-Voltage Detection •Brown-Out Protection•Enhanced Dynamic Response•Unique Soft-Start to Limit Start Up Current •Fulfills Class D Requirements of IEC 1000-3-2DescriptionThe ICE1PCS01/G is a 8-pin wide input range controller IC for active power factor correction converters. It is de-signed for converters in boost topology, and requires few external components. Its power supply is recommended to be provided by an external auxiliary supply which will switch on and off the IC.The IC operates in the CCM with average current control, and in DCM only under light load condition. The switching frequency is programmable by the resistor at pin 4. Both compensations for the current and voltage loop are exter-nal to allow full user control.There are various protection features incorporated to en-sure safe system operation conditions. Examples are peak current limitation, brown-out protection and output under voltage detection. The internal reference is trimmed (5V+2%) to ensure precise protection and control level. The device has an unique soft-start function which limits the start up current thus reducing the stress on the boost diode.1Pin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.1Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 1.2Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .52Representative Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.1General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.2Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.3Start-up (Soft-Start) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 3.4System Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.4.1Brown-Out Protection (BOP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.4.2Soft Over Current Control (SOC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.4.3Peak Current Limit (PCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 3.4.4Open Loop Protection / Input Under Voltage Protect (OLP) . . . . . . . . . . .9 3.4.5Output Under Voltage Detection (OUV) . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.4.6Over-Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.5Frequency Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.6Average Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.6.1Complete Current Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.6.2Current Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.6.3Pulse Width Modulation (PWM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3.6.4Nonlinear Gain Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.7PWM Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.8Voltage Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.8.1Voltage Loop Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 3.8.2Enhanced Dynamic Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 3.9Output Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 4Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.2Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 4.3Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3.1Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3.2Variable Frequency Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3.3PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 4.3.4System Protection Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 4.3.5Current Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.3.6Voltage Loop Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 4.3.7Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 5Outline Dimension . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17Pin Configuration and Functionality1Pin Configuration and Functionality1.1Pin ConfigurationFigure 1Pin Configuration (top view)1.2Pin FunctionalityGND (Ground)The ground potential of the IC.ICOMP (Current Loop Compensation)Low pass filter and compensation of the current control loop. The capacitor which is connected at this pin integrates the output current of OTA2 and averages the current sense signal.ISENSE (Current Sense Input)The ISENSE Pin senses the voltage drop at the external sense resistor (R1). This is the input signal for the average current regulation in the current loop. It is also fed to the peak current limitation block.During power up time, high inrush currents cause high voltage drop at R1, driving currents into pin 3 which could be beyond the absolute maximum ratings. Therefore a series resistor (R2) of around 220Ω is recommended in order to limit this current into the IC.FREQ (Frequency Setting)This pin allows the setting of the operating switching frequency by connecting a resistor to ground. The frequency range is from 50kHz to 250kHz.VSENSE (Voltage Sense/Feedback)The output bus voltage is sensed at this pin via a resistive divider. The reference voltage for this pin is 5V.VCOMP (Voltage Loop Compensation)This pin provides the compensation of the output voltage loop with a compensation network to ground (see Figure 2). This also gives the soft start function which controls an increasing AC input current during start-up.VCC (Power Supply)The VCC pin is the positive supply of the IC and should be connected to an external auxiliary supply. The operating range is between 10V and 21V. The turn-on threshold is at 11.2V and under voltage occurs at 10.2V. There is no internal clamp for a limitation of the power supply.GATEThe GATE pin is the output of the internal driver stage, which has a capability of 1.5A source and sink current.Its gate drive voltage is clamped at 11.5V (typically).Pin Symbol Function 1GND IC Ground2ICOMP Current Loop Compensation 3ISENSE Current Sense Input 4FREQ Switching Frequency Setting 5VCOMPVoltage Loop Compensation6VSENSE V OUT Sense (Feedback) Input7VCC IC Supply Voltage 8GATEGate Drive OutputCCM-PFCPreliminary DataICE1PCS01/GRepresentative Block diagram 2Representative Block diagram ArrayFigure 2Representative Block diagram3.1GeneralThe ICE1PCS01/G is a 8 pin control IC for power factor correction converters. It comes in both DIP and DSO packages and is suitable for wide range line input applications from 85 to 265 VAC. The IC supports converters in boost topology and it operates in continuous conduction mode (CCM) with average current control.The IC operates with a cascaded control; the inner current loop and the outer voltage loop. The inner current loop of the IC controls the sinusoidal profile for the average input current. It uses the dependency of the PWM duty cycle on the line input voltage to determine the corresponding input current. This means the average input current follows the input voltage as long as the device operates in CCM. Under light load condition, depending on the choke inductance, the system may enter into discontinuous conduction mode (DCM). In DCM, the average current waveform will be distorted but the resultant harmonics are still low enough to meet the Class D requirement of IEC 1000-3-2.The outer voltage loop controls the output bus voltage. Depending on the load condition, OTA1 establishes an appropriate voltage at VCOMP pin which controls the amplitude of the average input current.The IC is equipped with various protection features to ensure safe operating condition for both the system and device. Important protection features are namely Brown-out protection, Current Limitation and Output Under-voltage Protection.3.2Power SupplyAn internal under voltage lockout (UVLO) block monitors the VCC power supply. As soon as it exceeds 11.2V and the voltage at pin 6 (VSENSE) is >0.8V, the IC begins operating its gate drive and performs its Soft- Start as shown in Figure 3..Figure 3State of Operation respect to VCC If VCC drops below 10.2V, the IC is off. The IC will then be consuming typically 200µA, whereas consuming 18mA during normal operation.The IC can be turned off and forced into standby mode by pulling down the voltage at pin 6 (VSENSE) to lower than 0.8V. The current consumption is reduced to 3mA in this mode.3.3Start-up (Soft-Start)Figure 4 and 5 show the operation of OTA1 during startup. It sources a constant 10.8µA into the compensation network at pin 5 (VCOMP). The voltage at this pin rises linearly and so does the amplitude of the input current. As soon as the output voltage V OUT reaches 80% of its rated level, the startup procedure is finished and the normal voltage control takes over. In normal operation, the IC operates with a higher maximum current at OTA1 and therefore with a higher voltage loop gain in order to improve the dynamic behavior of the device..Figure 4Soft Start Circuitof audible noise. 3Functional Description3.4System ProtectionThe IC provides several protection features in order to ensure the PFC system in safe operating range. Depending on the input line voltage (V IN) and output bus voltage (V OUT), Figure 6 and 7 show the conditions when these protections are active.Figure 6VRelated Protection FeaturesFigure 7V OUT Related Protection FeaturesThe following sections describe the functionality of these protection features.3.4.1Brown-Out Protection (BOP)Brown-out occurs when the input voltage V IN falls below the minimum input voltage of the design (i.e. 85V for universal input voltage range) and the VCC has not entered into the V CCUVLO level yet. For a system without BOP, the boost converter will increasingly draw a higher current from the mains at a given output power which may exceed the maximum design values of the input current. The ICE1PCS01/G limits internally the current drawn from the mains and therefore also limits the input power. The difference of input and output power will result in decreasing output voltage. If the condition prolongs, the decreasing V OUT will terminate in output under voltage condition (OUV, 50% of rated), and the IC will be shut down (See section 3.4.5). Figure 8 shows the occurrence of BOP in respect to the ISENSE voltage.Figure 8BOP, SOC and PCL Protection as function of V ISENSEThe V IN threshold for BOP to occur is dependent on the voltage at ISENSE and thus the output power. The rated output power with a minimum V IN (V INMIN) isDue to the internal parameter tolerance, the maximum power with V INMIN before BOP occurs isAnd the BOP takes over the normal operation under rated output power latest at an input voltage of3.4.2Soft Over Current Control (SOC)The IC is designed not to support any output power that corresponds to a voltage lower than -0.73V at the ISENSE pin. A further increase in the inductor current, which results in a lower ISENSE voltage, will activate the Soft Over Current Control (SOC). This is a soft control as it does not directly switch off the gate drive like the PCL. It acts on the nonlinear gain block to result in a reduced PWM duty cycle.3.4.3Peak Current Limit (PCL)The IC provides a cycle by cycle peak current limitation (PCL). It is active when the voltage at pin 3 (ISENSE) reaches -1.08V. This voltage is amplified by OP1 by a factor of -1.43 and connected to comparator C2 with a reference voltage of 1.5V as shown in Figure 9. A deglitcher with 300ns after the comparator improves noise immunity to the activation of this protection.V ISENSE-0.6V-0.73V-1.08VNormalOperationSOC PCLP OUT(rated)BOPIC’sState(BOP occurs at V ISENSE = -0.6V Max)P OUT(max)P OUT rated()V INMIN0.6R12⋅---------------------×=P OUT max()V INMIN0.73R12⋅---------------------×=V BOPMAX P OUT rated()R12⋅0.73---------------------×=Figure 9Peak Current Limit (PCL)3.4.4Open Loop Protection / Input UnderVoltage Protect (OLP)Whenever VSENSE voltage falls below 0.8V, or equivalently V OUT falls below 16% of its rated value, it indicates an open loop condition (i.e. VSENSE pin not connected) or an insufficient input voltage V IN for normal operation. In this case, most of the blocks within the IC will be shutdown. It is implemented using comparator C3 with a threshold of 0.8V as shown in the IC block diagram in Figure 2.3.4.5Output Under Voltage Detection (OUV)In the event of main interrupt or brown-out condition, the PFC system is not able to deliver the rated output power. This will cause the output voltage V OUT to drop below its rated value. The IC provides an output under voltage detection that checks if V OUT is falling below 50% of its rated value. Comparator C4 as shown in the device block diagram (Figure 2) senses the voltage at pin 6 (VSENSE) with a reference of 2.5V. If comparator C4 trips, the IC will be shut down as in OLP. The IC will be ready to restart if there is sufficient V IN to pull V OUT out of OLP.3.4.6Over-Voltage Protection (OVP)Whenever V OUT exceeds the rated value by 5%, the over-voltage protection OVP is active as shown in Figure 7. This is implemented by sensing the voltage at pin VSENSE with respect to a reference voltage of 5.25V. A VSENSE voltage higher than 5.25V will immediately reduce the output duty cycle, bypassing the normal voltage loop control. This results in a lower input power to reduce the output voltage V OUT.3.5Frequency SettingThe switching frequency of the PFC converter can be set with an external resistor R5 at FREQ pin. The pin voltage V FREQ is typically 2.5V. The corresponding capacitor for the oscillator is integrated in the device and the R5/frequency relationship is given at the “Electrical Characteristic” section. The recommended operating frequency range is from50kHz to 250kHz. As an example, a R5 of 33kΩ at pin FREQ will set a switching frequency F SW of 133kHz typically.3.6Average Current Control3.6.1Complete Current LoopThe complete system current loop is shown in Figure 10.Figure 10Complete System Current LoopIt consists of the current loop block which averages the voltage at pin ISENSE, resulted from the inductor current flowing across R1. The averaged waveform is compared with an internal ramp in the ramp generator and PWM block. Once the ramp crosses the average waveform, the comparator C1 turns on the driver stage through the PWM logic block. The Nonlinear Gain block defines the amplitude of the inductor current. The following sections describe the functionality of each individual blocks.3.6.2Current Loop CompensationThe compensation of the current loop is done at the ICOMP pin. This is the OTA2 output and a capacitor C3has to be installed at this node to ground (see Figure 10). Under normal mode of operation, this pin gives a voltage which is proportional to the averaged inductor current. This pin is internally shorted to 5V in the eventof IC shuts down when OLP and UVLO occur.3.6.3Pulse Width Modulation (PWM)The IC employs an average current control scheme in continuous conduction mode (CCM) to achieve the power factor correction.Assuming the voltage loop is working and output voltage is kept constant, the off duty cycle D OFF for a CCM PFC system is given as From the above equation, D OFF is proportional to V IN .The objective of the current loop is to regulate the average inductor current such that it is proportional tothe off duty cycle D OFF , and thus to the input voltageV IN . Figure 11 shows the scheme to achieve theobjective.The PWM is performed by the intersection of a ramp signal with the averaged inductor current at pin 5 (ICOMP). The PWM cycle starts with the Gate turn off for a duration of T OFFMIN (250ns typ.) and the ramp is kept discharged. The ramp is then allowed to rise after T OFFMIN expires. The off time of the boost transistor ends at the intersection of the ramp signal and theaveraged current waveform. This results in the proportional relationship between the average current and the off duty cycle D OFF .Figure 12 shows the timing diagrams of T OFFMIN and the PWM waveforms.Figure 12Ramp and PWM waveforms3.6.4Nonlinear Gain BlockThe nonlinear gain block controls the amplitude of the regulated inductor current. The input of this block is thevoltage at pin VCOMP. This block has been designed to support the wide input voltage range (85-265VAC).3.7PWM Logic The PWM logic block prioritizes the control inputsignals and generates the final logic signal to turn onthe driver stage. The speed of the logic gates in thisblock, together with the width of the reset pulse T OFFMIN , are designed to meet a maximum duty cycle D MAX of 95% at the GATE output under 133kHz of operation.In case of high input currents which result in Peak Current Limitation, the GATE will be turned off immediately and maintained in off state for the current PWM cycle. The signal Toffmin resets (highest priority, overriding other input signals) both the current limit latch and the PWM on latch as illustrated in Figure 13.Figure 13PWM Logic 3.8Voltage LoopThe voltage loop is the outer loop of the cascadedcontrol scheme which controls the PFC output busvoltage V OUT . This loop is closed by the feedbacksensing voltage at VSENSE which is a resistive divider tapping from V OUT . The pin VSENSE is the input ofOTA1 which has an internal reference of 5V. Figure 14shows the important blocks of this voltage loop.3.8.1Voltage Loop CompensationThe compensation of the voltage loop is installed at the VCOMP pin (see Figure 14). This is the output of OTA1 and the compensation must be connected at this pin to ground. The compensation is also responsible for the soft start function which controls an increasing AC input current during start-up.D OFF V INVOUT-------------=T OFFMIN 250nsV CREF (1)V RAMP PWMramp releasedPWM cycle (1)V CREF is a function of V ICOMPtFunctional DescriptionFigure 14Voltage Loop3.8.2Enhanced Dynamic ResponseDue to the low frequency bandwidth of the voltage loop, the dynamic response is slow and in the range of about several 10ms. This may cause additional stress to the bus capacitor and the switching transistor of the PFC in the event of heavy load changes.The IC provides therefore a “window detector” for the feedback voltage V VSENSE at pin 6 (VSENSE). Whenever V VSENSE exceeds the reference value (5V) by +5%, it will act on the nonlinear gain block which in turn affect the gate drive duty cycle directly. This change in duty cycle is bypassing the slow changing VCOMP voltage, thus results in a fast dynamic response of V OUT.3.9Output Gate DriverThe output gate driver is a fast totem pole gate drive. It has an in-built cross conduction currents protection and a Zener diode Z1 (see Figure 15) to protect the external transistor switch against undesirable over voltages. The maximum voltage at pin 8 (GATE) is typically clamped at 11.5V.Figure 15Gate DriverThe output is active HIGH and at VCC voltages below the under voltage lockout threshold V CCUVLO, the gate drive is internally pull low to maintain the off state.4Electrical Characteristics4.1Absolute Maximum RatingsNote:Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of the integrated circuit.4.2Operating RangeNote:Within the operating range the IC operates as described in the functional description.Parameter Symbol Limit Values Unit Remarksmin.max.V CC Supply Voltage V CC -0.322V FREQ Voltage V FREQ -0.37V ICOMP Voltage V ICOMP -0.37V ISENSE Voltage V ISENSE -247V ISENSE Current I ISENSE -11mA Recommended R2=220ΩVSENSE Voltage V VSENSE -0.37V VSENSE Current I VSENSE -11mA R3>400k ΩVCOMP Voltage V VCOMP -0.37V GATE Voltage V GATE -0.322V Clamped at 11.5V if driven internally.Junction Temperature T j -40150°C Storage Temperature T S-55150°C Thermal ResistanceJunction-Ambient for DSO-8-3R thJA (DSO)-185K/W P-DSO-8-3Thermal ResistanceJunction-Ambient for DIP-8-4R thJA (DIP)-90K/W P-DIP-8-4ESD ProtectionV ESD-2kVHuman Body Model 1)1)According to EIA/JESD22-A114-B (discharging a 100pF capacitor through a 1.5k Ω series resistor)Parameter Symbol Limit Values Unit Remarksmin.max.V CC Supply Voltage V CC V CCUVLO 21V Junction TemperatureT JCon-40125°C4.3Characteristics4.3.1Supply SectionNote:The electrical characteristics involve the spread of values within the specified supply voltage and junction temperature range T J from – 40 °C to 125°C.Typical values represent the median values, which are related to 25°C. If not otherwise stated, a supply voltage of V CC =15V is assumed for test condition .4.3.2Variable Frequency SectionParameter SymbolLimit ValuesUnit Test Conditionmin.typ.max.VCC Turn-On Threshold V CCon 10.511.211.9V VCC Turn-Off Threshold/Under Voltage Lock Out V CCUVLO 9.410.210.8V VCC Turn-On/Off Hysteresis V CChy 0.81 1.3V Start Up Current Before V CConI CCstart 50100200µA V VCC =V VCCon -0.1V Operating Current with active GATE I CCHG 13.51822.5mA R5 = 33k ΩC L = 4.7nF Operating Current during StandbyI CCStdby2.02.63.2mAR5 = 33k ΩV VSENSE = 0.5VParameter SymbolLimit ValuesUnit Test Conditionmin.typ.max.Switching Frequency (Typical)F SWnom 106133161kHz R5 = 33k ΩSwitching Frequency (Min.)F SWmin 405670kHz R5 = 82k ΩSwitching Frequency (Max.)F SWmax 200250320kHz R5 = 15k ΩVoltage at FREQ pinV FREQ2.402.502.60V4.3.3PWM Section4.3.4System Protection SectionParameter SymbolLimit ValuesUnit Test Conditionmin.typ.max.Max. Duty Cycle D MAX 929598%F SW = F SWnom (R5 = 33k Ω)Min. Duty Cycle D MIN 0%V VCOMP = 0V, V VSENSE = 5V V ICOMP = 6.4VMin. Off TimeT OFFMIN150250350nsV VCOMP = 5V, V VSENSE = 5V V ISENSE = 0.1VParameter SymbolLimit ValuesUnit Test Conditionmin.typ.max.Open Loop Protection (OLP)VSENSE ThresholdV OLP 0.770.810.86V Peak Current Limitation (PCL)ISENSE ThresholdV PCL -1.15-1.08-1.00V Soft Over Current Control (SOC)ISENSE ThresholdV SOC -0.79-0.73-0.66V Output Under Voltage Detection (OUV)VSENSE ThresholdV OUV 2.45 2.55 2.65V Output Over-Voltage Protection (OVP)V OVP5.125.255.38V4.3.5Current Loop Section4.3.6Voltage Loop SectionParameter SymbolLimit ValuesUnit Test Conditionmin.typ.max.OTA2 Transconductance Gain Gm OTA20.91.1 1.3mS At Temp = 25°C OTA2 Output Linear Range I OTA2+/- 50µA Guaranteed by design ICOMP Voltage during OLPV ICOMPF3.64.0VV VSENSE = 0.5VParameter SymbolLimit ValuesUnit Test Conditionmin.typ.max.OTA1 Reference Voltage V OTA1 4.90 5.00 5.10V OTA1 Transconductance Gain Gm OTA131.54252.5µS OTA1 Max. Source Current Under Normal Operation I OTA1SO 213038µA V VSENSE = 4.25V V VCOMP = 4V OTA1 Max. Sink Current Under Normal Operation I OTA1SK 213038µA V VSENSE = 6V V VCOMP = 4VSoft Start End V SOFT 3.80 4.00 4.20V OTA1 Source Current Under Soft StartI OTA1SS8.010.813.4µAV VSENSE = 2V V VCOMP = 0V Enhanced Dynamic Response VSENSE High Threshold VSENSE Low ThresholdV Hi V Lo 5.124.63 5.254.75 5.384.87V V VSENSE Input Bias Current at 5V I VSEN5V 0 1.5µA V VSENSE = 5V VSENSE Input Bias Current at 1V I VSEN1V 01µA V VSENSE = 1V VCOMP Voltage during OLPV VCOMPF0.20.4VV VSENSE = 0.5V I VCOMP = 0.5mA。
MBI6901 Preliminary Datasheet V1.02-English
MacroblockFeaturesUniversal AC input from 80VAC to 265VACPreliminary DatasheetMBI6901AC/DC LED ControllerMini Small Outline PackageEfficiency> 90% @ VAC =110V, 350mA, 6-LEDsSetting current accuracy within ±5% To drive external MOSFET current up to 3 Amperes Hysteretic PFM improves efficiency at light loading Full protection: Thermal/UVLO/OVP/LED Open-/Short- Circuit Available in package: MSOP-8L GMS: MSOP-8L-118milProduct DescriptionThe MBI6901 is a high efficiency and step-down AC/DC controller which is designed to deliver constant current. The MBI6901 accepts universal input from 80VAC to 265VAC. It is specifically designed with hysteretic PFM control scheme to enhance the efficiency at light loading. The MBI6901 regulates the output current within ±5% preset current by well controlling the external MOSFET. In addition, LED current dimming can be controlled via output of photo coupler through DIM pin. The MBI6901 also has multiple features to protect the controller from fault conditions, including under voltage lockout (UVLO) and over voltage protection (OVP). Additionally, to ensure the system reliability, the MBI6901 is built with the thermal protection (TP) function. The function protects IC from over temperature (155 C) by turning off the external MOSFET. As soon as the temperature is below 125 C, the external MOSFET will resume to work again. The MBI6901 is available in MSOP-8L package.ApplicationsT-8 CFL Replacement LED Solution General Illumination Power Supply for Light PanelMacroblock, Inc. 2009 August 2009, V1.02 Floor 6-4, No.18, Pu-Ting Rd., Hsinchu, Taiwan 30077, ROC. TEL: +886-3-579-0068, FAX: +886-3-579-7534 E-mail: info@ -1-MBI6901Typical Application CircuitRSAC/DC LED ControllerRLimVDD DIM Fuse Vac Varistor EMI Filter COUT DR LEDn NTC VCCG CG CS L CF RSEN DF~ +Bridge Diode CINMBI6901 Q1 GATE R GS GND CS~ -LED1GNDEFigure 1 CIN: 10F/400V, 105 5000hrs electrolytic capacitor COUT: 10F/400V, 105 5000hrs electrolytic capacitor DR: 600V/1A, ultrafast diode DF: 600V/1A, ultrafast diode L: 2.2mH, 14*15 power inductor RS: 1Meg, resistor (sustaining voltage at least 400V) RLIM: 12, SMD resistor RGS: 20k, SMD resistor CS: 1F/50V, ceramic capacitor CF: 1F/16V, ceramic capacitor CG: 0.2F/25V, ceramic capacitor Q1: 600V/3.3A, N-channel MOSFET Note: GND and GNDE CAN NOT directly connect together to avoid IC damage and system malfunction.-2-August 2009, V1.02MBI6901Functional DiagramVDDAC/DC LED ControllerOver Voltage ProtectionUnder Voltage LockoutThermal ShutdownLDOVCCGRDIM DIM VrefGATEGNDCSFigure 2-3-August 2009, V1.02MBI6901Pin ConfigurationVDD 1 VCCG 2 GATE 3 CS 4MSOP-8L (Top View)AC/DC LED Controller8 Thermal Pad 7 6 5DIM NC NC GNDPin DescriptionPin NameVDD VCCG GATE CS GND NC DIMPin No.1 2 3 4 5 6, 7 8Function Supply voltage terminal and overvoltage protectionTerminal to connect a capacitor to enhance the stability of VCCG Terminal to drive the gate of the external MOSFETTerminal to sense LED string current Ground terminal for control logic and current sinkNo connectionTerminal for dimming control. If the dimming function is unused, this pin can be kept floating. Power dissipation terminal connected to GND*Thermal Pad-*To eliminate the noise influence, the thermal pad should connect to GND(Pin No. 5) on PCB. In addition, a heat-conducting copper foil on PCB soldered with thermal pad will improve the desired thermal conductivity.-4-August 2009, V1.02MBI6901Maximum RatingsAC/DC LED ControllerOperation above the maximum rating may cause device failure and affect the device reliability. Characteristic Supply Voltage Thermal Resistance (By simulation, on 4 Layer PCB)* Operating Junction Temperature Operating Temperature Storage Temperature * The PCB size is 76.2mm*114.3mm in simulation. GMS Type Symbol VDD Rth(j-a) Tj,max Topr Tstg Rating -0.4~44 38.93 125 -40~+85 -55~+150 Unit V °C/W °C °C °C-5-August 2009, V1.02MBI6901Electrical CharacteristicsAC/DC LED ControllerTest condition: VDD=12V, CIN=1F, COUT=0.5nF, TA=25°C; unless otherwise specified. Characteristics Symbol Condition Min. Supply Voltage VDD 9 IDD1 Quiescent Current HYSTERESIS CONTROL Sense Regulation Threshold Voltage Sense Over Current Threshold Voltage Threshold Hysteresis of VCS Input Current of VCS IDD2 The current before start-up voltage Switching frequency = 100KHz, driving 0.5nF load at gate terminal Change VCS until VGATE=High, please refer to Figure 3 Change VCS until VGATE=Low, please refer to Figure 3 VCS= - 0.2V VCS to GATE loop delay from high to low, VDD=12V, VCS = -0.15V to -0.25V, COUT=0.5nF VCS to GATE loop delay from low to high, VDD=12V, VCS= -0.15V to -0.25V, COUT=0.5nF COUT =0.5nF COUT =0.5nF -Typ. 20 2.5Max. 40 30 4.0Unit V uA mAVCSH VCSL ISEN TPDHL20 --170 -230 15 40 15060 300mV mV % uA nsInternal Propagation Delay Time TPDLH GATE DRIVER Output Voltage of Gate Gate Driver Rising Time Gate Driver Falling Time-150300nsVGATE tRISE tFALL7.0 145 -7.5 30 30 155 307.8 60 60 175 -V ns ns °C °CTHERMAL OVERLOAD Thermal Shutdown TSD Threshold Thermal Shutdown TSD-HYS Hysteresis START-UP & UNDER VOLTAGE LOCKOUT Start-up Voltage UVLO Voltage OVER VOLTAGE PROTECTION Over Voltage Protection PWM DIMMING Digital Dimming Logic “H” level “L” level VDIMIH VDIMIL RDIM VOVPVStart-up15 7.5 41 3.5 -16 8.0 44 10017 8.5 48 0.5 -V V V V V KVUVLOInternal Pull-up Resistor-6-August 2009, V1.02MBI6901Test Circuit for Electrical CharacteristicsVDDAC/DC LED ControllerV DIMIH V DIMILCINDIMVDD VCCGMBI6901CGVCSCSGATE GNDCOUTFigure 3-7-August 2009, V1.02MBI6901Application InformationAC/DC LED ControllerThe MBI6901 is a universal AC/DC constant current LED driver designed for high power LED applications. In the application, there are GND and GNDE in the circuit. The GND is the reference ground for internal circuit of MBI6901 while GNDE is the earth. Users should be aware that GND and GNDE CAN NOT directly connect together to avoid IC damage and system malfunction.Start-Up and UVLO (Under Voltage Lockout)When power is on, the voltage of CIN will charge Cs which is parallel to MBI6901 through Rs. The time for charging up to VStart-up is start-up time. The VStart-up is designed at 16V. The MBI6901 also includes UVLO protection. When VDD is below the UVLO threshold 8V (typ.), the UVLO starts to work and MBI6901 will be disabled as shown in Figure 4. The hysteresis of UVLO is 8V. Once reaching the VStart-up again, the output of GATE will turn on external MOSFET and start to regulate the desired constant current.VDD16V 8VVStart-up UVLO startsMBI6901 resumes to workUVLO protection Start-up time Normal Operation Normal OperationTimeFigure 4Setting Output CurrentThe output current (IOUT) is set by an external resistor, RSEN. The relationship between IOUT and RSEN is as below: VCS= - 0.2V; RSEN= IOUT= VCS /IOUT= 0.2V/IOUT; VCS /RSEN= 0.2V/RSENwhere RSEN is the resistance of the external resistor connecting to CS and GND pin. VCS is the voltage with respect to GND which is across on RSEN resistor. The magnitude of current (as a function of RSEN) is around 350mA at 0.57 .Hysteresis OperationIn the MBI6901, there is ±15% threshold hysteresis design in VCS. The parameter implies magnitude of LED ripple current as well. The operation of the MBI6901 is based on a hysteretic PFM control scheme resulting in the operatingfrequency remaining relatively constant with load and input voltage variations. The hysteretic PFM control requires no loop compensation resulting in very fast load transient response and achieving excellent efficiency performance at light loading.-8-August 2009, V1.02MBI6901Dimming ControlAC/DC LED ControllerDue to system configuration, it is a must to use photo coupler to dim the LED current when applying PWM signal as a dimming source as shown in Figure 5. It is suggested to add ceramic capacitor (CDIM) to filter out noise when coupling to DIM. Also, a RPull-up to speed up IC dimming is recommended. Users can refer to the Application Note of the MBI6901 for detailed information.MBI6901 1 VDD DIM NC NC GND CF 5 GND GND Q1 RGS RSEN DR C OUT L DF V LED Z DO ILED 8 CDIM RPULL-UP PhotoCoupler80~265 VacFuse NTC VaristorEMI FilterD1V INRS VDD CSIDDCIN Bridge Rectifier GND2 VCCG CG 3 GATEDimming Signal RLIM4 CSGNDE* Note: The "GND" and "GNDE" are different, please DON'T connect them togetherFigure 5OVP (Over Voltage Protection)When VDD reaches the OVP threshold 44V, the GATE is forced to go low. The GATE will start to pull high until the voltage falls down to the hysteresis level of 23V. This function prevents the driver from high voltage damage and protects LEDs. The threshold also limits the VLED and LED numbers that can be light up.LED Open-Circuit ProtectionWhen any LED connecting to the MBI6901 is open-circuited, it will trigger OVP and turn off the output current of the MBI6901.LED Short-Circuit ProtectionWhen any LED connecting to the MBI6901 is short-circuited, the MBI6901 will adapt and regulate the new loading.TP Function (Thermal Protection)When the junction temperature exceeds the threshold, TSD (155 C), the MBI6901 turns off the external MOSFET. Thus, the junction temperature starts to decrease. As soon as the junction temperature is below 125 C, the external MOSFET will be turned on again.-9-August 2009, V1.02MBI6901Design ExampleAC/DC LED ControllerThere is a design example for application reference. The design example is based on: The Input voltage of the target specification is from 80VAC to 265VAC. The expected LED current is 350mA. The LED numbers are 6pcs. VF=3.72V. Select LED Current The LED current(ILED) is set by RSEN Where RSEN = 0.2V/0.35A = 0.57. Choose RSEN =0.56. Therefore the power dissipation of PRSEN =(0.2V)2 / 0.56 = 0.0224W. It is suggested to use the RSEN resistance to equal 0.56/0.25W within 1% deviation. The result of LED current will be modified as ILED = 0.2V/ 0.56 = 357mA.Select the Inductor (L) and Switching Frequency (fsw) The inductance is determined by two factors: the switching frequency and the inductor ripple current. The calculation of the inductance, L, can be described as below:L=(VIN - VLED ) × D fSW × I LEDwhere D is the duty cycle of the MBI6901, D=VLED/VIN. fSW is the switching frequency of the MBI6901. ILED is the ripple current of inductor, ILED =(1.15xILED) (0.85x ILED)=0.3xILED.To avoid audio noise and overheating of power MOSFET (Q1), it is recommended to set fSW range within 40kHz ~ 100kHz. Based on the requirement, the selection of L and switching frequency fSW will both be satisfied within a range as well and can be calculated by equation below: Where L, REC-MAX = {[(80V x 2 ) – (3.72 x 6)] x [(3.72 x 6) / (80V x L, REC-MIN = {[(265V x 2 ) – (3.72 x 6)] x [(3.72 x 6) / (265V x Choose the inductor L = 2.2 mH, Choose the saturation current 1A and DCR=1.48. fSW, MIN = {[(80V x 2 ) – (3.72 x 6)] x [(3.72 x 6) / (80V x2 )]} / [0.3 x (40 x 1000) x 0.357] = 4.18 mH 2 )]} / [0.3 x (100 x 1000) x 0.357] = 1.96 mH2 )]} / [0.3 x (2.2 / 1000) x 0.357] = 76.04kHzfSW, MAX = {[(265x 2 ) – (3.72 x 6)] x [(3.72 x 6) / (265 x 2 )]} / [0.3 x (2.2 / 1000) x 0.357] = 89.05kHzSelect Bridge diode and Power MOSFET (Q1)The voltage rating of the bridge diode depends on the maximum value of the input voltage. It is reasonable to choose 1.2 times of VIN. MAX. as safety margin. Therefore, a 600V/1A bridge diode is enough.VBRIDGE = 1.2 × 2 × VIN.MAX = 1.2 × 2 × 265 = 450VIn this example, we adapt the bridge with the rating as 1000V/1.5A and forward voltage as 1.1V. Similar to the bridge diode, the voltage rating of power MOSFET can follow the calculation above. In typical application of the MBI6901, the output current usually ranges from 350mA to 1000mA. The 600V/2A - 10 August 2009, V1.02MOSFET or higher ratings are suitable. It is a recommended to minimize conduction loss by choosing the devices with low turn-on resistance. In the example, the rating of power MOSFET is 600V/3.3A.Filter Capacitor, C FTo ensure normal operation, the 1µF ceramic capacitor with 16V rating voltage to be C F is recommended.Gate Discharge Resistor, R GSIn this example, the recommended resistance of R GS is 20kΩ.Select F reewheeling Diode (D R and D F)In this example, the adopted device has the specification of reverse breakdown as 600V, forward current as 1A and forward voltage as 1.7V. The voltage rating of the freewheeling diode depends on the maximum value of the input voltage. It is reasonable to choose 1.2 times of V IN. MAX. as safety margin. The formula to select D R and D F is :×1.2IN.MAX=××=×2450V2265V1.2Therefore, a 600V/1A ultrafast diode is enough.Select Current Limit Resistor (R LIM) (Optional)The purpose of the R LIM is to protect D F. The small R LIM is enough. In this design example, R LIM =12 is suggested.Select Input Capacitor (C IN)The rated voltage of input capacitor should be at least 1.2 times of input voltage. An electrolytic capacitor can be used as an input capacitor. It is recommended to use 10µF/400V for 350mA and 22µF for above 700mA LED current application.Select Output Capacitor (C OUT) (Optional)A capacitor paralleled with cascaded LEDs can reduce the LED ripple current. An electrolytic capacitor can be used as an input capacitor. It is recommended to use 10µF/400V.Select Fuse, NTC, Varistor and EMI FilterPlease refer to MBI6901 Application Note and Design Tool for the selection of fuse, NTC and varistor. The EMI filter is optional. Therefore, users should choose the one based on their applications.MBI6901 GMS Outline DrawingDisclaimerMacroblock reserves the right to make changes, corrections, modifications, and improvements to their products and documents or discontinue any product or service without notice. Customers are advised to consult their sales representative for the latest product information before ordering. All products are sold subject to the terms and conditions supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.Macroblock’s products are not designed to be used as components in device intended to support or sustain life or in military applications. Use of Macroblock’s products in components intended for surgical implant into the body, or other applications in which failure of Macroblock’s products could create a situation where personal death or injury may occur, is not authorized without the express written approval of the Managing Director of Macroblock. Macroblock will not be held liable for any damages or claims resulting from the use of its products in medical and military applications.All text, images, logos and information contained on this document is the intellectual property of Macroblock. Unauthorized reproduction, duplication, extraction, use or disclosure of the above mentioned intellectual property will be deemed as infringement.。
SDIO接口模式WIFI模块规格书
WiFi-microSD 802.11b/g/n ModuleProduct Datasheet Preliminary V0.1Shenzhen Netcom Electronics Co.,Ltd.2011-02-22All rights are reserved by Shenzhen Netcom. Not allowed to be reproduced in any form without permission of Netcom. Subject to change without notice.Table of Contents1. Product Revision History (3)2. General Description (4)2.1 Block Diagram (4)2.2 Key Features (4)3. Dimensions and Footprint (5)4. Technical Specifications (8)4.1 Absolute Maximum Rating (8)4.2 Recommendable Operation Condition (8)4.2.1 General DC Electrical Characteristics(For 3.3V I/O Operation) (9)4.5 Typical Power Consumption performance (9)4.5.1 Typical Current Consumption [2.4GHz operation]-Continuous Receive (9)4.5.2 Typical Current Consumption [2.4GHz operation]-Continuous Transmit (9)5. I/O Characteristics (10)5.1 SDIO timing characteristics (10)6.2 SPI timing characteristics (12)7. Application Reference Design (12)8. Package Information (12)8.1 Marking (12)8.2 Package Dimension (13)8.3 Laser Mark (13)9. Ordering Information (13)1. Product Revision HistoryVersion No.Revised DateRevised byDescription NotesV0.1 2011-02-22 Min.Q Preliminary specification draft2. General DescriptionWiFi-microSD Module for 2.4 GHz Embedded WLAN Applications WiFi-microSD is 802.11b/g/n Wireless microSD Module which provides 802.11b/g/n WiFi access, which is optimized for cell phones, MIDs,PDAs, Multimedia players and other portable devices. WiFi-microSD is a highly integrated module, it integrated LNA, PA, Antenna and other necessary components. The WiFi-microSD provides multiple peripheral interfaces including SDIO, GSPI.WiFi-microSD is available in the standard microSD package with size by 11.0mm x 15.0mm x 0.7mm, and it is RoHS compliant and 100% lead (pb) free.2.1 Block DiagramA simplified block diagram of the WiFi-microSD module is depicted in the figure below.2.2 Key Features■Data Rates: 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, 54 (IEEE 802.11 b/g/n-compliant)■Modulation: QPSK, 16QAM, 64QAM DBPSK, DQPSK, CCK, OFDM with BPSK■WEP and AES hardware encryption accelerator up to 256 bits■Interface: SPI/SDIO■Leading-edge low power consumption■RoHS Compliant■ standar microSD package.3. Dimensions and FootprintThis section provides the dimensions and footprint of the WiFi-microSD. Figure 1-1 shows the contact pad view of the WiFi-microSD.Figure 1-1.Contact Pad ViewSD Mode SPI ModePin#Name Type Description Name Type Description 1 DAT2 I/O/PP DataLine[Bit2] RSV2 CD/DAT3 I/O/PP Card Detect/DataLine[Bit3]CS I ChipSelect(negtrue)3 CMD PP Command/Response DI I DataIn4 VDD S Supply voltage VDD S Supply voltage5 CLK I Clock SCLK I Clock6 VSS S Supply voltage ground VSS S Supply voltage ground7 DAT0 I/O/PP Data Line[Bit0] DO O/PP Data Out8 DAT1 I/O/PP DataLine[Bit1] RSVTable 1-1.Contact Pad DescriptionFigure 1-2. Mechanical Description: Top ViewFigure 1-3.Mechanical Description: Bottom ViewCOMMON DIMENSIONS COMMON DIMENSIONS SYMBOL MIN NOM MAX NOTE SYMBOL MIN NOM MAX NOTEA 10.90 11.00 11.10B11 1.1 1.2 1.3A1 9.60 9.70 9.80 B12 3.6 3.7 3.8A2 - 3.85 - BASIC B13 2.8 2.9 3A3 7.60 7.70 7.80 B14 8.2 - -A4 - 1.10 - BASIC B15 - - 6.2A5 0.75 0.80 0.85 C 0.9 1 1.1A6 - - 8.50 C1 0.6 0.7 0.8A7 0.90 - - C2 0.2 0.3 0.4A8 0.60 0.70 0.80 C3 0 - 0.15A9 0.80 - - D1 1 - -A10 1.35 1.40 1.45 D2 1 - -A11 6.50 6.60 6.70 D3 1 - -A12 0.50 0.55 0.60 R1 0.2 0.4 0.6A13 0.40 0.45 0.50 R2 0.2 0.4 0.6B 14.90 15.00 15.10R3 0.7 0.8 0.9B1 6.30 6.40 6.50 R4 0.7 0.8 0.9B2 1.64 1.84 2.04 R5 0.7 0.8 0.9B3 1.30 1.50 1.70 R6 0.7 0.8 0.9B4 0.42 0.52 0.62 R7 29.5 30 30.5B5 2.80 2.90 3.00 R10 - 0.2 -B6 5.50 - - R11 - 0.2 -B7 0.20 0.30 0.40 R17 0.1 0.2 0.3B8 1.00 1.10 1.20 R18 0.2 0.4 0.6B9 - - 9.00 R19 0.05 - 0.2B10 7.8 7.9 8 R20 0.02 - 0.15Table 1-2. microSD Package: Dimensions4. Technical Specifications4.1 Absolute Maximum RatingRatingUnit Symbol(Domain) Parameter MaxVDD Main Power 0 to 3.6 VI/O interface I/O voltage -0.3 to 3.6 VT store Storage temperature ℃discharge tolerance VESD Electrostatic4.2 Recommendable Operation ConditionUnitMaxTypSymbol(Domain) Parameter MinPower 2.8 3.3 3.6 VVDD MainT amblent Ambienttemperature ℃4.2.1 General DC Electrical Characteristics(For 3.3V I/O Operation)MaxTypUnitMinSymbol Parameter ConditionsV IH High Level Input V oltage 0.25*VDD 3.6 VV IL Low Level Input V oltage -0.3 0.25*VDD VV OH High Level Output V oltage0.75x VDD VV OL Low Level Output V oltage 0.125*VDDV 4.5 Typical Power Consumption performance4.5.1 Typical Current Consumption [2.4GHz operation]-Continuous ReceiveTypical Current Consumption[mA]Mode/Rate[Mbps]3.3V(VDD)CCK, 1Mbps 41CCK, 11Mbps 41OFDM, 6Mbps 43OFDM, 54Mbps 46HT20, MCS0 45HT20, MCS7 454.5.2 Typical Current Consumption [2.4GHz operation]-Continuous TransmitTypical Current Consumption[mA]Mode/Rate[Mbps]3.3V(VDD)CCK, 1Mbps 188CCK, 11Mbps 186OFDM, 6Mbps 180OFDM, 54Mbps 174HT20, MCS0 170HT20, MCS7 1505. I/O Characteristics5.1 SDIO timing characteristicsThe SDIO/SPI-interface can run in three different modes, SDIO 1-bit mode, SDIO 4-bit mode or in SDIO/SPI 1-bit mode. Timing can be set for Default speed mode or High speed mode.SDIO 1-bit Default speed mode is selected at Power On Reset. The host can change mode by sending the corresponding command over the SDIO-interface.The Default mode is showed in Figure 5-1 and Table 5-1. For the high speed mode see Figure 5-2 and Table 5-2. Condition: VDDIO_SDIO= 1.7 – 3.6 V, Tamb= -20 – +70°CFigure 5-1. SDIO/SPI timing diagram (default mode)Table 5-1.SDIO timing parameter values (default mode)Figure 5-2. SDIO timing diagram (high speed mode)Table 5-2.SDIO timing diagram (high speed mode)6.2 SPI timing characteristicsThe SPI interface is intended to be used for application specific purposes, like communicating with an external memory, display or codec. Note that this interface can not be used as a host interface. The timing characteristics are shown in Figure 6-3 and Table 6-3.Figure 6-3. SPI timing diagramTable 6-3.SPI timing parameter values6. Application Reference DesignTBD7. Package Information7.1 MarkingTBD7.2 Package DimensionTBD7.3 Laser MarkTBD8. Ordering InformationShenzhen Netcom Technology Netcom Electronics Co., LtdTel: +86-755-8616 8848 FAX: +86-755-8616 9388Address: 8/F, 1 Building, Finance Base,No. 8, Kefa Road, High-Tech Park, Shenzhen, China。
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©Macroblock, Inc. 2010
Floor 6-4, No.18, Pu-Ting Rd., Hsinchu, Taiwan 30077, ROC.
特色
z 操作电压：3~5.5伏特 z
恒流输出范围值：3~45mA -在5伏特操作电压：3~45mA -在3.3伏特操作电压：3~30mA
z 与MBI5026及MBI5030封装相容
z 16个恒流输出通道 z 内建4K 位SRAM 内存支持1~8扫分时多任务扫描 z 16/14位PWM 灰阶控制
z 扫描S-PWM 技术可提升视觉更新率 z 6位可程控之电流增益功能 z
极为精确的电流输出值： 通道间一般差异值：<±1.5％ 芯片间一般差异值：<±3％
z 输出通道间的交错时间迟滞，可避免突波电流 z 高达 30MHz 时钟频率 z
具 Schmitt trigger 输入装置
产品说明
MBI5050是专为LED 全彩显示屏应用设计的驱动芯片，可选择内建16位或是14位灰阶控制的脉波宽度调变功能。
MBI5050内建16位位移寄存器可以将串行的输入资料转换成每个输出通道的灰阶像数。
而且，MBI5050的16个恒流输出通道所输出的电流值不受输出端负载电压影响，并提供一致并且恒定的输出电流。
MBI5050的使用者可以经由选用不同阻值的外接电阻来调整MBI5050各输出级的电流大小。
除此之外，MBI5050的使用者还可以藉由可程序化的电流增益调整来调整64阶的整体LED 的驱动电流。
MBI5050内建SRAM 的创新架构，可支持最高8扫LED 扫描屏。
使用者仅需送一次完整的帧数据(frame data)，并储存在LED 驱动芯片内的SRAM 。
此方式不但可节省数据频带，也可在非常低的数据时钟频率下达到高灰阶的效果。
藉由Scrambled-PWM (S-PWM) 的技术，MBI5050可加强脉波宽度调变的功能，并将导通的时间分散成数个较短的导通时间，进而增加了扫描屏的视觉更新率。
在建立16位灰阶应用的全彩显示屏时，可藉由S-PWM 来减少画面的闪烁。
同时，控制器只需提供数据给MBI5050。
MBI5050可以藉由输入的影像数据来调整相对应LED 的亮度。
而且，MBI5050可以使每个输出通道表现出16位(65,536灰阶)的颜色变化。
而藉由16位影像数据中用来补偿gamma 修正或是LED 偏差的信息来调整每一颗LED 明亮度。
图3
(2)
负载端供应电压
为使封装体散热能力达到最佳化，建议输出端电压
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